1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/MapVector.h"
18 #include "llvm/ADT/OwningPtr.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Twine.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/MC/MCAssembler.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCDisassembler.h"
28 #include "llvm/MC/MCELFStreamer.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/MC/MCInstrInfo.h"
33 #include "llvm/MC/MCParser/MCAsmLexer.h"
34 #include "llvm/MC/MCParser/MCAsmParser.h"
35 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/MC/MCSection.h"
38 #include "llvm/MC/MCStreamer.h"
39 #include "llvm/MC/MCSubtargetInfo.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/MC/MCTargetAsmParser.h"
42 #include "llvm/Support/ARMBuildAttributes.h"
43 #include "llvm/Support/ARMEHABI.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ELF.h"
46 #include "llvm/Support/MathExtras.h"
47 #include "llvm/Support/SourceMgr.h"
48 #include "llvm/Support/TargetRegistry.h"
49 #include "llvm/Support/raw_ostream.h"
57 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
62 typedef SmallVector<SMLoc, 4> Locs;
67 Locs PersonalityIndexLocs;
72 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
74 bool hasFnStart() const { return !FnStartLocs.empty(); }
75 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
76 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
77 bool hasPersonality() const {
78 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
81 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
82 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
83 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
84 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
85 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
87 void saveFPReg(int Reg) { FPReg = Reg; }
88 int getFPReg() const { return FPReg; }
90 void emitFnStartLocNotes() const {
91 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
93 Parser.Note(*FI, ".fnstart was specified here");
95 void emitCantUnwindLocNotes() const {
96 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
97 UE = CantUnwindLocs.end(); UI != UE; ++UI)
98 Parser.Note(*UI, ".cantunwind was specified here");
100 void emitHandlerDataLocNotes() const {
101 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
102 HE = HandlerDataLocs.end(); HI != HE; ++HI)
103 Parser.Note(*HI, ".handlerdata was specified here");
105 void emitPersonalityLocNotes() const {
106 for (Locs::const_iterator PI = PersonalityLocs.begin(),
107 PE = PersonalityLocs.end(),
108 PII = PersonalityIndexLocs.begin(),
109 PIE = PersonalityIndexLocs.end();
110 PI != PE || PII != PIE;) {
111 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
112 Parser.Note(*PI++, ".personality was specified here");
113 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
114 Parser.Note(*PII++, ".personalityindex was specified here");
116 llvm_unreachable(".personality and .personalityindex cannot be "
117 "at the same location");
122 FnStartLocs = Locs();
123 CantUnwindLocs = Locs();
124 PersonalityLocs = Locs();
125 HandlerDataLocs = Locs();
126 PersonalityIndexLocs = Locs();
131 class ARMAsmParser : public MCTargetAsmParser {
132 MCSubtargetInfo &STI;
134 const MCInstrInfo &MII;
135 const MCRegisterInfo *MRI;
138 ARMTargetStreamer &getTargetStreamer() {
139 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
140 return static_cast<ARMTargetStreamer &>(TS);
143 // Map of register aliases registers via the .req directive.
144 StringMap<unsigned> RegisterReqs;
146 bool NextSymbolIsThumb;
149 ARMCC::CondCodes Cond; // Condition for IT block.
150 unsigned Mask:4; // Condition mask for instructions.
151 // Starting at first 1 (from lsb).
152 // '1' condition as indicated in IT.
153 // '0' inverse of condition (else).
154 // Count of instructions in IT block is
155 // 4 - trailingzeroes(mask)
157 bool FirstCond; // Explicit flag for when we're parsing the
158 // First instruction in the IT block. It's
159 // implied in the mask, so needs special
162 unsigned CurPosition; // Current position in parsing of IT
163 // block. In range [0,3]. Initialized
164 // according to count of instructions in block.
165 // ~0U if no active IT block.
167 bool inITBlock() { return ITState.CurPosition != ~0U;}
168 void forwardITPosition() {
169 if (!inITBlock()) return;
170 // Move to the next instruction in the IT block, if there is one. If not,
171 // mark the block as done.
172 unsigned TZ = countTrailingZeros(ITState.Mask);
173 if (++ITState.CurPosition == 5 - TZ)
174 ITState.CurPosition = ~0U; // Done with the IT block after this.
178 MCAsmParser &getParser() const { return Parser; }
179 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
181 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
182 return Parser.Note(L, Msg, Ranges);
184 bool Warning(SMLoc L, const Twine &Msg,
185 ArrayRef<SMRange> Ranges = None) {
186 return Parser.Warning(L, Msg, Ranges);
188 bool Error(SMLoc L, const Twine &Msg,
189 ArrayRef<SMRange> Ranges = None) {
190 return Parser.Error(L, Msg, Ranges);
193 int tryParseRegister();
194 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
195 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
196 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
197 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
198 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
199 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
200 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
201 unsigned &ShiftAmount);
202 bool parseDirectiveWord(unsigned Size, SMLoc L);
203 bool parseDirectiveThumb(SMLoc L);
204 bool parseDirectiveARM(SMLoc L);
205 bool parseDirectiveThumbFunc(SMLoc L);
206 bool parseDirectiveCode(SMLoc L);
207 bool parseDirectiveSyntax(SMLoc L);
208 bool parseDirectiveReq(StringRef Name, SMLoc L);
209 bool parseDirectiveUnreq(SMLoc L);
210 bool parseDirectiveArch(SMLoc L);
211 bool parseDirectiveEabiAttr(SMLoc L);
212 bool parseDirectiveCPU(SMLoc L);
213 bool parseDirectiveFPU(SMLoc L);
214 bool parseDirectiveFnStart(SMLoc L);
215 bool parseDirectiveFnEnd(SMLoc L);
216 bool parseDirectiveCantUnwind(SMLoc L);
217 bool parseDirectivePersonality(SMLoc L);
218 bool parseDirectiveHandlerData(SMLoc L);
219 bool parseDirectiveSetFP(SMLoc L);
220 bool parseDirectivePad(SMLoc L);
221 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
222 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
223 bool parseDirectiveLtorg(SMLoc L);
224 bool parseDirectiveEven(SMLoc L);
225 bool parseDirectivePersonalityIndex(SMLoc L);
226 bool parseDirectiveUnwindRaw(SMLoc L);
227 bool parseDirectiveTLSDescSeq(SMLoc L);
228 bool parseDirectiveMovSP(SMLoc L);
229 bool parseDirectiveObjectArch(SMLoc L);
231 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
232 bool &CarrySetting, unsigned &ProcessorIMod,
234 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
235 bool &CanAcceptCarrySet,
236 bool &CanAcceptPredicationCode);
238 bool isThumb() const {
239 // FIXME: Can tablegen auto-generate this?
240 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
242 bool isThumbOne() const {
243 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
245 bool isThumbTwo() const {
246 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
248 bool hasThumb() const {
249 return STI.getFeatureBits() & ARM::HasV4TOps;
251 bool hasV6Ops() const {
252 return STI.getFeatureBits() & ARM::HasV6Ops;
254 bool hasV6MOps() const {
255 return STI.getFeatureBits() & ARM::HasV6MOps;
257 bool hasV7Ops() const {
258 return STI.getFeatureBits() & ARM::HasV7Ops;
260 bool hasV8Ops() const {
261 return STI.getFeatureBits() & ARM::HasV8Ops;
263 bool hasARM() const {
264 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
268 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
269 setAvailableFeatures(FB);
271 bool isMClass() const {
272 return STI.getFeatureBits() & ARM::FeatureMClass;
275 /// @name Auto-generated Match Functions
278 #define GET_ASSEMBLER_HEADER
279 #include "ARMGenAsmMatcher.inc"
283 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
284 OperandMatchResultTy parseCoprocNumOperand(
285 SmallVectorImpl<MCParsedAsmOperand*>&);
286 OperandMatchResultTy parseCoprocRegOperand(
287 SmallVectorImpl<MCParsedAsmOperand*>&);
288 OperandMatchResultTy parseCoprocOptionOperand(
289 SmallVectorImpl<MCParsedAsmOperand*>&);
290 OperandMatchResultTy parseMemBarrierOptOperand(
291 SmallVectorImpl<MCParsedAsmOperand*>&);
292 OperandMatchResultTy parseInstSyncBarrierOptOperand(
293 SmallVectorImpl<MCParsedAsmOperand*>&);
294 OperandMatchResultTy parseProcIFlagsOperand(
295 SmallVectorImpl<MCParsedAsmOperand*>&);
296 OperandMatchResultTy parseMSRMaskOperand(
297 SmallVectorImpl<MCParsedAsmOperand*>&);
298 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
299 StringRef Op, int Low, int High);
300 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
301 return parsePKHImm(O, "lsl", 0, 31);
303 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
304 return parsePKHImm(O, "asr", 1, 32);
306 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
307 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
308 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
309 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
310 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
311 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
312 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
313 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
314 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
317 // Asm Match Converter Methods
318 void cvtThumbMultiply(MCInst &Inst,
319 const SmallVectorImpl<MCParsedAsmOperand*> &);
320 void cvtThumbBranches(MCInst &Inst,
321 const SmallVectorImpl<MCParsedAsmOperand*> &);
323 bool validateInstruction(MCInst &Inst,
324 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
325 bool processInstruction(MCInst &Inst,
326 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
327 bool shouldOmitCCOutOperand(StringRef Mnemonic,
328 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
329 bool shouldOmitPredicateOperand(StringRef Mnemonic,
330 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
332 enum ARMMatchResultTy {
333 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
334 Match_RequiresNotITBlock,
336 Match_RequiresThumb2,
337 #define GET_OPERAND_DIAGNOSTIC_TYPES
338 #include "ARMGenAsmMatcher.inc"
342 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
343 const MCInstrInfo &MII)
344 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
345 MCAsmParserExtension::Initialize(_Parser);
347 // Cache the MCRegisterInfo.
348 MRI = getContext().getRegisterInfo();
350 // Initialize the set of available features.
351 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
353 // Not in an ITBlock to start with.
354 ITState.CurPosition = ~0U;
356 NextSymbolIsThumb = false;
359 // Implementation of the MCTargetAsmParser interface:
360 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
361 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
363 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
364 bool ParseDirective(AsmToken DirectiveID);
366 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
367 unsigned checkTargetMatchPredicate(MCInst &Inst);
369 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
370 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
371 MCStreamer &Out, unsigned &ErrorInfo,
372 bool MatchingInlineAsm);
373 void onLabelParsed(MCSymbol *Symbol);
375 } // end anonymous namespace
379 /// ARMOperand - Instances of this class represent a parsed ARM machine
381 class ARMOperand : public MCParsedAsmOperand {
391 k_InstSyncBarrierOpt,
402 k_VectorListAllLanes,
408 k_BitfieldDescriptor,
412 SMLoc StartLoc, EndLoc;
413 SmallVector<unsigned, 8> Registers;
416 ARMCC::CondCodes Val;
423 struct CoprocOptionOp {
436 ARM_ISB::InstSyncBOpt Val;
440 ARM_PROC::IFlags Val;
456 // A vector register list is a sequential list of 1 to 4 registers.
457 struct VectorListOp {
464 struct VectorIndexOp {
472 /// Combined record for all forms of ARM address expressions.
475 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
477 const MCConstantExpr *OffsetImm; // Offset immediate value
478 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
479 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
480 unsigned ShiftImm; // shift for OffsetReg.
481 unsigned Alignment; // 0 = no alignment specified
482 // n = alignment in bytes (2, 4, 8, 16, or 32)
483 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
486 struct PostIdxRegOp {
489 ARM_AM::ShiftOpc ShiftTy;
493 struct ShifterImmOp {
498 struct RegShiftedRegOp {
499 ARM_AM::ShiftOpc ShiftTy;
505 struct RegShiftedImmOp {
506 ARM_AM::ShiftOpc ShiftTy;
523 struct CoprocOptionOp CoprocOption;
524 struct MBOptOp MBOpt;
525 struct ISBOptOp ISBOpt;
526 struct ITMaskOp ITMask;
527 struct IFlagsOp IFlags;
528 struct MMaskOp MMask;
531 struct VectorListOp VectorList;
532 struct VectorIndexOp VectorIndex;
534 struct MemoryOp Memory;
535 struct PostIdxRegOp PostIdxReg;
536 struct ShifterImmOp ShifterImm;
537 struct RegShiftedRegOp RegShiftedReg;
538 struct RegShiftedImmOp RegShiftedImm;
539 struct RotImmOp RotImm;
540 struct BitfieldOp Bitfield;
543 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
545 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
547 StartLoc = o.StartLoc;
564 case k_DPRRegisterList:
565 case k_SPRRegisterList:
566 Registers = o.Registers;
569 case k_VectorListAllLanes:
570 case k_VectorListIndexed:
571 VectorList = o.VectorList;
578 CoprocOption = o.CoprocOption;
583 case k_MemBarrierOpt:
586 case k_InstSyncBarrierOpt:
591 case k_PostIndexRegister:
592 PostIdxReg = o.PostIdxReg;
600 case k_ShifterImmediate:
601 ShifterImm = o.ShifterImm;
603 case k_ShiftedRegister:
604 RegShiftedReg = o.RegShiftedReg;
606 case k_ShiftedImmediate:
607 RegShiftedImm = o.RegShiftedImm;
609 case k_RotateImmediate:
612 case k_BitfieldDescriptor:
613 Bitfield = o.Bitfield;
616 VectorIndex = o.VectorIndex;
621 /// getStartLoc - Get the location of the first token of this operand.
622 SMLoc getStartLoc() const { return StartLoc; }
623 /// getEndLoc - Get the location of the last token of this operand.
624 SMLoc getEndLoc() const { return EndLoc; }
625 /// getLocRange - Get the range between the first and last token of this
627 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
629 ARMCC::CondCodes getCondCode() const {
630 assert(Kind == k_CondCode && "Invalid access!");
634 unsigned getCoproc() const {
635 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
639 StringRef getToken() const {
640 assert(Kind == k_Token && "Invalid access!");
641 return StringRef(Tok.Data, Tok.Length);
644 unsigned getReg() const {
645 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
649 const SmallVectorImpl<unsigned> &getRegList() const {
650 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
651 Kind == k_SPRRegisterList) && "Invalid access!");
655 const MCExpr *getImm() const {
656 assert(isImm() && "Invalid access!");
660 unsigned getVectorIndex() const {
661 assert(Kind == k_VectorIndex && "Invalid access!");
662 return VectorIndex.Val;
665 ARM_MB::MemBOpt getMemBarrierOpt() const {
666 assert(Kind == k_MemBarrierOpt && "Invalid access!");
670 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
671 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
675 ARM_PROC::IFlags getProcIFlags() const {
676 assert(Kind == k_ProcIFlags && "Invalid access!");
680 unsigned getMSRMask() const {
681 assert(Kind == k_MSRMask && "Invalid access!");
685 bool isCoprocNum() const { return Kind == k_CoprocNum; }
686 bool isCoprocReg() const { return Kind == k_CoprocReg; }
687 bool isCoprocOption() const { return Kind == k_CoprocOption; }
688 bool isCondCode() const { return Kind == k_CondCode; }
689 bool isCCOut() const { return Kind == k_CCOut; }
690 bool isITMask() const { return Kind == k_ITCondMask; }
691 bool isITCondCode() const { return Kind == k_CondCode; }
692 bool isImm() const { return Kind == k_Immediate; }
693 // checks whether this operand is an unsigned offset which fits is a field
694 // of specified width and scaled by a specific number of bits
695 template<unsigned width, unsigned scale>
696 bool isUnsignedOffset() const {
697 if (!isImm()) return false;
698 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
699 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
700 int64_t Val = CE->getValue();
701 int64_t Align = 1LL << scale;
702 int64_t Max = Align * ((1LL << width) - 1);
703 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
707 // checks whether this operand is an signed offset which fits is a field
708 // of specified width and scaled by a specific number of bits
709 template<unsigned width, unsigned scale>
710 bool isSignedOffset() const {
711 if (!isImm()) return false;
712 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
713 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
714 int64_t Val = CE->getValue();
715 int64_t Align = 1LL << scale;
716 int64_t Max = Align * ((1LL << (width-1)) - 1);
717 int64_t Min = -Align * (1LL << (width-1));
718 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
723 // checks whether this operand is a memory operand computed as an offset
724 // applied to PC. the offset may have 8 bits of magnitude and is represented
725 // with two bits of shift. textually it may be either [pc, #imm], #imm or
726 // relocable expression...
727 bool isThumbMemPC() const {
730 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
731 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
732 if (!CE) return false;
733 Val = CE->getValue();
736 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
737 if(Memory.BaseRegNum != ARM::PC) return false;
738 Val = Memory.OffsetImm->getValue();
741 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
743 bool isFPImm() const {
744 if (!isImm()) return false;
745 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
746 if (!CE) return false;
747 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
750 bool isFBits16() const {
751 if (!isImm()) return false;
752 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
753 if (!CE) return false;
754 int64_t Value = CE->getValue();
755 return Value >= 0 && Value <= 16;
757 bool isFBits32() const {
758 if (!isImm()) return false;
759 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
760 if (!CE) return false;
761 int64_t Value = CE->getValue();
762 return Value >= 1 && Value <= 32;
764 bool isImm8s4() const {
765 if (!isImm()) return false;
766 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
767 if (!CE) return false;
768 int64_t Value = CE->getValue();
769 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
771 bool isImm0_1020s4() const {
772 if (!isImm()) return false;
773 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
774 if (!CE) return false;
775 int64_t Value = CE->getValue();
776 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
778 bool isImm0_508s4() const {
779 if (!isImm()) return false;
780 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
781 if (!CE) return false;
782 int64_t Value = CE->getValue();
783 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
785 bool isImm0_508s4Neg() const {
786 if (!isImm()) return false;
787 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
788 if (!CE) return false;
789 int64_t Value = -CE->getValue();
790 // explicitly exclude zero. we want that to use the normal 0_508 version.
791 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
793 bool isImm0_239() const {
794 if (!isImm()) return false;
795 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
796 if (!CE) return false;
797 int64_t Value = CE->getValue();
798 return Value >= 0 && Value < 240;
800 bool isImm0_255() const {
801 if (!isImm()) return false;
802 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
803 if (!CE) return false;
804 int64_t Value = CE->getValue();
805 return Value >= 0 && Value < 256;
807 bool isImm0_4095() const {
808 if (!isImm()) return false;
809 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
810 if (!CE) return false;
811 int64_t Value = CE->getValue();
812 return Value >= 0 && Value < 4096;
814 bool isImm0_4095Neg() const {
815 if (!isImm()) return false;
816 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
817 if (!CE) return false;
818 int64_t Value = -CE->getValue();
819 return Value > 0 && Value < 4096;
821 bool isImm0_1() const {
822 if (!isImm()) return false;
823 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
824 if (!CE) return false;
825 int64_t Value = CE->getValue();
826 return Value >= 0 && Value < 2;
828 bool isImm0_3() const {
829 if (!isImm()) return false;
830 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
831 if (!CE) return false;
832 int64_t Value = CE->getValue();
833 return Value >= 0 && Value < 4;
835 bool isImm0_7() const {
836 if (!isImm()) return false;
837 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
838 if (!CE) return false;
839 int64_t Value = CE->getValue();
840 return Value >= 0 && Value < 8;
842 bool isImm0_15() const {
843 if (!isImm()) return false;
844 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
845 if (!CE) return false;
846 int64_t Value = CE->getValue();
847 return Value >= 0 && Value < 16;
849 bool isImm0_31() const {
850 if (!isImm()) return false;
851 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
852 if (!CE) return false;
853 int64_t Value = CE->getValue();
854 return Value >= 0 && Value < 32;
856 bool isImm0_63() const {
857 if (!isImm()) return false;
858 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
859 if (!CE) return false;
860 int64_t Value = CE->getValue();
861 return Value >= 0 && Value < 64;
863 bool isImm8() const {
864 if (!isImm()) return false;
865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
866 if (!CE) return false;
867 int64_t Value = CE->getValue();
870 bool isImm16() const {
871 if (!isImm()) return false;
872 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
873 if (!CE) return false;
874 int64_t Value = CE->getValue();
877 bool isImm32() const {
878 if (!isImm()) return false;
879 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
880 if (!CE) return false;
881 int64_t Value = CE->getValue();
884 bool isShrImm8() const {
885 if (!isImm()) return false;
886 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
887 if (!CE) return false;
888 int64_t Value = CE->getValue();
889 return Value > 0 && Value <= 8;
891 bool isShrImm16() const {
892 if (!isImm()) return false;
893 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
894 if (!CE) return false;
895 int64_t Value = CE->getValue();
896 return Value > 0 && Value <= 16;
898 bool isShrImm32() const {
899 if (!isImm()) return false;
900 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
901 if (!CE) return false;
902 int64_t Value = CE->getValue();
903 return Value > 0 && Value <= 32;
905 bool isShrImm64() const {
906 if (!isImm()) return false;
907 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
908 if (!CE) return false;
909 int64_t Value = CE->getValue();
910 return Value > 0 && Value <= 64;
912 bool isImm1_7() const {
913 if (!isImm()) return false;
914 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
915 if (!CE) return false;
916 int64_t Value = CE->getValue();
917 return Value > 0 && Value < 8;
919 bool isImm1_15() const {
920 if (!isImm()) return false;
921 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
922 if (!CE) return false;
923 int64_t Value = CE->getValue();
924 return Value > 0 && Value < 16;
926 bool isImm1_31() const {
927 if (!isImm()) return false;
928 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
929 if (!CE) return false;
930 int64_t Value = CE->getValue();
931 return Value > 0 && Value < 32;
933 bool isImm1_16() const {
934 if (!isImm()) return false;
935 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
936 if (!CE) return false;
937 int64_t Value = CE->getValue();
938 return Value > 0 && Value < 17;
940 bool isImm1_32() const {
941 if (!isImm()) return false;
942 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
943 if (!CE) return false;
944 int64_t Value = CE->getValue();
945 return Value > 0 && Value < 33;
947 bool isImm0_32() const {
948 if (!isImm()) return false;
949 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
950 if (!CE) return false;
951 int64_t Value = CE->getValue();
952 return Value >= 0 && Value < 33;
954 bool isImm0_65535() const {
955 if (!isImm()) return false;
956 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
957 if (!CE) return false;
958 int64_t Value = CE->getValue();
959 return Value >= 0 && Value < 65536;
961 bool isImm256_65535Expr() const {
962 if (!isImm()) return false;
963 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
964 // If it's not a constant expression, it'll generate a fixup and be
966 if (!CE) return true;
967 int64_t Value = CE->getValue();
968 return Value >= 256 && Value < 65536;
970 bool isImm0_65535Expr() const {
971 if (!isImm()) return false;
972 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
973 // If it's not a constant expression, it'll generate a fixup and be
975 if (!CE) return true;
976 int64_t Value = CE->getValue();
977 return Value >= 0 && Value < 65536;
979 bool isImm24bit() const {
980 if (!isImm()) return false;
981 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
982 if (!CE) return false;
983 int64_t Value = CE->getValue();
984 return Value >= 0 && Value <= 0xffffff;
986 bool isImmThumbSR() const {
987 if (!isImm()) return false;
988 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
989 if (!CE) return false;
990 int64_t Value = CE->getValue();
991 return Value > 0 && Value < 33;
993 bool isPKHLSLImm() const {
994 if (!isImm()) return false;
995 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
996 if (!CE) return false;
997 int64_t Value = CE->getValue();
998 return Value >= 0 && Value < 32;
1000 bool isPKHASRImm() const {
1001 if (!isImm()) return false;
1002 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1003 if (!CE) return false;
1004 int64_t Value = CE->getValue();
1005 return Value > 0 && Value <= 32;
1007 bool isAdrLabel() const {
1008 // If we have an immediate that's not a constant, treat it as a label
1009 // reference needing a fixup. If it is a constant, but it can't fit
1010 // into shift immediate encoding, we reject it.
1011 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1012 else return (isARMSOImm() || isARMSOImmNeg());
1014 bool isARMSOImm() const {
1015 if (!isImm()) return false;
1016 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1017 if (!CE) return false;
1018 int64_t Value = CE->getValue();
1019 return ARM_AM::getSOImmVal(Value) != -1;
1021 bool isARMSOImmNot() const {
1022 if (!isImm()) return false;
1023 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1024 if (!CE) return false;
1025 int64_t Value = CE->getValue();
1026 return ARM_AM::getSOImmVal(~Value) != -1;
1028 bool isARMSOImmNeg() const {
1029 if (!isImm()) return false;
1030 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1031 if (!CE) return false;
1032 int64_t Value = CE->getValue();
1033 // Only use this when not representable as a plain so_imm.
1034 return ARM_AM::getSOImmVal(Value) == -1 &&
1035 ARM_AM::getSOImmVal(-Value) != -1;
1037 bool isT2SOImm() const {
1038 if (!isImm()) return false;
1039 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1040 if (!CE) return false;
1041 int64_t Value = CE->getValue();
1042 return ARM_AM::getT2SOImmVal(Value) != -1;
1044 bool isT2SOImmNot() const {
1045 if (!isImm()) return false;
1046 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1047 if (!CE) return false;
1048 int64_t Value = CE->getValue();
1049 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1050 ARM_AM::getT2SOImmVal(~Value) != -1;
1052 bool isT2SOImmNeg() const {
1053 if (!isImm()) return false;
1054 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1055 if (!CE) return false;
1056 int64_t Value = CE->getValue();
1057 // Only use this when not representable as a plain so_imm.
1058 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1059 ARM_AM::getT2SOImmVal(-Value) != -1;
1061 bool isSetEndImm() const {
1062 if (!isImm()) return false;
1063 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1064 if (!CE) return false;
1065 int64_t Value = CE->getValue();
1066 return Value == 1 || Value == 0;
1068 bool isReg() const { return Kind == k_Register; }
1069 bool isRegList() const { return Kind == k_RegisterList; }
1070 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1071 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1072 bool isToken() const { return Kind == k_Token; }
1073 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1074 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1075 bool isMem() const { return Kind == k_Memory; }
1076 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1077 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1078 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1079 bool isRotImm() const { return Kind == k_RotateImmediate; }
1080 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1081 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1082 bool isPostIdxReg() const {
1083 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1085 bool isMemNoOffset(bool alignOK = false) const {
1088 // No offset of any kind.
1089 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
1090 (alignOK || Memory.Alignment == 0);
1092 bool isMemPCRelImm12() const {
1093 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1095 // Base register must be PC.
1096 if (Memory.BaseRegNum != ARM::PC)
1098 // Immediate offset in range [-4095, 4095].
1099 if (!Memory.OffsetImm) return true;
1100 int64_t Val = Memory.OffsetImm->getValue();
1101 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1103 bool isAlignedMemory() const {
1104 return isMemNoOffset(true);
1106 bool isAddrMode2() const {
1107 if (!isMem() || Memory.Alignment != 0) return false;
1108 // Check for register offset.
1109 if (Memory.OffsetRegNum) return true;
1110 // Immediate offset in range [-4095, 4095].
1111 if (!Memory.OffsetImm) return true;
1112 int64_t Val = Memory.OffsetImm->getValue();
1113 return Val > -4096 && Val < 4096;
1115 bool isAM2OffsetImm() const {
1116 if (!isImm()) return false;
1117 // Immediate offset in range [-4095, 4095].
1118 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1119 if (!CE) return false;
1120 int64_t Val = CE->getValue();
1121 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1123 bool isAddrMode3() const {
1124 // If we have an immediate that's not a constant, treat it as a label
1125 // reference needing a fixup. If it is a constant, it's something else
1126 // and we reject it.
1127 if (isImm() && !isa<MCConstantExpr>(getImm()))
1129 if (!isMem() || Memory.Alignment != 0) return false;
1130 // No shifts are legal for AM3.
1131 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1132 // Check for register offset.
1133 if (Memory.OffsetRegNum) return true;
1134 // Immediate offset in range [-255, 255].
1135 if (!Memory.OffsetImm) return true;
1136 int64_t Val = Memory.OffsetImm->getValue();
1137 // The #-0 offset is encoded as INT32_MIN, and we have to check
1139 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1141 bool isAM3Offset() const {
1142 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1144 if (Kind == k_PostIndexRegister)
1145 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1146 // Immediate offset in range [-255, 255].
1147 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1148 if (!CE) return false;
1149 int64_t Val = CE->getValue();
1150 // Special case, #-0 is INT32_MIN.
1151 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1153 bool isAddrMode5() const {
1154 // If we have an immediate that's not a constant, treat it as a label
1155 // reference needing a fixup. If it is a constant, it's something else
1156 // and we reject it.
1157 if (isImm() && !isa<MCConstantExpr>(getImm()))
1159 if (!isMem() || Memory.Alignment != 0) return false;
1160 // Check for register offset.
1161 if (Memory.OffsetRegNum) return false;
1162 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1163 if (!Memory.OffsetImm) return true;
1164 int64_t Val = Memory.OffsetImm->getValue();
1165 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1168 bool isMemTBB() const {
1169 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1170 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1174 bool isMemTBH() const {
1175 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1176 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1177 Memory.Alignment != 0 )
1181 bool isMemRegOffset() const {
1182 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1186 bool isT2MemRegOffset() const {
1187 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1188 Memory.Alignment != 0)
1190 // Only lsl #{0, 1, 2, 3} allowed.
1191 if (Memory.ShiftType == ARM_AM::no_shift)
1193 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1197 bool isMemThumbRR() const {
1198 // Thumb reg+reg addressing is simple. Just two registers, a base and
1199 // an offset. No shifts, negations or any other complicating factors.
1200 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1201 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1203 return isARMLowRegister(Memory.BaseRegNum) &&
1204 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1206 bool isMemThumbRIs4() const {
1207 if (!isMem() || Memory.OffsetRegNum != 0 ||
1208 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1210 // Immediate offset, multiple of 4 in range [0, 124].
1211 if (!Memory.OffsetImm) return true;
1212 int64_t Val = Memory.OffsetImm->getValue();
1213 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1215 bool isMemThumbRIs2() const {
1216 if (!isMem() || Memory.OffsetRegNum != 0 ||
1217 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1219 // Immediate offset, multiple of 4 in range [0, 62].
1220 if (!Memory.OffsetImm) return true;
1221 int64_t Val = Memory.OffsetImm->getValue();
1222 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1224 bool isMemThumbRIs1() const {
1225 if (!isMem() || Memory.OffsetRegNum != 0 ||
1226 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1228 // Immediate offset in range [0, 31].
1229 if (!Memory.OffsetImm) return true;
1230 int64_t Val = Memory.OffsetImm->getValue();
1231 return Val >= 0 && Val <= 31;
1233 bool isMemThumbSPI() const {
1234 if (!isMem() || Memory.OffsetRegNum != 0 ||
1235 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1237 // Immediate offset, multiple of 4 in range [0, 1020].
1238 if (!Memory.OffsetImm) return true;
1239 int64_t Val = Memory.OffsetImm->getValue();
1240 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1242 bool isMemImm8s4Offset() const {
1243 // If we have an immediate that's not a constant, treat it as a label
1244 // reference needing a fixup. If it is a constant, it's something else
1245 // and we reject it.
1246 if (isImm() && !isa<MCConstantExpr>(getImm()))
1248 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1250 // Immediate offset a multiple of 4 in range [-1020, 1020].
1251 if (!Memory.OffsetImm) return true;
1252 int64_t Val = Memory.OffsetImm->getValue();
1253 // Special case, #-0 is INT32_MIN.
1254 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1256 bool isMemImm0_1020s4Offset() const {
1257 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1259 // Immediate offset a multiple of 4 in range [0, 1020].
1260 if (!Memory.OffsetImm) return true;
1261 int64_t Val = Memory.OffsetImm->getValue();
1262 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1264 bool isMemImm8Offset() const {
1265 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1267 // Base reg of PC isn't allowed for these encodings.
1268 if (Memory.BaseRegNum == ARM::PC) return false;
1269 // Immediate offset in range [-255, 255].
1270 if (!Memory.OffsetImm) return true;
1271 int64_t Val = Memory.OffsetImm->getValue();
1272 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1274 bool isMemPosImm8Offset() const {
1275 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1277 // Immediate offset in range [0, 255].
1278 if (!Memory.OffsetImm) return true;
1279 int64_t Val = Memory.OffsetImm->getValue();
1280 return Val >= 0 && Val < 256;
1282 bool isMemNegImm8Offset() const {
1283 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1285 // Base reg of PC isn't allowed for these encodings.
1286 if (Memory.BaseRegNum == ARM::PC) return false;
1287 // Immediate offset in range [-255, -1].
1288 if (!Memory.OffsetImm) return false;
1289 int64_t Val = Memory.OffsetImm->getValue();
1290 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1292 bool isMemUImm12Offset() const {
1293 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1295 // Immediate offset in range [0, 4095].
1296 if (!Memory.OffsetImm) return true;
1297 int64_t Val = Memory.OffsetImm->getValue();
1298 return (Val >= 0 && Val < 4096);
1300 bool isMemImm12Offset() const {
1301 // If we have an immediate that's not a constant, treat it as a label
1302 // reference needing a fixup. If it is a constant, it's something else
1303 // and we reject it.
1304 if (isImm() && !isa<MCConstantExpr>(getImm()))
1307 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1309 // Immediate offset in range [-4095, 4095].
1310 if (!Memory.OffsetImm) return true;
1311 int64_t Val = Memory.OffsetImm->getValue();
1312 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1314 bool isPostIdxImm8() const {
1315 if (!isImm()) return false;
1316 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1317 if (!CE) return false;
1318 int64_t Val = CE->getValue();
1319 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1321 bool isPostIdxImm8s4() const {
1322 if (!isImm()) return false;
1323 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1324 if (!CE) return false;
1325 int64_t Val = CE->getValue();
1326 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1330 bool isMSRMask() const { return Kind == k_MSRMask; }
1331 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1334 bool isSingleSpacedVectorList() const {
1335 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1337 bool isDoubleSpacedVectorList() const {
1338 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1340 bool isVecListOneD() const {
1341 if (!isSingleSpacedVectorList()) return false;
1342 return VectorList.Count == 1;
1345 bool isVecListDPair() const {
1346 if (!isSingleSpacedVectorList()) return false;
1347 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1348 .contains(VectorList.RegNum));
1351 bool isVecListThreeD() const {
1352 if (!isSingleSpacedVectorList()) return false;
1353 return VectorList.Count == 3;
1356 bool isVecListFourD() const {
1357 if (!isSingleSpacedVectorList()) return false;
1358 return VectorList.Count == 4;
1361 bool isVecListDPairSpaced() const {
1362 if (isSingleSpacedVectorList()) return false;
1363 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1364 .contains(VectorList.RegNum));
1367 bool isVecListThreeQ() const {
1368 if (!isDoubleSpacedVectorList()) return false;
1369 return VectorList.Count == 3;
1372 bool isVecListFourQ() const {
1373 if (!isDoubleSpacedVectorList()) return false;
1374 return VectorList.Count == 4;
1377 bool isSingleSpacedVectorAllLanes() const {
1378 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1380 bool isDoubleSpacedVectorAllLanes() const {
1381 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1383 bool isVecListOneDAllLanes() const {
1384 if (!isSingleSpacedVectorAllLanes()) return false;
1385 return VectorList.Count == 1;
1388 bool isVecListDPairAllLanes() const {
1389 if (!isSingleSpacedVectorAllLanes()) return false;
1390 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1391 .contains(VectorList.RegNum));
1394 bool isVecListDPairSpacedAllLanes() const {
1395 if (!isDoubleSpacedVectorAllLanes()) return false;
1396 return VectorList.Count == 2;
1399 bool isVecListThreeDAllLanes() const {
1400 if (!isSingleSpacedVectorAllLanes()) return false;
1401 return VectorList.Count == 3;
1404 bool isVecListThreeQAllLanes() const {
1405 if (!isDoubleSpacedVectorAllLanes()) return false;
1406 return VectorList.Count == 3;
1409 bool isVecListFourDAllLanes() const {
1410 if (!isSingleSpacedVectorAllLanes()) return false;
1411 return VectorList.Count == 4;
1414 bool isVecListFourQAllLanes() const {
1415 if (!isDoubleSpacedVectorAllLanes()) return false;
1416 return VectorList.Count == 4;
1419 bool isSingleSpacedVectorIndexed() const {
1420 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1422 bool isDoubleSpacedVectorIndexed() const {
1423 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1425 bool isVecListOneDByteIndexed() const {
1426 if (!isSingleSpacedVectorIndexed()) return false;
1427 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1430 bool isVecListOneDHWordIndexed() const {
1431 if (!isSingleSpacedVectorIndexed()) return false;
1432 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1435 bool isVecListOneDWordIndexed() const {
1436 if (!isSingleSpacedVectorIndexed()) return false;
1437 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1440 bool isVecListTwoDByteIndexed() const {
1441 if (!isSingleSpacedVectorIndexed()) return false;
1442 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1445 bool isVecListTwoDHWordIndexed() const {
1446 if (!isSingleSpacedVectorIndexed()) return false;
1447 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1450 bool isVecListTwoQWordIndexed() const {
1451 if (!isDoubleSpacedVectorIndexed()) return false;
1452 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1455 bool isVecListTwoQHWordIndexed() const {
1456 if (!isDoubleSpacedVectorIndexed()) return false;
1457 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1460 bool isVecListTwoDWordIndexed() const {
1461 if (!isSingleSpacedVectorIndexed()) return false;
1462 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1465 bool isVecListThreeDByteIndexed() const {
1466 if (!isSingleSpacedVectorIndexed()) return false;
1467 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1470 bool isVecListThreeDHWordIndexed() const {
1471 if (!isSingleSpacedVectorIndexed()) return false;
1472 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1475 bool isVecListThreeQWordIndexed() const {
1476 if (!isDoubleSpacedVectorIndexed()) return false;
1477 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1480 bool isVecListThreeQHWordIndexed() const {
1481 if (!isDoubleSpacedVectorIndexed()) return false;
1482 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1485 bool isVecListThreeDWordIndexed() const {
1486 if (!isSingleSpacedVectorIndexed()) return false;
1487 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1490 bool isVecListFourDByteIndexed() const {
1491 if (!isSingleSpacedVectorIndexed()) return false;
1492 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1495 bool isVecListFourDHWordIndexed() const {
1496 if (!isSingleSpacedVectorIndexed()) return false;
1497 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1500 bool isVecListFourQWordIndexed() const {
1501 if (!isDoubleSpacedVectorIndexed()) return false;
1502 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1505 bool isVecListFourQHWordIndexed() const {
1506 if (!isDoubleSpacedVectorIndexed()) return false;
1507 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1510 bool isVecListFourDWordIndexed() const {
1511 if (!isSingleSpacedVectorIndexed()) return false;
1512 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1515 bool isVectorIndex8() const {
1516 if (Kind != k_VectorIndex) return false;
1517 return VectorIndex.Val < 8;
1519 bool isVectorIndex16() const {
1520 if (Kind != k_VectorIndex) return false;
1521 return VectorIndex.Val < 4;
1523 bool isVectorIndex32() const {
1524 if (Kind != k_VectorIndex) return false;
1525 return VectorIndex.Val < 2;
1528 bool isNEONi8splat() const {
1529 if (!isImm()) return false;
1530 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1531 // Must be a constant.
1532 if (!CE) return false;
1533 int64_t Value = CE->getValue();
1534 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1536 return Value >= 0 && Value < 256;
1539 bool isNEONi16splat() const {
1540 if (!isImm()) return false;
1541 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1542 // Must be a constant.
1543 if (!CE) return false;
1544 int64_t Value = CE->getValue();
1545 // i16 value in the range [0,255] or [0x0100, 0xff00]
1546 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1549 bool isNEONi32splat() const {
1550 if (!isImm()) return false;
1551 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1552 // Must be a constant.
1553 if (!CE) return false;
1554 int64_t Value = CE->getValue();
1555 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1556 return (Value >= 0 && Value < 256) ||
1557 (Value >= 0x0100 && Value <= 0xff00) ||
1558 (Value >= 0x010000 && Value <= 0xff0000) ||
1559 (Value >= 0x01000000 && Value <= 0xff000000);
1562 bool isNEONi32vmov() const {
1563 if (!isImm()) return false;
1564 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1565 // Must be a constant.
1566 if (!CE) return false;
1567 int64_t Value = CE->getValue();
1568 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1569 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1570 return (Value >= 0 && Value < 256) ||
1571 (Value >= 0x0100 && Value <= 0xff00) ||
1572 (Value >= 0x010000 && Value <= 0xff0000) ||
1573 (Value >= 0x01000000 && Value <= 0xff000000) ||
1574 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1575 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1577 bool isNEONi32vmovNeg() const {
1578 if (!isImm()) return false;
1579 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1580 // Must be a constant.
1581 if (!CE) return false;
1582 int64_t Value = ~CE->getValue();
1583 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1584 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1585 return (Value >= 0 && Value < 256) ||
1586 (Value >= 0x0100 && Value <= 0xff00) ||
1587 (Value >= 0x010000 && Value <= 0xff0000) ||
1588 (Value >= 0x01000000 && Value <= 0xff000000) ||
1589 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1590 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1593 bool isNEONi64splat() const {
1594 if (!isImm()) return false;
1595 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1596 // Must be a constant.
1597 if (!CE) return false;
1598 uint64_t Value = CE->getValue();
1599 // i64 value with each byte being either 0 or 0xff.
1600 for (unsigned i = 0; i < 8; ++i)
1601 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1605 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1606 // Add as immediates when possible. Null MCExpr = 0.
1608 Inst.addOperand(MCOperand::CreateImm(0));
1609 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1610 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1612 Inst.addOperand(MCOperand::CreateExpr(Expr));
1615 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1616 assert(N == 2 && "Invalid number of operands!");
1617 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1618 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1619 Inst.addOperand(MCOperand::CreateReg(RegNum));
1622 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1623 assert(N == 1 && "Invalid number of operands!");
1624 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1627 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1628 assert(N == 1 && "Invalid number of operands!");
1629 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1632 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1633 assert(N == 1 && "Invalid number of operands!");
1634 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1637 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1638 assert(N == 1 && "Invalid number of operands!");
1639 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1642 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1643 assert(N == 1 && "Invalid number of operands!");
1644 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1647 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1648 assert(N == 1 && "Invalid number of operands!");
1649 Inst.addOperand(MCOperand::CreateReg(getReg()));
1652 void addRegOperands(MCInst &Inst, unsigned N) const {
1653 assert(N == 1 && "Invalid number of operands!");
1654 Inst.addOperand(MCOperand::CreateReg(getReg()));
1657 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1658 assert(N == 3 && "Invalid number of operands!");
1659 assert(isRegShiftedReg() &&
1660 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1661 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1662 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1663 Inst.addOperand(MCOperand::CreateImm(
1664 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1667 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1668 assert(N == 2 && "Invalid number of operands!");
1669 assert(isRegShiftedImm() &&
1670 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1671 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1672 // Shift of #32 is encoded as 0 where permitted
1673 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1674 Inst.addOperand(MCOperand::CreateImm(
1675 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1678 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1679 assert(N == 1 && "Invalid number of operands!");
1680 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1684 void addRegListOperands(MCInst &Inst, unsigned N) const {
1685 assert(N == 1 && "Invalid number of operands!");
1686 const SmallVectorImpl<unsigned> &RegList = getRegList();
1687 for (SmallVectorImpl<unsigned>::const_iterator
1688 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1689 Inst.addOperand(MCOperand::CreateReg(*I));
1692 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1693 addRegListOperands(Inst, N);
1696 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1697 addRegListOperands(Inst, N);
1700 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1701 assert(N == 1 && "Invalid number of operands!");
1702 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1703 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1706 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1707 assert(N == 1 && "Invalid number of operands!");
1708 // Munge the lsb/width into a bitfield mask.
1709 unsigned lsb = Bitfield.LSB;
1710 unsigned width = Bitfield.Width;
1711 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1712 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1713 (32 - (lsb + width)));
1714 Inst.addOperand(MCOperand::CreateImm(Mask));
1717 void addImmOperands(MCInst &Inst, unsigned N) const {
1718 assert(N == 1 && "Invalid number of operands!");
1719 addExpr(Inst, getImm());
1722 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1723 assert(N == 1 && "Invalid number of operands!");
1724 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1725 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1728 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1729 assert(N == 1 && "Invalid number of operands!");
1730 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1731 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1734 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1735 assert(N == 1 && "Invalid number of operands!");
1736 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1737 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1738 Inst.addOperand(MCOperand::CreateImm(Val));
1741 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1742 assert(N == 1 && "Invalid number of operands!");
1743 // FIXME: We really want to scale the value here, but the LDRD/STRD
1744 // instruction don't encode operands that way yet.
1745 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1746 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1749 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1750 assert(N == 1 && "Invalid number of operands!");
1751 // The immediate is scaled by four in the encoding and is stored
1752 // in the MCInst as such. Lop off the low two bits here.
1753 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1754 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1757 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1758 assert(N == 1 && "Invalid number of operands!");
1759 // The immediate is scaled by four in the encoding and is stored
1760 // in the MCInst as such. Lop off the low two bits here.
1761 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1762 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1765 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1766 assert(N == 1 && "Invalid number of operands!");
1767 // The immediate is scaled by four in the encoding and is stored
1768 // in the MCInst as such. Lop off the low two bits here.
1769 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1770 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1773 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1774 assert(N == 1 && "Invalid number of operands!");
1775 // The constant encodes as the immediate-1, and we store in the instruction
1776 // the bits as encoded, so subtract off one here.
1777 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1778 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1781 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1782 assert(N == 1 && "Invalid number of operands!");
1783 // The constant encodes as the immediate-1, and we store in the instruction
1784 // the bits as encoded, so subtract off one here.
1785 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1786 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1789 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1790 assert(N == 1 && "Invalid number of operands!");
1791 // The constant encodes as the immediate, except for 32, which encodes as
1793 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1794 unsigned Imm = CE->getValue();
1795 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1798 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1799 assert(N == 1 && "Invalid number of operands!");
1800 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1801 // the instruction as well.
1802 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1803 int Val = CE->getValue();
1804 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1807 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1808 assert(N == 1 && "Invalid number of operands!");
1809 // The operand is actually a t2_so_imm, but we have its bitwise
1810 // negation in the assembly source, so twiddle it here.
1811 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1812 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1815 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1816 assert(N == 1 && "Invalid number of operands!");
1817 // The operand is actually a t2_so_imm, but we have its
1818 // negation in the assembly source, so twiddle it here.
1819 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1820 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1823 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1824 assert(N == 1 && "Invalid number of operands!");
1825 // The operand is actually an imm0_4095, but we have its
1826 // negation in the assembly source, so twiddle it here.
1827 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1828 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1831 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1832 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1833 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1837 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1838 assert(SR && "Unknown value type!");
1839 Inst.addOperand(MCOperand::CreateExpr(SR));
1842 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1843 assert(N == 1 && "Invalid number of operands!");
1845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1847 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1851 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1852 assert(SR && "Unknown value type!");
1853 Inst.addOperand(MCOperand::CreateExpr(SR));
1857 assert(isMem() && "Unknown value type!");
1858 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1859 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1862 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1863 assert(N == 1 && "Invalid number of operands!");
1864 // The operand is actually a so_imm, but we have its bitwise
1865 // negation in the assembly source, so twiddle it here.
1866 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1867 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1870 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1871 assert(N == 1 && "Invalid number of operands!");
1872 // The operand is actually a so_imm, but we have its
1873 // negation in the assembly source, so twiddle it here.
1874 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1875 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1878 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1879 assert(N == 1 && "Invalid number of operands!");
1880 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1883 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1884 assert(N == 1 && "Invalid number of operands!");
1885 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1888 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1889 assert(N == 1 && "Invalid number of operands!");
1890 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1893 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1894 assert(N == 1 && "Invalid number of operands!");
1895 int32_t Imm = Memory.OffsetImm->getValue();
1896 Inst.addOperand(MCOperand::CreateImm(Imm));
1899 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1900 assert(N == 1 && "Invalid number of operands!");
1901 assert(isImm() && "Not an immediate!");
1903 // If we have an immediate that's not a constant, treat it as a label
1904 // reference needing a fixup.
1905 if (!isa<MCConstantExpr>(getImm())) {
1906 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1910 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1911 int Val = CE->getValue();
1912 Inst.addOperand(MCOperand::CreateImm(Val));
1915 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1916 assert(N == 2 && "Invalid number of operands!");
1917 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1918 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1921 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1922 assert(N == 3 && "Invalid number of operands!");
1923 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1924 if (!Memory.OffsetRegNum) {
1925 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1926 // Special case for #-0
1927 if (Val == INT32_MIN) Val = 0;
1928 if (Val < 0) Val = -Val;
1929 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1931 // For register offset, we encode the shift type and negation flag
1933 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1934 Memory.ShiftImm, Memory.ShiftType);
1936 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1937 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1938 Inst.addOperand(MCOperand::CreateImm(Val));
1941 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1942 assert(N == 2 && "Invalid number of operands!");
1943 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1944 assert(CE && "non-constant AM2OffsetImm operand!");
1945 int32_t Val = CE->getValue();
1946 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1947 // Special case for #-0
1948 if (Val == INT32_MIN) Val = 0;
1949 if (Val < 0) Val = -Val;
1950 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1951 Inst.addOperand(MCOperand::CreateReg(0));
1952 Inst.addOperand(MCOperand::CreateImm(Val));
1955 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1956 assert(N == 3 && "Invalid number of operands!");
1957 // If we have an immediate that's not a constant, treat it as a label
1958 // reference needing a fixup. If it is a constant, it's something else
1959 // and we reject it.
1961 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1962 Inst.addOperand(MCOperand::CreateReg(0));
1963 Inst.addOperand(MCOperand::CreateImm(0));
1967 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1968 if (!Memory.OffsetRegNum) {
1969 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1970 // Special case for #-0
1971 if (Val == INT32_MIN) Val = 0;
1972 if (Val < 0) Val = -Val;
1973 Val = ARM_AM::getAM3Opc(AddSub, Val);
1975 // For register offset, we encode the shift type and negation flag
1977 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1979 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1980 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1981 Inst.addOperand(MCOperand::CreateImm(Val));
1984 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1985 assert(N == 2 && "Invalid number of operands!");
1986 if (Kind == k_PostIndexRegister) {
1988 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1989 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1990 Inst.addOperand(MCOperand::CreateImm(Val));
1995 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1996 int32_t Val = CE->getValue();
1997 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1998 // Special case for #-0
1999 if (Val == INT32_MIN) Val = 0;
2000 if (Val < 0) Val = -Val;
2001 Val = ARM_AM::getAM3Opc(AddSub, Val);
2002 Inst.addOperand(MCOperand::CreateReg(0));
2003 Inst.addOperand(MCOperand::CreateImm(Val));
2006 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2007 assert(N == 2 && "Invalid number of operands!");
2008 // If we have an immediate that's not a constant, treat it as a label
2009 // reference needing a fixup. If it is a constant, it's something else
2010 // and we reject it.
2012 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2013 Inst.addOperand(MCOperand::CreateImm(0));
2017 // The lower two bits are always zero and as such are not encoded.
2018 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2019 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2020 // Special case for #-0
2021 if (Val == INT32_MIN) Val = 0;
2022 if (Val < 0) Val = -Val;
2023 Val = ARM_AM::getAM5Opc(AddSub, Val);
2024 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2025 Inst.addOperand(MCOperand::CreateImm(Val));
2028 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2029 assert(N == 2 && "Invalid number of operands!");
2030 // If we have an immediate that's not a constant, treat it as a label
2031 // reference needing a fixup. If it is a constant, it's something else
2032 // and we reject it.
2034 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2035 Inst.addOperand(MCOperand::CreateImm(0));
2039 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2040 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2041 Inst.addOperand(MCOperand::CreateImm(Val));
2044 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2045 assert(N == 2 && "Invalid number of operands!");
2046 // The lower two bits are always zero and as such are not encoded.
2047 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2048 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2049 Inst.addOperand(MCOperand::CreateImm(Val));
2052 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2053 assert(N == 2 && "Invalid number of operands!");
2054 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2055 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2056 Inst.addOperand(MCOperand::CreateImm(Val));
2059 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2060 addMemImm8OffsetOperands(Inst, N);
2063 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2064 addMemImm8OffsetOperands(Inst, N);
2067 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2068 assert(N == 2 && "Invalid number of operands!");
2069 // If this is an immediate, it's a label reference.
2071 addExpr(Inst, getImm());
2072 Inst.addOperand(MCOperand::CreateImm(0));
2076 // Otherwise, it's a normal memory reg+offset.
2077 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2078 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2079 Inst.addOperand(MCOperand::CreateImm(Val));
2082 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2083 assert(N == 2 && "Invalid number of operands!");
2084 // If this is an immediate, it's a label reference.
2086 addExpr(Inst, getImm());
2087 Inst.addOperand(MCOperand::CreateImm(0));
2091 // Otherwise, it's a normal memory reg+offset.
2092 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2093 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2094 Inst.addOperand(MCOperand::CreateImm(Val));
2097 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2098 assert(N == 2 && "Invalid number of operands!");
2099 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2100 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2103 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2104 assert(N == 2 && "Invalid number of operands!");
2105 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2106 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2109 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2110 assert(N == 3 && "Invalid number of operands!");
2112 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2113 Memory.ShiftImm, Memory.ShiftType);
2114 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2115 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2116 Inst.addOperand(MCOperand::CreateImm(Val));
2119 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2120 assert(N == 3 && "Invalid number of operands!");
2121 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2122 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2123 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2126 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2127 assert(N == 2 && "Invalid number of operands!");
2128 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2129 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2132 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2133 assert(N == 2 && "Invalid number of operands!");
2134 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2135 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2136 Inst.addOperand(MCOperand::CreateImm(Val));
2139 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2140 assert(N == 2 && "Invalid number of operands!");
2141 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2142 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2143 Inst.addOperand(MCOperand::CreateImm(Val));
2146 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2147 assert(N == 2 && "Invalid number of operands!");
2148 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2149 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2150 Inst.addOperand(MCOperand::CreateImm(Val));
2153 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2154 assert(N == 2 && "Invalid number of operands!");
2155 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2156 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2157 Inst.addOperand(MCOperand::CreateImm(Val));
2160 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2161 assert(N == 1 && "Invalid number of operands!");
2162 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2163 assert(CE && "non-constant post-idx-imm8 operand!");
2164 int Imm = CE->getValue();
2165 bool isAdd = Imm >= 0;
2166 if (Imm == INT32_MIN) Imm = 0;
2167 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2168 Inst.addOperand(MCOperand::CreateImm(Imm));
2171 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2172 assert(N == 1 && "Invalid number of operands!");
2173 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2174 assert(CE && "non-constant post-idx-imm8s4 operand!");
2175 int Imm = CE->getValue();
2176 bool isAdd = Imm >= 0;
2177 if (Imm == INT32_MIN) Imm = 0;
2178 // Immediate is scaled by 4.
2179 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2180 Inst.addOperand(MCOperand::CreateImm(Imm));
2183 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2184 assert(N == 2 && "Invalid number of operands!");
2185 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2186 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2189 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2190 assert(N == 2 && "Invalid number of operands!");
2191 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2192 // The sign, shift type, and shift amount are encoded in a single operand
2193 // using the AM2 encoding helpers.
2194 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2195 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2196 PostIdxReg.ShiftTy);
2197 Inst.addOperand(MCOperand::CreateImm(Imm));
2200 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2201 assert(N == 1 && "Invalid number of operands!");
2202 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2205 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2206 assert(N == 1 && "Invalid number of operands!");
2207 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2210 void addVecListOperands(MCInst &Inst, unsigned N) const {
2211 assert(N == 1 && "Invalid number of operands!");
2212 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2215 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2216 assert(N == 2 && "Invalid number of operands!");
2217 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2218 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2221 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2222 assert(N == 1 && "Invalid number of operands!");
2223 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2226 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2227 assert(N == 1 && "Invalid number of operands!");
2228 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2231 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2232 assert(N == 1 && "Invalid number of operands!");
2233 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2236 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2237 assert(N == 1 && "Invalid number of operands!");
2238 // The immediate encodes the type of constant as well as the value.
2239 // Mask in that this is an i8 splat.
2240 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2241 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2244 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2245 assert(N == 1 && "Invalid number of operands!");
2246 // The immediate encodes the type of constant as well as the value.
2247 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2248 unsigned Value = CE->getValue();
2250 Value = (Value >> 8) | 0xa00;
2253 Inst.addOperand(MCOperand::CreateImm(Value));
2256 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2257 assert(N == 1 && "Invalid number of operands!");
2258 // The immediate encodes the type of constant as well as the value.
2259 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2260 unsigned Value = CE->getValue();
2261 if (Value >= 256 && Value <= 0xff00)
2262 Value = (Value >> 8) | 0x200;
2263 else if (Value > 0xffff && Value <= 0xff0000)
2264 Value = (Value >> 16) | 0x400;
2265 else if (Value > 0xffffff)
2266 Value = (Value >> 24) | 0x600;
2267 Inst.addOperand(MCOperand::CreateImm(Value));
2270 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2271 assert(N == 1 && "Invalid number of operands!");
2272 // The immediate encodes the type of constant as well as the value.
2273 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2274 unsigned Value = CE->getValue();
2275 if (Value >= 256 && Value <= 0xffff)
2276 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2277 else if (Value > 0xffff && Value <= 0xffffff)
2278 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2279 else if (Value > 0xffffff)
2280 Value = (Value >> 24) | 0x600;
2281 Inst.addOperand(MCOperand::CreateImm(Value));
2284 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2285 assert(N == 1 && "Invalid number of operands!");
2286 // The immediate encodes the type of constant as well as the value.
2287 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2288 unsigned Value = ~CE->getValue();
2289 if (Value >= 256 && Value <= 0xffff)
2290 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2291 else if (Value > 0xffff && Value <= 0xffffff)
2292 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2293 else if (Value > 0xffffff)
2294 Value = (Value >> 24) | 0x600;
2295 Inst.addOperand(MCOperand::CreateImm(Value));
2298 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2299 assert(N == 1 && "Invalid number of operands!");
2300 // The immediate encodes the type of constant as well as the value.
2301 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2302 uint64_t Value = CE->getValue();
2304 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2305 Imm |= (Value & 1) << i;
2307 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2310 virtual void print(raw_ostream &OS) const;
2312 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2313 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2314 Op->ITMask.Mask = Mask;
2320 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2321 ARMOperand *Op = new ARMOperand(k_CondCode);
2328 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2329 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2330 Op->Cop.Val = CopVal;
2336 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2337 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2338 Op->Cop.Val = CopVal;
2344 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2345 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2352 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2353 ARMOperand *Op = new ARMOperand(k_CCOut);
2354 Op->Reg.RegNum = RegNum;
2360 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2361 ARMOperand *Op = new ARMOperand(k_Token);
2362 Op->Tok.Data = Str.data();
2363 Op->Tok.Length = Str.size();
2369 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2370 ARMOperand *Op = new ARMOperand(k_Register);
2371 Op->Reg.RegNum = RegNum;
2377 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2382 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2383 Op->RegShiftedReg.ShiftTy = ShTy;
2384 Op->RegShiftedReg.SrcReg = SrcReg;
2385 Op->RegShiftedReg.ShiftReg = ShiftReg;
2386 Op->RegShiftedReg.ShiftImm = ShiftImm;
2392 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2396 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2397 Op->RegShiftedImm.ShiftTy = ShTy;
2398 Op->RegShiftedImm.SrcReg = SrcReg;
2399 Op->RegShiftedImm.ShiftImm = ShiftImm;
2405 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2407 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2408 Op->ShifterImm.isASR = isASR;
2409 Op->ShifterImm.Imm = Imm;
2415 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2416 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2417 Op->RotImm.Imm = Imm;
2423 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2425 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2426 Op->Bitfield.LSB = LSB;
2427 Op->Bitfield.Width = Width;
2434 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2435 SMLoc StartLoc, SMLoc EndLoc) {
2436 assert (Regs.size() > 0 && "RegList contains no registers?");
2437 KindTy Kind = k_RegisterList;
2439 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2440 Kind = k_DPRRegisterList;
2441 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2442 contains(Regs.front().second))
2443 Kind = k_SPRRegisterList;
2445 // Sort based on the register encoding values.
2446 array_pod_sort(Regs.begin(), Regs.end());
2448 ARMOperand *Op = new ARMOperand(Kind);
2449 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2450 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2451 Op->Registers.push_back(I->second);
2452 Op->StartLoc = StartLoc;
2453 Op->EndLoc = EndLoc;
2457 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2458 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2459 ARMOperand *Op = new ARMOperand(k_VectorList);
2460 Op->VectorList.RegNum = RegNum;
2461 Op->VectorList.Count = Count;
2462 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2468 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2469 bool isDoubleSpaced,
2471 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2472 Op->VectorList.RegNum = RegNum;
2473 Op->VectorList.Count = Count;
2474 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2480 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2482 bool isDoubleSpaced,
2484 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2485 Op->VectorList.RegNum = RegNum;
2486 Op->VectorList.Count = Count;
2487 Op->VectorList.LaneIndex = Index;
2488 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2494 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2496 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2497 Op->VectorIndex.Val = Idx;
2503 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2504 ARMOperand *Op = new ARMOperand(k_Immediate);
2511 static ARMOperand *CreateMem(unsigned BaseRegNum,
2512 const MCConstantExpr *OffsetImm,
2513 unsigned OffsetRegNum,
2514 ARM_AM::ShiftOpc ShiftType,
2519 ARMOperand *Op = new ARMOperand(k_Memory);
2520 Op->Memory.BaseRegNum = BaseRegNum;
2521 Op->Memory.OffsetImm = OffsetImm;
2522 Op->Memory.OffsetRegNum = OffsetRegNum;
2523 Op->Memory.ShiftType = ShiftType;
2524 Op->Memory.ShiftImm = ShiftImm;
2525 Op->Memory.Alignment = Alignment;
2526 Op->Memory.isNegative = isNegative;
2532 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2533 ARM_AM::ShiftOpc ShiftTy,
2536 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2537 Op->PostIdxReg.RegNum = RegNum;
2538 Op->PostIdxReg.isAdd = isAdd;
2539 Op->PostIdxReg.ShiftTy = ShiftTy;
2540 Op->PostIdxReg.ShiftImm = ShiftImm;
2546 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2547 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2548 Op->MBOpt.Val = Opt;
2554 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2556 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2557 Op->ISBOpt.Val = Opt;
2563 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2564 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2565 Op->IFlags.Val = IFlags;
2571 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2572 ARMOperand *Op = new ARMOperand(k_MSRMask);
2573 Op->MMask.Val = MMask;
2580 } // end anonymous namespace.
2582 void ARMOperand::print(raw_ostream &OS) const {
2585 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2588 OS << "<ccout " << getReg() << ">";
2590 case k_ITCondMask: {
2591 static const char *const MaskStr[] = {
2592 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2593 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2595 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2596 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2600 OS << "<coprocessor number: " << getCoproc() << ">";
2603 OS << "<coprocessor register: " << getCoproc() << ">";
2605 case k_CoprocOption:
2606 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2609 OS << "<mask: " << getMSRMask() << ">";
2612 getImm()->print(OS);
2614 case k_MemBarrierOpt:
2615 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2617 case k_InstSyncBarrierOpt:
2618 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2622 << " base:" << Memory.BaseRegNum;
2625 case k_PostIndexRegister:
2626 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2627 << PostIdxReg.RegNum;
2628 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2629 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2630 << PostIdxReg.ShiftImm;
2633 case k_ProcIFlags: {
2634 OS << "<ARM_PROC::";
2635 unsigned IFlags = getProcIFlags();
2636 for (int i=2; i >= 0; --i)
2637 if (IFlags & (1 << i))
2638 OS << ARM_PROC::IFlagsToString(1 << i);
2643 OS << "<register " << getReg() << ">";
2645 case k_ShifterImmediate:
2646 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2647 << " #" << ShifterImm.Imm << ">";
2649 case k_ShiftedRegister:
2650 OS << "<so_reg_reg "
2651 << RegShiftedReg.SrcReg << " "
2652 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2653 << " " << RegShiftedReg.ShiftReg << ">";
2655 case k_ShiftedImmediate:
2656 OS << "<so_reg_imm "
2657 << RegShiftedImm.SrcReg << " "
2658 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2659 << " #" << RegShiftedImm.ShiftImm << ">";
2661 case k_RotateImmediate:
2662 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2664 case k_BitfieldDescriptor:
2665 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2666 << ", width: " << Bitfield.Width << ">";
2668 case k_RegisterList:
2669 case k_DPRRegisterList:
2670 case k_SPRRegisterList: {
2671 OS << "<register_list ";
2673 const SmallVectorImpl<unsigned> &RegList = getRegList();
2674 for (SmallVectorImpl<unsigned>::const_iterator
2675 I = RegList.begin(), E = RegList.end(); I != E; ) {
2677 if (++I < E) OS << ", ";
2684 OS << "<vector_list " << VectorList.Count << " * "
2685 << VectorList.RegNum << ">";
2687 case k_VectorListAllLanes:
2688 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2689 << VectorList.RegNum << ">";
2691 case k_VectorListIndexed:
2692 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2693 << VectorList.Count << " * " << VectorList.RegNum << ">";
2696 OS << "'" << getToken() << "'";
2699 OS << "<vectorindex " << getVectorIndex() << ">";
2704 /// @name Auto-generated Match Functions
2707 static unsigned MatchRegisterName(StringRef Name);
2711 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2712 SMLoc &StartLoc, SMLoc &EndLoc) {
2713 StartLoc = Parser.getTok().getLoc();
2714 EndLoc = Parser.getTok().getEndLoc();
2715 RegNo = tryParseRegister();
2717 return (RegNo == (unsigned)-1);
2720 /// Try to parse a register name. The token must be an Identifier when called,
2721 /// and if it is a register name the token is eaten and the register number is
2722 /// returned. Otherwise return -1.
2724 int ARMAsmParser::tryParseRegister() {
2725 const AsmToken &Tok = Parser.getTok();
2726 if (Tok.isNot(AsmToken::Identifier)) return -1;
2728 std::string lowerCase = Tok.getString().lower();
2729 unsigned RegNum = MatchRegisterName(lowerCase);
2731 RegNum = StringSwitch<unsigned>(lowerCase)
2732 .Case("r13", ARM::SP)
2733 .Case("r14", ARM::LR)
2734 .Case("r15", ARM::PC)
2735 .Case("ip", ARM::R12)
2736 // Additional register name aliases for 'gas' compatibility.
2737 .Case("a1", ARM::R0)
2738 .Case("a2", ARM::R1)
2739 .Case("a3", ARM::R2)
2740 .Case("a4", ARM::R3)
2741 .Case("v1", ARM::R4)
2742 .Case("v2", ARM::R5)
2743 .Case("v3", ARM::R6)
2744 .Case("v4", ARM::R7)
2745 .Case("v5", ARM::R8)
2746 .Case("v6", ARM::R9)
2747 .Case("v7", ARM::R10)
2748 .Case("v8", ARM::R11)
2749 .Case("sb", ARM::R9)
2750 .Case("sl", ARM::R10)
2751 .Case("fp", ARM::R11)
2755 // Check for aliases registered via .req. Canonicalize to lower case.
2756 // That's more consistent since register names are case insensitive, and
2757 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2758 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2759 // If no match, return failure.
2760 if (Entry == RegisterReqs.end())
2762 Parser.Lex(); // Eat identifier token.
2763 return Entry->getValue();
2766 Parser.Lex(); // Eat identifier token.
2771 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2772 // If a recoverable error occurs, return 1. If an irrecoverable error
2773 // occurs, return -1. An irrecoverable error is one where tokens have been
2774 // consumed in the process of trying to parse the shifter (i.e., when it is
2775 // indeed a shifter operand, but malformed).
2776 int ARMAsmParser::tryParseShiftRegister(
2777 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2778 SMLoc S = Parser.getTok().getLoc();
2779 const AsmToken &Tok = Parser.getTok();
2780 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2782 std::string lowerCase = Tok.getString().lower();
2783 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2784 .Case("asl", ARM_AM::lsl)
2785 .Case("lsl", ARM_AM::lsl)
2786 .Case("lsr", ARM_AM::lsr)
2787 .Case("asr", ARM_AM::asr)
2788 .Case("ror", ARM_AM::ror)
2789 .Case("rrx", ARM_AM::rrx)
2790 .Default(ARM_AM::no_shift);
2792 if (ShiftTy == ARM_AM::no_shift)
2795 Parser.Lex(); // Eat the operator.
2797 // The source register for the shift has already been added to the
2798 // operand list, so we need to pop it off and combine it into the shifted
2799 // register operand instead.
2800 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2801 if (!PrevOp->isReg())
2802 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2803 int SrcReg = PrevOp->getReg();
2808 if (ShiftTy == ARM_AM::rrx) {
2809 // RRX Doesn't have an explicit shift amount. The encoder expects
2810 // the shift register to be the same as the source register. Seems odd,
2814 // Figure out if this is shifted by a constant or a register (for non-RRX).
2815 if (Parser.getTok().is(AsmToken::Hash) ||
2816 Parser.getTok().is(AsmToken::Dollar)) {
2817 Parser.Lex(); // Eat hash.
2818 SMLoc ImmLoc = Parser.getTok().getLoc();
2819 const MCExpr *ShiftExpr = 0;
2820 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2821 Error(ImmLoc, "invalid immediate shift value");
2824 // The expression must be evaluatable as an immediate.
2825 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2827 Error(ImmLoc, "invalid immediate shift value");
2830 // Range check the immediate.
2831 // lsl, ror: 0 <= imm <= 31
2832 // lsr, asr: 0 <= imm <= 32
2833 Imm = CE->getValue();
2835 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2836 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2837 Error(ImmLoc, "immediate shift value out of range");
2840 // shift by zero is a nop. Always send it through as lsl.
2841 // ('as' compatibility)
2843 ShiftTy = ARM_AM::lsl;
2844 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2845 SMLoc L = Parser.getTok().getLoc();
2846 EndLoc = Parser.getTok().getEndLoc();
2847 ShiftReg = tryParseRegister();
2848 if (ShiftReg == -1) {
2849 Error (L, "expected immediate or register in shift operand");
2853 Error (Parser.getTok().getLoc(),
2854 "expected immediate or register in shift operand");
2859 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2860 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2864 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2871 /// Try to parse a register name. The token must be an Identifier when called.
2872 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2873 /// if there is a "writeback". 'true' if it's not a register.
2875 /// TODO this is likely to change to allow different register types and or to
2876 /// parse for a specific register type.
2878 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2879 const AsmToken &RegTok = Parser.getTok();
2880 int RegNo = tryParseRegister();
2884 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2885 RegTok.getEndLoc()));
2887 const AsmToken &ExclaimTok = Parser.getTok();
2888 if (ExclaimTok.is(AsmToken::Exclaim)) {
2889 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2890 ExclaimTok.getLoc()));
2891 Parser.Lex(); // Eat exclaim token
2895 // Also check for an index operand. This is only legal for vector registers,
2896 // but that'll get caught OK in operand matching, so we don't need to
2897 // explicitly filter everything else out here.
2898 if (Parser.getTok().is(AsmToken::LBrac)) {
2899 SMLoc SIdx = Parser.getTok().getLoc();
2900 Parser.Lex(); // Eat left bracket token.
2902 const MCExpr *ImmVal;
2903 if (getParser().parseExpression(ImmVal))
2905 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2907 return TokError("immediate value expected for vector index");
2909 if (Parser.getTok().isNot(AsmToken::RBrac))
2910 return Error(Parser.getTok().getLoc(), "']' expected");
2912 SMLoc E = Parser.getTok().getEndLoc();
2913 Parser.Lex(); // Eat right bracket token.
2915 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2923 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2924 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2926 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2927 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2929 switch (Name.size()) {
2932 if (Name[0] != CoprocOp)
2948 if (Name[0] != CoprocOp || Name[1] != '1')
2952 // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
2953 case '0': return CoprocOp == 'p'? -1: 10;
2954 case '1': return CoprocOp == 'p'? -1: 11;
2955 case '2': return 12;
2956 case '3': return 13;
2957 case '4': return 14;
2958 case '5': return 15;
2963 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2964 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2965 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2966 SMLoc S = Parser.getTok().getLoc();
2967 const AsmToken &Tok = Parser.getTok();
2968 if (!Tok.is(AsmToken::Identifier))
2969 return MatchOperand_NoMatch;
2970 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2971 .Case("eq", ARMCC::EQ)
2972 .Case("ne", ARMCC::NE)
2973 .Case("hs", ARMCC::HS)
2974 .Case("cs", ARMCC::HS)
2975 .Case("lo", ARMCC::LO)
2976 .Case("cc", ARMCC::LO)
2977 .Case("mi", ARMCC::MI)
2978 .Case("pl", ARMCC::PL)
2979 .Case("vs", ARMCC::VS)
2980 .Case("vc", ARMCC::VC)
2981 .Case("hi", ARMCC::HI)
2982 .Case("ls", ARMCC::LS)
2983 .Case("ge", ARMCC::GE)
2984 .Case("lt", ARMCC::LT)
2985 .Case("gt", ARMCC::GT)
2986 .Case("le", ARMCC::LE)
2987 .Case("al", ARMCC::AL)
2990 return MatchOperand_NoMatch;
2991 Parser.Lex(); // Eat the token.
2993 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2995 return MatchOperand_Success;
2998 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2999 /// token must be an Identifier when called, and if it is a coprocessor
3000 /// number, the token is eaten and the operand is added to the operand list.
3001 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3002 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3003 SMLoc S = Parser.getTok().getLoc();
3004 const AsmToken &Tok = Parser.getTok();
3005 if (Tok.isNot(AsmToken::Identifier))
3006 return MatchOperand_NoMatch;
3008 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3010 return MatchOperand_NoMatch;
3012 Parser.Lex(); // Eat identifier token.
3013 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3014 return MatchOperand_Success;
3017 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3018 /// token must be an Identifier when called, and if it is a coprocessor
3019 /// number, the token is eaten and the operand is added to the operand list.
3020 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3021 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3022 SMLoc S = Parser.getTok().getLoc();
3023 const AsmToken &Tok = Parser.getTok();
3024 if (Tok.isNot(AsmToken::Identifier))
3025 return MatchOperand_NoMatch;
3027 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3029 return MatchOperand_NoMatch;
3031 Parser.Lex(); // Eat identifier token.
3032 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3033 return MatchOperand_Success;
3036 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3037 /// coproc_option : '{' imm0_255 '}'
3038 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3039 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3040 SMLoc S = Parser.getTok().getLoc();
3042 // If this isn't a '{', this isn't a coprocessor immediate operand.
3043 if (Parser.getTok().isNot(AsmToken::LCurly))
3044 return MatchOperand_NoMatch;
3045 Parser.Lex(); // Eat the '{'
3048 SMLoc Loc = Parser.getTok().getLoc();
3049 if (getParser().parseExpression(Expr)) {
3050 Error(Loc, "illegal expression");
3051 return MatchOperand_ParseFail;
3053 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3054 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3055 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3056 return MatchOperand_ParseFail;
3058 int Val = CE->getValue();
3060 // Check for and consume the closing '}'
3061 if (Parser.getTok().isNot(AsmToken::RCurly))
3062 return MatchOperand_ParseFail;
3063 SMLoc E = Parser.getTok().getEndLoc();
3064 Parser.Lex(); // Eat the '}'
3066 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3067 return MatchOperand_Success;
3070 // For register list parsing, we need to map from raw GPR register numbering
3071 // to the enumeration values. The enumeration values aren't sorted by
3072 // register number due to our using "sp", "lr" and "pc" as canonical names.
3073 static unsigned getNextRegister(unsigned Reg) {
3074 // If this is a GPR, we need to do it manually, otherwise we can rely
3075 // on the sort ordering of the enumeration since the other reg-classes
3077 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3080 default: llvm_unreachable("Invalid GPR number!");
3081 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3082 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3083 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3084 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3085 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3086 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3087 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3088 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3092 // Return the low-subreg of a given Q register.
3093 static unsigned getDRegFromQReg(unsigned QReg) {
3095 default: llvm_unreachable("expected a Q register!");
3096 case ARM::Q0: return ARM::D0;
3097 case ARM::Q1: return ARM::D2;
3098 case ARM::Q2: return ARM::D4;
3099 case ARM::Q3: return ARM::D6;
3100 case ARM::Q4: return ARM::D8;
3101 case ARM::Q5: return ARM::D10;
3102 case ARM::Q6: return ARM::D12;
3103 case ARM::Q7: return ARM::D14;
3104 case ARM::Q8: return ARM::D16;
3105 case ARM::Q9: return ARM::D18;
3106 case ARM::Q10: return ARM::D20;
3107 case ARM::Q11: return ARM::D22;
3108 case ARM::Q12: return ARM::D24;
3109 case ARM::Q13: return ARM::D26;
3110 case ARM::Q14: return ARM::D28;
3111 case ARM::Q15: return ARM::D30;
3115 /// Parse a register list.
3117 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3118 assert(Parser.getTok().is(AsmToken::LCurly) &&
3119 "Token is not a Left Curly Brace");
3120 SMLoc S = Parser.getTok().getLoc();
3121 Parser.Lex(); // Eat '{' token.
3122 SMLoc RegLoc = Parser.getTok().getLoc();
3124 // Check the first register in the list to see what register class
3125 // this is a list of.
3126 int Reg = tryParseRegister();
3128 return Error(RegLoc, "register expected");
3130 // The reglist instructions have at most 16 registers, so reserve
3131 // space for that many.
3133 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3135 // Allow Q regs and just interpret them as the two D sub-registers.
3136 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3137 Reg = getDRegFromQReg(Reg);
3138 EReg = MRI->getEncodingValue(Reg);
3139 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3142 const MCRegisterClass *RC;
3143 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3144 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3145 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3146 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3147 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3148 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3150 return Error(RegLoc, "invalid register in register list");
3152 // Store the register.
3153 EReg = MRI->getEncodingValue(Reg);
3154 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3156 // This starts immediately after the first register token in the list,
3157 // so we can see either a comma or a minus (range separator) as a legal
3159 while (Parser.getTok().is(AsmToken::Comma) ||
3160 Parser.getTok().is(AsmToken::Minus)) {
3161 if (Parser.getTok().is(AsmToken::Minus)) {
3162 Parser.Lex(); // Eat the minus.
3163 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3164 int EndReg = tryParseRegister();
3166 return Error(AfterMinusLoc, "register expected");
3167 // Allow Q regs and just interpret them as the two D sub-registers.
3168 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3169 EndReg = getDRegFromQReg(EndReg) + 1;
3170 // If the register is the same as the start reg, there's nothing
3174 // The register must be in the same register class as the first.
3175 if (!RC->contains(EndReg))
3176 return Error(AfterMinusLoc, "invalid register in register list");
3177 // Ranges must go from low to high.
3178 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3179 return Error(AfterMinusLoc, "bad range in register list");
3181 // Add all the registers in the range to the register list.
3182 while (Reg != EndReg) {
3183 Reg = getNextRegister(Reg);
3184 EReg = MRI->getEncodingValue(Reg);
3185 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3189 Parser.Lex(); // Eat the comma.
3190 RegLoc = Parser.getTok().getLoc();
3192 const AsmToken RegTok = Parser.getTok();
3193 Reg = tryParseRegister();
3195 return Error(RegLoc, "register expected");
3196 // Allow Q regs and just interpret them as the two D sub-registers.
3197 bool isQReg = false;
3198 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3199 Reg = getDRegFromQReg(Reg);
3202 // The register must be in the same register class as the first.
3203 if (!RC->contains(Reg))
3204 return Error(RegLoc, "invalid register in register list");
3205 // List must be monotonically increasing.
3206 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3207 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3208 Warning(RegLoc, "register list not in ascending order");
3210 return Error(RegLoc, "register list not in ascending order");
3212 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3213 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3214 ") in register list");
3217 // VFP register lists must also be contiguous.
3218 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3220 return Error(RegLoc, "non-contiguous register range");
3221 EReg = MRI->getEncodingValue(Reg);
3222 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3224 EReg = MRI->getEncodingValue(++Reg);
3225 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3229 if (Parser.getTok().isNot(AsmToken::RCurly))
3230 return Error(Parser.getTok().getLoc(), "'}' expected");
3231 SMLoc E = Parser.getTok().getEndLoc();
3232 Parser.Lex(); // Eat '}' token.
3234 // Push the register list operand.
3235 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3237 // The ARM system instruction variants for LDM/STM have a '^' token here.
3238 if (Parser.getTok().is(AsmToken::Caret)) {
3239 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3240 Parser.Lex(); // Eat '^' token.
3246 // Helper function to parse the lane index for vector lists.
3247 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3248 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3249 Index = 0; // Always return a defined index value.
3250 if (Parser.getTok().is(AsmToken::LBrac)) {
3251 Parser.Lex(); // Eat the '['.
3252 if (Parser.getTok().is(AsmToken::RBrac)) {
3253 // "Dn[]" is the 'all lanes' syntax.
3254 LaneKind = AllLanes;
3255 EndLoc = Parser.getTok().getEndLoc();
3256 Parser.Lex(); // Eat the ']'.
3257 return MatchOperand_Success;
3260 // There's an optional '#' token here. Normally there wouldn't be, but
3261 // inline assemble puts one in, and it's friendly to accept that.
3262 if (Parser.getTok().is(AsmToken::Hash))
3263 Parser.Lex(); // Eat '#' or '$'.
3265 const MCExpr *LaneIndex;
3266 SMLoc Loc = Parser.getTok().getLoc();
3267 if (getParser().parseExpression(LaneIndex)) {
3268 Error(Loc, "illegal expression");
3269 return MatchOperand_ParseFail;
3271 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3273 Error(Loc, "lane index must be empty or an integer");
3274 return MatchOperand_ParseFail;
3276 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3277 Error(Parser.getTok().getLoc(), "']' expected");
3278 return MatchOperand_ParseFail;
3280 EndLoc = Parser.getTok().getEndLoc();
3281 Parser.Lex(); // Eat the ']'.
3282 int64_t Val = CE->getValue();
3284 // FIXME: Make this range check context sensitive for .8, .16, .32.
3285 if (Val < 0 || Val > 7) {
3286 Error(Parser.getTok().getLoc(), "lane index out of range");
3287 return MatchOperand_ParseFail;
3290 LaneKind = IndexedLane;
3291 return MatchOperand_Success;
3294 return MatchOperand_Success;
3297 // parse a vector register list
3298 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3299 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3300 VectorLaneTy LaneKind;
3302 SMLoc S = Parser.getTok().getLoc();
3303 // As an extension (to match gas), support a plain D register or Q register
3304 // (without encosing curly braces) as a single or double entry list,
3306 if (Parser.getTok().is(AsmToken::Identifier)) {
3307 SMLoc E = Parser.getTok().getEndLoc();
3308 int Reg = tryParseRegister();
3310 return MatchOperand_NoMatch;
3311 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3312 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3313 if (Res != MatchOperand_Success)
3317 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3320 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3324 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3329 return MatchOperand_Success;
3331 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3332 Reg = getDRegFromQReg(Reg);
3333 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3334 if (Res != MatchOperand_Success)
3338 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3339 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3340 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3343 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3344 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3345 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3349 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3354 return MatchOperand_Success;
3356 Error(S, "vector register expected");
3357 return MatchOperand_ParseFail;
3360 if (Parser.getTok().isNot(AsmToken::LCurly))
3361 return MatchOperand_NoMatch;
3363 Parser.Lex(); // Eat '{' token.
3364 SMLoc RegLoc = Parser.getTok().getLoc();
3366 int Reg = tryParseRegister();
3368 Error(RegLoc, "register expected");
3369 return MatchOperand_ParseFail;
3373 unsigned FirstReg = Reg;
3374 // The list is of D registers, but we also allow Q regs and just interpret
3375 // them as the two D sub-registers.
3376 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3377 FirstReg = Reg = getDRegFromQReg(Reg);
3378 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3379 // it's ambiguous with four-register single spaced.
3385 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3386 return MatchOperand_ParseFail;
3388 while (Parser.getTok().is(AsmToken::Comma) ||
3389 Parser.getTok().is(AsmToken::Minus)) {
3390 if (Parser.getTok().is(AsmToken::Minus)) {
3392 Spacing = 1; // Register range implies a single spaced list.
3393 else if (Spacing == 2) {
3394 Error(Parser.getTok().getLoc(),
3395 "sequential registers in double spaced list");
3396 return MatchOperand_ParseFail;
3398 Parser.Lex(); // Eat the minus.
3399 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3400 int EndReg = tryParseRegister();
3402 Error(AfterMinusLoc, "register expected");
3403 return MatchOperand_ParseFail;
3405 // Allow Q regs and just interpret them as the two D sub-registers.
3406 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3407 EndReg = getDRegFromQReg(EndReg) + 1;
3408 // If the register is the same as the start reg, there's nothing
3412 // The register must be in the same register class as the first.
3413 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3414 Error(AfterMinusLoc, "invalid register in register list");
3415 return MatchOperand_ParseFail;
3417 // Ranges must go from low to high.
3419 Error(AfterMinusLoc, "bad range in register list");
3420 return MatchOperand_ParseFail;
3422 // Parse the lane specifier if present.
3423 VectorLaneTy NextLaneKind;
3424 unsigned NextLaneIndex;
3425 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3426 MatchOperand_Success)
3427 return MatchOperand_ParseFail;
3428 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3429 Error(AfterMinusLoc, "mismatched lane index in register list");
3430 return MatchOperand_ParseFail;
3433 // Add all the registers in the range to the register list.
3434 Count += EndReg - Reg;
3438 Parser.Lex(); // Eat the comma.
3439 RegLoc = Parser.getTok().getLoc();
3441 Reg = tryParseRegister();
3443 Error(RegLoc, "register expected");
3444 return MatchOperand_ParseFail;
3446 // vector register lists must be contiguous.
3447 // It's OK to use the enumeration values directly here rather, as the
3448 // VFP register classes have the enum sorted properly.
3450 // The list is of D registers, but we also allow Q regs and just interpret
3451 // them as the two D sub-registers.
3452 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3454 Spacing = 1; // Register range implies a single spaced list.
3455 else if (Spacing == 2) {
3457 "invalid register in double-spaced list (must be 'D' register')");
3458 return MatchOperand_ParseFail;
3460 Reg = getDRegFromQReg(Reg);
3461 if (Reg != OldReg + 1) {
3462 Error(RegLoc, "non-contiguous register range");
3463 return MatchOperand_ParseFail;
3467 // Parse the lane specifier if present.
3468 VectorLaneTy NextLaneKind;
3469 unsigned NextLaneIndex;
3470 SMLoc LaneLoc = Parser.getTok().getLoc();
3471 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3472 MatchOperand_Success)
3473 return MatchOperand_ParseFail;
3474 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3475 Error(LaneLoc, "mismatched lane index in register list");
3476 return MatchOperand_ParseFail;
3480 // Normal D register.
3481 // Figure out the register spacing (single or double) of the list if
3482 // we don't know it already.
3484 Spacing = 1 + (Reg == OldReg + 2);
3486 // Just check that it's contiguous and keep going.
3487 if (Reg != OldReg + Spacing) {
3488 Error(RegLoc, "non-contiguous register range");
3489 return MatchOperand_ParseFail;
3492 // Parse the lane specifier if present.
3493 VectorLaneTy NextLaneKind;
3494 unsigned NextLaneIndex;
3495 SMLoc EndLoc = Parser.getTok().getLoc();
3496 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3497 return MatchOperand_ParseFail;
3498 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3499 Error(EndLoc, "mismatched lane index in register list");
3500 return MatchOperand_ParseFail;
3504 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3505 Error(Parser.getTok().getLoc(), "'}' expected");
3506 return MatchOperand_ParseFail;
3508 E = Parser.getTok().getEndLoc();
3509 Parser.Lex(); // Eat '}' token.
3513 // Two-register operands have been converted to the
3514 // composite register classes.
3516 const MCRegisterClass *RC = (Spacing == 1) ?
3517 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3518 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3519 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3522 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3523 (Spacing == 2), S, E));
3526 // Two-register operands have been converted to the
3527 // composite register classes.
3529 const MCRegisterClass *RC = (Spacing == 1) ?
3530 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3531 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3532 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3534 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3539 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3545 return MatchOperand_Success;
3548 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3549 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3550 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3551 SMLoc S = Parser.getTok().getLoc();
3552 const AsmToken &Tok = Parser.getTok();
3555 if (Tok.is(AsmToken::Identifier)) {
3556 StringRef OptStr = Tok.getString();
3558 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3559 .Case("sy", ARM_MB::SY)
3560 .Case("st", ARM_MB::ST)
3561 .Case("ld", ARM_MB::LD)
3562 .Case("sh", ARM_MB::ISH)
3563 .Case("ish", ARM_MB::ISH)
3564 .Case("shst", ARM_MB::ISHST)
3565 .Case("ishst", ARM_MB::ISHST)
3566 .Case("ishld", ARM_MB::ISHLD)
3567 .Case("nsh", ARM_MB::NSH)
3568 .Case("un", ARM_MB::NSH)
3569 .Case("nshst", ARM_MB::NSHST)
3570 .Case("nshld", ARM_MB::NSHLD)
3571 .Case("unst", ARM_MB::NSHST)
3572 .Case("osh", ARM_MB::OSH)
3573 .Case("oshst", ARM_MB::OSHST)
3574 .Case("oshld", ARM_MB::OSHLD)
3577 // ishld, oshld, nshld and ld are only available from ARMv8.
3578 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3579 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3583 return MatchOperand_NoMatch;
3585 Parser.Lex(); // Eat identifier token.
3586 } else if (Tok.is(AsmToken::Hash) ||
3587 Tok.is(AsmToken::Dollar) ||
3588 Tok.is(AsmToken::Integer)) {
3589 if (Parser.getTok().isNot(AsmToken::Integer))
3590 Parser.Lex(); // Eat '#' or '$'.
3591 SMLoc Loc = Parser.getTok().getLoc();
3593 const MCExpr *MemBarrierID;
3594 if (getParser().parseExpression(MemBarrierID)) {
3595 Error(Loc, "illegal expression");
3596 return MatchOperand_ParseFail;
3599 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3601 Error(Loc, "constant expression expected");
3602 return MatchOperand_ParseFail;
3605 int Val = CE->getValue();
3607 Error(Loc, "immediate value out of range");
3608 return MatchOperand_ParseFail;
3611 Opt = ARM_MB::RESERVED_0 + Val;
3613 return MatchOperand_ParseFail;
3615 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3616 return MatchOperand_Success;
3619 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3620 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3621 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3622 SMLoc S = Parser.getTok().getLoc();
3623 const AsmToken &Tok = Parser.getTok();
3626 if (Tok.is(AsmToken::Identifier)) {
3627 StringRef OptStr = Tok.getString();
3629 if (OptStr.equals_lower("sy"))
3632 return MatchOperand_NoMatch;
3634 Parser.Lex(); // Eat identifier token.
3635 } else if (Tok.is(AsmToken::Hash) ||
3636 Tok.is(AsmToken::Dollar) ||
3637 Tok.is(AsmToken::Integer)) {
3638 if (Parser.getTok().isNot(AsmToken::Integer))
3639 Parser.Lex(); // Eat '#' or '$'.
3640 SMLoc Loc = Parser.getTok().getLoc();
3642 const MCExpr *ISBarrierID;
3643 if (getParser().parseExpression(ISBarrierID)) {
3644 Error(Loc, "illegal expression");
3645 return MatchOperand_ParseFail;
3648 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3650 Error(Loc, "constant expression expected");
3651 return MatchOperand_ParseFail;
3654 int Val = CE->getValue();
3656 Error(Loc, "immediate value out of range");
3657 return MatchOperand_ParseFail;
3660 Opt = ARM_ISB::RESERVED_0 + Val;
3662 return MatchOperand_ParseFail;
3664 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3665 (ARM_ISB::InstSyncBOpt)Opt, S));
3666 return MatchOperand_Success;
3670 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3671 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3672 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3673 SMLoc S = Parser.getTok().getLoc();
3674 const AsmToken &Tok = Parser.getTok();
3675 if (!Tok.is(AsmToken::Identifier))
3676 return MatchOperand_NoMatch;
3677 StringRef IFlagsStr = Tok.getString();
3679 // An iflags string of "none" is interpreted to mean that none of the AIF
3680 // bits are set. Not a terribly useful instruction, but a valid encoding.
3681 unsigned IFlags = 0;
3682 if (IFlagsStr != "none") {
3683 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3684 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3685 .Case("a", ARM_PROC::A)
3686 .Case("i", ARM_PROC::I)
3687 .Case("f", ARM_PROC::F)
3690 // If some specific iflag is already set, it means that some letter is
3691 // present more than once, this is not acceptable.
3692 if (Flag == ~0U || (IFlags & Flag))
3693 return MatchOperand_NoMatch;
3699 Parser.Lex(); // Eat identifier token.
3700 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3701 return MatchOperand_Success;
3704 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3705 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3706 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3707 SMLoc S = Parser.getTok().getLoc();
3708 const AsmToken &Tok = Parser.getTok();
3709 if (!Tok.is(AsmToken::Identifier))
3710 return MatchOperand_NoMatch;
3711 StringRef Mask = Tok.getString();
3714 // See ARMv6-M 10.1.1
3715 std::string Name = Mask.lower();
3716 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3717 // Note: in the documentation:
3718 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3719 // for MSR APSR_nzcvq.
3720 // but we do make it an alias here. This is so to get the "mask encoding"
3721 // bits correct on MSR APSR writes.
3723 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3724 // should really only be allowed when writing a special register. Note
3725 // they get dropped in the MRS instruction reading a special register as
3726 // the SYSm field is only 8 bits.
3728 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3729 // includes the DSP extension but that is not checked.
3730 .Case("apsr", 0x800)
3731 .Case("apsr_nzcvq", 0x800)
3732 .Case("apsr_g", 0x400)
3733 .Case("apsr_nzcvqg", 0xc00)
3734 .Case("iapsr", 0x801)
3735 .Case("iapsr_nzcvq", 0x801)
3736 .Case("iapsr_g", 0x401)
3737 .Case("iapsr_nzcvqg", 0xc01)
3738 .Case("eapsr", 0x802)
3739 .Case("eapsr_nzcvq", 0x802)
3740 .Case("eapsr_g", 0x402)
3741 .Case("eapsr_nzcvqg", 0xc02)
3742 .Case("xpsr", 0x803)
3743 .Case("xpsr_nzcvq", 0x803)
3744 .Case("xpsr_g", 0x403)
3745 .Case("xpsr_nzcvqg", 0xc03)
3746 .Case("ipsr", 0x805)
3747 .Case("epsr", 0x806)
3748 .Case("iepsr", 0x807)
3751 .Case("primask", 0x810)
3752 .Case("basepri", 0x811)
3753 .Case("basepri_max", 0x812)
3754 .Case("faultmask", 0x813)
3755 .Case("control", 0x814)
3758 if (FlagsVal == ~0U)
3759 return MatchOperand_NoMatch;
3761 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3762 // basepri, basepri_max and faultmask only valid for V7m.
3763 return MatchOperand_NoMatch;
3765 Parser.Lex(); // Eat identifier token.
3766 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3767 return MatchOperand_Success;
3770 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3771 size_t Start = 0, Next = Mask.find('_');
3772 StringRef Flags = "";
3773 std::string SpecReg = Mask.slice(Start, Next).lower();
3774 if (Next != StringRef::npos)
3775 Flags = Mask.slice(Next+1, Mask.size());
3777 // FlagsVal contains the complete mask:
3779 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3780 unsigned FlagsVal = 0;
3782 if (SpecReg == "apsr") {
3783 FlagsVal = StringSwitch<unsigned>(Flags)
3784 .Case("nzcvq", 0x8) // same as CPSR_f
3785 .Case("g", 0x4) // same as CPSR_s
3786 .Case("nzcvqg", 0xc) // same as CPSR_fs
3789 if (FlagsVal == ~0U) {
3791 return MatchOperand_NoMatch;
3793 FlagsVal = 8; // No flag
3795 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3796 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3797 if (Flags == "all" || Flags == "")
3799 for (int i = 0, e = Flags.size(); i != e; ++i) {
3800 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3807 // If some specific flag is already set, it means that some letter is
3808 // present more than once, this is not acceptable.
3809 if (FlagsVal == ~0U || (FlagsVal & Flag))
3810 return MatchOperand_NoMatch;
3813 } else // No match for special register.
3814 return MatchOperand_NoMatch;
3816 // Special register without flags is NOT equivalent to "fc" flags.
3817 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3818 // two lines would enable gas compatibility at the expense of breaking
3824 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3825 if (SpecReg == "spsr")
3828 Parser.Lex(); // Eat identifier token.
3829 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3830 return MatchOperand_Success;
3833 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3834 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3835 int Low, int High) {
3836 const AsmToken &Tok = Parser.getTok();
3837 if (Tok.isNot(AsmToken::Identifier)) {
3838 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3839 return MatchOperand_ParseFail;
3841 StringRef ShiftName = Tok.getString();
3842 std::string LowerOp = Op.lower();
3843 std::string UpperOp = Op.upper();
3844 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3845 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3846 return MatchOperand_ParseFail;
3848 Parser.Lex(); // Eat shift type token.
3850 // There must be a '#' and a shift amount.
3851 if (Parser.getTok().isNot(AsmToken::Hash) &&
3852 Parser.getTok().isNot(AsmToken::Dollar)) {
3853 Error(Parser.getTok().getLoc(), "'#' expected");
3854 return MatchOperand_ParseFail;
3856 Parser.Lex(); // Eat hash token.
3858 const MCExpr *ShiftAmount;
3859 SMLoc Loc = Parser.getTok().getLoc();
3861 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3862 Error(Loc, "illegal expression");
3863 return MatchOperand_ParseFail;
3865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3867 Error(Loc, "constant expression expected");
3868 return MatchOperand_ParseFail;
3870 int Val = CE->getValue();
3871 if (Val < Low || Val > High) {
3872 Error(Loc, "immediate value out of range");
3873 return MatchOperand_ParseFail;
3876 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3878 return MatchOperand_Success;
3881 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3882 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3883 const AsmToken &Tok = Parser.getTok();
3884 SMLoc S = Tok.getLoc();
3885 if (Tok.isNot(AsmToken::Identifier)) {
3886 Error(S, "'be' or 'le' operand expected");
3887 return MatchOperand_ParseFail;
3889 int Val = StringSwitch<int>(Tok.getString().lower())
3893 Parser.Lex(); // Eat the token.
3896 Error(S, "'be' or 'le' operand expected");
3897 return MatchOperand_ParseFail;
3899 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3901 S, Tok.getEndLoc()));
3902 return MatchOperand_Success;
3905 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3906 /// instructions. Legal values are:
3907 /// lsl #n 'n' in [0,31]
3908 /// asr #n 'n' in [1,32]
3909 /// n == 32 encoded as n == 0.
3910 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3911 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3912 const AsmToken &Tok = Parser.getTok();
3913 SMLoc S = Tok.getLoc();
3914 if (Tok.isNot(AsmToken::Identifier)) {
3915 Error(S, "shift operator 'asr' or 'lsl' expected");
3916 return MatchOperand_ParseFail;
3918 StringRef ShiftName = Tok.getString();
3920 if (ShiftName == "lsl" || ShiftName == "LSL")
3922 else if (ShiftName == "asr" || ShiftName == "ASR")
3925 Error(S, "shift operator 'asr' or 'lsl' expected");
3926 return MatchOperand_ParseFail;
3928 Parser.Lex(); // Eat the operator.
3930 // A '#' and a shift amount.
3931 if (Parser.getTok().isNot(AsmToken::Hash) &&
3932 Parser.getTok().isNot(AsmToken::Dollar)) {
3933 Error(Parser.getTok().getLoc(), "'#' expected");
3934 return MatchOperand_ParseFail;
3936 Parser.Lex(); // Eat hash token.
3937 SMLoc ExLoc = Parser.getTok().getLoc();
3939 const MCExpr *ShiftAmount;
3941 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3942 Error(ExLoc, "malformed shift expression");
3943 return MatchOperand_ParseFail;
3945 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3947 Error(ExLoc, "shift amount must be an immediate");
3948 return MatchOperand_ParseFail;
3951 int64_t Val = CE->getValue();
3953 // Shift amount must be in [1,32]
3954 if (Val < 1 || Val > 32) {
3955 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3956 return MatchOperand_ParseFail;
3958 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3959 if (isThumb() && Val == 32) {
3960 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3961 return MatchOperand_ParseFail;
3963 if (Val == 32) Val = 0;
3965 // Shift amount must be in [1,32]
3966 if (Val < 0 || Val > 31) {
3967 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3968 return MatchOperand_ParseFail;
3972 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3974 return MatchOperand_Success;
3977 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3978 /// of instructions. Legal values are:
3979 /// ror #n 'n' in {0, 8, 16, 24}
3980 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3981 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3982 const AsmToken &Tok = Parser.getTok();
3983 SMLoc S = Tok.getLoc();
3984 if (Tok.isNot(AsmToken::Identifier))
3985 return MatchOperand_NoMatch;
3986 StringRef ShiftName = Tok.getString();
3987 if (ShiftName != "ror" && ShiftName != "ROR")
3988 return MatchOperand_NoMatch;
3989 Parser.Lex(); // Eat the operator.
3991 // A '#' and a rotate amount.
3992 if (Parser.getTok().isNot(AsmToken::Hash) &&
3993 Parser.getTok().isNot(AsmToken::Dollar)) {
3994 Error(Parser.getTok().getLoc(), "'#' expected");
3995 return MatchOperand_ParseFail;
3997 Parser.Lex(); // Eat hash token.
3998 SMLoc ExLoc = Parser.getTok().getLoc();
4000 const MCExpr *ShiftAmount;
4002 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4003 Error(ExLoc, "malformed rotate expression");
4004 return MatchOperand_ParseFail;
4006 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4008 Error(ExLoc, "rotate amount must be an immediate");
4009 return MatchOperand_ParseFail;
4012 int64_t Val = CE->getValue();
4013 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4014 // normally, zero is represented in asm by omitting the rotate operand
4016 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4017 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4018 return MatchOperand_ParseFail;
4021 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4023 return MatchOperand_Success;
4026 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4027 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4028 SMLoc S = Parser.getTok().getLoc();
4029 // The bitfield descriptor is really two operands, the LSB and the width.
4030 if (Parser.getTok().isNot(AsmToken::Hash) &&
4031 Parser.getTok().isNot(AsmToken::Dollar)) {
4032 Error(Parser.getTok().getLoc(), "'#' expected");
4033 return MatchOperand_ParseFail;
4035 Parser.Lex(); // Eat hash token.
4037 const MCExpr *LSBExpr;
4038 SMLoc E = Parser.getTok().getLoc();
4039 if (getParser().parseExpression(LSBExpr)) {
4040 Error(E, "malformed immediate expression");
4041 return MatchOperand_ParseFail;
4043 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4045 Error(E, "'lsb' operand must be an immediate");
4046 return MatchOperand_ParseFail;
4049 int64_t LSB = CE->getValue();
4050 // The LSB must be in the range [0,31]
4051 if (LSB < 0 || LSB > 31) {
4052 Error(E, "'lsb' operand must be in the range [0,31]");
4053 return MatchOperand_ParseFail;
4055 E = Parser.getTok().getLoc();
4057 // Expect another immediate operand.
4058 if (Parser.getTok().isNot(AsmToken::Comma)) {
4059 Error(Parser.getTok().getLoc(), "too few operands");
4060 return MatchOperand_ParseFail;
4062 Parser.Lex(); // Eat hash token.
4063 if (Parser.getTok().isNot(AsmToken::Hash) &&
4064 Parser.getTok().isNot(AsmToken::Dollar)) {
4065 Error(Parser.getTok().getLoc(), "'#' expected");
4066 return MatchOperand_ParseFail;
4068 Parser.Lex(); // Eat hash token.
4070 const MCExpr *WidthExpr;
4072 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4073 Error(E, "malformed immediate expression");
4074 return MatchOperand_ParseFail;
4076 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4078 Error(E, "'width' operand must be an immediate");
4079 return MatchOperand_ParseFail;
4082 int64_t Width = CE->getValue();
4083 // The LSB must be in the range [1,32-lsb]
4084 if (Width < 1 || Width > 32 - LSB) {
4085 Error(E, "'width' operand must be in the range [1,32-lsb]");
4086 return MatchOperand_ParseFail;
4089 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4091 return MatchOperand_Success;
4094 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4095 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4096 // Check for a post-index addressing register operand. Specifically:
4097 // postidx_reg := '+' register {, shift}
4098 // | '-' register {, shift}
4099 // | register {, shift}
4101 // This method must return MatchOperand_NoMatch without consuming any tokens
4102 // in the case where there is no match, as other alternatives take other
4104 AsmToken Tok = Parser.getTok();
4105 SMLoc S = Tok.getLoc();
4106 bool haveEaten = false;
4108 if (Tok.is(AsmToken::Plus)) {
4109 Parser.Lex(); // Eat the '+' token.
4111 } else if (Tok.is(AsmToken::Minus)) {
4112 Parser.Lex(); // Eat the '-' token.
4117 SMLoc E = Parser.getTok().getEndLoc();
4118 int Reg = tryParseRegister();
4121 return MatchOperand_NoMatch;
4122 Error(Parser.getTok().getLoc(), "register expected");
4123 return MatchOperand_ParseFail;
4126 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4127 unsigned ShiftImm = 0;
4128 if (Parser.getTok().is(AsmToken::Comma)) {
4129 Parser.Lex(); // Eat the ','.
4130 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4131 return MatchOperand_ParseFail;
4133 // FIXME: Only approximates end...may include intervening whitespace.
4134 E = Parser.getTok().getLoc();
4137 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4140 return MatchOperand_Success;
4143 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4144 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4145 // Check for a post-index addressing register operand. Specifically:
4146 // am3offset := '+' register
4153 // This method must return MatchOperand_NoMatch without consuming any tokens
4154 // in the case where there is no match, as other alternatives take other
4156 AsmToken Tok = Parser.getTok();
4157 SMLoc S = Tok.getLoc();
4159 // Do immediates first, as we always parse those if we have a '#'.
4160 if (Parser.getTok().is(AsmToken::Hash) ||
4161 Parser.getTok().is(AsmToken::Dollar)) {
4162 Parser.Lex(); // Eat '#' or '$'.
4163 // Explicitly look for a '-', as we need to encode negative zero
4165 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4166 const MCExpr *Offset;
4168 if (getParser().parseExpression(Offset, E))
4169 return MatchOperand_ParseFail;
4170 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4172 Error(S, "constant expression expected");
4173 return MatchOperand_ParseFail;
4175 // Negative zero is encoded as the flag value INT32_MIN.
4176 int32_t Val = CE->getValue();
4177 if (isNegative && Val == 0)
4181 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4183 return MatchOperand_Success;
4187 bool haveEaten = false;
4189 if (Tok.is(AsmToken::Plus)) {
4190 Parser.Lex(); // Eat the '+' token.
4192 } else if (Tok.is(AsmToken::Minus)) {
4193 Parser.Lex(); // Eat the '-' token.
4198 Tok = Parser.getTok();
4199 int Reg = tryParseRegister();
4202 return MatchOperand_NoMatch;
4203 Error(Tok.getLoc(), "register expected");
4204 return MatchOperand_ParseFail;
4207 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4208 0, S, Tok.getEndLoc()));
4210 return MatchOperand_Success;
4213 /// Convert parsed operands to MCInst. Needed here because this instruction
4214 /// only has two register operands, but multiplication is commutative so
4215 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4217 cvtThumbMultiply(MCInst &Inst,
4218 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4219 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4220 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4221 // If we have a three-operand form, make sure to set Rn to be the operand
4222 // that isn't the same as Rd.
4224 if (Operands.size() == 6 &&
4225 ((ARMOperand*)Operands[4])->getReg() ==
4226 ((ARMOperand*)Operands[3])->getReg())
4228 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4229 Inst.addOperand(Inst.getOperand(0));
4230 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4234 cvtThumbBranches(MCInst &Inst,
4235 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4236 int CondOp = -1, ImmOp = -1;
4237 switch(Inst.getOpcode()) {
4239 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4242 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4244 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4246 // first decide whether or not the branch should be conditional
4247 // by looking at it's location relative to an IT block
4249 // inside an IT block we cannot have any conditional branches. any
4250 // such instructions needs to be converted to unconditional form
4251 switch(Inst.getOpcode()) {
4252 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4253 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4256 // outside IT blocks we can only have unconditional branches with AL
4257 // condition code or conditional branches with non-AL condition code
4258 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4259 switch(Inst.getOpcode()) {
4262 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4266 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4271 // now decide on encoding size based on branch target range
4272 switch(Inst.getOpcode()) {
4273 // classify tB as either t2B or t1B based on range of immediate operand
4275 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4276 if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4277 Inst.setOpcode(ARM::t2B);
4280 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4282 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4283 if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4284 Inst.setOpcode(ARM::t2Bcc);
4288 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4289 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4292 /// Parse an ARM memory expression, return false if successful else return true
4293 /// or an error. The first token must be a '[' when called.
4295 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4297 assert(Parser.getTok().is(AsmToken::LBrac) &&
4298 "Token is not a Left Bracket");
4299 S = Parser.getTok().getLoc();
4300 Parser.Lex(); // Eat left bracket token.
4302 const AsmToken &BaseRegTok = Parser.getTok();
4303 int BaseRegNum = tryParseRegister();
4304 if (BaseRegNum == -1)
4305 return Error(BaseRegTok.getLoc(), "register expected");
4307 // The next token must either be a comma, a colon or a closing bracket.
4308 const AsmToken &Tok = Parser.getTok();
4309 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4310 !Tok.is(AsmToken::RBrac))
4311 return Error(Tok.getLoc(), "malformed memory operand");
4313 if (Tok.is(AsmToken::RBrac)) {
4314 E = Tok.getEndLoc();
4315 Parser.Lex(); // Eat right bracket token.
4317 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4318 0, 0, false, S, E));
4320 // If there's a pre-indexing writeback marker, '!', just add it as a token
4321 // operand. It's rather odd, but syntactically valid.
4322 if (Parser.getTok().is(AsmToken::Exclaim)) {
4323 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4324 Parser.Lex(); // Eat the '!'.
4330 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4331 "Lost colon or comma in memory operand?!");
4332 if (Tok.is(AsmToken::Comma)) {
4333 Parser.Lex(); // Eat the comma.
4336 // If we have a ':', it's an alignment specifier.
4337 if (Parser.getTok().is(AsmToken::Colon)) {
4338 Parser.Lex(); // Eat the ':'.
4339 E = Parser.getTok().getLoc();
4342 if (getParser().parseExpression(Expr))
4345 // The expression has to be a constant. Memory references with relocations
4346 // don't come through here, as they use the <label> forms of the relevant
4348 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4350 return Error (E, "constant expression expected");
4353 switch (CE->getValue()) {
4356 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4357 case 16: Align = 2; break;
4358 case 32: Align = 4; break;
4359 case 64: Align = 8; break;
4360 case 128: Align = 16; break;
4361 case 256: Align = 32; break;
4364 // Now we should have the closing ']'
4365 if (Parser.getTok().isNot(AsmToken::RBrac))
4366 return Error(Parser.getTok().getLoc(), "']' expected");
4367 E = Parser.getTok().getEndLoc();
4368 Parser.Lex(); // Eat right bracket token.
4370 // Don't worry about range checking the value here. That's handled by
4371 // the is*() predicates.
4372 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4373 ARM_AM::no_shift, 0, Align,
4376 // If there's a pre-indexing writeback marker, '!', just add it as a token
4378 if (Parser.getTok().is(AsmToken::Exclaim)) {
4379 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4380 Parser.Lex(); // Eat the '!'.
4386 // If we have a '#', it's an immediate offset, else assume it's a register
4387 // offset. Be friendly and also accept a plain integer (without a leading
4388 // hash) for gas compatibility.
4389 if (Parser.getTok().is(AsmToken::Hash) ||
4390 Parser.getTok().is(AsmToken::Dollar) ||
4391 Parser.getTok().is(AsmToken::Integer)) {
4392 if (Parser.getTok().isNot(AsmToken::Integer))
4393 Parser.Lex(); // Eat '#' or '$'.
4394 E = Parser.getTok().getLoc();
4396 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4397 const MCExpr *Offset;
4398 if (getParser().parseExpression(Offset))
4401 // The expression has to be a constant. Memory references with relocations
4402 // don't come through here, as they use the <label> forms of the relevant
4404 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4406 return Error (E, "constant expression expected");
4408 // If the constant was #-0, represent it as INT32_MIN.
4409 int32_t Val = CE->getValue();
4410 if (isNegative && Val == 0)
4411 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4413 // Now we should have the closing ']'
4414 if (Parser.getTok().isNot(AsmToken::RBrac))
4415 return Error(Parser.getTok().getLoc(), "']' expected");
4416 E = Parser.getTok().getEndLoc();
4417 Parser.Lex(); // Eat right bracket token.
4419 // Don't worry about range checking the value here. That's handled by
4420 // the is*() predicates.
4421 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4422 ARM_AM::no_shift, 0, 0,
4425 // If there's a pre-indexing writeback marker, '!', just add it as a token
4427 if (Parser.getTok().is(AsmToken::Exclaim)) {
4428 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4429 Parser.Lex(); // Eat the '!'.
4435 // The register offset is optionally preceded by a '+' or '-'
4436 bool isNegative = false;
4437 if (Parser.getTok().is(AsmToken::Minus)) {
4439 Parser.Lex(); // Eat the '-'.
4440 } else if (Parser.getTok().is(AsmToken::Plus)) {
4442 Parser.Lex(); // Eat the '+'.
4445 E = Parser.getTok().getLoc();
4446 int OffsetRegNum = tryParseRegister();
4447 if (OffsetRegNum == -1)
4448 return Error(E, "register expected");
4450 // If there's a shift operator, handle it.
4451 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4452 unsigned ShiftImm = 0;
4453 if (Parser.getTok().is(AsmToken::Comma)) {
4454 Parser.Lex(); // Eat the ','.
4455 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4459 // Now we should have the closing ']'
4460 if (Parser.getTok().isNot(AsmToken::RBrac))
4461 return Error(Parser.getTok().getLoc(), "']' expected");
4462 E = Parser.getTok().getEndLoc();
4463 Parser.Lex(); // Eat right bracket token.
4465 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4466 ShiftType, ShiftImm, 0, isNegative,
4469 // If there's a pre-indexing writeback marker, '!', just add it as a token
4471 if (Parser.getTok().is(AsmToken::Exclaim)) {
4472 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4473 Parser.Lex(); // Eat the '!'.
4479 /// parseMemRegOffsetShift - one of these two:
4480 /// ( lsl | lsr | asr | ror ) , # shift_amount
4482 /// return true if it parses a shift otherwise it returns false.
4483 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4485 SMLoc Loc = Parser.getTok().getLoc();
4486 const AsmToken &Tok = Parser.getTok();
4487 if (Tok.isNot(AsmToken::Identifier))
4489 StringRef ShiftName = Tok.getString();
4490 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4491 ShiftName == "asl" || ShiftName == "ASL")
4493 else if (ShiftName == "lsr" || ShiftName == "LSR")
4495 else if (ShiftName == "asr" || ShiftName == "ASR")
4497 else if (ShiftName == "ror" || ShiftName == "ROR")
4499 else if (ShiftName == "rrx" || ShiftName == "RRX")
4502 return Error(Loc, "illegal shift operator");
4503 Parser.Lex(); // Eat shift type token.
4505 // rrx stands alone.
4507 if (St != ARM_AM::rrx) {
4508 Loc = Parser.getTok().getLoc();
4509 // A '#' and a shift amount.
4510 const AsmToken &HashTok = Parser.getTok();
4511 if (HashTok.isNot(AsmToken::Hash) &&
4512 HashTok.isNot(AsmToken::Dollar))
4513 return Error(HashTok.getLoc(), "'#' expected");
4514 Parser.Lex(); // Eat hash token.
4517 if (getParser().parseExpression(Expr))
4519 // Range check the immediate.
4520 // lsl, ror: 0 <= imm <= 31
4521 // lsr, asr: 0 <= imm <= 32
4522 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4524 return Error(Loc, "shift amount must be an immediate");
4525 int64_t Imm = CE->getValue();
4527 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4528 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4529 return Error(Loc, "immediate shift value out of range");
4530 // If <ShiftTy> #0, turn it into a no_shift.
4533 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4542 /// parseFPImm - A floating point immediate expression operand.
4543 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4544 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4545 // Anything that can accept a floating point constant as an operand
4546 // needs to go through here, as the regular parseExpression is
4549 // This routine still creates a generic Immediate operand, containing
4550 // a bitcast of the 64-bit floating point value. The various operands
4551 // that accept floats can check whether the value is valid for them
4552 // via the standard is*() predicates.
4554 SMLoc S = Parser.getTok().getLoc();
4556 if (Parser.getTok().isNot(AsmToken::Hash) &&
4557 Parser.getTok().isNot(AsmToken::Dollar))
4558 return MatchOperand_NoMatch;
4560 // Disambiguate the VMOV forms that can accept an FP immediate.
4561 // vmov.f32 <sreg>, #imm
4562 // vmov.f64 <dreg>, #imm
4563 // vmov.f32 <dreg>, #imm @ vector f32x2
4564 // vmov.f32 <qreg>, #imm @ vector f32x4
4566 // There are also the NEON VMOV instructions which expect an
4567 // integer constant. Make sure we don't try to parse an FPImm
4569 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4570 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4571 bool isVmovf = TyOp->isToken() && (TyOp->getToken() == ".f32" ||
4572 TyOp->getToken() == ".f64");
4573 ARMOperand *Mnemonic = static_cast<ARMOperand*>(Operands[0]);
4574 bool isFconst = Mnemonic->isToken() && (Mnemonic->getToken() == "fconstd" ||
4575 Mnemonic->getToken() == "fconsts");
4576 if (!(isVmovf || isFconst))
4577 return MatchOperand_NoMatch;
4579 Parser.Lex(); // Eat '#' or '$'.
4581 // Handle negation, as that still comes through as a separate token.
4582 bool isNegative = false;
4583 if (Parser.getTok().is(AsmToken::Minus)) {
4587 const AsmToken &Tok = Parser.getTok();
4588 SMLoc Loc = Tok.getLoc();
4589 if (Tok.is(AsmToken::Real) && isVmovf) {
4590 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4591 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4592 // If we had a '-' in front, toggle the sign bit.
4593 IntVal ^= (uint64_t)isNegative << 31;
4594 Parser.Lex(); // Eat the token.
4595 Operands.push_back(ARMOperand::CreateImm(
4596 MCConstantExpr::Create(IntVal, getContext()),
4597 S, Parser.getTok().getLoc()));
4598 return MatchOperand_Success;
4600 // Also handle plain integers. Instructions which allow floating point
4601 // immediates also allow a raw encoded 8-bit value.
4602 if (Tok.is(AsmToken::Integer) && isFconst) {
4603 int64_t Val = Tok.getIntVal();
4604 Parser.Lex(); // Eat the token.
4605 if (Val > 255 || Val < 0) {
4606 Error(Loc, "encoded floating point value out of range");
4607 return MatchOperand_ParseFail;
4609 float RealVal = ARM_AM::getFPImmFloat(Val);
4610 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
4612 Operands.push_back(ARMOperand::CreateImm(
4613 MCConstantExpr::Create(Val, getContext()), S,
4614 Parser.getTok().getLoc()));
4615 return MatchOperand_Success;
4618 Error(Loc, "invalid floating point immediate");
4619 return MatchOperand_ParseFail;
4622 /// Parse a arm instruction operand. For now this parses the operand regardless
4623 /// of the mnemonic.
4624 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4625 StringRef Mnemonic) {
4628 // Check if the current operand has a custom associated parser, if so, try to
4629 // custom parse the operand, or fallback to the general approach.
4630 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4631 if (ResTy == MatchOperand_Success)
4633 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4634 // there was a match, but an error occurred, in which case, just return that
4635 // the operand parsing failed.
4636 if (ResTy == MatchOperand_ParseFail)
4639 switch (getLexer().getKind()) {
4641 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4643 case AsmToken::Identifier: {
4644 // If we've seen a branch mnemonic, the next operand must be a label. This
4645 // is true even if the label is a register name. So "br r1" means branch to
4647 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4649 if (!tryParseRegisterWithWriteBack(Operands))
4651 int Res = tryParseShiftRegister(Operands);
4652 if (Res == 0) // success
4654 else if (Res == -1) // irrecoverable error
4656 // If this is VMRS, check for the apsr_nzcv operand.
4657 if (Mnemonic == "vmrs" &&
4658 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4659 S = Parser.getTok().getLoc();
4661 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4666 // Fall though for the Identifier case that is not a register or a
4669 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4670 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4671 case AsmToken::String: // quoted label names.
4672 case AsmToken::Dot: { // . as a branch target
4673 // This was not a register so parse other operands that start with an
4674 // identifier (like labels) as expressions and create them as immediates.
4675 const MCExpr *IdVal;
4676 S = Parser.getTok().getLoc();
4677 if (getParser().parseExpression(IdVal))
4679 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4680 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4683 case AsmToken::LBrac:
4684 return parseMemory(Operands);
4685 case AsmToken::LCurly:
4686 return parseRegisterList(Operands);
4687 case AsmToken::Dollar:
4688 case AsmToken::Hash: {
4689 // #42 -> immediate.
4690 S = Parser.getTok().getLoc();
4693 if (Parser.getTok().isNot(AsmToken::Colon)) {
4694 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4695 const MCExpr *ImmVal;
4696 if (getParser().parseExpression(ImmVal))
4698 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4700 int32_t Val = CE->getValue();
4701 if (isNegative && Val == 0)
4702 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4704 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4705 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4707 // There can be a trailing '!' on operands that we want as a separate
4708 // '!' Token operand. Handle that here. For example, the compatibility
4709 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4710 if (Parser.getTok().is(AsmToken::Exclaim)) {
4711 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4712 Parser.getTok().getLoc()));
4713 Parser.Lex(); // Eat exclaim token
4717 // w/ a ':' after the '#', it's just like a plain ':'.
4720 case AsmToken::Colon: {
4721 // ":lower16:" and ":upper16:" expression prefixes
4722 // FIXME: Check it's an expression prefix,
4723 // e.g. (FOO - :lower16:BAR) isn't legal.
4724 ARMMCExpr::VariantKind RefKind;
4725 if (parsePrefix(RefKind))
4728 const MCExpr *SubExprVal;
4729 if (getParser().parseExpression(SubExprVal))
4732 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4734 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4735 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4738 case AsmToken::Equal: {
4739 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
4740 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
4742 Parser.Lex(); // Eat '='
4743 const MCExpr *SubExprVal;
4744 if (getParser().parseExpression(SubExprVal))
4746 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4748 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
4749 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
4755 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4756 // :lower16: and :upper16:.
4757 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4758 RefKind = ARMMCExpr::VK_ARM_None;
4760 // consume an optional '#' (GNU compatibility)
4761 if (getLexer().is(AsmToken::Hash))
4764 // :lower16: and :upper16: modifiers
4765 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4766 Parser.Lex(); // Eat ':'
4768 if (getLexer().isNot(AsmToken::Identifier)) {
4769 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4773 StringRef IDVal = Parser.getTok().getIdentifier();
4774 if (IDVal == "lower16") {
4775 RefKind = ARMMCExpr::VK_ARM_LO16;
4776 } else if (IDVal == "upper16") {
4777 RefKind = ARMMCExpr::VK_ARM_HI16;
4779 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4784 if (getLexer().isNot(AsmToken::Colon)) {
4785 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4788 Parser.Lex(); // Eat the last ':'
4792 /// \brief Given a mnemonic, split out possible predication code and carry
4793 /// setting letters to form a canonical mnemonic and flags.
4795 // FIXME: Would be nice to autogen this.
4796 // FIXME: This is a bit of a maze of special cases.
4797 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4798 unsigned &PredicationCode,
4800 unsigned &ProcessorIMod,
4801 StringRef &ITMask) {
4802 PredicationCode = ARMCC::AL;
4803 CarrySetting = false;
4806 // Ignore some mnemonics we know aren't predicated forms.
4808 // FIXME: Would be nice to autogen this.
4809 if ((Mnemonic == "movs" && isThumb()) ||
4810 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4811 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4812 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4813 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4814 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
4815 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4816 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4817 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4818 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4819 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
4820 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4821 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4824 // First, split out any predication code. Ignore mnemonics we know aren't
4825 // predicated but do have a carry-set and so weren't caught above.
4826 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4827 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4828 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4829 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4830 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4831 .Case("eq", ARMCC::EQ)
4832 .Case("ne", ARMCC::NE)
4833 .Case("hs", ARMCC::HS)
4834 .Case("cs", ARMCC::HS)
4835 .Case("lo", ARMCC::LO)
4836 .Case("cc", ARMCC::LO)
4837 .Case("mi", ARMCC::MI)
4838 .Case("pl", ARMCC::PL)
4839 .Case("vs", ARMCC::VS)
4840 .Case("vc", ARMCC::VC)
4841 .Case("hi", ARMCC::HI)
4842 .Case("ls", ARMCC::LS)
4843 .Case("ge", ARMCC::GE)
4844 .Case("lt", ARMCC::LT)
4845 .Case("gt", ARMCC::GT)
4846 .Case("le", ARMCC::LE)
4847 .Case("al", ARMCC::AL)
4850 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4851 PredicationCode = CC;
4855 // Next, determine if we have a carry setting bit. We explicitly ignore all
4856 // the instructions we know end in 's'.
4857 if (Mnemonic.endswith("s") &&
4858 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4859 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4860 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4861 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4862 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4863 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4864 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4865 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4866 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
4867 (Mnemonic == "movs" && isThumb()))) {
4868 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4869 CarrySetting = true;
4872 // The "cps" instruction can have a interrupt mode operand which is glued into
4873 // the mnemonic. Check if this is the case, split it and parse the imod op
4874 if (Mnemonic.startswith("cps")) {
4875 // Split out any imod code.
4877 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4878 .Case("ie", ARM_PROC::IE)
4879 .Case("id", ARM_PROC::ID)
4882 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4883 ProcessorIMod = IMod;
4887 // The "it" instruction has the condition mask on the end of the mnemonic.
4888 if (Mnemonic.startswith("it")) {
4889 ITMask = Mnemonic.slice(2, Mnemonic.size());
4890 Mnemonic = Mnemonic.slice(0, 2);
4896 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4897 /// inclusion of carry set or predication code operands.
4899 // FIXME: It would be nice to autogen this.
4901 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
4902 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
4903 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4904 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4905 Mnemonic == "add" || Mnemonic == "adc" ||
4906 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4907 Mnemonic == "orr" || Mnemonic == "mvn" ||
4908 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4909 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4910 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4911 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4912 Mnemonic == "mla" || Mnemonic == "smlal" ||
4913 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4914 CanAcceptCarrySet = true;
4916 CanAcceptCarrySet = false;
4918 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4919 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
4920 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") ||
4921 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
4922 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
4923 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
4924 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4925 Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
4926 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
4927 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
4928 // These mnemonics are never predicable
4929 CanAcceptPredicationCode = false;
4930 } else if (!isThumb()) {
4931 // Some instructions are only predicable in Thumb mode
4932 CanAcceptPredicationCode
4933 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
4934 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
4935 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
4936 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
4937 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
4938 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
4939 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
4940 } else if (isThumbOne()) {
4942 CanAcceptPredicationCode = Mnemonic != "movs";
4944 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
4946 CanAcceptPredicationCode = true;
4949 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4950 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4951 // FIXME: This is all horribly hacky. We really need a better way to deal
4952 // with optional operands like this in the matcher table.
4954 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4955 // another does not. Specifically, the MOVW instruction does not. So we
4956 // special case it here and remove the defaulted (non-setting) cc_out
4957 // operand if that's the instruction we're trying to match.
4959 // We do this as post-processing of the explicit operands rather than just
4960 // conditionally adding the cc_out in the first place because we need
4961 // to check the type of the parsed immediate operand.
4962 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4963 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4964 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4965 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4968 // Register-register 'add' for thumb does not have a cc_out operand
4969 // when there are only two register operands.
4970 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4971 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4972 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4973 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4975 // Register-register 'add' for thumb does not have a cc_out operand
4976 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4977 // have to check the immediate range here since Thumb2 has a variant
4978 // that can handle a different range and has a cc_out operand.
4979 if (((isThumb() && Mnemonic == "add") ||
4980 (isThumbTwo() && Mnemonic == "sub")) &&
4981 Operands.size() == 6 &&
4982 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4983 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4984 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4985 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4986 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4987 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4989 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4990 // imm0_4095 variant. That's the least-preferred variant when
4991 // selecting via the generic "add" mnemonic, so to know that we
4992 // should remove the cc_out operand, we have to explicitly check that
4993 // it's not one of the other variants. Ugh.
4994 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4995 Operands.size() == 6 &&
4996 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4997 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4998 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4999 // Nest conditions rather than one big 'if' statement for readability.
5001 // If both registers are low, we're in an IT block, and the immediate is
5002 // in range, we should use encoding T1 instead, which has a cc_out.
5004 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5005 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
5006 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
5008 // Check against T3. If the second register is the PC, this is an
5009 // alternate form of ADR, which uses encoding T4, so check for that too.
5010 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
5011 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
5014 // Otherwise, we use encoding T4, which does not have a cc_out
5019 // The thumb2 multiply instruction doesn't have a CCOut register, so
5020 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5021 // use the 16-bit encoding or not.
5022 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5023 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5024 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5025 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5026 static_cast<ARMOperand*>(Operands[5])->isReg() &&
5027 // If the registers aren't low regs, the destination reg isn't the
5028 // same as one of the source regs, or the cc_out operand is zero
5029 // outside of an IT block, we have to use the 32-bit encoding, so
5030 // remove the cc_out operand.
5031 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5032 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5033 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
5035 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
5036 static_cast<ARMOperand*>(Operands[5])->getReg() &&
5037 static_cast<ARMOperand*>(Operands[3])->getReg() !=
5038 static_cast<ARMOperand*>(Operands[4])->getReg())))
5041 // Also check the 'mul' syntax variant that doesn't specify an explicit
5042 // destination register.
5043 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5044 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5045 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5046 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5047 // If the registers aren't low regs or the cc_out operand is zero
5048 // outside of an IT block, we have to use the 32-bit encoding, so
5049 // remove the cc_out operand.
5050 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5051 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5057 // Register-register 'add/sub' for thumb does not have a cc_out operand
5058 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5059 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5060 // right, this will result in better diagnostics (which operand is off)
5062 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5063 (Operands.size() == 5 || Operands.size() == 6) &&
5064 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5065 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5066 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5067 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
5068 (Operands.size() == 6 &&
5069 static_cast<ARMOperand*>(Operands[5])->isImm())))
5075 bool ARMAsmParser::shouldOmitPredicateOperand(
5076 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
5077 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5078 unsigned RegIdx = 3;
5079 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5080 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
5081 if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
5082 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
5085 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
5086 (ARMMCRegisterClasses[ARM::DPRRegClassID]
5087 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
5088 ARMMCRegisterClasses[ARM::QPRRegClassID]
5089 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
5095 static bool isDataTypeToken(StringRef Tok) {
5096 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5097 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5098 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5099 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5100 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5101 Tok == ".f" || Tok == ".d";
5104 // FIXME: This bit should probably be handled via an explicit match class
5105 // in the .td files that matches the suffix instead of having it be
5106 // a literal string token the way it is now.
5107 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5108 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5110 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5111 unsigned VariantID);
5113 static bool RequiresVFPRegListValidation(StringRef Inst,
5114 bool &AcceptSinglePrecisionOnly,
5115 bool &AcceptDoublePrecisionOnly) {
5116 if (Inst.size() < 7)
5119 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5120 StringRef AddressingMode = Inst.substr(4, 2);
5121 if (AddressingMode == "ia" || AddressingMode == "db" ||
5122 AddressingMode == "ea" || AddressingMode == "fd") {
5123 AcceptSinglePrecisionOnly = Inst[6] == 's';
5124 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5132 /// Parse an arm instruction mnemonic followed by its operands.
5133 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5135 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5136 // FIXME: Can this be done via tablegen in some fashion?
5137 bool RequireVFPRegisterListCheck;
5138 bool AcceptSinglePrecisionOnly;
5139 bool AcceptDoublePrecisionOnly;
5140 RequireVFPRegisterListCheck =
5141 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5142 AcceptDoublePrecisionOnly);
5144 // Apply mnemonic aliases before doing anything else, as the destination
5145 // mnemonic may include suffices and we want to handle them normally.
5146 // The generic tblgen'erated code does this later, at the start of
5147 // MatchInstructionImpl(), but that's too late for aliases that include
5148 // any sort of suffix.
5149 unsigned AvailableFeatures = getAvailableFeatures();
5150 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5151 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5153 // First check for the ARM-specific .req directive.
5154 if (Parser.getTok().is(AsmToken::Identifier) &&
5155 Parser.getTok().getIdentifier() == ".req") {
5156 parseDirectiveReq(Name, NameLoc);
5157 // We always return 'error' for this, as we're done with this
5158 // statement and don't need to match the 'instruction."
5162 // Create the leading tokens for the mnemonic, split by '.' characters.
5163 size_t Start = 0, Next = Name.find('.');
5164 StringRef Mnemonic = Name.slice(Start, Next);
5166 // Split out the predication code and carry setting flag from the mnemonic.
5167 unsigned PredicationCode;
5168 unsigned ProcessorIMod;
5171 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5172 ProcessorIMod, ITMask);
5174 // In Thumb1, only the branch (B) instruction can be predicated.
5175 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5176 Parser.eatToEndOfStatement();
5177 return Error(NameLoc, "conditional execution not supported in Thumb1");
5180 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5182 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5183 // is the mask as it will be for the IT encoding if the conditional
5184 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5185 // where the conditional bit0 is zero, the instruction post-processing
5186 // will adjust the mask accordingly.
5187 if (Mnemonic == "it") {
5188 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5189 if (ITMask.size() > 3) {
5190 Parser.eatToEndOfStatement();
5191 return Error(Loc, "too many conditions on IT instruction");
5194 for (unsigned i = ITMask.size(); i != 0; --i) {
5195 char pos = ITMask[i - 1];
5196 if (pos != 't' && pos != 'e') {
5197 Parser.eatToEndOfStatement();
5198 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5201 if (ITMask[i - 1] == 't')
5204 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5207 // FIXME: This is all a pretty gross hack. We should automatically handle
5208 // optional operands like this via tblgen.
5210 // Next, add the CCOut and ConditionCode operands, if needed.
5212 // For mnemonics which can ever incorporate a carry setting bit or predication
5213 // code, our matching model involves us always generating CCOut and
5214 // ConditionCode operands to match the mnemonic "as written" and then we let
5215 // the matcher deal with finding the right instruction or generating an
5216 // appropriate error.
5217 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5218 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5220 // If we had a carry-set on an instruction that can't do that, issue an
5222 if (!CanAcceptCarrySet && CarrySetting) {
5223 Parser.eatToEndOfStatement();
5224 return Error(NameLoc, "instruction '" + Mnemonic +
5225 "' can not set flags, but 's' suffix specified");
5227 // If we had a predication code on an instruction that can't do that, issue an
5229 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5230 Parser.eatToEndOfStatement();
5231 return Error(NameLoc, "instruction '" + Mnemonic +
5232 "' is not predicable, but condition code specified");
5235 // Add the carry setting operand, if necessary.
5236 if (CanAcceptCarrySet) {
5237 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5238 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5242 // Add the predication code operand, if necessary.
5243 if (CanAcceptPredicationCode) {
5244 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5246 Operands.push_back(ARMOperand::CreateCondCode(
5247 ARMCC::CondCodes(PredicationCode), Loc));
5250 // Add the processor imod operand, if necessary.
5251 if (ProcessorIMod) {
5252 Operands.push_back(ARMOperand::CreateImm(
5253 MCConstantExpr::Create(ProcessorIMod, getContext()),
5257 // Add the remaining tokens in the mnemonic.
5258 while (Next != StringRef::npos) {
5260 Next = Name.find('.', Start + 1);
5261 StringRef ExtraToken = Name.slice(Start, Next);
5263 // Some NEON instructions have an optional datatype suffix that is
5264 // completely ignored. Check for that.
5265 if (isDataTypeToken(ExtraToken) &&
5266 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5269 // For for ARM mode generate an error if the .n qualifier is used.
5270 if (ExtraToken == ".n" && !isThumb()) {
5271 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5272 Parser.eatToEndOfStatement();
5273 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5277 // The .n qualifier is always discarded as that is what the tables
5278 // and matcher expect. In ARM mode the .w qualifier has no effect,
5279 // so discard it to avoid errors that can be caused by the matcher.
5280 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5281 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5282 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5286 // Read the remaining operands.
5287 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5288 // Read the first operand.
5289 if (parseOperand(Operands, Mnemonic)) {
5290 Parser.eatToEndOfStatement();
5294 while (getLexer().is(AsmToken::Comma)) {
5295 Parser.Lex(); // Eat the comma.
5297 // Parse and remember the operand.
5298 if (parseOperand(Operands, Mnemonic)) {
5299 Parser.eatToEndOfStatement();
5305 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5306 SMLoc Loc = getLexer().getLoc();
5307 Parser.eatToEndOfStatement();
5308 return Error(Loc, "unexpected token in argument list");
5311 Parser.Lex(); // Consume the EndOfStatement
5313 if (RequireVFPRegisterListCheck) {
5314 ARMOperand *Op = static_cast<ARMOperand*>(Operands.back());
5315 if (AcceptSinglePrecisionOnly && !Op->isSPRRegList())
5316 return Error(Op->getStartLoc(),
5317 "VFP/Neon single precision register expected");
5318 if (AcceptDoublePrecisionOnly && !Op->isDPRRegList())
5319 return Error(Op->getStartLoc(),
5320 "VFP/Neon double precision register expected");
5323 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5324 // do and don't have a cc_out optional-def operand. With some spot-checks
5325 // of the operand list, we can figure out which variant we're trying to
5326 // parse and adjust accordingly before actually matching. We shouldn't ever
5327 // try to remove a cc_out operand that was explicitly set on the the
5328 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5329 // table driven matcher doesn't fit well with the ARM instruction set.
5330 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5331 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5332 Operands.erase(Operands.begin() + 1);
5336 // Some instructions have the same mnemonic, but don't always
5337 // have a predicate. Distinguish them here and delete the
5338 // predicate if needed.
5339 if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5340 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5341 Operands.erase(Operands.begin() + 1);
5345 // ARM mode 'blx' need special handling, as the register operand version
5346 // is predicable, but the label operand version is not. So, we can't rely
5347 // on the Mnemonic based checking to correctly figure out when to put
5348 // a k_CondCode operand in the list. If we're trying to match the label
5349 // version, remove the k_CondCode operand here.
5350 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5351 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5352 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5353 Operands.erase(Operands.begin() + 1);
5357 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5358 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5359 // a single GPRPair reg operand is used in the .td file to replace the two
5360 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5361 // expressed as a GPRPair, so we have to manually merge them.
5362 // FIXME: We would really like to be able to tablegen'erate this.
5363 if (!isThumb() && Operands.size() > 4 &&
5364 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5365 Mnemonic == "stlexd")) {
5366 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5367 unsigned Idx = isLoad ? 2 : 3;
5368 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5369 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5371 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5372 // Adjust only if Op1 and Op2 are GPRs.
5373 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5374 MRC.contains(Op2->getReg())) {
5375 unsigned Reg1 = Op1->getReg();
5376 unsigned Reg2 = Op2->getReg();
5377 unsigned Rt = MRI->getEncodingValue(Reg1);
5378 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5380 // Rt2 must be Rt + 1 and Rt must be even.
5381 if (Rt + 1 != Rt2 || (Rt & 1)) {
5382 Error(Op2->getStartLoc(), isLoad ?
5383 "destination operands must be sequential" :
5384 "source operands must be sequential");
5387 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5388 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5389 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5390 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5391 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5397 // GNU Assembler extension (compatibility)
5398 if ((Mnemonic == "ldrd" || Mnemonic == "strd") && !isThumb() &&
5399 Operands.size() == 4) {
5400 ARMOperand *Op = static_cast<ARMOperand *>(Operands[2]);
5401 assert(Op->isReg() && "expected register argument");
5402 assert(MRI->getMatchingSuperReg(Op->getReg(), ARM::gsub_0,
5403 &MRI->getRegClass(ARM::GPRPairRegClassID))
5404 && "expected register pair");
5405 Operands.insert(Operands.begin() + 3,
5406 ARMOperand::CreateReg(Op->getReg() + 1, Op->getStartLoc(),
5410 // FIXME: As said above, this is all a pretty gross hack. This instruction
5411 // does not fit with other "subs" and tblgen.
5412 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5413 // so the Mnemonic is the original name "subs" and delete the predicate
5414 // operand so it will match the table entry.
5415 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5416 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5417 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5418 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5419 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5420 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5421 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5422 Operands.erase(Operands.begin());
5424 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5426 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5427 Operands.erase(Operands.begin() + 1);
5433 // Validate context-sensitive operand constraints.
5435 // return 'true' if register list contains non-low GPR registers,
5436 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5437 // 'containsReg' to true.
5438 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5439 unsigned HiReg, bool &containsReg) {
5440 containsReg = false;
5441 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5442 unsigned OpReg = Inst.getOperand(i).getReg();
5445 // Anything other than a low register isn't legal here.
5446 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5452 // Check if the specified regisgter is in the register list of the inst,
5453 // starting at the indicated operand number.
5454 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5455 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5456 unsigned OpReg = Inst.getOperand(i).getReg();
5463 // Return true if instruction has the interesting property of being
5464 // allowed in IT blocks, but not being predicable.
5465 static bool instIsBreakpoint(const MCInst &Inst) {
5466 return Inst.getOpcode() == ARM::tBKPT ||
5467 Inst.getOpcode() == ARM::BKPT ||
5468 Inst.getOpcode() == ARM::tHLT ||
5469 Inst.getOpcode() == ARM::HLT;
5473 // FIXME: We would really like to be able to tablegen'erate this.
5475 validateInstruction(MCInst &Inst,
5476 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5477 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5478 SMLoc Loc = Operands[0]->getStartLoc();
5480 // Check the IT block state first.
5481 // NOTE: BKPT and HLT instructions have the interesting property of being
5482 // allowed in IT blocks, but not being predicable. They just always execute.
5483 if (inITBlock() && !instIsBreakpoint(Inst)) {
5485 if (ITState.FirstCond)
5486 ITState.FirstCond = false;
5488 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5489 // The instruction must be predicable.
5490 if (!MCID.isPredicable())
5491 return Error(Loc, "instructions in IT block must be predicable");
5492 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5493 unsigned ITCond = Bit ? ITState.Cond :
5494 ARMCC::getOppositeCondition(ITState.Cond);
5495 if (Cond != ITCond) {
5496 // Find the condition code Operand to get its SMLoc information.
5498 for (unsigned I = 1; I < Operands.size(); ++I)
5499 if (static_cast<ARMOperand*>(Operands[I])->isCondCode())
5500 CondLoc = Operands[I]->getStartLoc();
5501 return Error(CondLoc, "incorrect condition in IT block; got '" +
5502 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5503 "', but expected '" +
5504 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5506 // Check for non-'al' condition codes outside of the IT block.
5507 } else if (isThumbTwo() && MCID.isPredicable() &&
5508 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5509 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5510 Inst.getOpcode() != ARM::t2Bcc)
5511 return Error(Loc, "predicated instructions must be in IT block");
5513 const unsigned Opcode = Inst.getOpcode();
5517 case ARM::LDRD_POST: {
5518 const unsigned RtReg = Inst.getOperand(0).getReg();
5521 if (RtReg == ARM::LR)
5522 return Error(Operands[3]->getStartLoc(),
5525 const unsigned Rt = MRI->getEncodingValue(RtReg);
5526 // Rt must be even-numbered.
5528 return Error(Operands[3]->getStartLoc(),
5529 "Rt must be even-numbered");
5531 // Rt2 must be Rt + 1.
5532 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5534 return Error(Operands[3]->getStartLoc(),
5535 "destination operands must be sequential");
5537 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5538 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5539 // For addressing modes with writeback, the base register needs to be
5540 // different from the destination registers.
5541 if (Rn == Rt || Rn == Rt2)
5542 return Error(Operands[3]->getStartLoc(),
5543 "base register needs to be different from destination "
5550 case ARM::t2LDRD_PRE:
5551 case ARM::t2LDRD_POST: {
5552 // Rt2 must be different from Rt.
5553 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5554 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5556 return Error(Operands[3]->getStartLoc(),
5557 "destination operands can't be identical");
5561 // Rt2 must be Rt + 1.
5562 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5563 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5565 return Error(Operands[3]->getStartLoc(),
5566 "source operands must be sequential");
5570 case ARM::STRD_POST: {
5571 // Rt2 must be Rt + 1.
5572 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5573 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5575 return Error(Operands[3]->getStartLoc(),
5576 "source operands must be sequential");
5581 // Width must be in range [1, 32-lsb].
5582 unsigned LSB = Inst.getOperand(2).getImm();
5583 unsigned Widthm1 = Inst.getOperand(3).getImm();
5584 if (Widthm1 >= 32 - LSB)
5585 return Error(Operands[5]->getStartLoc(),
5586 "bitfield width must be in range [1,32-lsb]");
5589 // Notionally handles ARM::tLDMIA_UPD too.
5591 // If we're parsing Thumb2, the .w variant is available and handles
5592 // most cases that are normally illegal for a Thumb1 LDM instruction.
5593 // We'll make the transformation in processInstruction() if necessary.
5595 // Thumb LDM instructions are writeback iff the base register is not
5596 // in the register list.
5597 unsigned Rn = Inst.getOperand(0).getReg();
5598 bool HasWritebackToken =
5599 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5600 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5601 bool ListContainsBase;
5602 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5603 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5604 "registers must be in range r0-r7");
5605 // If we should have writeback, then there should be a '!' token.
5606 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5607 return Error(Operands[2]->getStartLoc(),
5608 "writeback operator '!' expected");
5609 // If we should not have writeback, there must not be a '!'. This is
5610 // true even for the 32-bit wide encodings.
5611 if (ListContainsBase && HasWritebackToken)
5612 return Error(Operands[3]->getStartLoc(),
5613 "writeback operator '!' not allowed when base register "
5614 "in register list");
5618 case ARM::LDMIA_UPD:
5619 case ARM::LDMDB_UPD:
5620 case ARM::LDMIB_UPD:
5621 case ARM::LDMDA_UPD:
5622 // ARM variants loading and updating the same register are only officially
5623 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5627 case ARM::t2LDMIA_UPD:
5628 case ARM::t2LDMDB_UPD:
5629 case ARM::t2STMIA_UPD:
5630 case ARM::t2STMDB_UPD: {
5631 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5632 return Error(Operands.back()->getStartLoc(),
5633 "writeback register not allowed in register list");
5636 case ARM::sysLDMIA_UPD:
5637 case ARM::sysLDMDA_UPD:
5638 case ARM::sysLDMDB_UPD:
5639 case ARM::sysLDMIB_UPD:
5640 if (!listContainsReg(Inst, 3, ARM::PC))
5641 return Error(Operands[4]->getStartLoc(),
5642 "writeback register only allowed on system LDM "
5643 "if PC in register-list");
5645 case ARM::sysSTMIA_UPD:
5646 case ARM::sysSTMDA_UPD:
5647 case ARM::sysSTMDB_UPD:
5648 case ARM::sysSTMIB_UPD:
5649 return Error(Operands[2]->getStartLoc(),
5650 "system STM cannot have writeback register");
5653 // The second source operand must be the same register as the destination
5656 // In this case, we must directly check the parsed operands because the
5657 // cvtThumbMultiply() function is written in such a way that it guarantees
5658 // this first statement is always true for the new Inst. Essentially, the
5659 // destination is unconditionally copied into the second source operand
5660 // without checking to see if it matches what we actually parsed.
5661 if (Operands.size() == 6 &&
5662 (((ARMOperand*)Operands[3])->getReg() !=
5663 ((ARMOperand*)Operands[5])->getReg()) &&
5664 (((ARMOperand*)Operands[3])->getReg() !=
5665 ((ARMOperand*)Operands[4])->getReg())) {
5666 return Error(Operands[3]->getStartLoc(),
5667 "destination register must match source register");
5671 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5672 // so only issue a diagnostic for thumb1. The instructions will be
5673 // switched to the t2 encodings in processInstruction() if necessary.
5675 bool ListContainsBase;
5676 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5678 return Error(Operands[2]->getStartLoc(),
5679 "registers must be in range r0-r7 or pc");
5683 bool ListContainsBase;
5684 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5686 return Error(Operands[2]->getStartLoc(),
5687 "registers must be in range r0-r7 or lr");
5690 case ARM::tSTMIA_UPD: {
5691 bool ListContainsBase, InvalidLowList;
5692 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5693 0, ListContainsBase);
5694 if (InvalidLowList && !isThumbTwo())
5695 return Error(Operands[4]->getStartLoc(),
5696 "registers must be in range r0-r7");
5698 // This would be converted to a 32-bit stm, but that's not valid if the
5699 // writeback register is in the list.
5700 if (InvalidLowList && ListContainsBase)
5701 return Error(Operands[4]->getStartLoc(),
5702 "writeback operator '!' not allowed when base register "
5703 "in register list");
5706 case ARM::tADDrSP: {
5707 // If the non-SP source operand and the destination operand are not the
5708 // same, we need thumb2 (for the wide encoding), or we have an error.
5709 if (!isThumbTwo() &&
5710 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5711 return Error(Operands[4]->getStartLoc(),
5712 "source register must be the same as destination");
5716 // Final range checking for Thumb unconditional branch instructions.
5718 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5719 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5722 int op = (Operands[2]->isImm()) ? 2 : 3;
5723 if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5724 return Error(Operands[op]->getStartLoc(), "branch target out of range");
5727 // Final range checking for Thumb conditional branch instructions.
5729 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5730 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5733 int Op = (Operands[2]->isImm()) ? 2 : 3;
5734 if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>())
5735 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
5743 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5745 default: llvm_unreachable("unexpected opcode!");
5747 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5748 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5749 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5750 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5751 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5752 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5753 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5754 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5755 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5758 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5759 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5760 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5761 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5762 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5764 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5765 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5766 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5767 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5768 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5770 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5771 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5772 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5773 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5774 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5777 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5778 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5779 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5780 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5781 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5782 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5783 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5784 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5785 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5786 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5787 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5788 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5789 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5790 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5791 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5794 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5795 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5796 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5797 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5798 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5799 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5800 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5801 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5802 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5803 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5804 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5805 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5806 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5807 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5808 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5809 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5810 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5811 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5814 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5815 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5816 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5817 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5818 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5819 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5820 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5821 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5822 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5823 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5824 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5825 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5826 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5827 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5828 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5831 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5832 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5833 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5834 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5835 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5836 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5837 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5838 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5839 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5840 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5841 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5842 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5843 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5844 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5845 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5846 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5847 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5848 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5852 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5854 default: llvm_unreachable("unexpected opcode!");
5856 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5857 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5858 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5859 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5860 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5861 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5862 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5863 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5864 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5867 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5868 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5869 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5870 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5871 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5872 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5873 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5874 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5875 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5876 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5877 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5878 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5879 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5880 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5881 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5884 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5885 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5886 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5887 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5888 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5889 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5890 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5891 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5892 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5893 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5894 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5895 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5896 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5897 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5898 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5899 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5900 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5901 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5904 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5905 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5906 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5907 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5908 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5909 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5910 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5911 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5912 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5913 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5914 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5915 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5916 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5917 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5918 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5921 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5922 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5923 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5924 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5925 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5926 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5927 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5928 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5929 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5930 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5931 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5932 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5933 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5934 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5935 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5936 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5937 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5938 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5941 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5942 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5943 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5944 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5945 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5946 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5947 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5948 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5949 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5950 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5951 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5952 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5953 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5954 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5955 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5958 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5959 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5960 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5961 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5962 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5963 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5964 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5965 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5966 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5967 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5968 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5969 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5970 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5971 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5972 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5973 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5974 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5975 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5978 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5979 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5980 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5981 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5982 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5983 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5984 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5985 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5986 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5987 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5988 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5989 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5990 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5991 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5992 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5993 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5994 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5995 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6000 processInstruction(MCInst &Inst,
6001 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
6002 switch (Inst.getOpcode()) {
6003 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6004 case ARM::LDRT_POST:
6005 case ARM::LDRBT_POST: {
6006 const unsigned Opcode =
6007 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6008 : ARM::LDRBT_POST_IMM;
6010 TmpInst.setOpcode(Opcode);
6011 TmpInst.addOperand(Inst.getOperand(0));
6012 TmpInst.addOperand(Inst.getOperand(1));
6013 TmpInst.addOperand(Inst.getOperand(1));
6014 TmpInst.addOperand(MCOperand::CreateReg(0));
6015 TmpInst.addOperand(MCOperand::CreateImm(0));
6016 TmpInst.addOperand(Inst.getOperand(2));
6017 TmpInst.addOperand(Inst.getOperand(3));
6021 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6022 case ARM::STRT_POST:
6023 case ARM::STRBT_POST: {
6024 const unsigned Opcode =
6025 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6026 : ARM::STRBT_POST_IMM;
6028 TmpInst.setOpcode(Opcode);
6029 TmpInst.addOperand(Inst.getOperand(1));
6030 TmpInst.addOperand(Inst.getOperand(0));
6031 TmpInst.addOperand(Inst.getOperand(1));
6032 TmpInst.addOperand(MCOperand::CreateReg(0));
6033 TmpInst.addOperand(MCOperand::CreateImm(0));
6034 TmpInst.addOperand(Inst.getOperand(2));
6035 TmpInst.addOperand(Inst.getOperand(3));
6039 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6041 if (Inst.getOperand(1).getReg() != ARM::PC ||
6042 Inst.getOperand(5).getReg() != 0)
6045 TmpInst.setOpcode(ARM::ADR);
6046 TmpInst.addOperand(Inst.getOperand(0));
6047 TmpInst.addOperand(Inst.getOperand(2));
6048 TmpInst.addOperand(Inst.getOperand(3));
6049 TmpInst.addOperand(Inst.getOperand(4));
6053 // Aliases for alternate PC+imm syntax of LDR instructions.
6054 case ARM::t2LDRpcrel:
6055 // Select the narrow version if the immediate will fit.
6056 if (Inst.getOperand(1).getImm() > 0 &&
6057 Inst.getOperand(1).getImm() <= 0xff &&
6058 !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
6059 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
6060 Inst.setOpcode(ARM::tLDRpci);
6062 Inst.setOpcode(ARM::t2LDRpci);
6064 case ARM::t2LDRBpcrel:
6065 Inst.setOpcode(ARM::t2LDRBpci);
6067 case ARM::t2LDRHpcrel:
6068 Inst.setOpcode(ARM::t2LDRHpci);
6070 case ARM::t2LDRSBpcrel:
6071 Inst.setOpcode(ARM::t2LDRSBpci);
6073 case ARM::t2LDRSHpcrel:
6074 Inst.setOpcode(ARM::t2LDRSHpci);
6076 // Handle NEON VST complex aliases.
6077 case ARM::VST1LNdWB_register_Asm_8:
6078 case ARM::VST1LNdWB_register_Asm_16:
6079 case ARM::VST1LNdWB_register_Asm_32: {
6081 // Shuffle the operands around so the lane index operand is in the
6084 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6085 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6086 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6087 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6088 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6089 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6090 TmpInst.addOperand(Inst.getOperand(1)); // lane
6091 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6092 TmpInst.addOperand(Inst.getOperand(6));
6097 case ARM::VST2LNdWB_register_Asm_8:
6098 case ARM::VST2LNdWB_register_Asm_16:
6099 case ARM::VST2LNdWB_register_Asm_32:
6100 case ARM::VST2LNqWB_register_Asm_16:
6101 case ARM::VST2LNqWB_register_Asm_32: {
6103 // Shuffle the operands around so the lane index operand is in the
6106 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6107 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6108 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6109 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6110 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6111 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6112 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6114 TmpInst.addOperand(Inst.getOperand(1)); // lane
6115 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6116 TmpInst.addOperand(Inst.getOperand(6));
6121 case ARM::VST3LNdWB_register_Asm_8:
6122 case ARM::VST3LNdWB_register_Asm_16:
6123 case ARM::VST3LNdWB_register_Asm_32:
6124 case ARM::VST3LNqWB_register_Asm_16:
6125 case ARM::VST3LNqWB_register_Asm_32: {
6127 // Shuffle the operands around so the lane index operand is in the
6130 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6131 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6132 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6133 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6134 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6135 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6136 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6138 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6140 TmpInst.addOperand(Inst.getOperand(1)); // lane
6141 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6142 TmpInst.addOperand(Inst.getOperand(6));
6147 case ARM::VST4LNdWB_register_Asm_8:
6148 case ARM::VST4LNdWB_register_Asm_16:
6149 case ARM::VST4LNdWB_register_Asm_32:
6150 case ARM::VST4LNqWB_register_Asm_16:
6151 case ARM::VST4LNqWB_register_Asm_32: {
6153 // Shuffle the operands around so the lane index operand is in the
6156 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6157 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6158 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6159 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6160 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6161 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6162 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6164 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6166 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6168 TmpInst.addOperand(Inst.getOperand(1)); // lane
6169 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6170 TmpInst.addOperand(Inst.getOperand(6));
6175 case ARM::VST1LNdWB_fixed_Asm_8:
6176 case ARM::VST1LNdWB_fixed_Asm_16:
6177 case ARM::VST1LNdWB_fixed_Asm_32: {
6179 // Shuffle the operands around so the lane index operand is in the
6182 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6183 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6184 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6185 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6186 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6187 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6188 TmpInst.addOperand(Inst.getOperand(1)); // lane
6189 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6190 TmpInst.addOperand(Inst.getOperand(5));
6195 case ARM::VST2LNdWB_fixed_Asm_8:
6196 case ARM::VST2LNdWB_fixed_Asm_16:
6197 case ARM::VST2LNdWB_fixed_Asm_32:
6198 case ARM::VST2LNqWB_fixed_Asm_16:
6199 case ARM::VST2LNqWB_fixed_Asm_32: {
6201 // Shuffle the operands around so the lane index operand is in the
6204 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6205 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6206 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6207 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6208 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6209 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6210 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6212 TmpInst.addOperand(Inst.getOperand(1)); // lane
6213 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6214 TmpInst.addOperand(Inst.getOperand(5));
6219 case ARM::VST3LNdWB_fixed_Asm_8:
6220 case ARM::VST3LNdWB_fixed_Asm_16:
6221 case ARM::VST3LNdWB_fixed_Asm_32:
6222 case ARM::VST3LNqWB_fixed_Asm_16:
6223 case ARM::VST3LNqWB_fixed_Asm_32: {
6225 // Shuffle the operands around so the lane index operand is in the
6228 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6229 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6230 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6231 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6232 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6233 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6234 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6236 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6238 TmpInst.addOperand(Inst.getOperand(1)); // lane
6239 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6240 TmpInst.addOperand(Inst.getOperand(5));
6245 case ARM::VST4LNdWB_fixed_Asm_8:
6246 case ARM::VST4LNdWB_fixed_Asm_16:
6247 case ARM::VST4LNdWB_fixed_Asm_32:
6248 case ARM::VST4LNqWB_fixed_Asm_16:
6249 case ARM::VST4LNqWB_fixed_Asm_32: {
6251 // Shuffle the operands around so the lane index operand is in the
6254 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6255 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6256 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6257 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6258 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6259 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6260 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6262 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6264 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6266 TmpInst.addOperand(Inst.getOperand(1)); // lane
6267 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6268 TmpInst.addOperand(Inst.getOperand(5));
6273 case ARM::VST1LNdAsm_8:
6274 case ARM::VST1LNdAsm_16:
6275 case ARM::VST1LNdAsm_32: {
6277 // Shuffle the operands around so the lane index operand is in the
6280 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6281 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6282 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6283 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6284 TmpInst.addOperand(Inst.getOperand(1)); // lane
6285 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6286 TmpInst.addOperand(Inst.getOperand(5));
6291 case ARM::VST2LNdAsm_8:
6292 case ARM::VST2LNdAsm_16:
6293 case ARM::VST2LNdAsm_32:
6294 case ARM::VST2LNqAsm_16:
6295 case ARM::VST2LNqAsm_32: {
6297 // Shuffle the operands around so the lane index operand is in the
6300 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6301 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6302 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6303 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6304 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6306 TmpInst.addOperand(Inst.getOperand(1)); // lane
6307 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6308 TmpInst.addOperand(Inst.getOperand(5));
6313 case ARM::VST3LNdAsm_8:
6314 case ARM::VST3LNdAsm_16:
6315 case ARM::VST3LNdAsm_32:
6316 case ARM::VST3LNqAsm_16:
6317 case ARM::VST3LNqAsm_32: {
6319 // Shuffle the operands around so the lane index operand is in the
6322 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6323 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6324 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6325 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6326 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6328 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6330 TmpInst.addOperand(Inst.getOperand(1)); // lane
6331 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6332 TmpInst.addOperand(Inst.getOperand(5));
6337 case ARM::VST4LNdAsm_8:
6338 case ARM::VST4LNdAsm_16:
6339 case ARM::VST4LNdAsm_32:
6340 case ARM::VST4LNqAsm_16:
6341 case ARM::VST4LNqAsm_32: {
6343 // Shuffle the operands around so the lane index operand is in the
6346 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6347 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6348 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6349 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6350 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6352 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6354 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6356 TmpInst.addOperand(Inst.getOperand(1)); // lane
6357 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6358 TmpInst.addOperand(Inst.getOperand(5));
6363 // Handle NEON VLD complex aliases.
6364 case ARM::VLD1LNdWB_register_Asm_8:
6365 case ARM::VLD1LNdWB_register_Asm_16:
6366 case ARM::VLD1LNdWB_register_Asm_32: {
6368 // Shuffle the operands around so the lane index operand is in the
6371 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6372 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6373 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6374 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6375 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6376 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6377 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6378 TmpInst.addOperand(Inst.getOperand(1)); // lane
6379 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6380 TmpInst.addOperand(Inst.getOperand(6));
6385 case ARM::VLD2LNdWB_register_Asm_8:
6386 case ARM::VLD2LNdWB_register_Asm_16:
6387 case ARM::VLD2LNdWB_register_Asm_32:
6388 case ARM::VLD2LNqWB_register_Asm_16:
6389 case ARM::VLD2LNqWB_register_Asm_32: {
6391 // Shuffle the operands around so the lane index operand is in the
6394 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6395 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6396 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6398 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6399 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6400 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6401 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6402 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6403 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6405 TmpInst.addOperand(Inst.getOperand(1)); // lane
6406 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6407 TmpInst.addOperand(Inst.getOperand(6));
6412 case ARM::VLD3LNdWB_register_Asm_8:
6413 case ARM::VLD3LNdWB_register_Asm_16:
6414 case ARM::VLD3LNdWB_register_Asm_32:
6415 case ARM::VLD3LNqWB_register_Asm_16:
6416 case ARM::VLD3LNqWB_register_Asm_32: {
6418 // Shuffle the operands around so the lane index operand is in the
6421 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6422 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6423 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6425 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6427 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6428 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6429 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6430 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6431 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6432 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6434 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6436 TmpInst.addOperand(Inst.getOperand(1)); // lane
6437 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6438 TmpInst.addOperand(Inst.getOperand(6));
6443 case ARM::VLD4LNdWB_register_Asm_8:
6444 case ARM::VLD4LNdWB_register_Asm_16:
6445 case ARM::VLD4LNdWB_register_Asm_32:
6446 case ARM::VLD4LNqWB_register_Asm_16:
6447 case ARM::VLD4LNqWB_register_Asm_32: {
6449 // Shuffle the operands around so the lane index operand is in the
6452 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6453 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6454 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6456 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6458 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6460 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6461 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6462 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6463 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6464 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6465 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6467 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6469 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6471 TmpInst.addOperand(Inst.getOperand(1)); // lane
6472 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6473 TmpInst.addOperand(Inst.getOperand(6));
6478 case ARM::VLD1LNdWB_fixed_Asm_8:
6479 case ARM::VLD1LNdWB_fixed_Asm_16:
6480 case ARM::VLD1LNdWB_fixed_Asm_32: {
6482 // Shuffle the operands around so the lane index operand is in the
6485 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6486 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6487 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6488 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6489 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6490 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6491 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6492 TmpInst.addOperand(Inst.getOperand(1)); // lane
6493 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6494 TmpInst.addOperand(Inst.getOperand(5));
6499 case ARM::VLD2LNdWB_fixed_Asm_8:
6500 case ARM::VLD2LNdWB_fixed_Asm_16:
6501 case ARM::VLD2LNdWB_fixed_Asm_32:
6502 case ARM::VLD2LNqWB_fixed_Asm_16:
6503 case ARM::VLD2LNqWB_fixed_Asm_32: {
6505 // Shuffle the operands around so the lane index operand is in the
6508 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6509 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6510 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6512 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6513 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6514 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6515 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6516 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6517 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6519 TmpInst.addOperand(Inst.getOperand(1)); // lane
6520 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6521 TmpInst.addOperand(Inst.getOperand(5));
6526 case ARM::VLD3LNdWB_fixed_Asm_8:
6527 case ARM::VLD3LNdWB_fixed_Asm_16:
6528 case ARM::VLD3LNdWB_fixed_Asm_32:
6529 case ARM::VLD3LNqWB_fixed_Asm_16:
6530 case ARM::VLD3LNqWB_fixed_Asm_32: {
6532 // Shuffle the operands around so the lane index operand is in the
6535 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6536 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6537 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6539 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6541 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6542 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6543 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6544 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6545 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6546 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6548 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6550 TmpInst.addOperand(Inst.getOperand(1)); // lane
6551 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6552 TmpInst.addOperand(Inst.getOperand(5));
6557 case ARM::VLD4LNdWB_fixed_Asm_8:
6558 case ARM::VLD4LNdWB_fixed_Asm_16:
6559 case ARM::VLD4LNdWB_fixed_Asm_32:
6560 case ARM::VLD4LNqWB_fixed_Asm_16:
6561 case ARM::VLD4LNqWB_fixed_Asm_32: {
6563 // Shuffle the operands around so the lane index operand is in the
6566 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6567 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6568 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6570 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6572 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6574 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6575 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6576 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6577 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6578 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6579 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6581 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6583 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6585 TmpInst.addOperand(Inst.getOperand(1)); // lane
6586 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6587 TmpInst.addOperand(Inst.getOperand(5));
6592 case ARM::VLD1LNdAsm_8:
6593 case ARM::VLD1LNdAsm_16:
6594 case ARM::VLD1LNdAsm_32: {
6596 // Shuffle the operands around so the lane index operand is in the
6599 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6600 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6601 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6602 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6603 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6604 TmpInst.addOperand(Inst.getOperand(1)); // lane
6605 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6606 TmpInst.addOperand(Inst.getOperand(5));
6611 case ARM::VLD2LNdAsm_8:
6612 case ARM::VLD2LNdAsm_16:
6613 case ARM::VLD2LNdAsm_32:
6614 case ARM::VLD2LNqAsm_16:
6615 case ARM::VLD2LNqAsm_32: {
6617 // Shuffle the operands around so the lane index operand is in the
6620 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6621 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6622 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6624 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6625 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6626 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6627 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6629 TmpInst.addOperand(Inst.getOperand(1)); // lane
6630 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6631 TmpInst.addOperand(Inst.getOperand(5));
6636 case ARM::VLD3LNdAsm_8:
6637 case ARM::VLD3LNdAsm_16:
6638 case ARM::VLD3LNdAsm_32:
6639 case ARM::VLD3LNqAsm_16:
6640 case ARM::VLD3LNqAsm_32: {
6642 // Shuffle the operands around so the lane index operand is in the
6645 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6646 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6647 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6649 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6651 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6652 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6653 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6654 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6656 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6658 TmpInst.addOperand(Inst.getOperand(1)); // lane
6659 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6660 TmpInst.addOperand(Inst.getOperand(5));
6665 case ARM::VLD4LNdAsm_8:
6666 case ARM::VLD4LNdAsm_16:
6667 case ARM::VLD4LNdAsm_32:
6668 case ARM::VLD4LNqAsm_16:
6669 case ARM::VLD4LNqAsm_32: {
6671 // Shuffle the operands around so the lane index operand is in the
6674 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6675 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6676 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6678 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6680 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6682 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6683 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6684 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6685 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6687 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6689 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6691 TmpInst.addOperand(Inst.getOperand(1)); // lane
6692 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6693 TmpInst.addOperand(Inst.getOperand(5));
6698 // VLD3DUP single 3-element structure to all lanes instructions.
6699 case ARM::VLD3DUPdAsm_8:
6700 case ARM::VLD3DUPdAsm_16:
6701 case ARM::VLD3DUPdAsm_32:
6702 case ARM::VLD3DUPqAsm_8:
6703 case ARM::VLD3DUPqAsm_16:
6704 case ARM::VLD3DUPqAsm_32: {
6707 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6708 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6709 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6711 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6713 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6714 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6715 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6716 TmpInst.addOperand(Inst.getOperand(4));
6721 case ARM::VLD3DUPdWB_fixed_Asm_8:
6722 case ARM::VLD3DUPdWB_fixed_Asm_16:
6723 case ARM::VLD3DUPdWB_fixed_Asm_32:
6724 case ARM::VLD3DUPqWB_fixed_Asm_8:
6725 case ARM::VLD3DUPqWB_fixed_Asm_16:
6726 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6729 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6730 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6731 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6733 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6735 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6736 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6737 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6738 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6739 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6740 TmpInst.addOperand(Inst.getOperand(4));
6745 case ARM::VLD3DUPdWB_register_Asm_8:
6746 case ARM::VLD3DUPdWB_register_Asm_16:
6747 case ARM::VLD3DUPdWB_register_Asm_32:
6748 case ARM::VLD3DUPqWB_register_Asm_8:
6749 case ARM::VLD3DUPqWB_register_Asm_16:
6750 case ARM::VLD3DUPqWB_register_Asm_32: {
6753 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6754 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6755 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6757 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6759 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6760 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6761 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6762 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6763 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6764 TmpInst.addOperand(Inst.getOperand(5));
6769 // VLD3 multiple 3-element structure instructions.
6770 case ARM::VLD3dAsm_8:
6771 case ARM::VLD3dAsm_16:
6772 case ARM::VLD3dAsm_32:
6773 case ARM::VLD3qAsm_8:
6774 case ARM::VLD3qAsm_16:
6775 case ARM::VLD3qAsm_32: {
6778 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6779 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6780 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6782 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6784 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6785 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6786 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6787 TmpInst.addOperand(Inst.getOperand(4));
6792 case ARM::VLD3dWB_fixed_Asm_8:
6793 case ARM::VLD3dWB_fixed_Asm_16:
6794 case ARM::VLD3dWB_fixed_Asm_32:
6795 case ARM::VLD3qWB_fixed_Asm_8:
6796 case ARM::VLD3qWB_fixed_Asm_16:
6797 case ARM::VLD3qWB_fixed_Asm_32: {
6800 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6801 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6802 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6804 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6806 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6807 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6808 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6809 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6810 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6811 TmpInst.addOperand(Inst.getOperand(4));
6816 case ARM::VLD3dWB_register_Asm_8:
6817 case ARM::VLD3dWB_register_Asm_16:
6818 case ARM::VLD3dWB_register_Asm_32:
6819 case ARM::VLD3qWB_register_Asm_8:
6820 case ARM::VLD3qWB_register_Asm_16:
6821 case ARM::VLD3qWB_register_Asm_32: {
6824 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6825 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6826 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6828 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6830 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6831 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6832 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6833 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6834 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6835 TmpInst.addOperand(Inst.getOperand(5));
6840 // VLD4DUP single 3-element structure to all lanes instructions.
6841 case ARM::VLD4DUPdAsm_8:
6842 case ARM::VLD4DUPdAsm_16:
6843 case ARM::VLD4DUPdAsm_32:
6844 case ARM::VLD4DUPqAsm_8:
6845 case ARM::VLD4DUPqAsm_16:
6846 case ARM::VLD4DUPqAsm_32: {
6849 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6850 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6851 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6853 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6855 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6857 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6858 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6859 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6860 TmpInst.addOperand(Inst.getOperand(4));
6865 case ARM::VLD4DUPdWB_fixed_Asm_8:
6866 case ARM::VLD4DUPdWB_fixed_Asm_16:
6867 case ARM::VLD4DUPdWB_fixed_Asm_32:
6868 case ARM::VLD4DUPqWB_fixed_Asm_8:
6869 case ARM::VLD4DUPqWB_fixed_Asm_16:
6870 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6873 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6874 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6875 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6877 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6879 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6881 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6882 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6883 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6884 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6885 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6886 TmpInst.addOperand(Inst.getOperand(4));
6891 case ARM::VLD4DUPdWB_register_Asm_8:
6892 case ARM::VLD4DUPdWB_register_Asm_16:
6893 case ARM::VLD4DUPdWB_register_Asm_32:
6894 case ARM::VLD4DUPqWB_register_Asm_8:
6895 case ARM::VLD4DUPqWB_register_Asm_16:
6896 case ARM::VLD4DUPqWB_register_Asm_32: {
6899 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6900 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6901 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6903 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6905 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6907 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6908 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6909 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6910 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6911 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6912 TmpInst.addOperand(Inst.getOperand(5));
6917 // VLD4 multiple 4-element structure instructions.
6918 case ARM::VLD4dAsm_8:
6919 case ARM::VLD4dAsm_16:
6920 case ARM::VLD4dAsm_32:
6921 case ARM::VLD4qAsm_8:
6922 case ARM::VLD4qAsm_16:
6923 case ARM::VLD4qAsm_32: {
6926 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6927 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6928 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6930 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6932 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6934 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6935 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6936 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6937 TmpInst.addOperand(Inst.getOperand(4));
6942 case ARM::VLD4dWB_fixed_Asm_8:
6943 case ARM::VLD4dWB_fixed_Asm_16:
6944 case ARM::VLD4dWB_fixed_Asm_32:
6945 case ARM::VLD4qWB_fixed_Asm_8:
6946 case ARM::VLD4qWB_fixed_Asm_16:
6947 case ARM::VLD4qWB_fixed_Asm_32: {
6950 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6951 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6952 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6954 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6956 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6958 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6959 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6960 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6961 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6962 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6963 TmpInst.addOperand(Inst.getOperand(4));
6968 case ARM::VLD4dWB_register_Asm_8:
6969 case ARM::VLD4dWB_register_Asm_16:
6970 case ARM::VLD4dWB_register_Asm_32:
6971 case ARM::VLD4qWB_register_Asm_8:
6972 case ARM::VLD4qWB_register_Asm_16:
6973 case ARM::VLD4qWB_register_Asm_32: {
6976 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6977 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6978 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6980 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6982 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6984 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6985 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6986 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6987 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6988 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6989 TmpInst.addOperand(Inst.getOperand(5));
6994 // VST3 multiple 3-element structure instructions.
6995 case ARM::VST3dAsm_8:
6996 case ARM::VST3dAsm_16:
6997 case ARM::VST3dAsm_32:
6998 case ARM::VST3qAsm_8:
6999 case ARM::VST3qAsm_16:
7000 case ARM::VST3qAsm_32: {
7003 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7004 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7005 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7006 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7007 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7009 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7011 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7012 TmpInst.addOperand(Inst.getOperand(4));
7017 case ARM::VST3dWB_fixed_Asm_8:
7018 case ARM::VST3dWB_fixed_Asm_16:
7019 case ARM::VST3dWB_fixed_Asm_32:
7020 case ARM::VST3qWB_fixed_Asm_8:
7021 case ARM::VST3qWB_fixed_Asm_16:
7022 case ARM::VST3qWB_fixed_Asm_32: {
7025 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7026 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7027 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7028 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7029 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7030 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7031 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7033 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7035 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7036 TmpInst.addOperand(Inst.getOperand(4));
7041 case ARM::VST3dWB_register_Asm_8:
7042 case ARM::VST3dWB_register_Asm_16:
7043 case ARM::VST3dWB_register_Asm_32:
7044 case ARM::VST3qWB_register_Asm_8:
7045 case ARM::VST3qWB_register_Asm_16:
7046 case ARM::VST3qWB_register_Asm_32: {
7049 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7050 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7051 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7052 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7053 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7054 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7055 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7057 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7059 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7060 TmpInst.addOperand(Inst.getOperand(5));
7065 // VST4 multiple 3-element structure instructions.
7066 case ARM::VST4dAsm_8:
7067 case ARM::VST4dAsm_16:
7068 case ARM::VST4dAsm_32:
7069 case ARM::VST4qAsm_8:
7070 case ARM::VST4qAsm_16:
7071 case ARM::VST4qAsm_32: {
7074 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7075 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7076 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7077 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7078 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7080 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7082 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7084 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7085 TmpInst.addOperand(Inst.getOperand(4));
7090 case ARM::VST4dWB_fixed_Asm_8:
7091 case ARM::VST4dWB_fixed_Asm_16:
7092 case ARM::VST4dWB_fixed_Asm_32:
7093 case ARM::VST4qWB_fixed_Asm_8:
7094 case ARM::VST4qWB_fixed_Asm_16:
7095 case ARM::VST4qWB_fixed_Asm_32: {
7098 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7099 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7100 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7101 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7102 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7103 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7104 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7106 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7108 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7110 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7111 TmpInst.addOperand(Inst.getOperand(4));
7116 case ARM::VST4dWB_register_Asm_8:
7117 case ARM::VST4dWB_register_Asm_16:
7118 case ARM::VST4dWB_register_Asm_32:
7119 case ARM::VST4qWB_register_Asm_8:
7120 case ARM::VST4qWB_register_Asm_16:
7121 case ARM::VST4qWB_register_Asm_32: {
7124 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7125 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7126 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7127 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7128 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7129 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7130 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7132 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7134 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7136 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7137 TmpInst.addOperand(Inst.getOperand(5));
7142 // Handle encoding choice for the shift-immediate instructions.
7145 case ARM::t2ASRri: {
7146 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7147 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7148 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7149 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
7150 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
7152 switch (Inst.getOpcode()) {
7153 default: llvm_unreachable("unexpected opcode");
7154 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7155 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7156 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7158 // The Thumb1 operands aren't in the same order. Awesome, eh?
7160 TmpInst.setOpcode(NewOpc);
7161 TmpInst.addOperand(Inst.getOperand(0));
7162 TmpInst.addOperand(Inst.getOperand(5));
7163 TmpInst.addOperand(Inst.getOperand(1));
7164 TmpInst.addOperand(Inst.getOperand(2));
7165 TmpInst.addOperand(Inst.getOperand(3));
7166 TmpInst.addOperand(Inst.getOperand(4));
7173 // Handle the Thumb2 mode MOV complex aliases.
7175 case ARM::t2MOVSsr: {
7176 // Which instruction to expand to depends on the CCOut operand and
7177 // whether we're in an IT block if the register operands are low
7179 bool isNarrow = false;
7180 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7181 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7182 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7183 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7184 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7188 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7189 default: llvm_unreachable("unexpected opcode!");
7190 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7191 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7192 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7193 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7195 TmpInst.setOpcode(newOpc);
7196 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7198 TmpInst.addOperand(MCOperand::CreateReg(
7199 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7200 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7201 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7202 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7203 TmpInst.addOperand(Inst.getOperand(5));
7205 TmpInst.addOperand(MCOperand::CreateReg(
7206 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7211 case ARM::t2MOVSsi: {
7212 // Which instruction to expand to depends on the CCOut operand and
7213 // whether we're in an IT block if the register operands are low
7215 bool isNarrow = false;
7216 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7217 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7218 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7222 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7223 default: llvm_unreachable("unexpected opcode!");
7224 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7225 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7226 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7227 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7228 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7230 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7231 if (Amount == 32) Amount = 0;
7232 TmpInst.setOpcode(newOpc);
7233 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7235 TmpInst.addOperand(MCOperand::CreateReg(
7236 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7237 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7238 if (newOpc != ARM::t2RRX)
7239 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7240 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7241 TmpInst.addOperand(Inst.getOperand(4));
7243 TmpInst.addOperand(MCOperand::CreateReg(
7244 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7248 // Handle the ARM mode MOV complex aliases.
7253 ARM_AM::ShiftOpc ShiftTy;
7254 switch(Inst.getOpcode()) {
7255 default: llvm_unreachable("unexpected opcode!");
7256 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7257 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7258 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7259 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7261 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7263 TmpInst.setOpcode(ARM::MOVsr);
7264 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7265 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7266 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7267 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7268 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7269 TmpInst.addOperand(Inst.getOperand(4));
7270 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7278 ARM_AM::ShiftOpc ShiftTy;
7279 switch(Inst.getOpcode()) {
7280 default: llvm_unreachable("unexpected opcode!");
7281 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7282 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7283 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7284 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7286 // A shift by zero is a plain MOVr, not a MOVsi.
7287 unsigned Amt = Inst.getOperand(2).getImm();
7288 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7289 // A shift by 32 should be encoded as 0 when permitted
7290 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7292 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7294 TmpInst.setOpcode(Opc);
7295 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7296 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7297 if (Opc == ARM::MOVsi)
7298 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7299 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7300 TmpInst.addOperand(Inst.getOperand(4));
7301 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7306 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7308 TmpInst.setOpcode(ARM::MOVsi);
7309 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7310 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7311 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7312 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7313 TmpInst.addOperand(Inst.getOperand(3));
7314 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7318 case ARM::t2LDMIA_UPD: {
7319 // If this is a load of a single register, then we should use
7320 // a post-indexed LDR instruction instead, per the ARM ARM.
7321 if (Inst.getNumOperands() != 5)
7324 TmpInst.setOpcode(ARM::t2LDR_POST);
7325 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7326 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7327 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7328 TmpInst.addOperand(MCOperand::CreateImm(4));
7329 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7330 TmpInst.addOperand(Inst.getOperand(3));
7334 case ARM::t2STMDB_UPD: {
7335 // If this is a store of a single register, then we should use
7336 // a pre-indexed STR instruction instead, per the ARM ARM.
7337 if (Inst.getNumOperands() != 5)
7340 TmpInst.setOpcode(ARM::t2STR_PRE);
7341 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7342 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7343 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7344 TmpInst.addOperand(MCOperand::CreateImm(-4));
7345 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7346 TmpInst.addOperand(Inst.getOperand(3));
7350 case ARM::LDMIA_UPD:
7351 // If this is a load of a single register via a 'pop', then we should use
7352 // a post-indexed LDR instruction instead, per the ARM ARM.
7353 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7354 Inst.getNumOperands() == 5) {
7356 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7357 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7358 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7359 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7360 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7361 TmpInst.addOperand(MCOperand::CreateImm(4));
7362 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7363 TmpInst.addOperand(Inst.getOperand(3));
7368 case ARM::STMDB_UPD:
7369 // If this is a store of a single register via a 'push', then we should use
7370 // a pre-indexed STR instruction instead, per the ARM ARM.
7371 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7372 Inst.getNumOperands() == 5) {
7374 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7375 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7376 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7377 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7378 TmpInst.addOperand(MCOperand::CreateImm(-4));
7379 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7380 TmpInst.addOperand(Inst.getOperand(3));
7384 case ARM::t2ADDri12:
7385 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7386 // mnemonic was used (not "addw"), encoding T3 is preferred.
7387 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7388 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7390 Inst.setOpcode(ARM::t2ADDri);
7391 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7393 case ARM::t2SUBri12:
7394 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7395 // mnemonic was used (not "subw"), encoding T3 is preferred.
7396 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7397 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7399 Inst.setOpcode(ARM::t2SUBri);
7400 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7403 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7404 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7405 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7406 // to encoding T1 if <Rd> is omitted."
7407 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7408 Inst.setOpcode(ARM::tADDi3);
7413 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7414 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7415 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7416 // to encoding T1 if <Rd> is omitted."
7417 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7418 Inst.setOpcode(ARM::tSUBi3);
7423 case ARM::t2SUBri: {
7424 // If the destination and first source operand are the same, and
7425 // the flags are compatible with the current IT status, use encoding T2
7426 // instead of T3. For compatibility with the system 'as'. Make sure the
7427 // wide encoding wasn't explicit.
7428 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7429 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7430 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7431 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7432 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7433 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7434 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7437 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7438 ARM::tADDi8 : ARM::tSUBi8);
7439 TmpInst.addOperand(Inst.getOperand(0));
7440 TmpInst.addOperand(Inst.getOperand(5));
7441 TmpInst.addOperand(Inst.getOperand(0));
7442 TmpInst.addOperand(Inst.getOperand(2));
7443 TmpInst.addOperand(Inst.getOperand(3));
7444 TmpInst.addOperand(Inst.getOperand(4));
7448 case ARM::t2ADDrr: {
7449 // If the destination and first source operand are the same, and
7450 // there's no setting of the flags, use encoding T2 instead of T3.
7451 // Note that this is only for ADD, not SUB. This mirrors the system
7452 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7453 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7454 Inst.getOperand(5).getReg() != 0 ||
7455 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7456 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7459 TmpInst.setOpcode(ARM::tADDhirr);
7460 TmpInst.addOperand(Inst.getOperand(0));
7461 TmpInst.addOperand(Inst.getOperand(0));
7462 TmpInst.addOperand(Inst.getOperand(2));
7463 TmpInst.addOperand(Inst.getOperand(3));
7464 TmpInst.addOperand(Inst.getOperand(4));
7468 case ARM::tADDrSP: {
7469 // If the non-SP source operand and the destination operand are not the
7470 // same, we need to use the 32-bit encoding if it's available.
7471 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7472 Inst.setOpcode(ARM::t2ADDrr);
7473 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7479 // A Thumb conditional branch outside of an IT block is a tBcc.
7480 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7481 Inst.setOpcode(ARM::tBcc);
7486 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7487 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7488 Inst.setOpcode(ARM::t2Bcc);
7493 // If the conditional is AL or we're in an IT block, we really want t2B.
7494 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7495 Inst.setOpcode(ARM::t2B);
7500 // If the conditional is AL, we really want tB.
7501 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7502 Inst.setOpcode(ARM::tB);
7507 // If the register list contains any high registers, or if the writeback
7508 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7509 // instead if we're in Thumb2. Otherwise, this should have generated
7510 // an error in validateInstruction().
7511 unsigned Rn = Inst.getOperand(0).getReg();
7512 bool hasWritebackToken =
7513 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7514 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7515 bool listContainsBase;
7516 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7517 (!listContainsBase && !hasWritebackToken) ||
7518 (listContainsBase && hasWritebackToken)) {
7519 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7520 assert (isThumbTwo());
7521 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7522 // If we're switching to the updating version, we need to insert
7523 // the writeback tied operand.
7524 if (hasWritebackToken)
7525 Inst.insert(Inst.begin(),
7526 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7531 case ARM::tSTMIA_UPD: {
7532 // If the register list contains any high registers, we need to use
7533 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7534 // should have generated an error in validateInstruction().
7535 unsigned Rn = Inst.getOperand(0).getReg();
7536 bool listContainsBase;
7537 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7538 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7539 assert (isThumbTwo());
7540 Inst.setOpcode(ARM::t2STMIA_UPD);
7546 bool listContainsBase;
7547 // If the register list contains any high registers, we need to use
7548 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7549 // should have generated an error in validateInstruction().
7550 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7552 assert (isThumbTwo());
7553 Inst.setOpcode(ARM::t2LDMIA_UPD);
7554 // Add the base register and writeback operands.
7555 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7556 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7560 bool listContainsBase;
7561 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7563 assert (isThumbTwo());
7564 Inst.setOpcode(ARM::t2STMDB_UPD);
7565 // Add the base register and writeback operands.
7566 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7567 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7571 // If we can use the 16-bit encoding and the user didn't explicitly
7572 // request the 32-bit variant, transform it here.
7573 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7574 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7575 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7576 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7577 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7578 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7579 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7580 // The operands aren't in the same order for tMOVi8...
7582 TmpInst.setOpcode(ARM::tMOVi8);
7583 TmpInst.addOperand(Inst.getOperand(0));
7584 TmpInst.addOperand(Inst.getOperand(4));
7585 TmpInst.addOperand(Inst.getOperand(1));
7586 TmpInst.addOperand(Inst.getOperand(2));
7587 TmpInst.addOperand(Inst.getOperand(3));
7594 // If we can use the 16-bit encoding and the user didn't explicitly
7595 // request the 32-bit variant, transform it here.
7596 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7597 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7598 Inst.getOperand(2).getImm() == ARMCC::AL &&
7599 Inst.getOperand(4).getReg() == ARM::CPSR &&
7600 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7601 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7602 // The operands aren't the same for tMOV[S]r... (no cc_out)
7604 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7605 TmpInst.addOperand(Inst.getOperand(0));
7606 TmpInst.addOperand(Inst.getOperand(1));
7607 TmpInst.addOperand(Inst.getOperand(2));
7608 TmpInst.addOperand(Inst.getOperand(3));
7618 // If we can use the 16-bit encoding and the user didn't explicitly
7619 // request the 32-bit variant, transform it here.
7620 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7621 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7622 Inst.getOperand(2).getImm() == 0 &&
7623 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7624 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7626 switch (Inst.getOpcode()) {
7627 default: llvm_unreachable("Illegal opcode!");
7628 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7629 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7630 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7631 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7633 // The operands aren't the same for thumb1 (no rotate operand).
7635 TmpInst.setOpcode(NewOpc);
7636 TmpInst.addOperand(Inst.getOperand(0));
7637 TmpInst.addOperand(Inst.getOperand(1));
7638 TmpInst.addOperand(Inst.getOperand(3));
7639 TmpInst.addOperand(Inst.getOperand(4));
7646 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7647 // rrx shifts and asr/lsr of #32 is encoded as 0
7648 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7650 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7651 // Shifting by zero is accepted as a vanilla 'MOVr'
7653 TmpInst.setOpcode(ARM::MOVr);
7654 TmpInst.addOperand(Inst.getOperand(0));
7655 TmpInst.addOperand(Inst.getOperand(1));
7656 TmpInst.addOperand(Inst.getOperand(3));
7657 TmpInst.addOperand(Inst.getOperand(4));
7658 TmpInst.addOperand(Inst.getOperand(5));
7671 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7672 if (SOpc == ARM_AM::rrx) return false;
7673 switch (Inst.getOpcode()) {
7674 default: llvm_unreachable("unexpected opcode!");
7675 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7676 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7677 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7678 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7679 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7680 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7682 // If the shift is by zero, use the non-shifted instruction definition.
7683 // The exception is for right shifts, where 0 == 32
7684 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7685 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7687 TmpInst.setOpcode(newOpc);
7688 TmpInst.addOperand(Inst.getOperand(0));
7689 TmpInst.addOperand(Inst.getOperand(1));
7690 TmpInst.addOperand(Inst.getOperand(2));
7691 TmpInst.addOperand(Inst.getOperand(4));
7692 TmpInst.addOperand(Inst.getOperand(5));
7693 TmpInst.addOperand(Inst.getOperand(6));
7701 // The mask bits for all but the first condition are represented as
7702 // the low bit of the condition code value implies 't'. We currently
7703 // always have 1 implies 't', so XOR toggle the bits if the low bit
7704 // of the condition code is zero.
7705 MCOperand &MO = Inst.getOperand(1);
7706 unsigned Mask = MO.getImm();
7707 unsigned OrigMask = Mask;
7708 unsigned TZ = countTrailingZeros(Mask);
7709 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7710 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7711 Mask ^= (0xE << TZ) & 0xF;
7715 // Set up the IT block state according to the IT instruction we just
7717 assert(!inITBlock() && "nested IT blocks?!");
7718 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7719 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7720 ITState.CurPosition = 0;
7721 ITState.FirstCond = true;
7731 // Assemblers should use the narrow encodings of these instructions when permissible.
7732 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7733 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7734 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7735 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7736 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7737 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7738 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7740 switch (Inst.getOpcode()) {
7741 default: llvm_unreachable("unexpected opcode");
7742 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7743 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7744 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7745 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7746 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7747 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7750 TmpInst.setOpcode(NewOpc);
7751 TmpInst.addOperand(Inst.getOperand(0));
7752 TmpInst.addOperand(Inst.getOperand(5));
7753 TmpInst.addOperand(Inst.getOperand(1));
7754 TmpInst.addOperand(Inst.getOperand(2));
7755 TmpInst.addOperand(Inst.getOperand(3));
7756 TmpInst.addOperand(Inst.getOperand(4));
7767 // Assemblers should use the narrow encodings of these instructions when permissible.
7768 // These instructions are special in that they are commutable, so shorter encodings
7769 // are available more often.
7770 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7771 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7772 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7773 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7774 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7775 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7776 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7777 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7779 switch (Inst.getOpcode()) {
7780 default: llvm_unreachable("unexpected opcode");
7781 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7782 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7783 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7784 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7787 TmpInst.setOpcode(NewOpc);
7788 TmpInst.addOperand(Inst.getOperand(0));
7789 TmpInst.addOperand(Inst.getOperand(5));
7790 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7791 TmpInst.addOperand(Inst.getOperand(1));
7792 TmpInst.addOperand(Inst.getOperand(2));
7794 TmpInst.addOperand(Inst.getOperand(2));
7795 TmpInst.addOperand(Inst.getOperand(1));
7797 TmpInst.addOperand(Inst.getOperand(3));
7798 TmpInst.addOperand(Inst.getOperand(4));
7808 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7809 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7810 // suffix depending on whether they're in an IT block or not.
7811 unsigned Opc = Inst.getOpcode();
7812 const MCInstrDesc &MCID = MII.get(Opc);
7813 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7814 assert(MCID.hasOptionalDef() &&
7815 "optionally flag setting instruction missing optional def operand");
7816 assert(MCID.NumOperands == Inst.getNumOperands() &&
7817 "operand count mismatch!");
7818 // Find the optional-def operand (cc_out).
7821 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7824 // If we're parsing Thumb1, reject it completely.
7825 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7826 return Match_MnemonicFail;
7827 // If we're parsing Thumb2, which form is legal depends on whether we're
7829 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7831 return Match_RequiresITBlock;
7832 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7834 return Match_RequiresNotITBlock;
7836 // Some high-register supporting Thumb1 encodings only allow both registers
7837 // to be from r0-r7 when in Thumb2.
7838 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7839 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7840 isARMLowRegister(Inst.getOperand(2).getReg()))
7841 return Match_RequiresThumb2;
7842 // Others only require ARMv6 or later.
7843 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7844 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7845 isARMLowRegister(Inst.getOperand(1).getReg()))
7846 return Match_RequiresV6;
7847 return Match_Success;
7850 static const char *getSubtargetFeatureName(unsigned Val);
7852 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7853 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7854 MCStreamer &Out, unsigned &ErrorInfo,
7855 bool MatchingInlineAsm) {
7857 unsigned MatchResult;
7859 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7861 switch (MatchResult) {
7864 // Context sensitive operand constraints aren't handled by the matcher,
7865 // so check them here.
7866 if (validateInstruction(Inst, Operands)) {
7867 // Still progress the IT block, otherwise one wrong condition causes
7868 // nasty cascading errors.
7869 forwardITPosition();
7873 { // processInstruction() updates inITBlock state, we need to save it away
7874 bool wasInITBlock = inITBlock();
7876 // Some instructions need post-processing to, for example, tweak which
7877 // encoding is selected. Loop on it while changes happen so the
7878 // individual transformations can chain off each other. E.g.,
7879 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7880 while (processInstruction(Inst, Operands))
7883 // Only after the instruction is fully processed, we can validate it
7884 if (wasInITBlock && hasV8Ops() && isThumb() &&
7885 !isV8EligibleForIT(&Inst)) {
7886 Warning(IDLoc, "deprecated instruction in IT block");
7890 // Only move forward at the very end so that everything in validate
7891 // and process gets a consistent answer about whether we're in an IT
7893 forwardITPosition();
7895 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7896 // doesn't actually encode.
7897 if (Inst.getOpcode() == ARM::ITasm)
7901 Out.EmitInstruction(Inst, STI);
7903 case Match_MissingFeature: {
7904 assert(ErrorInfo && "Unknown missing feature!");
7905 // Special case the error message for the very common case where only
7906 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7907 std::string Msg = "instruction requires:";
7909 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7910 if (ErrorInfo & Mask) {
7912 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7916 return Error(IDLoc, Msg);
7918 case Match_InvalidOperand: {
7919 SMLoc ErrorLoc = IDLoc;
7920 if (ErrorInfo != ~0U) {
7921 if (ErrorInfo >= Operands.size())
7922 return Error(IDLoc, "too few operands for instruction");
7924 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7925 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7928 return Error(ErrorLoc, "invalid operand for instruction");
7930 case Match_MnemonicFail:
7931 return Error(IDLoc, "invalid instruction",
7932 ((ARMOperand*)Operands[0])->getLocRange());
7933 case Match_RequiresNotITBlock:
7934 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7935 case Match_RequiresITBlock:
7936 return Error(IDLoc, "instruction only valid inside IT block");
7937 case Match_RequiresV6:
7938 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7939 case Match_RequiresThumb2:
7940 return Error(IDLoc, "instruction variant requires Thumb2");
7941 case Match_ImmRange0_15: {
7942 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7943 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7944 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7946 case Match_ImmRange0_239: {
7947 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7948 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7949 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
7953 llvm_unreachable("Implement any new match types added!");
7956 /// parseDirective parses the arm specific directives
7957 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7958 StringRef IDVal = DirectiveID.getIdentifier();
7959 if (IDVal == ".word")
7960 return parseDirectiveWord(4, DirectiveID.getLoc());
7961 else if (IDVal == ".thumb")
7962 return parseDirectiveThumb(DirectiveID.getLoc());
7963 else if (IDVal == ".arm")
7964 return parseDirectiveARM(DirectiveID.getLoc());
7965 else if (IDVal == ".thumb_func")
7966 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7967 else if (IDVal == ".code")
7968 return parseDirectiveCode(DirectiveID.getLoc());
7969 else if (IDVal == ".syntax")
7970 return parseDirectiveSyntax(DirectiveID.getLoc());
7971 else if (IDVal == ".unreq")
7972 return parseDirectiveUnreq(DirectiveID.getLoc());
7973 else if (IDVal == ".arch")
7974 return parseDirectiveArch(DirectiveID.getLoc());
7975 else if (IDVal == ".eabi_attribute")
7976 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7977 else if (IDVal == ".cpu")
7978 return parseDirectiveCPU(DirectiveID.getLoc());
7979 else if (IDVal == ".fpu")
7980 return parseDirectiveFPU(DirectiveID.getLoc());
7981 else if (IDVal == ".fnstart")
7982 return parseDirectiveFnStart(DirectiveID.getLoc());
7983 else if (IDVal == ".fnend")
7984 return parseDirectiveFnEnd(DirectiveID.getLoc());
7985 else if (IDVal == ".cantunwind")
7986 return parseDirectiveCantUnwind(DirectiveID.getLoc());
7987 else if (IDVal == ".personality")
7988 return parseDirectivePersonality(DirectiveID.getLoc());
7989 else if (IDVal == ".handlerdata")
7990 return parseDirectiveHandlerData(DirectiveID.getLoc());
7991 else if (IDVal == ".setfp")
7992 return parseDirectiveSetFP(DirectiveID.getLoc());
7993 else if (IDVal == ".pad")
7994 return parseDirectivePad(DirectiveID.getLoc());
7995 else if (IDVal == ".save")
7996 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
7997 else if (IDVal == ".vsave")
7998 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
7999 else if (IDVal == ".inst")
8000 return parseDirectiveInst(DirectiveID.getLoc());
8001 else if (IDVal == ".inst.n")
8002 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8003 else if (IDVal == ".inst.w")
8004 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8005 else if (IDVal == ".ltorg" || IDVal == ".pool")
8006 return parseDirectiveLtorg(DirectiveID.getLoc());
8007 else if (IDVal == ".even")
8008 return parseDirectiveEven(DirectiveID.getLoc());
8009 else if (IDVal == ".personalityindex")
8010 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8011 else if (IDVal == ".unwind_raw")
8012 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8013 else if (IDVal == ".tlsdescseq")
8014 return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8015 else if (IDVal == ".movsp")
8016 return parseDirectiveMovSP(DirectiveID.getLoc());
8017 else if (IDVal == ".object_arch")
8018 return parseDirectiveObjectArch(DirectiveID.getLoc());
8022 /// parseDirectiveWord
8023 /// ::= .word [ expression (, expression)* ]
8024 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
8025 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8027 const MCExpr *Value;
8028 if (getParser().parseExpression(Value)) {
8029 Parser.eatToEndOfStatement();
8033 getParser().getStreamer().EmitValue(Value, Size);
8035 if (getLexer().is(AsmToken::EndOfStatement))
8038 // FIXME: Improve diagnostic.
8039 if (getLexer().isNot(AsmToken::Comma)) {
8040 Error(L, "unexpected token in directive");
8051 /// parseDirectiveThumb
8053 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8054 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8055 Error(L, "unexpected token in directive");
8061 Error(L, "target does not support Thumb mode");
8067 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8071 /// parseDirectiveARM
8073 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8074 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8075 Error(L, "unexpected token in directive");
8081 Error(L, "target does not support ARM mode");
8087 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8091 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8092 if (NextSymbolIsThumb) {
8093 getParser().getStreamer().EmitThumbFunc(Symbol);
8094 NextSymbolIsThumb = false;
8098 /// parseDirectiveThumbFunc
8099 /// ::= .thumbfunc symbol_name
8100 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8101 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8102 bool isMachO = MAI->hasSubsectionsViaSymbols();
8104 // Darwin asm has (optionally) function name after .thumb_func direction
8107 const AsmToken &Tok = Parser.getTok();
8108 if (Tok.isNot(AsmToken::EndOfStatement)) {
8109 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8110 Error(L, "unexpected token in .thumb_func directive");
8115 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8116 getParser().getStreamer().EmitThumbFunc(Func);
8117 Parser.Lex(); // Consume the identifier token.
8122 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8123 Error(L, "unexpected token in directive");
8127 NextSymbolIsThumb = true;
8131 /// parseDirectiveSyntax
8132 /// ::= .syntax unified | divided
8133 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8134 const AsmToken &Tok = Parser.getTok();
8135 if (Tok.isNot(AsmToken::Identifier)) {
8136 Error(L, "unexpected token in .syntax directive");
8140 StringRef Mode = Tok.getString();
8141 if (Mode == "unified" || Mode == "UNIFIED") {
8143 } else if (Mode == "divided" || Mode == "DIVIDED") {
8144 Error(L, "'.syntax divided' arm asssembly not supported");
8147 Error(L, "unrecognized syntax mode in .syntax directive");
8151 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8152 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8157 // TODO tell the MC streamer the mode
8158 // getParser().getStreamer().Emit???();
8162 /// parseDirectiveCode
8163 /// ::= .code 16 | 32
8164 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8165 const AsmToken &Tok = Parser.getTok();
8166 if (Tok.isNot(AsmToken::Integer)) {
8167 Error(L, "unexpected token in .code directive");
8170 int64_t Val = Parser.getTok().getIntVal();
8171 if (Val != 16 && Val != 32) {
8172 Error(L, "invalid operand to .code directive");
8177 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8178 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8185 Error(L, "target does not support Thumb mode");
8191 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8194 Error(L, "target does not support ARM mode");
8200 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8206 /// parseDirectiveReq
8207 /// ::= name .req registername
8208 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8209 Parser.Lex(); // Eat the '.req' token.
8211 SMLoc SRegLoc, ERegLoc;
8212 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8213 Parser.eatToEndOfStatement();
8214 Error(SRegLoc, "register name expected");
8218 // Shouldn't be anything else.
8219 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8220 Parser.eatToEndOfStatement();
8221 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8225 Parser.Lex(); // Consume the EndOfStatement
8227 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8228 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8235 /// parseDirectiveUneq
8236 /// ::= .unreq registername
8237 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8238 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8239 Parser.eatToEndOfStatement();
8240 Error(L, "unexpected input in .unreq directive.");
8243 RegisterReqs.erase(Parser.getTok().getIdentifier());
8244 Parser.Lex(); // Eat the identifier.
8248 /// parseDirectiveArch
8250 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8251 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8253 unsigned ID = StringSwitch<unsigned>(Arch)
8254 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8255 .Case(NAME, ARM::ID)
8256 #define ARM_ARCH_ALIAS(NAME, ID) \
8257 .Case(NAME, ARM::ID)
8258 #include "MCTargetDesc/ARMArchName.def"
8259 .Default(ARM::INVALID_ARCH);
8261 if (ID == ARM::INVALID_ARCH) {
8262 Error(L, "Unknown arch name");
8266 getTargetStreamer().emitArch(ID);
8270 /// parseDirectiveEabiAttr
8271 /// ::= .eabi_attribute int, int [, "str"]
8272 /// ::= .eabi_attribute Tag_name, int [, "str"]
8273 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8277 TagLoc = Parser.getTok().getLoc();
8278 if (Parser.getTok().is(AsmToken::Identifier)) {
8279 StringRef Name = Parser.getTok().getIdentifier();
8280 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8282 Error(TagLoc, "attribute name not recognised: " + Name);
8283 Parser.eatToEndOfStatement();
8288 const MCExpr *AttrExpr;
8290 TagLoc = Parser.getTok().getLoc();
8291 if (Parser.parseExpression(AttrExpr)) {
8292 Parser.eatToEndOfStatement();
8296 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8298 Error(TagLoc, "expected numeric constant");
8299 Parser.eatToEndOfStatement();
8303 Tag = CE->getValue();
8306 if (Parser.getTok().isNot(AsmToken::Comma)) {
8307 Error(Parser.getTok().getLoc(), "comma expected");
8308 Parser.eatToEndOfStatement();
8311 Parser.Lex(); // skip comma
8313 StringRef StringValue = "";
8314 bool IsStringValue = false;
8316 int64_t IntegerValue = 0;
8317 bool IsIntegerValue = false;
8319 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8320 IsStringValue = true;
8321 else if (Tag == ARMBuildAttrs::compatibility) {
8322 IsStringValue = true;
8323 IsIntegerValue = true;
8324 } else if (Tag < 32 || Tag % 2 == 0)
8325 IsIntegerValue = true;
8326 else if (Tag % 2 == 1)
8327 IsStringValue = true;
8329 llvm_unreachable("invalid tag type");
8331 if (IsIntegerValue) {
8332 const MCExpr *ValueExpr;
8333 SMLoc ValueExprLoc = Parser.getTok().getLoc();
8334 if (Parser.parseExpression(ValueExpr)) {
8335 Parser.eatToEndOfStatement();
8339 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8341 Error(ValueExprLoc, "expected numeric constant");
8342 Parser.eatToEndOfStatement();
8346 IntegerValue = CE->getValue();
8349 if (Tag == ARMBuildAttrs::compatibility) {
8350 if (Parser.getTok().isNot(AsmToken::Comma))
8351 IsStringValue = false;
8356 if (IsStringValue) {
8357 if (Parser.getTok().isNot(AsmToken::String)) {
8358 Error(Parser.getTok().getLoc(), "bad string constant");
8359 Parser.eatToEndOfStatement();
8363 StringValue = Parser.getTok().getStringContents();
8367 if (IsIntegerValue && IsStringValue) {
8368 assert(Tag == ARMBuildAttrs::compatibility);
8369 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8370 } else if (IsIntegerValue)
8371 getTargetStreamer().emitAttribute(Tag, IntegerValue);
8372 else if (IsStringValue)
8373 getTargetStreamer().emitTextAttribute(Tag, StringValue);
8377 /// parseDirectiveCPU
8379 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8380 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8381 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8385 /// parseDirectiveFPU
8387 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8388 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8390 unsigned ID = StringSwitch<unsigned>(FPU)
8391 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8392 #include "ARMFPUName.def"
8393 .Default(ARM::INVALID_FPU);
8395 if (ID == ARM::INVALID_FPU) {
8396 Error(L, "Unknown FPU name");
8400 getTargetStreamer().emitFPU(ID);
8404 /// parseDirectiveFnStart
8406 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8407 if (UC.hasFnStart()) {
8408 Error(L, ".fnstart starts before the end of previous one");
8409 UC.emitFnStartLocNotes();
8413 // Reset the unwind directives parser state
8416 getTargetStreamer().emitFnStart();
8418 UC.recordFnStart(L);
8422 /// parseDirectiveFnEnd
8424 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8425 // Check the ordering of unwind directives
8426 if (!UC.hasFnStart()) {
8427 Error(L, ".fnstart must precede .fnend directive");
8431 // Reset the unwind directives parser state
8432 getTargetStreamer().emitFnEnd();
8438 /// parseDirectiveCantUnwind
8440 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8441 UC.recordCantUnwind(L);
8443 // Check the ordering of unwind directives
8444 if (!UC.hasFnStart()) {
8445 Error(L, ".fnstart must precede .cantunwind directive");
8448 if (UC.hasHandlerData()) {
8449 Error(L, ".cantunwind can't be used with .handlerdata directive");
8450 UC.emitHandlerDataLocNotes();
8453 if (UC.hasPersonality()) {
8454 Error(L, ".cantunwind can't be used with .personality directive");
8455 UC.emitPersonalityLocNotes();
8459 getTargetStreamer().emitCantUnwind();
8463 /// parseDirectivePersonality
8464 /// ::= .personality name
8465 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8466 bool HasExistingPersonality = UC.hasPersonality();
8468 UC.recordPersonality(L);
8470 // Check the ordering of unwind directives
8471 if (!UC.hasFnStart()) {
8472 Error(L, ".fnstart must precede .personality directive");
8475 if (UC.cantUnwind()) {
8476 Error(L, ".personality can't be used with .cantunwind directive");
8477 UC.emitCantUnwindLocNotes();
8480 if (UC.hasHandlerData()) {
8481 Error(L, ".personality must precede .handlerdata directive");
8482 UC.emitHandlerDataLocNotes();
8485 if (HasExistingPersonality) {
8486 Parser.eatToEndOfStatement();
8487 Error(L, "multiple personality directives");
8488 UC.emitPersonalityLocNotes();
8492 // Parse the name of the personality routine
8493 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8494 Parser.eatToEndOfStatement();
8495 Error(L, "unexpected input in .personality directive.");
8498 StringRef Name(Parser.getTok().getIdentifier());
8501 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8502 getTargetStreamer().emitPersonality(PR);
8506 /// parseDirectiveHandlerData
8507 /// ::= .handlerdata
8508 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8509 UC.recordHandlerData(L);
8511 // Check the ordering of unwind directives
8512 if (!UC.hasFnStart()) {
8513 Error(L, ".fnstart must precede .personality directive");
8516 if (UC.cantUnwind()) {
8517 Error(L, ".handlerdata can't be used with .cantunwind directive");
8518 UC.emitCantUnwindLocNotes();
8522 getTargetStreamer().emitHandlerData();
8526 /// parseDirectiveSetFP
8527 /// ::= .setfp fpreg, spreg [, offset]
8528 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8529 // Check the ordering of unwind directives
8530 if (!UC.hasFnStart()) {
8531 Error(L, ".fnstart must precede .setfp directive");
8534 if (UC.hasHandlerData()) {
8535 Error(L, ".setfp must precede .handlerdata directive");
8540 SMLoc FPRegLoc = Parser.getTok().getLoc();
8541 int FPReg = tryParseRegister();
8543 Error(FPRegLoc, "frame pointer register expected");
8548 if (Parser.getTok().isNot(AsmToken::Comma)) {
8549 Error(Parser.getTok().getLoc(), "comma expected");
8552 Parser.Lex(); // skip comma
8555 SMLoc SPRegLoc = Parser.getTok().getLoc();
8556 int SPReg = tryParseRegister();
8558 Error(SPRegLoc, "stack pointer register expected");
8562 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
8563 Error(SPRegLoc, "register should be either $sp or the latest fp register");
8567 // Update the frame pointer register
8568 UC.saveFPReg(FPReg);
8572 if (Parser.getTok().is(AsmToken::Comma)) {
8573 Parser.Lex(); // skip comma
8575 if (Parser.getTok().isNot(AsmToken::Hash) &&
8576 Parser.getTok().isNot(AsmToken::Dollar)) {
8577 Error(Parser.getTok().getLoc(), "'#' expected");
8580 Parser.Lex(); // skip hash token.
8582 const MCExpr *OffsetExpr;
8583 SMLoc ExLoc = Parser.getTok().getLoc();
8585 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8586 Error(ExLoc, "malformed setfp offset");
8589 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8591 Error(ExLoc, "setfp offset must be an immediate");
8595 Offset = CE->getValue();
8598 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
8599 static_cast<unsigned>(SPReg), Offset);
8605 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8606 // Check the ordering of unwind directives
8607 if (!UC.hasFnStart()) {
8608 Error(L, ".fnstart must precede .pad directive");
8611 if (UC.hasHandlerData()) {
8612 Error(L, ".pad must precede .handlerdata directive");
8617 if (Parser.getTok().isNot(AsmToken::Hash) &&
8618 Parser.getTok().isNot(AsmToken::Dollar)) {
8619 Error(Parser.getTok().getLoc(), "'#' expected");
8622 Parser.Lex(); // skip hash token.
8624 const MCExpr *OffsetExpr;
8625 SMLoc ExLoc = Parser.getTok().getLoc();
8627 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8628 Error(ExLoc, "malformed pad offset");
8631 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8633 Error(ExLoc, "pad offset must be an immediate");
8637 getTargetStreamer().emitPad(CE->getValue());
8641 /// parseDirectiveRegSave
8642 /// ::= .save { registers }
8643 /// ::= .vsave { registers }
8644 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8645 // Check the ordering of unwind directives
8646 if (!UC.hasFnStart()) {
8647 Error(L, ".fnstart must precede .save or .vsave directives");
8650 if (UC.hasHandlerData()) {
8651 Error(L, ".save or .vsave must precede .handlerdata directive");
8655 // RAII object to make sure parsed operands are deleted.
8656 struct CleanupObject {
8657 SmallVector<MCParsedAsmOperand *, 1> Operands;
8659 for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8664 // Parse the register list
8665 if (parseRegisterList(CO.Operands))
8667 ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8668 if (!IsVector && !Op->isRegList()) {
8669 Error(L, ".save expects GPR registers");
8672 if (IsVector && !Op->isDPRRegList()) {
8673 Error(L, ".vsave expects DPR registers");
8677 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector);
8681 /// parseDirectiveInst
8682 /// ::= .inst opcode [, ...]
8683 /// ::= .inst.n opcode [, ...]
8684 /// ::= .inst.w opcode [, ...]
8685 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
8697 Parser.eatToEndOfStatement();
8698 Error(Loc, "cannot determine Thumb instruction size, "
8699 "use inst.n/inst.w instead");
8704 Parser.eatToEndOfStatement();
8705 Error(Loc, "width suffixes are invalid in ARM mode");
8711 if (getLexer().is(AsmToken::EndOfStatement)) {
8712 Parser.eatToEndOfStatement();
8713 Error(Loc, "expected expression following directive");
8720 if (getParser().parseExpression(Expr)) {
8721 Error(Loc, "expected expression");
8725 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
8727 Error(Loc, "expected constant expression");
8733 if (Value->getValue() > 0xffff) {
8734 Error(Loc, "inst.n operand is too big, use inst.w instead");
8739 if (Value->getValue() > 0xffffffff) {
8741 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
8746 llvm_unreachable("only supported widths are 2 and 4");
8749 getTargetStreamer().emitInst(Value->getValue(), Suffix);
8751 if (getLexer().is(AsmToken::EndOfStatement))
8754 if (getLexer().isNot(AsmToken::Comma)) {
8755 Error(Loc, "unexpected token in directive");
8766 /// parseDirectiveLtorg
8767 /// ::= .ltorg | .pool
8768 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
8769 getTargetStreamer().emitCurrentConstantPool();
8773 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
8774 const MCSection *Section = getStreamer().getCurrentSection().first;
8776 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8777 TokError("unexpected token in directive");
8782 getStreamer().InitSections();
8783 Section = getStreamer().getCurrentSection().first;
8786 if (Section->UseCodeAlign())
8787 getStreamer().EmitCodeAlignment(2, 0);
8789 getStreamer().EmitValueToAlignment(2, 0, 1, 0);
8794 /// parseDirectivePersonalityIndex
8795 /// ::= .personalityindex index
8796 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
8797 bool HasExistingPersonality = UC.hasPersonality();
8799 UC.recordPersonalityIndex(L);
8801 if (!UC.hasFnStart()) {
8802 Parser.eatToEndOfStatement();
8803 Error(L, ".fnstart must precede .personalityindex directive");
8806 if (UC.cantUnwind()) {
8807 Parser.eatToEndOfStatement();
8808 Error(L, ".personalityindex cannot be used with .cantunwind");
8809 UC.emitCantUnwindLocNotes();
8812 if (UC.hasHandlerData()) {
8813 Parser.eatToEndOfStatement();
8814 Error(L, ".personalityindex must precede .handlerdata directive");
8815 UC.emitHandlerDataLocNotes();
8818 if (HasExistingPersonality) {
8819 Parser.eatToEndOfStatement();
8820 Error(L, "multiple personality directives");
8821 UC.emitPersonalityLocNotes();
8825 const MCExpr *IndexExpression;
8826 SMLoc IndexLoc = Parser.getTok().getLoc();
8827 if (Parser.parseExpression(IndexExpression)) {
8828 Parser.eatToEndOfStatement();
8832 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
8834 Parser.eatToEndOfStatement();
8835 Error(IndexLoc, "index must be a constant number");
8838 if (CE->getValue() < 0 ||
8839 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
8840 Parser.eatToEndOfStatement();
8841 Error(IndexLoc, "personality routine index should be in range [0-3]");
8845 getTargetStreamer().emitPersonalityIndex(CE->getValue());
8849 /// parseDirectiveUnwindRaw
8850 /// ::= .unwind_raw offset, opcode [, opcode...]
8851 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
8852 if (!UC.hasFnStart()) {
8853 Parser.eatToEndOfStatement();
8854 Error(L, ".fnstart must precede .unwind_raw directives");
8858 int64_t StackOffset;
8860 const MCExpr *OffsetExpr;
8861 SMLoc OffsetLoc = getLexer().getLoc();
8862 if (getLexer().is(AsmToken::EndOfStatement) ||
8863 getParser().parseExpression(OffsetExpr)) {
8864 Error(OffsetLoc, "expected expression");
8865 Parser.eatToEndOfStatement();
8869 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8871 Error(OffsetLoc, "offset must be a constant");
8872 Parser.eatToEndOfStatement();
8876 StackOffset = CE->getValue();
8878 if (getLexer().isNot(AsmToken::Comma)) {
8879 Error(getLexer().getLoc(), "expected comma");
8880 Parser.eatToEndOfStatement();
8885 SmallVector<uint8_t, 16> Opcodes;
8889 SMLoc OpcodeLoc = getLexer().getLoc();
8890 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
8891 Error(OpcodeLoc, "expected opcode expression");
8892 Parser.eatToEndOfStatement();
8896 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
8898 Error(OpcodeLoc, "opcode value must be a constant");
8899 Parser.eatToEndOfStatement();
8903 const int64_t Opcode = OC->getValue();
8904 if (Opcode & ~0xff) {
8905 Error(OpcodeLoc, "invalid opcode");
8906 Parser.eatToEndOfStatement();
8910 Opcodes.push_back(uint8_t(Opcode));
8912 if (getLexer().is(AsmToken::EndOfStatement))
8915 if (getLexer().isNot(AsmToken::Comma)) {
8916 Error(getLexer().getLoc(), "unexpected token in directive");
8917 Parser.eatToEndOfStatement();
8924 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
8930 /// parseDirectiveTLSDescSeq
8931 /// ::= .tlsdescseq tls-variable
8932 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
8933 if (getLexer().isNot(AsmToken::Identifier)) {
8934 TokError("expected variable after '.tlsdescseq' directive");
8935 Parser.eatToEndOfStatement();
8939 const MCSymbolRefExpr *SRE =
8940 MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
8941 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
8944 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8945 Error(Parser.getTok().getLoc(), "unexpected token");
8946 Parser.eatToEndOfStatement();
8950 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
8954 /// parseDirectiveMovSP
8955 /// ::= .movsp reg [, #offset]
8956 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
8957 if (!UC.hasFnStart()) {
8958 Parser.eatToEndOfStatement();
8959 Error(L, ".fnstart must precede .movsp directives");
8962 if (UC.getFPReg() != ARM::SP) {
8963 Parser.eatToEndOfStatement();
8964 Error(L, "unexpected .movsp directive");
8968 SMLoc SPRegLoc = Parser.getTok().getLoc();
8969 int SPReg = tryParseRegister();
8971 Parser.eatToEndOfStatement();
8972 Error(SPRegLoc, "register expected");
8976 if (SPReg == ARM::SP || SPReg == ARM::PC) {
8977 Parser.eatToEndOfStatement();
8978 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
8983 if (Parser.getTok().is(AsmToken::Comma)) {
8986 if (Parser.getTok().isNot(AsmToken::Hash)) {
8987 Error(Parser.getTok().getLoc(), "expected #constant");
8988 Parser.eatToEndOfStatement();
8993 const MCExpr *OffsetExpr;
8994 SMLoc OffsetLoc = Parser.getTok().getLoc();
8995 if (Parser.parseExpression(OffsetExpr)) {
8996 Parser.eatToEndOfStatement();
8997 Error(OffsetLoc, "malformed offset expression");
9001 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9003 Parser.eatToEndOfStatement();
9004 Error(OffsetLoc, "offset must be an immediate constant");
9008 Offset = CE->getValue();
9011 getTargetStreamer().emitMovSP(SPReg, Offset);
9012 UC.saveFPReg(SPReg);
9017 /// parseDirectiveObjectArch
9018 /// ::= .object_arch name
9019 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9020 if (getLexer().isNot(AsmToken::Identifier)) {
9021 Error(getLexer().getLoc(), "unexpected token");
9022 Parser.eatToEndOfStatement();
9026 StringRef Arch = Parser.getTok().getString();
9027 SMLoc ArchLoc = Parser.getTok().getLoc();
9030 unsigned ID = StringSwitch<unsigned>(Arch)
9031 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9032 .Case(NAME, ARM::ID)
9033 #define ARM_ARCH_ALIAS(NAME, ID) \
9034 .Case(NAME, ARM::ID)
9035 #include "MCTargetDesc/ARMArchName.def"
9036 #undef ARM_ARCH_NAME
9037 #undef ARM_ARCH_ALIAS
9038 .Default(ARM::INVALID_ARCH);
9040 if (ID == ARM::INVALID_ARCH) {
9041 Error(ArchLoc, "unknown architecture '" + Arch + "'");
9042 Parser.eatToEndOfStatement();
9046 getTargetStreamer().emitObjectArch(ID);
9048 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9049 Error(getLexer().getLoc(), "unexpected token");
9050 Parser.eatToEndOfStatement();
9056 /// Force static initialization.
9057 extern "C" void LLVMInitializeARMAsmParser() {
9058 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
9059 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
9062 #define GET_REGISTER_MATCHER
9063 #define GET_SUBTARGET_FEATURE_NAME
9064 #define GET_MATCHER_IMPLEMENTATION
9065 #include "ARMGenAsmMatcher.inc"
9067 // Define this matcher function after the auto-generated include so we
9068 // have the match class enum definitions.
9069 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
9071 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
9072 // If the kind is a token for a literal immediate, check if our asm
9073 // operand matches. This is for InstAliases which have a fixed-value
9074 // immediate in the syntax.
9079 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()))
9080 if (CE->getValue() == 0)
9081 return Match_Success;
9085 const MCExpr *SOExpr = Op->getImm();
9087 if (!SOExpr->EvaluateAsAbsolute(Value))
9088 return Match_Success;
9089 assert((Value >= INT32_MIN && Value <= INT32_MAX) &&
9090 "expression value must be representiable in 32 bits");
9095 MRI->getRegClass(ARM::GPRRegClassID).contains(Op->getReg()))
9096 return Match_Success;
9099 return Match_InvalidOperand;