1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCAssembler.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCDisassembler.h"
25 #include "llvm/MC/MCELFStreamer.h"
26 #include "llvm/MC/MCExpr.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/MC/MCInstrInfo.h"
30 #include "llvm/MC/MCObjectFileInfo.h"
31 #include "llvm/MC/MCParser/MCAsmLexer.h"
32 #include "llvm/MC/MCParser/MCAsmParser.h"
33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34 #include "llvm/MC/MCRegisterInfo.h"
35 #include "llvm/MC/MCSection.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/MC/MCTargetAsmParser.h"
40 #include "llvm/Support/ARMBuildAttributes.h"
41 #include "llvm/Support/ARMEHABI.h"
42 #include "llvm/Support/COFF.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ELF.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/SourceMgr.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Support/raw_ostream.h"
56 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
61 typedef SmallVector<SMLoc, 4> Locs;
66 Locs PersonalityIndexLocs;
71 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
73 bool hasFnStart() const { return !FnStartLocs.empty(); }
74 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
75 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
76 bool hasPersonality() const {
77 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
80 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
81 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
82 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
83 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
84 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
86 void saveFPReg(int Reg) { FPReg = Reg; }
87 int getFPReg() const { return FPReg; }
89 void emitFnStartLocNotes() const {
90 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
92 Parser.Note(*FI, ".fnstart was specified here");
94 void emitCantUnwindLocNotes() const {
95 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
96 UE = CantUnwindLocs.end(); UI != UE; ++UI)
97 Parser.Note(*UI, ".cantunwind was specified here");
99 void emitHandlerDataLocNotes() const {
100 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
101 HE = HandlerDataLocs.end(); HI != HE; ++HI)
102 Parser.Note(*HI, ".handlerdata was specified here");
104 void emitPersonalityLocNotes() const {
105 for (Locs::const_iterator PI = PersonalityLocs.begin(),
106 PE = PersonalityLocs.end(),
107 PII = PersonalityIndexLocs.begin(),
108 PIE = PersonalityIndexLocs.end();
109 PI != PE || PII != PIE;) {
110 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
111 Parser.Note(*PI++, ".personality was specified here");
112 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
113 Parser.Note(*PII++, ".personalityindex was specified here");
115 llvm_unreachable(".personality and .personalityindex cannot be "
116 "at the same location");
121 FnStartLocs = Locs();
122 CantUnwindLocs = Locs();
123 PersonalityLocs = Locs();
124 HandlerDataLocs = Locs();
125 PersonalityIndexLocs = Locs();
130 class ARMAsmParser : public MCTargetAsmParser {
131 MCSubtargetInfo &STI;
133 const MCInstrInfo &MII;
134 const MCRegisterInfo *MRI;
137 ARMTargetStreamer &getTargetStreamer() {
138 assert(getParser().getStreamer().getTargetStreamer() &&
139 "do not have a target streamer");
140 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
141 return static_cast<ARMTargetStreamer &>(TS);
144 // Map of register aliases registers via the .req directive.
145 StringMap<unsigned> RegisterReqs;
147 bool NextSymbolIsThumb;
150 ARMCC::CondCodes Cond; // Condition for IT block.
151 unsigned Mask:4; // Condition mask for instructions.
152 // Starting at first 1 (from lsb).
153 // '1' condition as indicated in IT.
154 // '0' inverse of condition (else).
155 // Count of instructions in IT block is
156 // 4 - trailingzeroes(mask)
158 bool FirstCond; // Explicit flag for when we're parsing the
159 // First instruction in the IT block. It's
160 // implied in the mask, so needs special
163 unsigned CurPosition; // Current position in parsing of IT
164 // block. In range [0,3]. Initialized
165 // according to count of instructions in block.
166 // ~0U if no active IT block.
168 bool inITBlock() { return ITState.CurPosition != ~0U;}
169 void forwardITPosition() {
170 if (!inITBlock()) return;
171 // Move to the next instruction in the IT block, if there is one. If not,
172 // mark the block as done.
173 unsigned TZ = countTrailingZeros(ITState.Mask);
174 if (++ITState.CurPosition == 5 - TZ)
175 ITState.CurPosition = ~0U; // Done with the IT block after this.
179 MCAsmParser &getParser() const { return Parser; }
180 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
182 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
183 return Parser.Note(L, Msg, Ranges);
185 bool Warning(SMLoc L, const Twine &Msg,
186 ArrayRef<SMRange> Ranges = None) {
187 return Parser.Warning(L, Msg, Ranges);
189 bool Error(SMLoc L, const Twine &Msg,
190 ArrayRef<SMRange> Ranges = None) {
191 return Parser.Error(L, Msg, Ranges);
194 int tryParseRegister();
195 bool tryParseRegisterWithWriteBack(OperandVector &);
196 int tryParseShiftRegister(OperandVector &);
197 bool parseRegisterList(OperandVector &);
198 bool parseMemory(OperandVector &);
199 bool parseOperand(OperandVector &, StringRef Mnemonic);
200 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
201 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
202 unsigned &ShiftAmount);
203 bool parseLiteralValues(unsigned Size, SMLoc L);
204 bool parseDirectiveThumb(SMLoc L);
205 bool parseDirectiveARM(SMLoc L);
206 bool parseDirectiveThumbFunc(SMLoc L);
207 bool parseDirectiveCode(SMLoc L);
208 bool parseDirectiveSyntax(SMLoc L);
209 bool parseDirectiveReq(StringRef Name, SMLoc L);
210 bool parseDirectiveUnreq(SMLoc L);
211 bool parseDirectiveArch(SMLoc L);
212 bool parseDirectiveEabiAttr(SMLoc L);
213 bool parseDirectiveCPU(SMLoc L);
214 bool parseDirectiveFPU(SMLoc L);
215 bool parseDirectiveFnStart(SMLoc L);
216 bool parseDirectiveFnEnd(SMLoc L);
217 bool parseDirectiveCantUnwind(SMLoc L);
218 bool parseDirectivePersonality(SMLoc L);
219 bool parseDirectiveHandlerData(SMLoc L);
220 bool parseDirectiveSetFP(SMLoc L);
221 bool parseDirectivePad(SMLoc L);
222 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
223 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
224 bool parseDirectiveLtorg(SMLoc L);
225 bool parseDirectiveEven(SMLoc L);
226 bool parseDirectivePersonalityIndex(SMLoc L);
227 bool parseDirectiveUnwindRaw(SMLoc L);
228 bool parseDirectiveTLSDescSeq(SMLoc L);
229 bool parseDirectiveMovSP(SMLoc L);
230 bool parseDirectiveObjectArch(SMLoc L);
231 bool parseDirectiveArchExtension(SMLoc L);
232 bool parseDirectiveAlign(SMLoc L);
233 bool parseDirectiveThumbSet(SMLoc L);
235 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
236 bool &CarrySetting, unsigned &ProcessorIMod,
238 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
239 bool &CanAcceptCarrySet,
240 bool &CanAcceptPredicationCode);
242 bool isThumb() const {
243 // FIXME: Can tablegen auto-generate this?
244 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
246 bool isThumbOne() const {
247 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
249 bool isThumbTwo() const {
250 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
252 bool hasThumb() const {
253 return STI.getFeatureBits() & ARM::HasV4TOps;
255 bool hasV6Ops() const {
256 return STI.getFeatureBits() & ARM::HasV6Ops;
258 bool hasV6MOps() const {
259 return STI.getFeatureBits() & ARM::HasV6MOps;
261 bool hasV7Ops() const {
262 return STI.getFeatureBits() & ARM::HasV7Ops;
264 bool hasV8Ops() const {
265 return STI.getFeatureBits() & ARM::HasV8Ops;
267 bool hasARM() const {
268 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
270 bool hasThumb2DSP() const {
271 return STI.getFeatureBits() & ARM::FeatureDSPThumb2;
275 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
276 setAvailableFeatures(FB);
278 bool isMClass() const {
279 return STI.getFeatureBits() & ARM::FeatureMClass;
282 /// @name Auto-generated Match Functions
285 #define GET_ASSEMBLER_HEADER
286 #include "ARMGenAsmMatcher.inc"
290 OperandMatchResultTy parseITCondCode(OperandVector &);
291 OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
292 OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
293 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
294 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
295 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
296 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
297 OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
298 OperandMatchResultTy parseBankedRegOperand(OperandVector &);
299 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
301 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
302 return parsePKHImm(O, "lsl", 0, 31);
304 OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
305 return parsePKHImm(O, "asr", 1, 32);
307 OperandMatchResultTy parseSetEndImm(OperandVector &);
308 OperandMatchResultTy parseShifterImm(OperandVector &);
309 OperandMatchResultTy parseRotImm(OperandVector &);
310 OperandMatchResultTy parseBitfield(OperandVector &);
311 OperandMatchResultTy parsePostIdxReg(OperandVector &);
312 OperandMatchResultTy parseAM3Offset(OperandVector &);
313 OperandMatchResultTy parseFPImm(OperandVector &);
314 OperandMatchResultTy parseVectorList(OperandVector &);
315 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
318 // Asm Match Converter Methods
319 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
320 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
322 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
323 bool processInstruction(MCInst &Inst, const OperandVector &Ops);
324 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
325 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
328 enum ARMMatchResultTy {
329 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
330 Match_RequiresNotITBlock,
332 Match_RequiresThumb2,
333 #define GET_OPERAND_DIAGNOSTIC_TYPES
334 #include "ARMGenAsmMatcher.inc"
338 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
339 const MCInstrInfo &MII,
340 const MCTargetOptions &Options)
341 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
342 MCAsmParserExtension::Initialize(_Parser);
344 // Cache the MCRegisterInfo.
345 MRI = getContext().getRegisterInfo();
347 // Initialize the set of available features.
348 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
350 // Not in an ITBlock to start with.
351 ITState.CurPosition = ~0U;
353 NextSymbolIsThumb = false;
356 // Implementation of the MCTargetAsmParser interface:
357 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
358 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
359 SMLoc NameLoc, OperandVector &Operands) override;
360 bool ParseDirective(AsmToken DirectiveID) override;
362 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
363 unsigned Kind) override;
364 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
366 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
367 OperandVector &Operands, MCStreamer &Out,
369 bool MatchingInlineAsm) override;
370 void onLabelParsed(MCSymbol *Symbol) override;
372 } // end anonymous namespace
376 /// ARMOperand - Instances of this class represent a parsed ARM machine
378 class ARMOperand : public MCParsedAsmOperand {
388 k_InstSyncBarrierOpt,
400 k_VectorListAllLanes,
406 k_BitfieldDescriptor,
410 SMLoc StartLoc, EndLoc, AlignmentLoc;
411 SmallVector<unsigned, 8> Registers;
414 ARMCC::CondCodes Val;
421 struct CoprocOptionOp {
434 ARM_ISB::InstSyncBOpt Val;
438 ARM_PROC::IFlags Val;
458 // A vector register list is a sequential list of 1 to 4 registers.
459 struct VectorListOp {
466 struct VectorIndexOp {
474 /// Combined record for all forms of ARM address expressions.
477 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
479 const MCConstantExpr *OffsetImm; // Offset immediate value
480 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
481 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
482 unsigned ShiftImm; // shift for OffsetReg.
483 unsigned Alignment; // 0 = no alignment specified
484 // n = alignment in bytes (2, 4, 8, 16, or 32)
485 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
488 struct PostIdxRegOp {
491 ARM_AM::ShiftOpc ShiftTy;
495 struct ShifterImmOp {
500 struct RegShiftedRegOp {
501 ARM_AM::ShiftOpc ShiftTy;
507 struct RegShiftedImmOp {
508 ARM_AM::ShiftOpc ShiftTy;
525 struct CoprocOptionOp CoprocOption;
526 struct MBOptOp MBOpt;
527 struct ISBOptOp ISBOpt;
528 struct ITMaskOp ITMask;
529 struct IFlagsOp IFlags;
530 struct MMaskOp MMask;
531 struct BankedRegOp BankedReg;
534 struct VectorListOp VectorList;
535 struct VectorIndexOp VectorIndex;
537 struct MemoryOp Memory;
538 struct PostIdxRegOp PostIdxReg;
539 struct ShifterImmOp ShifterImm;
540 struct RegShiftedRegOp RegShiftedReg;
541 struct RegShiftedImmOp RegShiftedImm;
542 struct RotImmOp RotImm;
543 struct BitfieldOp Bitfield;
547 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
548 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
550 StartLoc = o.StartLoc;
567 case k_DPRRegisterList:
568 case k_SPRRegisterList:
569 Registers = o.Registers;
572 case k_VectorListAllLanes:
573 case k_VectorListIndexed:
574 VectorList = o.VectorList;
581 CoprocOption = o.CoprocOption;
586 case k_MemBarrierOpt:
589 case k_InstSyncBarrierOpt:
594 case k_PostIndexRegister:
595 PostIdxReg = o.PostIdxReg;
601 BankedReg = o.BankedReg;
606 case k_ShifterImmediate:
607 ShifterImm = o.ShifterImm;
609 case k_ShiftedRegister:
610 RegShiftedReg = o.RegShiftedReg;
612 case k_ShiftedImmediate:
613 RegShiftedImm = o.RegShiftedImm;
615 case k_RotateImmediate:
618 case k_BitfieldDescriptor:
619 Bitfield = o.Bitfield;
622 VectorIndex = o.VectorIndex;
627 /// getStartLoc - Get the location of the first token of this operand.
628 SMLoc getStartLoc() const override { return StartLoc; }
629 /// getEndLoc - Get the location of the last token of this operand.
630 SMLoc getEndLoc() const override { return EndLoc; }
631 /// getLocRange - Get the range between the first and last token of this
633 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
635 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
636 SMLoc getAlignmentLoc() const {
637 assert(Kind == k_Memory && "Invalid access!");
641 ARMCC::CondCodes getCondCode() const {
642 assert(Kind == k_CondCode && "Invalid access!");
646 unsigned getCoproc() const {
647 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
651 StringRef getToken() const {
652 assert(Kind == k_Token && "Invalid access!");
653 return StringRef(Tok.Data, Tok.Length);
656 unsigned getReg() const override {
657 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
661 const SmallVectorImpl<unsigned> &getRegList() const {
662 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
663 Kind == k_SPRRegisterList) && "Invalid access!");
667 const MCExpr *getImm() const {
668 assert(isImm() && "Invalid access!");
672 unsigned getVectorIndex() const {
673 assert(Kind == k_VectorIndex && "Invalid access!");
674 return VectorIndex.Val;
677 ARM_MB::MemBOpt getMemBarrierOpt() const {
678 assert(Kind == k_MemBarrierOpt && "Invalid access!");
682 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
683 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
687 ARM_PROC::IFlags getProcIFlags() const {
688 assert(Kind == k_ProcIFlags && "Invalid access!");
692 unsigned getMSRMask() const {
693 assert(Kind == k_MSRMask && "Invalid access!");
697 unsigned getBankedReg() const {
698 assert(Kind == k_BankedReg && "Invalid access!");
699 return BankedReg.Val;
702 bool isCoprocNum() const { return Kind == k_CoprocNum; }
703 bool isCoprocReg() const { return Kind == k_CoprocReg; }
704 bool isCoprocOption() const { return Kind == k_CoprocOption; }
705 bool isCondCode() const { return Kind == k_CondCode; }
706 bool isCCOut() const { return Kind == k_CCOut; }
707 bool isITMask() const { return Kind == k_ITCondMask; }
708 bool isITCondCode() const { return Kind == k_CondCode; }
709 bool isImm() const override { return Kind == k_Immediate; }
710 // checks whether this operand is an unsigned offset which fits is a field
711 // of specified width and scaled by a specific number of bits
712 template<unsigned width, unsigned scale>
713 bool isUnsignedOffset() const {
714 if (!isImm()) return false;
715 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
716 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
717 int64_t Val = CE->getValue();
718 int64_t Align = 1LL << scale;
719 int64_t Max = Align * ((1LL << width) - 1);
720 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
724 // checks whether this operand is an signed offset which fits is a field
725 // of specified width and scaled by a specific number of bits
726 template<unsigned width, unsigned scale>
727 bool isSignedOffset() const {
728 if (!isImm()) return false;
729 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
730 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
731 int64_t Val = CE->getValue();
732 int64_t Align = 1LL << scale;
733 int64_t Max = Align * ((1LL << (width-1)) - 1);
734 int64_t Min = -Align * (1LL << (width-1));
735 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
740 // checks whether this operand is a memory operand computed as an offset
741 // applied to PC. the offset may have 8 bits of magnitude and is represented
742 // with two bits of shift. textually it may be either [pc, #imm], #imm or
743 // relocable expression...
744 bool isThumbMemPC() const {
747 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
748 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
749 if (!CE) return false;
750 Val = CE->getValue();
753 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
754 if(Memory.BaseRegNum != ARM::PC) return false;
755 Val = Memory.OffsetImm->getValue();
758 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
760 bool isFPImm() const {
761 if (!isImm()) return false;
762 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
763 if (!CE) return false;
764 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
767 bool isFBits16() const {
768 if (!isImm()) return false;
769 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
770 if (!CE) return false;
771 int64_t Value = CE->getValue();
772 return Value >= 0 && Value <= 16;
774 bool isFBits32() const {
775 if (!isImm()) return false;
776 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
777 if (!CE) return false;
778 int64_t Value = CE->getValue();
779 return Value >= 1 && Value <= 32;
781 bool isImm8s4() const {
782 if (!isImm()) return false;
783 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
784 if (!CE) return false;
785 int64_t Value = CE->getValue();
786 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
788 bool isImm0_1020s4() const {
789 if (!isImm()) return false;
790 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
791 if (!CE) return false;
792 int64_t Value = CE->getValue();
793 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
795 bool isImm0_508s4() const {
796 if (!isImm()) return false;
797 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
798 if (!CE) return false;
799 int64_t Value = CE->getValue();
800 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
802 bool isImm0_508s4Neg() const {
803 if (!isImm()) return false;
804 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
805 if (!CE) return false;
806 int64_t Value = -CE->getValue();
807 // explicitly exclude zero. we want that to use the normal 0_508 version.
808 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
810 bool isImm0_239() const {
811 if (!isImm()) return false;
812 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
813 if (!CE) return false;
814 int64_t Value = CE->getValue();
815 return Value >= 0 && Value < 240;
817 bool isImm0_255() const {
818 if (!isImm()) return false;
819 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
820 if (!CE) return false;
821 int64_t Value = CE->getValue();
822 return Value >= 0 && Value < 256;
824 bool isImm0_4095() const {
825 if (!isImm()) return false;
826 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
827 if (!CE) return false;
828 int64_t Value = CE->getValue();
829 return Value >= 0 && Value < 4096;
831 bool isImm0_4095Neg() const {
832 if (!isImm()) return false;
833 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
834 if (!CE) return false;
835 int64_t Value = -CE->getValue();
836 return Value > 0 && Value < 4096;
838 bool isImm0_1() const {
839 if (!isImm()) return false;
840 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
841 if (!CE) return false;
842 int64_t Value = CE->getValue();
843 return Value >= 0 && Value < 2;
845 bool isImm0_3() const {
846 if (!isImm()) return false;
847 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
848 if (!CE) return false;
849 int64_t Value = CE->getValue();
850 return Value >= 0 && Value < 4;
852 bool isImm0_7() const {
853 if (!isImm()) return false;
854 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
855 if (!CE) return false;
856 int64_t Value = CE->getValue();
857 return Value >= 0 && Value < 8;
859 bool isImm0_15() const {
860 if (!isImm()) return false;
861 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
862 if (!CE) return false;
863 int64_t Value = CE->getValue();
864 return Value >= 0 && Value < 16;
866 bool isImm0_31() const {
867 if (!isImm()) return false;
868 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
869 if (!CE) return false;
870 int64_t Value = CE->getValue();
871 return Value >= 0 && Value < 32;
873 bool isImm0_63() const {
874 if (!isImm()) return false;
875 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
876 if (!CE) return false;
877 int64_t Value = CE->getValue();
878 return Value >= 0 && Value < 64;
880 bool isImm8() const {
881 if (!isImm()) return false;
882 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
883 if (!CE) return false;
884 int64_t Value = CE->getValue();
887 bool isImm16() const {
888 if (!isImm()) return false;
889 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
890 if (!CE) return false;
891 int64_t Value = CE->getValue();
894 bool isImm32() const {
895 if (!isImm()) return false;
896 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
897 if (!CE) return false;
898 int64_t Value = CE->getValue();
901 bool isShrImm8() const {
902 if (!isImm()) return false;
903 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
904 if (!CE) return false;
905 int64_t Value = CE->getValue();
906 return Value > 0 && Value <= 8;
908 bool isShrImm16() const {
909 if (!isImm()) return false;
910 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
911 if (!CE) return false;
912 int64_t Value = CE->getValue();
913 return Value > 0 && Value <= 16;
915 bool isShrImm32() const {
916 if (!isImm()) return false;
917 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
918 if (!CE) return false;
919 int64_t Value = CE->getValue();
920 return Value > 0 && Value <= 32;
922 bool isShrImm64() const {
923 if (!isImm()) return false;
924 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
925 if (!CE) return false;
926 int64_t Value = CE->getValue();
927 return Value > 0 && Value <= 64;
929 bool isImm1_7() const {
930 if (!isImm()) return false;
931 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
932 if (!CE) return false;
933 int64_t Value = CE->getValue();
934 return Value > 0 && Value < 8;
936 bool isImm1_15() const {
937 if (!isImm()) return false;
938 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
939 if (!CE) return false;
940 int64_t Value = CE->getValue();
941 return Value > 0 && Value < 16;
943 bool isImm1_31() const {
944 if (!isImm()) return false;
945 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
946 if (!CE) return false;
947 int64_t Value = CE->getValue();
948 return Value > 0 && Value < 32;
950 bool isImm1_16() const {
951 if (!isImm()) return false;
952 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
953 if (!CE) return false;
954 int64_t Value = CE->getValue();
955 return Value > 0 && Value < 17;
957 bool isImm1_32() const {
958 if (!isImm()) return false;
959 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
960 if (!CE) return false;
961 int64_t Value = CE->getValue();
962 return Value > 0 && Value < 33;
964 bool isImm0_32() const {
965 if (!isImm()) return false;
966 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
967 if (!CE) return false;
968 int64_t Value = CE->getValue();
969 return Value >= 0 && Value < 33;
971 bool isImm0_65535() const {
972 if (!isImm()) return false;
973 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
974 if (!CE) return false;
975 int64_t Value = CE->getValue();
976 return Value >= 0 && Value < 65536;
978 bool isImm256_65535Expr() const {
979 if (!isImm()) return false;
980 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
981 // If it's not a constant expression, it'll generate a fixup and be
983 if (!CE) return true;
984 int64_t Value = CE->getValue();
985 return Value >= 256 && Value < 65536;
987 bool isImm0_65535Expr() const {
988 if (!isImm()) return false;
989 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
990 // If it's not a constant expression, it'll generate a fixup and be
992 if (!CE) return true;
993 int64_t Value = CE->getValue();
994 return Value >= 0 && Value < 65536;
996 bool isImm24bit() const {
997 if (!isImm()) return false;
998 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
999 if (!CE) return false;
1000 int64_t Value = CE->getValue();
1001 return Value >= 0 && Value <= 0xffffff;
1003 bool isImmThumbSR() const {
1004 if (!isImm()) return false;
1005 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1006 if (!CE) return false;
1007 int64_t Value = CE->getValue();
1008 return Value > 0 && Value < 33;
1010 bool isPKHLSLImm() const {
1011 if (!isImm()) return false;
1012 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1013 if (!CE) return false;
1014 int64_t Value = CE->getValue();
1015 return Value >= 0 && Value < 32;
1017 bool isPKHASRImm() const {
1018 if (!isImm()) return false;
1019 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1020 if (!CE) return false;
1021 int64_t Value = CE->getValue();
1022 return Value > 0 && Value <= 32;
1024 bool isAdrLabel() const {
1025 // If we have an immediate that's not a constant, treat it as a label
1026 // reference needing a fixup. If it is a constant, but it can't fit
1027 // into shift immediate encoding, we reject it.
1028 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1029 else return (isARMSOImm() || isARMSOImmNeg());
1031 bool isARMSOImm() const {
1032 if (!isImm()) return false;
1033 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1034 if (!CE) return false;
1035 int64_t Value = CE->getValue();
1036 return ARM_AM::getSOImmVal(Value) != -1;
1038 bool isARMSOImmNot() const {
1039 if (!isImm()) return false;
1040 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1041 if (!CE) return false;
1042 int64_t Value = CE->getValue();
1043 return ARM_AM::getSOImmVal(~Value) != -1;
1045 bool isARMSOImmNeg() const {
1046 if (!isImm()) return false;
1047 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1048 if (!CE) return false;
1049 int64_t Value = CE->getValue();
1050 // Only use this when not representable as a plain so_imm.
1051 return ARM_AM::getSOImmVal(Value) == -1 &&
1052 ARM_AM::getSOImmVal(-Value) != -1;
1054 bool isT2SOImm() const {
1055 if (!isImm()) return false;
1056 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1057 if (!CE) return false;
1058 int64_t Value = CE->getValue();
1059 return ARM_AM::getT2SOImmVal(Value) != -1;
1061 bool isT2SOImmNot() const {
1062 if (!isImm()) return false;
1063 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1064 if (!CE) return false;
1065 int64_t Value = CE->getValue();
1066 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1067 ARM_AM::getT2SOImmVal(~Value) != -1;
1069 bool isT2SOImmNeg() const {
1070 if (!isImm()) return false;
1071 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1072 if (!CE) return false;
1073 int64_t Value = CE->getValue();
1074 // Only use this when not representable as a plain so_imm.
1075 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1076 ARM_AM::getT2SOImmVal(-Value) != -1;
1078 bool isSetEndImm() const {
1079 if (!isImm()) return false;
1080 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1081 if (!CE) return false;
1082 int64_t Value = CE->getValue();
1083 return Value == 1 || Value == 0;
1085 bool isReg() const override { return Kind == k_Register; }
1086 bool isRegList() const { return Kind == k_RegisterList; }
1087 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1088 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1089 bool isToken() const override { return Kind == k_Token; }
1090 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1091 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1092 bool isMem() const override { return Kind == k_Memory; }
1093 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1094 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1095 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1096 bool isRotImm() const { return Kind == k_RotateImmediate; }
1097 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1098 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1099 bool isPostIdxReg() const {
1100 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1102 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1105 // No offset of any kind.
1106 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1107 (alignOK || Memory.Alignment == Alignment);
1109 bool isMemPCRelImm12() const {
1110 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1112 // Base register must be PC.
1113 if (Memory.BaseRegNum != ARM::PC)
1115 // Immediate offset in range [-4095, 4095].
1116 if (!Memory.OffsetImm) return true;
1117 int64_t Val = Memory.OffsetImm->getValue();
1118 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1120 bool isAlignedMemory() const {
1121 return isMemNoOffset(true);
1123 bool isAlignedMemoryNone() const {
1124 return isMemNoOffset(false, 0);
1126 bool isDupAlignedMemoryNone() const {
1127 return isMemNoOffset(false, 0);
1129 bool isAlignedMemory16() const {
1130 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1132 return isMemNoOffset(false, 0);
1134 bool isDupAlignedMemory16() const {
1135 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1137 return isMemNoOffset(false, 0);
1139 bool isAlignedMemory32() const {
1140 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1142 return isMemNoOffset(false, 0);
1144 bool isDupAlignedMemory32() const {
1145 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1147 return isMemNoOffset(false, 0);
1149 bool isAlignedMemory64() const {
1150 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1152 return isMemNoOffset(false, 0);
1154 bool isDupAlignedMemory64() const {
1155 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1157 return isMemNoOffset(false, 0);
1159 bool isAlignedMemory64or128() const {
1160 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1162 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1164 return isMemNoOffset(false, 0);
1166 bool isDupAlignedMemory64or128() const {
1167 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1169 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1171 return isMemNoOffset(false, 0);
1173 bool isAlignedMemory64or128or256() const {
1174 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1176 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1178 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1180 return isMemNoOffset(false, 0);
1182 bool isAddrMode2() const {
1183 if (!isMem() || Memory.Alignment != 0) return false;
1184 // Check for register offset.
1185 if (Memory.OffsetRegNum) return true;
1186 // Immediate offset in range [-4095, 4095].
1187 if (!Memory.OffsetImm) return true;
1188 int64_t Val = Memory.OffsetImm->getValue();
1189 return Val > -4096 && Val < 4096;
1191 bool isAM2OffsetImm() const {
1192 if (!isImm()) return false;
1193 // Immediate offset in range [-4095, 4095].
1194 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1195 if (!CE) return false;
1196 int64_t Val = CE->getValue();
1197 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1199 bool isAddrMode3() const {
1200 // If we have an immediate that's not a constant, treat it as a label
1201 // reference needing a fixup. If it is a constant, it's something else
1202 // and we reject it.
1203 if (isImm() && !isa<MCConstantExpr>(getImm()))
1205 if (!isMem() || Memory.Alignment != 0) return false;
1206 // No shifts are legal for AM3.
1207 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1208 // Check for register offset.
1209 if (Memory.OffsetRegNum) return true;
1210 // Immediate offset in range [-255, 255].
1211 if (!Memory.OffsetImm) return true;
1212 int64_t Val = Memory.OffsetImm->getValue();
1213 // The #-0 offset is encoded as INT32_MIN, and we have to check
1215 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1217 bool isAM3Offset() const {
1218 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1220 if (Kind == k_PostIndexRegister)
1221 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1222 // Immediate offset in range [-255, 255].
1223 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1224 if (!CE) return false;
1225 int64_t Val = CE->getValue();
1226 // Special case, #-0 is INT32_MIN.
1227 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1229 bool isAddrMode5() const {
1230 // If we have an immediate that's not a constant, treat it as a label
1231 // reference needing a fixup. If it is a constant, it's something else
1232 // and we reject it.
1233 if (isImm() && !isa<MCConstantExpr>(getImm()))
1235 if (!isMem() || Memory.Alignment != 0) return false;
1236 // Check for register offset.
1237 if (Memory.OffsetRegNum) return false;
1238 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1239 if (!Memory.OffsetImm) return true;
1240 int64_t Val = Memory.OffsetImm->getValue();
1241 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1244 bool isMemTBB() const {
1245 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1246 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1250 bool isMemTBH() const {
1251 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1252 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1253 Memory.Alignment != 0 )
1257 bool isMemRegOffset() const {
1258 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1262 bool isT2MemRegOffset() const {
1263 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1264 Memory.Alignment != 0)
1266 // Only lsl #{0, 1, 2, 3} allowed.
1267 if (Memory.ShiftType == ARM_AM::no_shift)
1269 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1273 bool isMemThumbRR() const {
1274 // Thumb reg+reg addressing is simple. Just two registers, a base and
1275 // an offset. No shifts, negations or any other complicating factors.
1276 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1277 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1279 return isARMLowRegister(Memory.BaseRegNum) &&
1280 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1282 bool isMemThumbRIs4() const {
1283 if (!isMem() || Memory.OffsetRegNum != 0 ||
1284 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1286 // Immediate offset, multiple of 4 in range [0, 124].
1287 if (!Memory.OffsetImm) return true;
1288 int64_t Val = Memory.OffsetImm->getValue();
1289 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1291 bool isMemThumbRIs2() const {
1292 if (!isMem() || Memory.OffsetRegNum != 0 ||
1293 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1295 // Immediate offset, multiple of 4 in range [0, 62].
1296 if (!Memory.OffsetImm) return true;
1297 int64_t Val = Memory.OffsetImm->getValue();
1298 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1300 bool isMemThumbRIs1() const {
1301 if (!isMem() || Memory.OffsetRegNum != 0 ||
1302 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1304 // Immediate offset in range [0, 31].
1305 if (!Memory.OffsetImm) return true;
1306 int64_t Val = Memory.OffsetImm->getValue();
1307 return Val >= 0 && Val <= 31;
1309 bool isMemThumbSPI() const {
1310 if (!isMem() || Memory.OffsetRegNum != 0 ||
1311 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1313 // Immediate offset, multiple of 4 in range [0, 1020].
1314 if (!Memory.OffsetImm) return true;
1315 int64_t Val = Memory.OffsetImm->getValue();
1316 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1318 bool isMemImm8s4Offset() const {
1319 // If we have an immediate that's not a constant, treat it as a label
1320 // reference needing a fixup. If it is a constant, it's something else
1321 // and we reject it.
1322 if (isImm() && !isa<MCConstantExpr>(getImm()))
1324 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1326 // Immediate offset a multiple of 4 in range [-1020, 1020].
1327 if (!Memory.OffsetImm) return true;
1328 int64_t Val = Memory.OffsetImm->getValue();
1329 // Special case, #-0 is INT32_MIN.
1330 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1332 bool isMemImm0_1020s4Offset() const {
1333 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1335 // Immediate offset a multiple of 4 in range [0, 1020].
1336 if (!Memory.OffsetImm) return true;
1337 int64_t Val = Memory.OffsetImm->getValue();
1338 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1340 bool isMemImm8Offset() const {
1341 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1343 // Base reg of PC isn't allowed for these encodings.
1344 if (Memory.BaseRegNum == ARM::PC) return false;
1345 // Immediate offset in range [-255, 255].
1346 if (!Memory.OffsetImm) return true;
1347 int64_t Val = Memory.OffsetImm->getValue();
1348 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1350 bool isMemPosImm8Offset() const {
1351 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1353 // Immediate offset in range [0, 255].
1354 if (!Memory.OffsetImm) return true;
1355 int64_t Val = Memory.OffsetImm->getValue();
1356 return Val >= 0 && Val < 256;
1358 bool isMemNegImm8Offset() const {
1359 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1361 // Base reg of PC isn't allowed for these encodings.
1362 if (Memory.BaseRegNum == ARM::PC) return false;
1363 // Immediate offset in range [-255, -1].
1364 if (!Memory.OffsetImm) return false;
1365 int64_t Val = Memory.OffsetImm->getValue();
1366 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1368 bool isMemUImm12Offset() const {
1369 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1371 // Immediate offset in range [0, 4095].
1372 if (!Memory.OffsetImm) return true;
1373 int64_t Val = Memory.OffsetImm->getValue();
1374 return (Val >= 0 && Val < 4096);
1376 bool isMemImm12Offset() const {
1377 // If we have an immediate that's not a constant, treat it as a label
1378 // reference needing a fixup. If it is a constant, it's something else
1379 // and we reject it.
1380 if (isImm() && !isa<MCConstantExpr>(getImm()))
1383 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1385 // Immediate offset in range [-4095, 4095].
1386 if (!Memory.OffsetImm) return true;
1387 int64_t Val = Memory.OffsetImm->getValue();
1388 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1390 bool isPostIdxImm8() const {
1391 if (!isImm()) return false;
1392 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1393 if (!CE) return false;
1394 int64_t Val = CE->getValue();
1395 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1397 bool isPostIdxImm8s4() const {
1398 if (!isImm()) return false;
1399 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1400 if (!CE) return false;
1401 int64_t Val = CE->getValue();
1402 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1406 bool isMSRMask() const { return Kind == k_MSRMask; }
1407 bool isBankedReg() const { return Kind == k_BankedReg; }
1408 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1411 bool isSingleSpacedVectorList() const {
1412 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1414 bool isDoubleSpacedVectorList() const {
1415 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1417 bool isVecListOneD() const {
1418 if (!isSingleSpacedVectorList()) return false;
1419 return VectorList.Count == 1;
1422 bool isVecListDPair() const {
1423 if (!isSingleSpacedVectorList()) return false;
1424 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1425 .contains(VectorList.RegNum));
1428 bool isVecListThreeD() const {
1429 if (!isSingleSpacedVectorList()) return false;
1430 return VectorList.Count == 3;
1433 bool isVecListFourD() const {
1434 if (!isSingleSpacedVectorList()) return false;
1435 return VectorList.Count == 4;
1438 bool isVecListDPairSpaced() const {
1439 if (Kind != k_VectorList) return false;
1440 if (isSingleSpacedVectorList()) return false;
1441 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1442 .contains(VectorList.RegNum));
1445 bool isVecListThreeQ() const {
1446 if (!isDoubleSpacedVectorList()) return false;
1447 return VectorList.Count == 3;
1450 bool isVecListFourQ() const {
1451 if (!isDoubleSpacedVectorList()) return false;
1452 return VectorList.Count == 4;
1455 bool isSingleSpacedVectorAllLanes() const {
1456 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1458 bool isDoubleSpacedVectorAllLanes() const {
1459 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1461 bool isVecListOneDAllLanes() const {
1462 if (!isSingleSpacedVectorAllLanes()) return false;
1463 return VectorList.Count == 1;
1466 bool isVecListDPairAllLanes() const {
1467 if (!isSingleSpacedVectorAllLanes()) return false;
1468 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1469 .contains(VectorList.RegNum));
1472 bool isVecListDPairSpacedAllLanes() const {
1473 if (!isDoubleSpacedVectorAllLanes()) return false;
1474 return VectorList.Count == 2;
1477 bool isVecListThreeDAllLanes() const {
1478 if (!isSingleSpacedVectorAllLanes()) return false;
1479 return VectorList.Count == 3;
1482 bool isVecListThreeQAllLanes() const {
1483 if (!isDoubleSpacedVectorAllLanes()) return false;
1484 return VectorList.Count == 3;
1487 bool isVecListFourDAllLanes() const {
1488 if (!isSingleSpacedVectorAllLanes()) return false;
1489 return VectorList.Count == 4;
1492 bool isVecListFourQAllLanes() const {
1493 if (!isDoubleSpacedVectorAllLanes()) return false;
1494 return VectorList.Count == 4;
1497 bool isSingleSpacedVectorIndexed() const {
1498 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1500 bool isDoubleSpacedVectorIndexed() const {
1501 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1503 bool isVecListOneDByteIndexed() const {
1504 if (!isSingleSpacedVectorIndexed()) return false;
1505 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1508 bool isVecListOneDHWordIndexed() const {
1509 if (!isSingleSpacedVectorIndexed()) return false;
1510 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1513 bool isVecListOneDWordIndexed() const {
1514 if (!isSingleSpacedVectorIndexed()) return false;
1515 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1518 bool isVecListTwoDByteIndexed() const {
1519 if (!isSingleSpacedVectorIndexed()) return false;
1520 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1523 bool isVecListTwoDHWordIndexed() const {
1524 if (!isSingleSpacedVectorIndexed()) return false;
1525 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1528 bool isVecListTwoQWordIndexed() const {
1529 if (!isDoubleSpacedVectorIndexed()) return false;
1530 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1533 bool isVecListTwoQHWordIndexed() const {
1534 if (!isDoubleSpacedVectorIndexed()) return false;
1535 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1538 bool isVecListTwoDWordIndexed() const {
1539 if (!isSingleSpacedVectorIndexed()) return false;
1540 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1543 bool isVecListThreeDByteIndexed() const {
1544 if (!isSingleSpacedVectorIndexed()) return false;
1545 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1548 bool isVecListThreeDHWordIndexed() const {
1549 if (!isSingleSpacedVectorIndexed()) return false;
1550 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1553 bool isVecListThreeQWordIndexed() const {
1554 if (!isDoubleSpacedVectorIndexed()) return false;
1555 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1558 bool isVecListThreeQHWordIndexed() const {
1559 if (!isDoubleSpacedVectorIndexed()) return false;
1560 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1563 bool isVecListThreeDWordIndexed() const {
1564 if (!isSingleSpacedVectorIndexed()) return false;
1565 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1568 bool isVecListFourDByteIndexed() const {
1569 if (!isSingleSpacedVectorIndexed()) return false;
1570 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1573 bool isVecListFourDHWordIndexed() const {
1574 if (!isSingleSpacedVectorIndexed()) return false;
1575 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1578 bool isVecListFourQWordIndexed() const {
1579 if (!isDoubleSpacedVectorIndexed()) return false;
1580 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1583 bool isVecListFourQHWordIndexed() const {
1584 if (!isDoubleSpacedVectorIndexed()) return false;
1585 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1588 bool isVecListFourDWordIndexed() const {
1589 if (!isSingleSpacedVectorIndexed()) return false;
1590 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1593 bool isVectorIndex8() const {
1594 if (Kind != k_VectorIndex) return false;
1595 return VectorIndex.Val < 8;
1597 bool isVectorIndex16() const {
1598 if (Kind != k_VectorIndex) return false;
1599 return VectorIndex.Val < 4;
1601 bool isVectorIndex32() const {
1602 if (Kind != k_VectorIndex) return false;
1603 return VectorIndex.Val < 2;
1606 bool isNEONi8splat() const {
1607 if (!isImm()) return false;
1608 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1609 // Must be a constant.
1610 if (!CE) return false;
1611 int64_t Value = CE->getValue();
1612 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1614 return Value >= 0 && Value < 256;
1617 bool isNEONi16splat() const {
1618 if (isNEONByteReplicate(2))
1619 return false; // Leave that for bytes replication and forbid by default.
1622 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1623 // Must be a constant.
1624 if (!CE) return false;
1625 int64_t Value = CE->getValue();
1626 // i16 value in the range [0,255] or [0x0100, 0xff00]
1627 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1630 bool isNEONi32splat() const {
1631 if (isNEONByteReplicate(4))
1632 return false; // Leave that for bytes replication and forbid by default.
1635 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1636 // Must be a constant.
1637 if (!CE) return false;
1638 int64_t Value = CE->getValue();
1639 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1640 return (Value >= 0 && Value < 256) ||
1641 (Value >= 0x0100 && Value <= 0xff00) ||
1642 (Value >= 0x010000 && Value <= 0xff0000) ||
1643 (Value >= 0x01000000 && Value <= 0xff000000);
1646 bool isNEONByteReplicate(unsigned NumBytes) const {
1649 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1650 // Must be a constant.
1653 int64_t Value = CE->getValue();
1655 return false; // Don't bother with zero.
1657 unsigned char B = Value & 0xff;
1658 for (unsigned i = 1; i < NumBytes; ++i) {
1660 if ((Value & 0xff) != B)
1665 bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1666 bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1667 bool isNEONi32vmov() const {
1668 if (isNEONByteReplicate(4))
1669 return false; // Let it to be classified as byte-replicate case.
1672 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1673 // Must be a constant.
1676 int64_t Value = CE->getValue();
1677 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1678 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1679 return (Value >= 0 && Value < 256) ||
1680 (Value >= 0x0100 && Value <= 0xff00) ||
1681 (Value >= 0x010000 && Value <= 0xff0000) ||
1682 (Value >= 0x01000000 && Value <= 0xff000000) ||
1683 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1684 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1686 bool isNEONi32vmovNeg() const {
1687 if (!isImm()) return false;
1688 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1689 // Must be a constant.
1690 if (!CE) return false;
1691 int64_t Value = ~CE->getValue();
1692 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1693 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1694 return (Value >= 0 && Value < 256) ||
1695 (Value >= 0x0100 && Value <= 0xff00) ||
1696 (Value >= 0x010000 && Value <= 0xff0000) ||
1697 (Value >= 0x01000000 && Value <= 0xff000000) ||
1698 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1699 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1702 bool isNEONi64splat() const {
1703 if (!isImm()) return false;
1704 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1705 // Must be a constant.
1706 if (!CE) return false;
1707 uint64_t Value = CE->getValue();
1708 // i64 value with each byte being either 0 or 0xff.
1709 for (unsigned i = 0; i < 8; ++i)
1710 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1714 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1715 // Add as immediates when possible. Null MCExpr = 0.
1717 Inst.addOperand(MCOperand::CreateImm(0));
1718 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1719 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1721 Inst.addOperand(MCOperand::CreateExpr(Expr));
1724 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1725 assert(N == 2 && "Invalid number of operands!");
1726 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1727 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1728 Inst.addOperand(MCOperand::CreateReg(RegNum));
1731 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1732 assert(N == 1 && "Invalid number of operands!");
1733 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1736 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1737 assert(N == 1 && "Invalid number of operands!");
1738 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1741 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1742 assert(N == 1 && "Invalid number of operands!");
1743 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1746 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1747 assert(N == 1 && "Invalid number of operands!");
1748 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1751 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1752 assert(N == 1 && "Invalid number of operands!");
1753 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1756 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1757 assert(N == 1 && "Invalid number of operands!");
1758 Inst.addOperand(MCOperand::CreateReg(getReg()));
1761 void addRegOperands(MCInst &Inst, unsigned N) const {
1762 assert(N == 1 && "Invalid number of operands!");
1763 Inst.addOperand(MCOperand::CreateReg(getReg()));
1766 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1767 assert(N == 3 && "Invalid number of operands!");
1768 assert(isRegShiftedReg() &&
1769 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1770 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1771 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1772 Inst.addOperand(MCOperand::CreateImm(
1773 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1776 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1777 assert(N == 2 && "Invalid number of operands!");
1778 assert(isRegShiftedImm() &&
1779 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1780 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1781 // Shift of #32 is encoded as 0 where permitted
1782 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1783 Inst.addOperand(MCOperand::CreateImm(
1784 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1787 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1788 assert(N == 1 && "Invalid number of operands!");
1789 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1793 void addRegListOperands(MCInst &Inst, unsigned N) const {
1794 assert(N == 1 && "Invalid number of operands!");
1795 const SmallVectorImpl<unsigned> &RegList = getRegList();
1796 for (SmallVectorImpl<unsigned>::const_iterator
1797 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1798 Inst.addOperand(MCOperand::CreateReg(*I));
1801 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1802 addRegListOperands(Inst, N);
1805 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1806 addRegListOperands(Inst, N);
1809 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1810 assert(N == 1 && "Invalid number of operands!");
1811 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1812 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1815 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1816 assert(N == 1 && "Invalid number of operands!");
1817 // Munge the lsb/width into a bitfield mask.
1818 unsigned lsb = Bitfield.LSB;
1819 unsigned width = Bitfield.Width;
1820 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1821 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1822 (32 - (lsb + width)));
1823 Inst.addOperand(MCOperand::CreateImm(Mask));
1826 void addImmOperands(MCInst &Inst, unsigned N) const {
1827 assert(N == 1 && "Invalid number of operands!");
1828 addExpr(Inst, getImm());
1831 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1832 assert(N == 1 && "Invalid number of operands!");
1833 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1834 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1837 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1838 assert(N == 1 && "Invalid number of operands!");
1839 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1840 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1843 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1844 assert(N == 1 && "Invalid number of operands!");
1845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1846 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1847 Inst.addOperand(MCOperand::CreateImm(Val));
1850 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1851 assert(N == 1 && "Invalid number of operands!");
1852 // FIXME: We really want to scale the value here, but the LDRD/STRD
1853 // instruction don't encode operands that way yet.
1854 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1855 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1858 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1859 assert(N == 1 && "Invalid number of operands!");
1860 // The immediate is scaled by four in the encoding and is stored
1861 // in the MCInst as such. Lop off the low two bits here.
1862 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1863 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1866 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1867 assert(N == 1 && "Invalid number of operands!");
1868 // The immediate is scaled by four in the encoding and is stored
1869 // in the MCInst as such. Lop off the low two bits here.
1870 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1871 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1874 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1875 assert(N == 1 && "Invalid number of operands!");
1876 // The immediate is scaled by four in the encoding and is stored
1877 // in the MCInst as such. Lop off the low two bits here.
1878 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1879 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1882 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1883 assert(N == 1 && "Invalid number of operands!");
1884 // The constant encodes as the immediate-1, and we store in the instruction
1885 // the bits as encoded, so subtract off one here.
1886 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1887 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1890 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1891 assert(N == 1 && "Invalid number of operands!");
1892 // The constant encodes as the immediate-1, and we store in the instruction
1893 // the bits as encoded, so subtract off one here.
1894 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1895 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1898 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1899 assert(N == 1 && "Invalid number of operands!");
1900 // The constant encodes as the immediate, except for 32, which encodes as
1902 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1903 unsigned Imm = CE->getValue();
1904 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1907 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1908 assert(N == 1 && "Invalid number of operands!");
1909 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1910 // the instruction as well.
1911 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1912 int Val = CE->getValue();
1913 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1916 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1917 assert(N == 1 && "Invalid number of operands!");
1918 // The operand is actually a t2_so_imm, but we have its bitwise
1919 // negation in the assembly source, so twiddle it here.
1920 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1921 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1924 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1925 assert(N == 1 && "Invalid number of operands!");
1926 // The operand is actually a t2_so_imm, but we have its
1927 // negation in the assembly source, so twiddle it here.
1928 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1929 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1932 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1933 assert(N == 1 && "Invalid number of operands!");
1934 // The operand is actually an imm0_4095, but we have its
1935 // negation in the assembly source, so twiddle it here.
1936 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1937 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1940 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1941 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1942 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1946 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1947 assert(SR && "Unknown value type!");
1948 Inst.addOperand(MCOperand::CreateExpr(SR));
1951 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1952 assert(N == 1 && "Invalid number of operands!");
1954 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1956 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1960 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1961 assert(SR && "Unknown value type!");
1962 Inst.addOperand(MCOperand::CreateExpr(SR));
1966 assert(isMem() && "Unknown value type!");
1967 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1968 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1971 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1972 assert(N == 1 && "Invalid number of operands!");
1973 // The operand is actually a so_imm, but we have its bitwise
1974 // negation in the assembly source, so twiddle it here.
1975 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1976 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1979 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1980 assert(N == 1 && "Invalid number of operands!");
1981 // The operand is actually a so_imm, but we have its
1982 // negation in the assembly source, so twiddle it here.
1983 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1984 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1987 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1988 assert(N == 1 && "Invalid number of operands!");
1989 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1992 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1993 assert(N == 1 && "Invalid number of operands!");
1994 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1997 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1998 assert(N == 1 && "Invalid number of operands!");
1999 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2002 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2003 assert(N == 1 && "Invalid number of operands!");
2004 int32_t Imm = Memory.OffsetImm->getValue();
2005 Inst.addOperand(MCOperand::CreateImm(Imm));
2008 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2009 assert(N == 1 && "Invalid number of operands!");
2010 assert(isImm() && "Not an immediate!");
2012 // If we have an immediate that's not a constant, treat it as a label
2013 // reference needing a fixup.
2014 if (!isa<MCConstantExpr>(getImm())) {
2015 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2019 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2020 int Val = CE->getValue();
2021 Inst.addOperand(MCOperand::CreateImm(Val));
2024 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2025 assert(N == 2 && "Invalid number of operands!");
2026 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2027 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
2030 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2031 addAlignedMemoryOperands(Inst, N);
2034 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2035 addAlignedMemoryOperands(Inst, N);
2038 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2039 addAlignedMemoryOperands(Inst, N);
2042 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2043 addAlignedMemoryOperands(Inst, N);
2046 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2047 addAlignedMemoryOperands(Inst, N);
2050 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2051 addAlignedMemoryOperands(Inst, N);
2054 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2055 addAlignedMemoryOperands(Inst, N);
2058 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2059 addAlignedMemoryOperands(Inst, N);
2062 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2063 addAlignedMemoryOperands(Inst, N);
2066 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2067 addAlignedMemoryOperands(Inst, N);
2070 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2071 addAlignedMemoryOperands(Inst, N);
2074 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2075 assert(N == 3 && "Invalid number of operands!");
2076 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2077 if (!Memory.OffsetRegNum) {
2078 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2079 // Special case for #-0
2080 if (Val == INT32_MIN) Val = 0;
2081 if (Val < 0) Val = -Val;
2082 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2084 // For register offset, we encode the shift type and negation flag
2086 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2087 Memory.ShiftImm, Memory.ShiftType);
2089 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2090 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2091 Inst.addOperand(MCOperand::CreateImm(Val));
2094 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2095 assert(N == 2 && "Invalid number of operands!");
2096 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2097 assert(CE && "non-constant AM2OffsetImm operand!");
2098 int32_t Val = CE->getValue();
2099 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2100 // Special case for #-0
2101 if (Val == INT32_MIN) Val = 0;
2102 if (Val < 0) Val = -Val;
2103 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2104 Inst.addOperand(MCOperand::CreateReg(0));
2105 Inst.addOperand(MCOperand::CreateImm(Val));
2108 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2109 assert(N == 3 && "Invalid number of operands!");
2110 // If we have an immediate that's not a constant, treat it as a label
2111 // reference needing a fixup. If it is a constant, it's something else
2112 // and we reject it.
2114 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2115 Inst.addOperand(MCOperand::CreateReg(0));
2116 Inst.addOperand(MCOperand::CreateImm(0));
2120 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2121 if (!Memory.OffsetRegNum) {
2122 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2123 // Special case for #-0
2124 if (Val == INT32_MIN) Val = 0;
2125 if (Val < 0) Val = -Val;
2126 Val = ARM_AM::getAM3Opc(AddSub, Val);
2128 // For register offset, we encode the shift type and negation flag
2130 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2132 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2133 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2134 Inst.addOperand(MCOperand::CreateImm(Val));
2137 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2138 assert(N == 2 && "Invalid number of operands!");
2139 if (Kind == k_PostIndexRegister) {
2141 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2142 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2143 Inst.addOperand(MCOperand::CreateImm(Val));
2148 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2149 int32_t Val = CE->getValue();
2150 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2151 // Special case for #-0
2152 if (Val == INT32_MIN) Val = 0;
2153 if (Val < 0) Val = -Val;
2154 Val = ARM_AM::getAM3Opc(AddSub, Val);
2155 Inst.addOperand(MCOperand::CreateReg(0));
2156 Inst.addOperand(MCOperand::CreateImm(Val));
2159 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2160 assert(N == 2 && "Invalid number of operands!");
2161 // If we have an immediate that's not a constant, treat it as a label
2162 // reference needing a fixup. If it is a constant, it's something else
2163 // and we reject it.
2165 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2166 Inst.addOperand(MCOperand::CreateImm(0));
2170 // The lower two bits are always zero and as such are not encoded.
2171 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2172 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2173 // Special case for #-0
2174 if (Val == INT32_MIN) Val = 0;
2175 if (Val < 0) Val = -Val;
2176 Val = ARM_AM::getAM5Opc(AddSub, Val);
2177 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2178 Inst.addOperand(MCOperand::CreateImm(Val));
2181 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2182 assert(N == 2 && "Invalid number of operands!");
2183 // If we have an immediate that's not a constant, treat it as a label
2184 // reference needing a fixup. If it is a constant, it's something else
2185 // and we reject it.
2187 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2188 Inst.addOperand(MCOperand::CreateImm(0));
2192 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2193 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2194 Inst.addOperand(MCOperand::CreateImm(Val));
2197 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2198 assert(N == 2 && "Invalid number of operands!");
2199 // The lower two bits are always zero and as such are not encoded.
2200 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2201 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2202 Inst.addOperand(MCOperand::CreateImm(Val));
2205 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2206 assert(N == 2 && "Invalid number of operands!");
2207 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2208 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2209 Inst.addOperand(MCOperand::CreateImm(Val));
2212 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2213 addMemImm8OffsetOperands(Inst, N);
2216 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2217 addMemImm8OffsetOperands(Inst, N);
2220 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2221 assert(N == 2 && "Invalid number of operands!");
2222 // If this is an immediate, it's a label reference.
2224 addExpr(Inst, getImm());
2225 Inst.addOperand(MCOperand::CreateImm(0));
2229 // Otherwise, it's a normal memory reg+offset.
2230 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2231 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2232 Inst.addOperand(MCOperand::CreateImm(Val));
2235 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2236 assert(N == 2 && "Invalid number of operands!");
2237 // If this is an immediate, it's a label reference.
2239 addExpr(Inst, getImm());
2240 Inst.addOperand(MCOperand::CreateImm(0));
2244 // Otherwise, it's a normal memory reg+offset.
2245 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2246 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2247 Inst.addOperand(MCOperand::CreateImm(Val));
2250 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2251 assert(N == 2 && "Invalid number of operands!");
2252 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2253 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2256 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2257 assert(N == 2 && "Invalid number of operands!");
2258 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2259 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2262 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2263 assert(N == 3 && "Invalid number of operands!");
2265 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2266 Memory.ShiftImm, Memory.ShiftType);
2267 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2268 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2269 Inst.addOperand(MCOperand::CreateImm(Val));
2272 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2273 assert(N == 3 && "Invalid number of operands!");
2274 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2275 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2276 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2279 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2280 assert(N == 2 && "Invalid number of operands!");
2281 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2282 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2285 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2286 assert(N == 2 && "Invalid number of operands!");
2287 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2288 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2289 Inst.addOperand(MCOperand::CreateImm(Val));
2292 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2293 assert(N == 2 && "Invalid number of operands!");
2294 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2295 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2296 Inst.addOperand(MCOperand::CreateImm(Val));
2299 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2300 assert(N == 2 && "Invalid number of operands!");
2301 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2302 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2303 Inst.addOperand(MCOperand::CreateImm(Val));
2306 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2307 assert(N == 2 && "Invalid number of operands!");
2308 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2309 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2310 Inst.addOperand(MCOperand::CreateImm(Val));
2313 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2314 assert(N == 1 && "Invalid number of operands!");
2315 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2316 assert(CE && "non-constant post-idx-imm8 operand!");
2317 int Imm = CE->getValue();
2318 bool isAdd = Imm >= 0;
2319 if (Imm == INT32_MIN) Imm = 0;
2320 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2321 Inst.addOperand(MCOperand::CreateImm(Imm));
2324 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2325 assert(N == 1 && "Invalid number of operands!");
2326 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2327 assert(CE && "non-constant post-idx-imm8s4 operand!");
2328 int Imm = CE->getValue();
2329 bool isAdd = Imm >= 0;
2330 if (Imm == INT32_MIN) Imm = 0;
2331 // Immediate is scaled by 4.
2332 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2333 Inst.addOperand(MCOperand::CreateImm(Imm));
2336 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2337 assert(N == 2 && "Invalid number of operands!");
2338 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2339 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2342 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2343 assert(N == 2 && "Invalid number of operands!");
2344 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2345 // The sign, shift type, and shift amount are encoded in a single operand
2346 // using the AM2 encoding helpers.
2347 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2348 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2349 PostIdxReg.ShiftTy);
2350 Inst.addOperand(MCOperand::CreateImm(Imm));
2353 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2354 assert(N == 1 && "Invalid number of operands!");
2355 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2358 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2359 assert(N == 1 && "Invalid number of operands!");
2360 Inst.addOperand(MCOperand::CreateImm(unsigned(getBankedReg())));
2363 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2364 assert(N == 1 && "Invalid number of operands!");
2365 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2368 void addVecListOperands(MCInst &Inst, unsigned N) const {
2369 assert(N == 1 && "Invalid number of operands!");
2370 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2373 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2374 assert(N == 2 && "Invalid number of operands!");
2375 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2376 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2379 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2380 assert(N == 1 && "Invalid number of operands!");
2381 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2384 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2385 assert(N == 1 && "Invalid number of operands!");
2386 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2389 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2390 assert(N == 1 && "Invalid number of operands!");
2391 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2394 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2395 assert(N == 1 && "Invalid number of operands!");
2396 // The immediate encodes the type of constant as well as the value.
2397 // Mask in that this is an i8 splat.
2398 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2399 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2402 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2403 assert(N == 1 && "Invalid number of operands!");
2404 // The immediate encodes the type of constant as well as the value.
2405 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2406 unsigned Value = CE->getValue();
2408 Value = (Value >> 8) | 0xa00;
2411 Inst.addOperand(MCOperand::CreateImm(Value));
2414 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2415 assert(N == 1 && "Invalid number of operands!");
2416 // The immediate encodes the type of constant as well as the value.
2417 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2418 unsigned Value = CE->getValue();
2419 if (Value >= 256 && Value <= 0xff00)
2420 Value = (Value >> 8) | 0x200;
2421 else if (Value > 0xffff && Value <= 0xff0000)
2422 Value = (Value >> 16) | 0x400;
2423 else if (Value > 0xffffff)
2424 Value = (Value >> 24) | 0x600;
2425 Inst.addOperand(MCOperand::CreateImm(Value));
2428 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2429 assert(N == 1 && "Invalid number of operands!");
2430 // The immediate encodes the type of constant as well as the value.
2431 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2432 unsigned Value = CE->getValue();
2433 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2434 Inst.getOpcode() == ARM::VMOVv16i8) &&
2435 "All vmvn instructions that wants to replicate non-zero byte "
2436 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2437 unsigned B = ((~Value) & 0xff);
2438 B |= 0xe00; // cmode = 0b1110
2439 Inst.addOperand(MCOperand::CreateImm(B));
2441 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2442 assert(N == 1 && "Invalid number of operands!");
2443 // The immediate encodes the type of constant as well as the value.
2444 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2445 unsigned Value = CE->getValue();
2446 if (Value >= 256 && Value <= 0xffff)
2447 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2448 else if (Value > 0xffff && Value <= 0xffffff)
2449 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2450 else if (Value > 0xffffff)
2451 Value = (Value >> 24) | 0x600;
2452 Inst.addOperand(MCOperand::CreateImm(Value));
2455 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2456 assert(N == 1 && "Invalid number of operands!");
2457 // The immediate encodes the type of constant as well as the value.
2458 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2459 unsigned Value = CE->getValue();
2460 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2461 Inst.getOpcode() == ARM::VMOVv16i8) &&
2462 "All instructions that wants to replicate non-zero byte "
2463 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2464 unsigned B = Value & 0xff;
2465 B |= 0xe00; // cmode = 0b1110
2466 Inst.addOperand(MCOperand::CreateImm(B));
2468 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2469 assert(N == 1 && "Invalid number of operands!");
2470 // The immediate encodes the type of constant as well as the value.
2471 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2472 unsigned Value = ~CE->getValue();
2473 if (Value >= 256 && Value <= 0xffff)
2474 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2475 else if (Value > 0xffff && Value <= 0xffffff)
2476 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2477 else if (Value > 0xffffff)
2478 Value = (Value >> 24) | 0x600;
2479 Inst.addOperand(MCOperand::CreateImm(Value));
2482 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2483 assert(N == 1 && "Invalid number of operands!");
2484 // The immediate encodes the type of constant as well as the value.
2485 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2486 uint64_t Value = CE->getValue();
2488 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2489 Imm |= (Value & 1) << i;
2491 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2494 void print(raw_ostream &OS) const override;
2496 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2497 auto Op = make_unique<ARMOperand>(k_ITCondMask);
2498 Op->ITMask.Mask = Mask;
2504 static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2506 auto Op = make_unique<ARMOperand>(k_CondCode);
2513 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2514 auto Op = make_unique<ARMOperand>(k_CoprocNum);
2515 Op->Cop.Val = CopVal;
2521 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2522 auto Op = make_unique<ARMOperand>(k_CoprocReg);
2523 Op->Cop.Val = CopVal;
2529 static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2531 auto Op = make_unique<ARMOperand>(k_CoprocOption);
2538 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2539 auto Op = make_unique<ARMOperand>(k_CCOut);
2540 Op->Reg.RegNum = RegNum;
2546 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2547 auto Op = make_unique<ARMOperand>(k_Token);
2548 Op->Tok.Data = Str.data();
2549 Op->Tok.Length = Str.size();
2555 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2557 auto Op = make_unique<ARMOperand>(k_Register);
2558 Op->Reg.RegNum = RegNum;
2564 static std::unique_ptr<ARMOperand>
2565 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2566 unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2568 auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2569 Op->RegShiftedReg.ShiftTy = ShTy;
2570 Op->RegShiftedReg.SrcReg = SrcReg;
2571 Op->RegShiftedReg.ShiftReg = ShiftReg;
2572 Op->RegShiftedReg.ShiftImm = ShiftImm;
2578 static std::unique_ptr<ARMOperand>
2579 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2580 unsigned ShiftImm, SMLoc S, SMLoc E) {
2581 auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2582 Op->RegShiftedImm.ShiftTy = ShTy;
2583 Op->RegShiftedImm.SrcReg = SrcReg;
2584 Op->RegShiftedImm.ShiftImm = ShiftImm;
2590 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2592 auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2593 Op->ShifterImm.isASR = isASR;
2594 Op->ShifterImm.Imm = Imm;
2600 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2602 auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2603 Op->RotImm.Imm = Imm;
2609 static std::unique_ptr<ARMOperand>
2610 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2611 auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2612 Op->Bitfield.LSB = LSB;
2613 Op->Bitfield.Width = Width;
2619 static std::unique_ptr<ARMOperand>
2620 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2621 SMLoc StartLoc, SMLoc EndLoc) {
2622 assert (Regs.size() > 0 && "RegList contains no registers?");
2623 KindTy Kind = k_RegisterList;
2625 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2626 Kind = k_DPRRegisterList;
2627 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2628 contains(Regs.front().second))
2629 Kind = k_SPRRegisterList;
2631 // Sort based on the register encoding values.
2632 array_pod_sort(Regs.begin(), Regs.end());
2634 auto Op = make_unique<ARMOperand>(Kind);
2635 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2636 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2637 Op->Registers.push_back(I->second);
2638 Op->StartLoc = StartLoc;
2639 Op->EndLoc = EndLoc;
2643 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2645 bool isDoubleSpaced,
2647 auto Op = make_unique<ARMOperand>(k_VectorList);
2648 Op->VectorList.RegNum = RegNum;
2649 Op->VectorList.Count = Count;
2650 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2656 static std::unique_ptr<ARMOperand>
2657 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2659 auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2660 Op->VectorList.RegNum = RegNum;
2661 Op->VectorList.Count = Count;
2662 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2668 static std::unique_ptr<ARMOperand>
2669 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2670 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2671 auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2672 Op->VectorList.RegNum = RegNum;
2673 Op->VectorList.Count = Count;
2674 Op->VectorList.LaneIndex = Index;
2675 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2681 static std::unique_ptr<ARMOperand>
2682 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2683 auto Op = make_unique<ARMOperand>(k_VectorIndex);
2684 Op->VectorIndex.Val = Idx;
2690 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2692 auto Op = make_unique<ARMOperand>(k_Immediate);
2699 static std::unique_ptr<ARMOperand>
2700 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2701 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2702 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2703 SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2704 auto Op = make_unique<ARMOperand>(k_Memory);
2705 Op->Memory.BaseRegNum = BaseRegNum;
2706 Op->Memory.OffsetImm = OffsetImm;
2707 Op->Memory.OffsetRegNum = OffsetRegNum;
2708 Op->Memory.ShiftType = ShiftType;
2709 Op->Memory.ShiftImm = ShiftImm;
2710 Op->Memory.Alignment = Alignment;
2711 Op->Memory.isNegative = isNegative;
2714 Op->AlignmentLoc = AlignmentLoc;
2718 static std::unique_ptr<ARMOperand>
2719 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2720 unsigned ShiftImm, SMLoc S, SMLoc E) {
2721 auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
2722 Op->PostIdxReg.RegNum = RegNum;
2723 Op->PostIdxReg.isAdd = isAdd;
2724 Op->PostIdxReg.ShiftTy = ShiftTy;
2725 Op->PostIdxReg.ShiftImm = ShiftImm;
2731 static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2733 auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
2734 Op->MBOpt.Val = Opt;
2740 static std::unique_ptr<ARMOperand>
2741 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
2742 auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
2743 Op->ISBOpt.Val = Opt;
2749 static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
2751 auto Op = make_unique<ARMOperand>(k_ProcIFlags);
2752 Op->IFlags.Val = IFlags;
2758 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
2759 auto Op = make_unique<ARMOperand>(k_MSRMask);
2760 Op->MMask.Val = MMask;
2766 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
2767 auto Op = make_unique<ARMOperand>(k_BankedReg);
2768 Op->BankedReg.Val = Reg;
2775 } // end anonymous namespace.
2777 void ARMOperand::print(raw_ostream &OS) const {
2780 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2783 OS << "<ccout " << getReg() << ">";
2785 case k_ITCondMask: {
2786 static const char *const MaskStr[] = {
2787 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2788 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2790 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2791 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2795 OS << "<coprocessor number: " << getCoproc() << ">";
2798 OS << "<coprocessor register: " << getCoproc() << ">";
2800 case k_CoprocOption:
2801 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2804 OS << "<mask: " << getMSRMask() << ">";
2807 OS << "<banked reg: " << getBankedReg() << ">";
2810 getImm()->print(OS);
2812 case k_MemBarrierOpt:
2813 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2815 case k_InstSyncBarrierOpt:
2816 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2820 << " base:" << Memory.BaseRegNum;
2823 case k_PostIndexRegister:
2824 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2825 << PostIdxReg.RegNum;
2826 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2827 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2828 << PostIdxReg.ShiftImm;
2831 case k_ProcIFlags: {
2832 OS << "<ARM_PROC::";
2833 unsigned IFlags = getProcIFlags();
2834 for (int i=2; i >= 0; --i)
2835 if (IFlags & (1 << i))
2836 OS << ARM_PROC::IFlagsToString(1 << i);
2841 OS << "<register " << getReg() << ">";
2843 case k_ShifterImmediate:
2844 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2845 << " #" << ShifterImm.Imm << ">";
2847 case k_ShiftedRegister:
2848 OS << "<so_reg_reg "
2849 << RegShiftedReg.SrcReg << " "
2850 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2851 << " " << RegShiftedReg.ShiftReg << ">";
2853 case k_ShiftedImmediate:
2854 OS << "<so_reg_imm "
2855 << RegShiftedImm.SrcReg << " "
2856 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2857 << " #" << RegShiftedImm.ShiftImm << ">";
2859 case k_RotateImmediate:
2860 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2862 case k_BitfieldDescriptor:
2863 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2864 << ", width: " << Bitfield.Width << ">";
2866 case k_RegisterList:
2867 case k_DPRRegisterList:
2868 case k_SPRRegisterList: {
2869 OS << "<register_list ";
2871 const SmallVectorImpl<unsigned> &RegList = getRegList();
2872 for (SmallVectorImpl<unsigned>::const_iterator
2873 I = RegList.begin(), E = RegList.end(); I != E; ) {
2875 if (++I < E) OS << ", ";
2882 OS << "<vector_list " << VectorList.Count << " * "
2883 << VectorList.RegNum << ">";
2885 case k_VectorListAllLanes:
2886 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2887 << VectorList.RegNum << ">";
2889 case k_VectorListIndexed:
2890 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2891 << VectorList.Count << " * " << VectorList.RegNum << ">";
2894 OS << "'" << getToken() << "'";
2897 OS << "<vectorindex " << getVectorIndex() << ">";
2902 /// @name Auto-generated Match Functions
2905 static unsigned MatchRegisterName(StringRef Name);
2909 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2910 SMLoc &StartLoc, SMLoc &EndLoc) {
2911 StartLoc = Parser.getTok().getLoc();
2912 EndLoc = Parser.getTok().getEndLoc();
2913 RegNo = tryParseRegister();
2915 return (RegNo == (unsigned)-1);
2918 /// Try to parse a register name. The token must be an Identifier when called,
2919 /// and if it is a register name the token is eaten and the register number is
2920 /// returned. Otherwise return -1.
2922 int ARMAsmParser::tryParseRegister() {
2923 const AsmToken &Tok = Parser.getTok();
2924 if (Tok.isNot(AsmToken::Identifier)) return -1;
2926 std::string lowerCase = Tok.getString().lower();
2927 unsigned RegNum = MatchRegisterName(lowerCase);
2929 RegNum = StringSwitch<unsigned>(lowerCase)
2930 .Case("r13", ARM::SP)
2931 .Case("r14", ARM::LR)
2932 .Case("r15", ARM::PC)
2933 .Case("ip", ARM::R12)
2934 // Additional register name aliases for 'gas' compatibility.
2935 .Case("a1", ARM::R0)
2936 .Case("a2", ARM::R1)
2937 .Case("a3", ARM::R2)
2938 .Case("a4", ARM::R3)
2939 .Case("v1", ARM::R4)
2940 .Case("v2", ARM::R5)
2941 .Case("v3", ARM::R6)
2942 .Case("v4", ARM::R7)
2943 .Case("v5", ARM::R8)
2944 .Case("v6", ARM::R9)
2945 .Case("v7", ARM::R10)
2946 .Case("v8", ARM::R11)
2947 .Case("sb", ARM::R9)
2948 .Case("sl", ARM::R10)
2949 .Case("fp", ARM::R11)
2953 // Check for aliases registered via .req. Canonicalize to lower case.
2954 // That's more consistent since register names are case insensitive, and
2955 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2956 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2957 // If no match, return failure.
2958 if (Entry == RegisterReqs.end())
2960 Parser.Lex(); // Eat identifier token.
2961 return Entry->getValue();
2964 Parser.Lex(); // Eat identifier token.
2969 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2970 // If a recoverable error occurs, return 1. If an irrecoverable error
2971 // occurs, return -1. An irrecoverable error is one where tokens have been
2972 // consumed in the process of trying to parse the shifter (i.e., when it is
2973 // indeed a shifter operand, but malformed).
2974 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
2975 SMLoc S = Parser.getTok().getLoc();
2976 const AsmToken &Tok = Parser.getTok();
2977 if (Tok.isNot(AsmToken::Identifier))
2980 std::string lowerCase = Tok.getString().lower();
2981 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2982 .Case("asl", ARM_AM::lsl)
2983 .Case("lsl", ARM_AM::lsl)
2984 .Case("lsr", ARM_AM::lsr)
2985 .Case("asr", ARM_AM::asr)
2986 .Case("ror", ARM_AM::ror)
2987 .Case("rrx", ARM_AM::rrx)
2988 .Default(ARM_AM::no_shift);
2990 if (ShiftTy == ARM_AM::no_shift)
2993 Parser.Lex(); // Eat the operator.
2995 // The source register for the shift has already been added to the
2996 // operand list, so we need to pop it off and combine it into the shifted
2997 // register operand instead.
2998 std::unique_ptr<ARMOperand> PrevOp(
2999 (ARMOperand *)Operands.pop_back_val().release());
3000 if (!PrevOp->isReg())
3001 return Error(PrevOp->getStartLoc(), "shift must be of a register");
3002 int SrcReg = PrevOp->getReg();
3007 if (ShiftTy == ARM_AM::rrx) {
3008 // RRX Doesn't have an explicit shift amount. The encoder expects
3009 // the shift register to be the same as the source register. Seems odd,
3013 // Figure out if this is shifted by a constant or a register (for non-RRX).
3014 if (Parser.getTok().is(AsmToken::Hash) ||
3015 Parser.getTok().is(AsmToken::Dollar)) {
3016 Parser.Lex(); // Eat hash.
3017 SMLoc ImmLoc = Parser.getTok().getLoc();
3018 const MCExpr *ShiftExpr = nullptr;
3019 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3020 Error(ImmLoc, "invalid immediate shift value");
3023 // The expression must be evaluatable as an immediate.
3024 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3026 Error(ImmLoc, "invalid immediate shift value");
3029 // Range check the immediate.
3030 // lsl, ror: 0 <= imm <= 31
3031 // lsr, asr: 0 <= imm <= 32
3032 Imm = CE->getValue();
3034 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3035 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3036 Error(ImmLoc, "immediate shift value out of range");
3039 // shift by zero is a nop. Always send it through as lsl.
3040 // ('as' compatibility)
3042 ShiftTy = ARM_AM::lsl;
3043 } else if (Parser.getTok().is(AsmToken::Identifier)) {
3044 SMLoc L = Parser.getTok().getLoc();
3045 EndLoc = Parser.getTok().getEndLoc();
3046 ShiftReg = tryParseRegister();
3047 if (ShiftReg == -1) {
3048 Error(L, "expected immediate or register in shift operand");
3052 Error(Parser.getTok().getLoc(),
3053 "expected immediate or register in shift operand");
3058 if (ShiftReg && ShiftTy != ARM_AM::rrx)
3059 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3063 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3070 /// Try to parse a register name. The token must be an Identifier when called.
3071 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3072 /// if there is a "writeback". 'true' if it's not a register.
3074 /// TODO this is likely to change to allow different register types and or to
3075 /// parse for a specific register type.
3076 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3077 const AsmToken &RegTok = Parser.getTok();
3078 int RegNo = tryParseRegister();
3082 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3083 RegTok.getEndLoc()));
3085 const AsmToken &ExclaimTok = Parser.getTok();
3086 if (ExclaimTok.is(AsmToken::Exclaim)) {
3087 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3088 ExclaimTok.getLoc()));
3089 Parser.Lex(); // Eat exclaim token
3093 // Also check for an index operand. This is only legal for vector registers,
3094 // but that'll get caught OK in operand matching, so we don't need to
3095 // explicitly filter everything else out here.
3096 if (Parser.getTok().is(AsmToken::LBrac)) {
3097 SMLoc SIdx = Parser.getTok().getLoc();
3098 Parser.Lex(); // Eat left bracket token.
3100 const MCExpr *ImmVal;
3101 if (getParser().parseExpression(ImmVal))
3103 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3105 return TokError("immediate value expected for vector index");
3107 if (Parser.getTok().isNot(AsmToken::RBrac))
3108 return Error(Parser.getTok().getLoc(), "']' expected");
3110 SMLoc E = Parser.getTok().getEndLoc();
3111 Parser.Lex(); // Eat right bracket token.
3113 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3121 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3122 /// instruction with a symbolic operand name.
3123 /// We accept "crN" syntax for GAS compatibility.
3124 /// <operand-name> ::= <prefix><number>
3125 /// If CoprocOp is 'c', then:
3126 /// <prefix> ::= c | cr
3127 /// If CoprocOp is 'p', then :
3129 /// <number> ::= integer in range [0, 15]
3130 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3131 // Use the same layout as the tablegen'erated register name matcher. Ugly,
3133 if (Name.size() < 2 || Name[0] != CoprocOp)
3135 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3137 switch (Name.size()) {
3158 // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3159 // However, old cores (v5/v6) did use them in that way.
3160 case '0': return 10;
3161 case '1': return 11;
3162 case '2': return 12;
3163 case '3': return 13;
3164 case '4': return 14;
3165 case '5': return 15;
3170 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3171 ARMAsmParser::OperandMatchResultTy
3172 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3173 SMLoc S = Parser.getTok().getLoc();
3174 const AsmToken &Tok = Parser.getTok();
3175 if (!Tok.is(AsmToken::Identifier))
3176 return MatchOperand_NoMatch;
3177 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3178 .Case("eq", ARMCC::EQ)
3179 .Case("ne", ARMCC::NE)
3180 .Case("hs", ARMCC::HS)
3181 .Case("cs", ARMCC::HS)
3182 .Case("lo", ARMCC::LO)
3183 .Case("cc", ARMCC::LO)
3184 .Case("mi", ARMCC::MI)
3185 .Case("pl", ARMCC::PL)
3186 .Case("vs", ARMCC::VS)
3187 .Case("vc", ARMCC::VC)
3188 .Case("hi", ARMCC::HI)
3189 .Case("ls", ARMCC::LS)
3190 .Case("ge", ARMCC::GE)
3191 .Case("lt", ARMCC::LT)
3192 .Case("gt", ARMCC::GT)
3193 .Case("le", ARMCC::LE)
3194 .Case("al", ARMCC::AL)
3197 return MatchOperand_NoMatch;
3198 Parser.Lex(); // Eat the token.
3200 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3202 return MatchOperand_Success;
3205 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3206 /// token must be an Identifier when called, and if it is a coprocessor
3207 /// number, the token is eaten and the operand is added to the operand list.
3208 ARMAsmParser::OperandMatchResultTy
3209 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3210 SMLoc S = Parser.getTok().getLoc();
3211 const AsmToken &Tok = Parser.getTok();
3212 if (Tok.isNot(AsmToken::Identifier))
3213 return MatchOperand_NoMatch;
3215 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3217 return MatchOperand_NoMatch;
3218 // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3219 if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3220 return MatchOperand_NoMatch;
3222 Parser.Lex(); // Eat identifier token.
3223 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3224 return MatchOperand_Success;
3227 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3228 /// token must be an Identifier when called, and if it is a coprocessor
3229 /// number, the token is eaten and the operand is added to the operand list.
3230 ARMAsmParser::OperandMatchResultTy
3231 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3232 SMLoc S = Parser.getTok().getLoc();
3233 const AsmToken &Tok = Parser.getTok();
3234 if (Tok.isNot(AsmToken::Identifier))
3235 return MatchOperand_NoMatch;
3237 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3239 return MatchOperand_NoMatch;
3241 Parser.Lex(); // Eat identifier token.
3242 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3243 return MatchOperand_Success;
3246 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3247 /// coproc_option : '{' imm0_255 '}'
3248 ARMAsmParser::OperandMatchResultTy
3249 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3250 SMLoc S = Parser.getTok().getLoc();
3252 // If this isn't a '{', this isn't a coprocessor immediate operand.
3253 if (Parser.getTok().isNot(AsmToken::LCurly))
3254 return MatchOperand_NoMatch;
3255 Parser.Lex(); // Eat the '{'
3258 SMLoc Loc = Parser.getTok().getLoc();
3259 if (getParser().parseExpression(Expr)) {
3260 Error(Loc, "illegal expression");
3261 return MatchOperand_ParseFail;
3263 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3264 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3265 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3266 return MatchOperand_ParseFail;
3268 int Val = CE->getValue();
3270 // Check for and consume the closing '}'
3271 if (Parser.getTok().isNot(AsmToken::RCurly))
3272 return MatchOperand_ParseFail;
3273 SMLoc E = Parser.getTok().getEndLoc();
3274 Parser.Lex(); // Eat the '}'
3276 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3277 return MatchOperand_Success;
3280 // For register list parsing, we need to map from raw GPR register numbering
3281 // to the enumeration values. The enumeration values aren't sorted by
3282 // register number due to our using "sp", "lr" and "pc" as canonical names.
3283 static unsigned getNextRegister(unsigned Reg) {
3284 // If this is a GPR, we need to do it manually, otherwise we can rely
3285 // on the sort ordering of the enumeration since the other reg-classes
3287 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3290 default: llvm_unreachable("Invalid GPR number!");
3291 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3292 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3293 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3294 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3295 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3296 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3297 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3298 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3302 // Return the low-subreg of a given Q register.
3303 static unsigned getDRegFromQReg(unsigned QReg) {
3305 default: llvm_unreachable("expected a Q register!");
3306 case ARM::Q0: return ARM::D0;
3307 case ARM::Q1: return ARM::D2;
3308 case ARM::Q2: return ARM::D4;
3309 case ARM::Q3: return ARM::D6;
3310 case ARM::Q4: return ARM::D8;
3311 case ARM::Q5: return ARM::D10;
3312 case ARM::Q6: return ARM::D12;
3313 case ARM::Q7: return ARM::D14;
3314 case ARM::Q8: return ARM::D16;
3315 case ARM::Q9: return ARM::D18;
3316 case ARM::Q10: return ARM::D20;
3317 case ARM::Q11: return ARM::D22;
3318 case ARM::Q12: return ARM::D24;
3319 case ARM::Q13: return ARM::D26;
3320 case ARM::Q14: return ARM::D28;
3321 case ARM::Q15: return ARM::D30;
3325 /// Parse a register list.
3326 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3327 assert(Parser.getTok().is(AsmToken::LCurly) &&
3328 "Token is not a Left Curly Brace");
3329 SMLoc S = Parser.getTok().getLoc();
3330 Parser.Lex(); // Eat '{' token.
3331 SMLoc RegLoc = Parser.getTok().getLoc();
3333 // Check the first register in the list to see what register class
3334 // this is a list of.
3335 int Reg = tryParseRegister();
3337 return Error(RegLoc, "register expected");
3339 // The reglist instructions have at most 16 registers, so reserve
3340 // space for that many.
3342 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3344 // Allow Q regs and just interpret them as the two D sub-registers.
3345 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3346 Reg = getDRegFromQReg(Reg);
3347 EReg = MRI->getEncodingValue(Reg);
3348 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3351 const MCRegisterClass *RC;
3352 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3353 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3354 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3355 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3356 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3357 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3359 return Error(RegLoc, "invalid register in register list");
3361 // Store the register.
3362 EReg = MRI->getEncodingValue(Reg);
3363 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3365 // This starts immediately after the first register token in the list,
3366 // so we can see either a comma or a minus (range separator) as a legal
3368 while (Parser.getTok().is(AsmToken::Comma) ||
3369 Parser.getTok().is(AsmToken::Minus)) {
3370 if (Parser.getTok().is(AsmToken::Minus)) {
3371 Parser.Lex(); // Eat the minus.
3372 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3373 int EndReg = tryParseRegister();
3375 return Error(AfterMinusLoc, "register expected");
3376 // Allow Q regs and just interpret them as the two D sub-registers.
3377 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3378 EndReg = getDRegFromQReg(EndReg) + 1;
3379 // If the register is the same as the start reg, there's nothing
3383 // The register must be in the same register class as the first.
3384 if (!RC->contains(EndReg))
3385 return Error(AfterMinusLoc, "invalid register in register list");
3386 // Ranges must go from low to high.
3387 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3388 return Error(AfterMinusLoc, "bad range in register list");
3390 // Add all the registers in the range to the register list.
3391 while (Reg != EndReg) {
3392 Reg = getNextRegister(Reg);
3393 EReg = MRI->getEncodingValue(Reg);
3394 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3398 Parser.Lex(); // Eat the comma.
3399 RegLoc = Parser.getTok().getLoc();
3401 const AsmToken RegTok = Parser.getTok();
3402 Reg = tryParseRegister();
3404 return Error(RegLoc, "register expected");
3405 // Allow Q regs and just interpret them as the two D sub-registers.
3406 bool isQReg = false;
3407 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3408 Reg = getDRegFromQReg(Reg);
3411 // The register must be in the same register class as the first.
3412 if (!RC->contains(Reg))
3413 return Error(RegLoc, "invalid register in register list");
3414 // List must be monotonically increasing.
3415 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3416 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3417 Warning(RegLoc, "register list not in ascending order");
3419 return Error(RegLoc, "register list not in ascending order");
3421 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3422 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3423 ") in register list");
3426 // VFP register lists must also be contiguous.
3427 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3429 return Error(RegLoc, "non-contiguous register range");
3430 EReg = MRI->getEncodingValue(Reg);
3431 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3433 EReg = MRI->getEncodingValue(++Reg);
3434 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3438 if (Parser.getTok().isNot(AsmToken::RCurly))
3439 return Error(Parser.getTok().getLoc(), "'}' expected");
3440 SMLoc E = Parser.getTok().getEndLoc();
3441 Parser.Lex(); // Eat '}' token.
3443 // Push the register list operand.
3444 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3446 // The ARM system instruction variants for LDM/STM have a '^' token here.
3447 if (Parser.getTok().is(AsmToken::Caret)) {
3448 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3449 Parser.Lex(); // Eat '^' token.
3455 // Helper function to parse the lane index for vector lists.
3456 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3457 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3458 Index = 0; // Always return a defined index value.
3459 if (Parser.getTok().is(AsmToken::LBrac)) {
3460 Parser.Lex(); // Eat the '['.
3461 if (Parser.getTok().is(AsmToken::RBrac)) {
3462 // "Dn[]" is the 'all lanes' syntax.
3463 LaneKind = AllLanes;
3464 EndLoc = Parser.getTok().getEndLoc();
3465 Parser.Lex(); // Eat the ']'.
3466 return MatchOperand_Success;
3469 // There's an optional '#' token here. Normally there wouldn't be, but
3470 // inline assemble puts one in, and it's friendly to accept that.
3471 if (Parser.getTok().is(AsmToken::Hash))
3472 Parser.Lex(); // Eat '#' or '$'.
3474 const MCExpr *LaneIndex;
3475 SMLoc Loc = Parser.getTok().getLoc();
3476 if (getParser().parseExpression(LaneIndex)) {
3477 Error(Loc, "illegal expression");
3478 return MatchOperand_ParseFail;
3480 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3482 Error(Loc, "lane index must be empty or an integer");
3483 return MatchOperand_ParseFail;
3485 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3486 Error(Parser.getTok().getLoc(), "']' expected");
3487 return MatchOperand_ParseFail;
3489 EndLoc = Parser.getTok().getEndLoc();
3490 Parser.Lex(); // Eat the ']'.
3491 int64_t Val = CE->getValue();
3493 // FIXME: Make this range check context sensitive for .8, .16, .32.
3494 if (Val < 0 || Val > 7) {
3495 Error(Parser.getTok().getLoc(), "lane index out of range");
3496 return MatchOperand_ParseFail;
3499 LaneKind = IndexedLane;
3500 return MatchOperand_Success;
3503 return MatchOperand_Success;
3506 // parse a vector register list
3507 ARMAsmParser::OperandMatchResultTy
3508 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3509 VectorLaneTy LaneKind;
3511 SMLoc S = Parser.getTok().getLoc();
3512 // As an extension (to match gas), support a plain D register or Q register
3513 // (without encosing curly braces) as a single or double entry list,
3515 if (Parser.getTok().is(AsmToken::Identifier)) {
3516 SMLoc E = Parser.getTok().getEndLoc();
3517 int Reg = tryParseRegister();
3519 return MatchOperand_NoMatch;
3520 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3521 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3522 if (Res != MatchOperand_Success)
3526 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3529 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3533 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3538 return MatchOperand_Success;
3540 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3541 Reg = getDRegFromQReg(Reg);
3542 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3543 if (Res != MatchOperand_Success)
3547 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3548 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3549 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3552 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3553 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3554 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3558 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3563 return MatchOperand_Success;
3565 Error(S, "vector register expected");
3566 return MatchOperand_ParseFail;
3569 if (Parser.getTok().isNot(AsmToken::LCurly))
3570 return MatchOperand_NoMatch;
3572 Parser.Lex(); // Eat '{' token.
3573 SMLoc RegLoc = Parser.getTok().getLoc();
3575 int Reg = tryParseRegister();
3577 Error(RegLoc, "register expected");
3578 return MatchOperand_ParseFail;
3582 unsigned FirstReg = Reg;
3583 // The list is of D registers, but we also allow Q regs and just interpret
3584 // them as the two D sub-registers.
3585 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3586 FirstReg = Reg = getDRegFromQReg(Reg);
3587 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3588 // it's ambiguous with four-register single spaced.
3594 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3595 return MatchOperand_ParseFail;
3597 while (Parser.getTok().is(AsmToken::Comma) ||
3598 Parser.getTok().is(AsmToken::Minus)) {
3599 if (Parser.getTok().is(AsmToken::Minus)) {
3601 Spacing = 1; // Register range implies a single spaced list.
3602 else if (Spacing == 2) {
3603 Error(Parser.getTok().getLoc(),
3604 "sequential registers in double spaced list");
3605 return MatchOperand_ParseFail;
3607 Parser.Lex(); // Eat the minus.
3608 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3609 int EndReg = tryParseRegister();
3611 Error(AfterMinusLoc, "register expected");
3612 return MatchOperand_ParseFail;
3614 // Allow Q regs and just interpret them as the two D sub-registers.
3615 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3616 EndReg = getDRegFromQReg(EndReg) + 1;
3617 // If the register is the same as the start reg, there's nothing
3621 // The register must be in the same register class as the first.
3622 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3623 Error(AfterMinusLoc, "invalid register in register list");
3624 return MatchOperand_ParseFail;
3626 // Ranges must go from low to high.
3628 Error(AfterMinusLoc, "bad range in register list");
3629 return MatchOperand_ParseFail;
3631 // Parse the lane specifier if present.
3632 VectorLaneTy NextLaneKind;
3633 unsigned NextLaneIndex;
3634 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3635 MatchOperand_Success)
3636 return MatchOperand_ParseFail;
3637 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3638 Error(AfterMinusLoc, "mismatched lane index in register list");
3639 return MatchOperand_ParseFail;
3642 // Add all the registers in the range to the register list.
3643 Count += EndReg - Reg;
3647 Parser.Lex(); // Eat the comma.
3648 RegLoc = Parser.getTok().getLoc();
3650 Reg = tryParseRegister();
3652 Error(RegLoc, "register expected");
3653 return MatchOperand_ParseFail;
3655 // vector register lists must be contiguous.
3656 // It's OK to use the enumeration values directly here rather, as the
3657 // VFP register classes have the enum sorted properly.
3659 // The list is of D registers, but we also allow Q regs and just interpret
3660 // them as the two D sub-registers.
3661 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3663 Spacing = 1; // Register range implies a single spaced list.
3664 else if (Spacing == 2) {
3666 "invalid register in double-spaced list (must be 'D' register')");
3667 return MatchOperand_ParseFail;
3669 Reg = getDRegFromQReg(Reg);
3670 if (Reg != OldReg + 1) {
3671 Error(RegLoc, "non-contiguous register range");
3672 return MatchOperand_ParseFail;
3676 // Parse the lane specifier if present.
3677 VectorLaneTy NextLaneKind;
3678 unsigned NextLaneIndex;
3679 SMLoc LaneLoc = Parser.getTok().getLoc();
3680 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3681 MatchOperand_Success)
3682 return MatchOperand_ParseFail;
3683 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3684 Error(LaneLoc, "mismatched lane index in register list");
3685 return MatchOperand_ParseFail;
3689 // Normal D register.
3690 // Figure out the register spacing (single or double) of the list if
3691 // we don't know it already.
3693 Spacing = 1 + (Reg == OldReg + 2);
3695 // Just check that it's contiguous and keep going.
3696 if (Reg != OldReg + Spacing) {
3697 Error(RegLoc, "non-contiguous register range");
3698 return MatchOperand_ParseFail;
3701 // Parse the lane specifier if present.
3702 VectorLaneTy NextLaneKind;
3703 unsigned NextLaneIndex;
3704 SMLoc EndLoc = Parser.getTok().getLoc();
3705 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3706 return MatchOperand_ParseFail;
3707 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3708 Error(EndLoc, "mismatched lane index in register list");
3709 return MatchOperand_ParseFail;
3713 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3714 Error(Parser.getTok().getLoc(), "'}' expected");
3715 return MatchOperand_ParseFail;
3717 E = Parser.getTok().getEndLoc();
3718 Parser.Lex(); // Eat '}' token.
3722 // Two-register operands have been converted to the
3723 // composite register classes.
3725 const MCRegisterClass *RC = (Spacing == 1) ?
3726 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3727 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3728 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3731 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3732 (Spacing == 2), S, E));
3735 // Two-register operands have been converted to the
3736 // composite register classes.
3738 const MCRegisterClass *RC = (Spacing == 1) ?
3739 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3740 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3741 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3743 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3748 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3754 return MatchOperand_Success;
3757 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3758 ARMAsmParser::OperandMatchResultTy
3759 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
3760 SMLoc S = Parser.getTok().getLoc();
3761 const AsmToken &Tok = Parser.getTok();
3764 if (Tok.is(AsmToken::Identifier)) {
3765 StringRef OptStr = Tok.getString();
3767 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3768 .Case("sy", ARM_MB::SY)
3769 .Case("st", ARM_MB::ST)
3770 .Case("ld", ARM_MB::LD)
3771 .Case("sh", ARM_MB::ISH)
3772 .Case("ish", ARM_MB::ISH)
3773 .Case("shst", ARM_MB::ISHST)
3774 .Case("ishst", ARM_MB::ISHST)
3775 .Case("ishld", ARM_MB::ISHLD)
3776 .Case("nsh", ARM_MB::NSH)
3777 .Case("un", ARM_MB::NSH)
3778 .Case("nshst", ARM_MB::NSHST)
3779 .Case("nshld", ARM_MB::NSHLD)
3780 .Case("unst", ARM_MB::NSHST)
3781 .Case("osh", ARM_MB::OSH)
3782 .Case("oshst", ARM_MB::OSHST)
3783 .Case("oshld", ARM_MB::OSHLD)
3786 // ishld, oshld, nshld and ld are only available from ARMv8.
3787 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3788 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3792 return MatchOperand_NoMatch;
3794 Parser.Lex(); // Eat identifier token.
3795 } else if (Tok.is(AsmToken::Hash) ||
3796 Tok.is(AsmToken::Dollar) ||
3797 Tok.is(AsmToken::Integer)) {
3798 if (Parser.getTok().isNot(AsmToken::Integer))
3799 Parser.Lex(); // Eat '#' or '$'.
3800 SMLoc Loc = Parser.getTok().getLoc();
3802 const MCExpr *MemBarrierID;
3803 if (getParser().parseExpression(MemBarrierID)) {
3804 Error(Loc, "illegal expression");
3805 return MatchOperand_ParseFail;
3808 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3810 Error(Loc, "constant expression expected");
3811 return MatchOperand_ParseFail;
3814 int Val = CE->getValue();
3816 Error(Loc, "immediate value out of range");
3817 return MatchOperand_ParseFail;
3820 Opt = ARM_MB::RESERVED_0 + Val;
3822 return MatchOperand_ParseFail;
3824 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3825 return MatchOperand_Success;
3828 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3829 ARMAsmParser::OperandMatchResultTy
3830 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
3831 SMLoc S = Parser.getTok().getLoc();
3832 const AsmToken &Tok = Parser.getTok();
3835 if (Tok.is(AsmToken::Identifier)) {
3836 StringRef OptStr = Tok.getString();
3838 if (OptStr.equals_lower("sy"))
3841 return MatchOperand_NoMatch;
3843 Parser.Lex(); // Eat identifier token.
3844 } else if (Tok.is(AsmToken::Hash) ||
3845 Tok.is(AsmToken::Dollar) ||
3846 Tok.is(AsmToken::Integer)) {
3847 if (Parser.getTok().isNot(AsmToken::Integer))
3848 Parser.Lex(); // Eat '#' or '$'.
3849 SMLoc Loc = Parser.getTok().getLoc();
3851 const MCExpr *ISBarrierID;
3852 if (getParser().parseExpression(ISBarrierID)) {
3853 Error(Loc, "illegal expression");
3854 return MatchOperand_ParseFail;
3857 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3859 Error(Loc, "constant expression expected");
3860 return MatchOperand_ParseFail;
3863 int Val = CE->getValue();
3865 Error(Loc, "immediate value out of range");
3866 return MatchOperand_ParseFail;
3869 Opt = ARM_ISB::RESERVED_0 + Val;
3871 return MatchOperand_ParseFail;
3873 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3874 (ARM_ISB::InstSyncBOpt)Opt, S));
3875 return MatchOperand_Success;
3879 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3880 ARMAsmParser::OperandMatchResultTy
3881 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
3882 SMLoc S = Parser.getTok().getLoc();
3883 const AsmToken &Tok = Parser.getTok();
3884 if (!Tok.is(AsmToken::Identifier))
3885 return MatchOperand_NoMatch;
3886 StringRef IFlagsStr = Tok.getString();
3888 // An iflags string of "none" is interpreted to mean that none of the AIF
3889 // bits are set. Not a terribly useful instruction, but a valid encoding.
3890 unsigned IFlags = 0;
3891 if (IFlagsStr != "none") {
3892 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3893 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3894 .Case("a", ARM_PROC::A)
3895 .Case("i", ARM_PROC::I)
3896 .Case("f", ARM_PROC::F)
3899 // If some specific iflag is already set, it means that some letter is
3900 // present more than once, this is not acceptable.
3901 if (Flag == ~0U || (IFlags & Flag))
3902 return MatchOperand_NoMatch;
3908 Parser.Lex(); // Eat identifier token.
3909 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3910 return MatchOperand_Success;
3913 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3914 ARMAsmParser::OperandMatchResultTy
3915 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
3916 SMLoc S = Parser.getTok().getLoc();
3917 const AsmToken &Tok = Parser.getTok();
3918 if (!Tok.is(AsmToken::Identifier))
3919 return MatchOperand_NoMatch;
3920 StringRef Mask = Tok.getString();
3923 // See ARMv6-M 10.1.1
3924 std::string Name = Mask.lower();
3925 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3926 // Note: in the documentation:
3927 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3928 // for MSR APSR_nzcvq.
3929 // but we do make it an alias here. This is so to get the "mask encoding"
3930 // bits correct on MSR APSR writes.
3932 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3933 // should really only be allowed when writing a special register. Note
3934 // they get dropped in the MRS instruction reading a special register as
3935 // the SYSm field is only 8 bits.
3936 .Case("apsr", 0x800)
3937 .Case("apsr_nzcvq", 0x800)
3938 .Case("apsr_g", 0x400)
3939 .Case("apsr_nzcvqg", 0xc00)
3940 .Case("iapsr", 0x801)
3941 .Case("iapsr_nzcvq", 0x801)
3942 .Case("iapsr_g", 0x401)
3943 .Case("iapsr_nzcvqg", 0xc01)
3944 .Case("eapsr", 0x802)
3945 .Case("eapsr_nzcvq", 0x802)
3946 .Case("eapsr_g", 0x402)
3947 .Case("eapsr_nzcvqg", 0xc02)
3948 .Case("xpsr", 0x803)
3949 .Case("xpsr_nzcvq", 0x803)
3950 .Case("xpsr_g", 0x403)
3951 .Case("xpsr_nzcvqg", 0xc03)
3952 .Case("ipsr", 0x805)
3953 .Case("epsr", 0x806)
3954 .Case("iepsr", 0x807)
3957 .Case("primask", 0x810)
3958 .Case("basepri", 0x811)
3959 .Case("basepri_max", 0x812)
3960 .Case("faultmask", 0x813)
3961 .Case("control", 0x814)
3964 if (FlagsVal == ~0U)
3965 return MatchOperand_NoMatch;
3967 if (!hasThumb2DSP() && (FlagsVal & 0x400))
3968 // The _g and _nzcvqg versions are only valid if the DSP extension is
3970 return MatchOperand_NoMatch;
3972 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3973 // basepri, basepri_max and faultmask only valid for V7m.
3974 return MatchOperand_NoMatch;
3976 Parser.Lex(); // Eat identifier token.
3977 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3978 return MatchOperand_Success;
3981 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3982 size_t Start = 0, Next = Mask.find('_');
3983 StringRef Flags = "";
3984 std::string SpecReg = Mask.slice(Start, Next).lower();
3985 if (Next != StringRef::npos)
3986 Flags = Mask.slice(Next+1, Mask.size());
3988 // FlagsVal contains the complete mask:
3990 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3991 unsigned FlagsVal = 0;
3993 if (SpecReg == "apsr") {
3994 FlagsVal = StringSwitch<unsigned>(Flags)
3995 .Case("nzcvq", 0x8) // same as CPSR_f
3996 .Case("g", 0x4) // same as CPSR_s
3997 .Case("nzcvqg", 0xc) // same as CPSR_fs
4000 if (FlagsVal == ~0U) {
4002 return MatchOperand_NoMatch;
4004 FlagsVal = 8; // No flag
4006 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4007 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4008 if (Flags == "all" || Flags == "")
4010 for (int i = 0, e = Flags.size(); i != e; ++i) {
4011 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4018 // If some specific flag is already set, it means that some letter is
4019 // present more than once, this is not acceptable.
4020 if (FlagsVal == ~0U || (FlagsVal & Flag))
4021 return MatchOperand_NoMatch;
4024 } else // No match for special register.
4025 return MatchOperand_NoMatch;
4027 // Special register without flags is NOT equivalent to "fc" flags.
4028 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
4029 // two lines would enable gas compatibility at the expense of breaking
4035 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4036 if (SpecReg == "spsr")
4039 Parser.Lex(); // Eat identifier token.
4040 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4041 return MatchOperand_Success;
4044 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4045 /// use in the MRS/MSR instructions added to support virtualization.
4046 ARMAsmParser::OperandMatchResultTy
4047 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4048 SMLoc S = Parser.getTok().getLoc();
4049 const AsmToken &Tok = Parser.getTok();
4050 if (!Tok.is(AsmToken::Identifier))
4051 return MatchOperand_NoMatch;
4052 StringRef RegName = Tok.getString();
4054 // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
4056 unsigned Encoding = StringSwitch<unsigned>(RegName.lower())
4057 .Case("r8_usr", 0x00)
4058 .Case("r9_usr", 0x01)
4059 .Case("r10_usr", 0x02)
4060 .Case("r11_usr", 0x03)
4061 .Case("r12_usr", 0x04)
4062 .Case("sp_usr", 0x05)
4063 .Case("lr_usr", 0x06)
4064 .Case("r8_fiq", 0x08)
4065 .Case("r9_fiq", 0x09)
4066 .Case("r10_fiq", 0x0a)
4067 .Case("r11_fiq", 0x0b)
4068 .Case("r12_fiq", 0x0c)
4069 .Case("sp_fiq", 0x0d)
4070 .Case("lr_fiq", 0x0e)
4071 .Case("lr_irq", 0x10)
4072 .Case("sp_irq", 0x11)
4073 .Case("lr_svc", 0x12)
4074 .Case("sp_svc", 0x13)
4075 .Case("lr_abt", 0x14)
4076 .Case("sp_abt", 0x15)
4077 .Case("lr_und", 0x16)
4078 .Case("sp_und", 0x17)
4079 .Case("lr_mon", 0x1c)
4080 .Case("sp_mon", 0x1d)
4081 .Case("elr_hyp", 0x1e)
4082 .Case("sp_hyp", 0x1f)
4083 .Case("spsr_fiq", 0x2e)
4084 .Case("spsr_irq", 0x30)
4085 .Case("spsr_svc", 0x32)
4086 .Case("spsr_abt", 0x34)
4087 .Case("spsr_und", 0x36)
4088 .Case("spsr_mon", 0x3c)
4089 .Case("spsr_hyp", 0x3e)
4092 if (Encoding == ~0U)
4093 return MatchOperand_NoMatch;
4095 Parser.Lex(); // Eat identifier token.
4096 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4097 return MatchOperand_Success;
4100 ARMAsmParser::OperandMatchResultTy
4101 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4103 const AsmToken &Tok = Parser.getTok();
4104 if (Tok.isNot(AsmToken::Identifier)) {
4105 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4106 return MatchOperand_ParseFail;
4108 StringRef ShiftName = Tok.getString();
4109 std::string LowerOp = Op.lower();
4110 std::string UpperOp = Op.upper();
4111 if (ShiftName != LowerOp && ShiftName != UpperOp) {
4112 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4113 return MatchOperand_ParseFail;
4115 Parser.Lex(); // Eat shift type token.
4117 // There must be a '#' and a shift amount.
4118 if (Parser.getTok().isNot(AsmToken::Hash) &&
4119 Parser.getTok().isNot(AsmToken::Dollar)) {
4120 Error(Parser.getTok().getLoc(), "'#' expected");
4121 return MatchOperand_ParseFail;
4123 Parser.Lex(); // Eat hash token.
4125 const MCExpr *ShiftAmount;
4126 SMLoc Loc = Parser.getTok().getLoc();
4128 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4129 Error(Loc, "illegal expression");
4130 return MatchOperand_ParseFail;
4132 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4134 Error(Loc, "constant expression expected");
4135 return MatchOperand_ParseFail;
4137 int Val = CE->getValue();
4138 if (Val < Low || Val > High) {
4139 Error(Loc, "immediate value out of range");
4140 return MatchOperand_ParseFail;
4143 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4145 return MatchOperand_Success;
4148 ARMAsmParser::OperandMatchResultTy
4149 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4150 const AsmToken &Tok = Parser.getTok();
4151 SMLoc S = Tok.getLoc();
4152 if (Tok.isNot(AsmToken::Identifier)) {
4153 Error(S, "'be' or 'le' operand expected");
4154 return MatchOperand_ParseFail;
4156 int Val = StringSwitch<int>(Tok.getString().lower())
4160 Parser.Lex(); // Eat the token.
4163 Error(S, "'be' or 'le' operand expected");
4164 return MatchOperand_ParseFail;
4166 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
4168 S, Tok.getEndLoc()));
4169 return MatchOperand_Success;
4172 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4173 /// instructions. Legal values are:
4174 /// lsl #n 'n' in [0,31]
4175 /// asr #n 'n' in [1,32]
4176 /// n == 32 encoded as n == 0.
4177 ARMAsmParser::OperandMatchResultTy
4178 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4179 const AsmToken &Tok = Parser.getTok();
4180 SMLoc S = Tok.getLoc();
4181 if (Tok.isNot(AsmToken::Identifier)) {
4182 Error(S, "shift operator 'asr' or 'lsl' expected");
4183 return MatchOperand_ParseFail;
4185 StringRef ShiftName = Tok.getString();
4187 if (ShiftName == "lsl" || ShiftName == "LSL")
4189 else if (ShiftName == "asr" || ShiftName == "ASR")
4192 Error(S, "shift operator 'asr' or 'lsl' expected");
4193 return MatchOperand_ParseFail;
4195 Parser.Lex(); // Eat the operator.
4197 // A '#' and a shift amount.
4198 if (Parser.getTok().isNot(AsmToken::Hash) &&
4199 Parser.getTok().isNot(AsmToken::Dollar)) {
4200 Error(Parser.getTok().getLoc(), "'#' expected");
4201 return MatchOperand_ParseFail;
4203 Parser.Lex(); // Eat hash token.
4204 SMLoc ExLoc = Parser.getTok().getLoc();
4206 const MCExpr *ShiftAmount;
4208 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4209 Error(ExLoc, "malformed shift expression");
4210 return MatchOperand_ParseFail;
4212 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4214 Error(ExLoc, "shift amount must be an immediate");
4215 return MatchOperand_ParseFail;
4218 int64_t Val = CE->getValue();
4220 // Shift amount must be in [1,32]
4221 if (Val < 1 || Val > 32) {
4222 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4223 return MatchOperand_ParseFail;
4225 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4226 if (isThumb() && Val == 32) {
4227 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4228 return MatchOperand_ParseFail;
4230 if (Val == 32) Val = 0;
4232 // Shift amount must be in [1,32]
4233 if (Val < 0 || Val > 31) {
4234 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4235 return MatchOperand_ParseFail;
4239 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4241 return MatchOperand_Success;
4244 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4245 /// of instructions. Legal values are:
4246 /// ror #n 'n' in {0, 8, 16, 24}
4247 ARMAsmParser::OperandMatchResultTy
4248 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4249 const AsmToken &Tok = Parser.getTok();
4250 SMLoc S = Tok.getLoc();
4251 if (Tok.isNot(AsmToken::Identifier))
4252 return MatchOperand_NoMatch;
4253 StringRef ShiftName = Tok.getString();
4254 if (ShiftName != "ror" && ShiftName != "ROR")
4255 return MatchOperand_NoMatch;
4256 Parser.Lex(); // Eat the operator.
4258 // A '#' and a rotate amount.
4259 if (Parser.getTok().isNot(AsmToken::Hash) &&
4260 Parser.getTok().isNot(AsmToken::Dollar)) {
4261 Error(Parser.getTok().getLoc(), "'#' expected");
4262 return MatchOperand_ParseFail;
4264 Parser.Lex(); // Eat hash token.
4265 SMLoc ExLoc = Parser.getTok().getLoc();
4267 const MCExpr *ShiftAmount;
4269 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4270 Error(ExLoc, "malformed rotate expression");
4271 return MatchOperand_ParseFail;
4273 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4275 Error(ExLoc, "rotate amount must be an immediate");
4276 return MatchOperand_ParseFail;
4279 int64_t Val = CE->getValue();
4280 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4281 // normally, zero is represented in asm by omitting the rotate operand
4283 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4284 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4285 return MatchOperand_ParseFail;
4288 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4290 return MatchOperand_Success;
4293 ARMAsmParser::OperandMatchResultTy
4294 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4295 SMLoc S = Parser.getTok().getLoc();
4296 // The bitfield descriptor is really two operands, the LSB and the width.
4297 if (Parser.getTok().isNot(AsmToken::Hash) &&
4298 Parser.getTok().isNot(AsmToken::Dollar)) {
4299 Error(Parser.getTok().getLoc(), "'#' expected");
4300 return MatchOperand_ParseFail;
4302 Parser.Lex(); // Eat hash token.
4304 const MCExpr *LSBExpr;
4305 SMLoc E = Parser.getTok().getLoc();
4306 if (getParser().parseExpression(LSBExpr)) {
4307 Error(E, "malformed immediate expression");
4308 return MatchOperand_ParseFail;
4310 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4312 Error(E, "'lsb' operand must be an immediate");
4313 return MatchOperand_ParseFail;
4316 int64_t LSB = CE->getValue();
4317 // The LSB must be in the range [0,31]
4318 if (LSB < 0 || LSB > 31) {
4319 Error(E, "'lsb' operand must be in the range [0,31]");
4320 return MatchOperand_ParseFail;
4322 E = Parser.getTok().getLoc();
4324 // Expect another immediate operand.
4325 if (Parser.getTok().isNot(AsmToken::Comma)) {
4326 Error(Parser.getTok().getLoc(), "too few operands");
4327 return MatchOperand_ParseFail;
4329 Parser.Lex(); // Eat hash token.
4330 if (Parser.getTok().isNot(AsmToken::Hash) &&
4331 Parser.getTok().isNot(AsmToken::Dollar)) {
4332 Error(Parser.getTok().getLoc(), "'#' expected");
4333 return MatchOperand_ParseFail;
4335 Parser.Lex(); // Eat hash token.
4337 const MCExpr *WidthExpr;
4339 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4340 Error(E, "malformed immediate expression");
4341 return MatchOperand_ParseFail;
4343 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4345 Error(E, "'width' operand must be an immediate");
4346 return MatchOperand_ParseFail;
4349 int64_t Width = CE->getValue();
4350 // The LSB must be in the range [1,32-lsb]
4351 if (Width < 1 || Width > 32 - LSB) {
4352 Error(E, "'width' operand must be in the range [1,32-lsb]");
4353 return MatchOperand_ParseFail;
4356 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4358 return MatchOperand_Success;
4361 ARMAsmParser::OperandMatchResultTy
4362 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4363 // Check for a post-index addressing register operand. Specifically:
4364 // postidx_reg := '+' register {, shift}
4365 // | '-' register {, shift}
4366 // | register {, shift}
4368 // This method must return MatchOperand_NoMatch without consuming any tokens
4369 // in the case where there is no match, as other alternatives take other
4371 AsmToken Tok = Parser.getTok();
4372 SMLoc S = Tok.getLoc();
4373 bool haveEaten = false;
4375 if (Tok.is(AsmToken::Plus)) {
4376 Parser.Lex(); // Eat the '+' token.
4378 } else if (Tok.is(AsmToken::Minus)) {
4379 Parser.Lex(); // Eat the '-' token.
4384 SMLoc E = Parser.getTok().getEndLoc();
4385 int Reg = tryParseRegister();
4388 return MatchOperand_NoMatch;
4389 Error(Parser.getTok().getLoc(), "register expected");
4390 return MatchOperand_ParseFail;
4393 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4394 unsigned ShiftImm = 0;
4395 if (Parser.getTok().is(AsmToken::Comma)) {
4396 Parser.Lex(); // Eat the ','.
4397 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4398 return MatchOperand_ParseFail;
4400 // FIXME: Only approximates end...may include intervening whitespace.
4401 E = Parser.getTok().getLoc();
4404 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4407 return MatchOperand_Success;
4410 ARMAsmParser::OperandMatchResultTy
4411 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4412 // Check for a post-index addressing register operand. Specifically:
4413 // am3offset := '+' register
4420 // This method must return MatchOperand_NoMatch without consuming any tokens
4421 // in the case where there is no match, as other alternatives take other
4423 AsmToken Tok = Parser.getTok();
4424 SMLoc S = Tok.getLoc();
4426 // Do immediates first, as we always parse those if we have a '#'.
4427 if (Parser.getTok().is(AsmToken::Hash) ||
4428 Parser.getTok().is(AsmToken::Dollar)) {
4429 Parser.Lex(); // Eat '#' or '$'.
4430 // Explicitly look for a '-', as we need to encode negative zero
4432 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4433 const MCExpr *Offset;
4435 if (getParser().parseExpression(Offset, E))
4436 return MatchOperand_ParseFail;
4437 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4439 Error(S, "constant expression expected");
4440 return MatchOperand_ParseFail;
4442 // Negative zero is encoded as the flag value INT32_MIN.
4443 int32_t Val = CE->getValue();
4444 if (isNegative && Val == 0)
4448 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4450 return MatchOperand_Success;
4454 bool haveEaten = false;
4456 if (Tok.is(AsmToken::Plus)) {
4457 Parser.Lex(); // Eat the '+' token.
4459 } else if (Tok.is(AsmToken::Minus)) {
4460 Parser.Lex(); // Eat the '-' token.
4465 Tok = Parser.getTok();
4466 int Reg = tryParseRegister();
4469 return MatchOperand_NoMatch;
4470 Error(Tok.getLoc(), "register expected");
4471 return MatchOperand_ParseFail;
4474 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4475 0, S, Tok.getEndLoc()));
4477 return MatchOperand_Success;
4480 /// Convert parsed operands to MCInst. Needed here because this instruction
4481 /// only has two register operands, but multiplication is commutative so
4482 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4483 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4484 const OperandVector &Operands) {
4485 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4486 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4487 // If we have a three-operand form, make sure to set Rn to be the operand
4488 // that isn't the same as Rd.
4490 if (Operands.size() == 6 &&
4491 ((ARMOperand &)*Operands[4]).getReg() ==
4492 ((ARMOperand &)*Operands[3]).getReg())
4494 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4495 Inst.addOperand(Inst.getOperand(0));
4496 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4499 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4500 const OperandVector &Operands) {
4501 int CondOp = -1, ImmOp = -1;
4502 switch(Inst.getOpcode()) {
4504 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4507 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4509 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4511 // first decide whether or not the branch should be conditional
4512 // by looking at it's location relative to an IT block
4514 // inside an IT block we cannot have any conditional branches. any
4515 // such instructions needs to be converted to unconditional form
4516 switch(Inst.getOpcode()) {
4517 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4518 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4521 // outside IT blocks we can only have unconditional branches with AL
4522 // condition code or conditional branches with non-AL condition code
4523 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4524 switch(Inst.getOpcode()) {
4527 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4531 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4536 // now decide on encoding size based on branch target range
4537 switch(Inst.getOpcode()) {
4538 // classify tB as either t2B or t1B based on range of immediate operand
4540 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4541 if (!op.isSignedOffset<11, 1>() && isThumbTwo())
4542 Inst.setOpcode(ARM::t2B);
4545 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4547 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4548 if (!op.isSignedOffset<8, 1>() && isThumbTwo())
4549 Inst.setOpcode(ARM::t2Bcc);
4553 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4554 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4557 /// Parse an ARM memory expression, return false if successful else return true
4558 /// or an error. The first token must be a '[' when called.
4559 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4561 assert(Parser.getTok().is(AsmToken::LBrac) &&
4562 "Token is not a Left Bracket");
4563 S = Parser.getTok().getLoc();
4564 Parser.Lex(); // Eat left bracket token.
4566 const AsmToken &BaseRegTok = Parser.getTok();
4567 int BaseRegNum = tryParseRegister();
4568 if (BaseRegNum == -1)
4569 return Error(BaseRegTok.getLoc(), "register expected");
4571 // The next token must either be a comma, a colon or a closing bracket.
4572 const AsmToken &Tok = Parser.getTok();
4573 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4574 !Tok.is(AsmToken::RBrac))
4575 return Error(Tok.getLoc(), "malformed memory operand");
4577 if (Tok.is(AsmToken::RBrac)) {
4578 E = Tok.getEndLoc();
4579 Parser.Lex(); // Eat right bracket token.
4581 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4582 ARM_AM::no_shift, 0, 0, false,
4585 // If there's a pre-indexing writeback marker, '!', just add it as a token
4586 // operand. It's rather odd, but syntactically valid.
4587 if (Parser.getTok().is(AsmToken::Exclaim)) {
4588 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4589 Parser.Lex(); // Eat the '!'.
4595 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4596 "Lost colon or comma in memory operand?!");
4597 if (Tok.is(AsmToken::Comma)) {
4598 Parser.Lex(); // Eat the comma.
4601 // If we have a ':', it's an alignment specifier.
4602 if (Parser.getTok().is(AsmToken::Colon)) {
4603 Parser.Lex(); // Eat the ':'.
4604 E = Parser.getTok().getLoc();
4605 SMLoc AlignmentLoc = Tok.getLoc();
4608 if (getParser().parseExpression(Expr))
4611 // The expression has to be a constant. Memory references with relocations
4612 // don't come through here, as they use the <label> forms of the relevant
4614 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4616 return Error (E, "constant expression expected");
4619 switch (CE->getValue()) {
4622 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4623 case 16: Align = 2; break;
4624 case 32: Align = 4; break;
4625 case 64: Align = 8; break;
4626 case 128: Align = 16; break;
4627 case 256: Align = 32; break;
4630 // Now we should have the closing ']'
4631 if (Parser.getTok().isNot(AsmToken::RBrac))
4632 return Error(Parser.getTok().getLoc(), "']' expected");
4633 E = Parser.getTok().getEndLoc();
4634 Parser.Lex(); // Eat right bracket token.
4636 // Don't worry about range checking the value here. That's handled by
4637 // the is*() predicates.
4638 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4639 ARM_AM::no_shift, 0, Align,
4640 false, S, E, AlignmentLoc));
4642 // If there's a pre-indexing writeback marker, '!', just add it as a token
4644 if (Parser.getTok().is(AsmToken::Exclaim)) {
4645 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4646 Parser.Lex(); // Eat the '!'.
4652 // If we have a '#', it's an immediate offset, else assume it's a register
4653 // offset. Be friendly and also accept a plain integer (without a leading
4654 // hash) for gas compatibility.
4655 if (Parser.getTok().is(AsmToken::Hash) ||
4656 Parser.getTok().is(AsmToken::Dollar) ||
4657 Parser.getTok().is(AsmToken::Integer)) {
4658 if (Parser.getTok().isNot(AsmToken::Integer))
4659 Parser.Lex(); // Eat '#' or '$'.
4660 E = Parser.getTok().getLoc();
4662 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4663 const MCExpr *Offset;
4664 if (getParser().parseExpression(Offset))
4667 // The expression has to be a constant. Memory references with relocations
4668 // don't come through here, as they use the <label> forms of the relevant
4670 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4672 return Error (E, "constant expression expected");
4674 // If the constant was #-0, represent it as INT32_MIN.
4675 int32_t Val = CE->getValue();
4676 if (isNegative && Val == 0)
4677 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4679 // Now we should have the closing ']'
4680 if (Parser.getTok().isNot(AsmToken::RBrac))
4681 return Error(Parser.getTok().getLoc(), "']' expected");
4682 E = Parser.getTok().getEndLoc();
4683 Parser.Lex(); // Eat right bracket token.
4685 // Don't worry about range checking the value here. That's handled by
4686 // the is*() predicates.
4687 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4688 ARM_AM::no_shift, 0, 0,
4691 // If there's a pre-indexing writeback marker, '!', just add it as a token
4693 if (Parser.getTok().is(AsmToken::Exclaim)) {
4694 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4695 Parser.Lex(); // Eat the '!'.
4701 // The register offset is optionally preceded by a '+' or '-'
4702 bool isNegative = false;
4703 if (Parser.getTok().is(AsmToken::Minus)) {
4705 Parser.Lex(); // Eat the '-'.
4706 } else if (Parser.getTok().is(AsmToken::Plus)) {
4708 Parser.Lex(); // Eat the '+'.
4711 E = Parser.getTok().getLoc();
4712 int OffsetRegNum = tryParseRegister();
4713 if (OffsetRegNum == -1)
4714 return Error(E, "register expected");
4716 // If there's a shift operator, handle it.
4717 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4718 unsigned ShiftImm = 0;
4719 if (Parser.getTok().is(AsmToken::Comma)) {
4720 Parser.Lex(); // Eat the ','.
4721 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4725 // Now we should have the closing ']'
4726 if (Parser.getTok().isNot(AsmToken::RBrac))
4727 return Error(Parser.getTok().getLoc(), "']' expected");
4728 E = Parser.getTok().getEndLoc();
4729 Parser.Lex(); // Eat right bracket token.
4731 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4732 ShiftType, ShiftImm, 0, isNegative,
4735 // If there's a pre-indexing writeback marker, '!', just add it as a token
4737 if (Parser.getTok().is(AsmToken::Exclaim)) {
4738 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4739 Parser.Lex(); // Eat the '!'.
4745 /// parseMemRegOffsetShift - one of these two:
4746 /// ( lsl | lsr | asr | ror ) , # shift_amount
4748 /// return true if it parses a shift otherwise it returns false.
4749 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4751 SMLoc Loc = Parser.getTok().getLoc();
4752 const AsmToken &Tok = Parser.getTok();
4753 if (Tok.isNot(AsmToken::Identifier))
4755 StringRef ShiftName = Tok.getString();
4756 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4757 ShiftName == "asl" || ShiftName == "ASL")
4759 else if (ShiftName == "lsr" || ShiftName == "LSR")
4761 else if (ShiftName == "asr" || ShiftName == "ASR")
4763 else if (ShiftName == "ror" || ShiftName == "ROR")
4765 else if (ShiftName == "rrx" || ShiftName == "RRX")
4768 return Error(Loc, "illegal shift operator");
4769 Parser.Lex(); // Eat shift type token.
4771 // rrx stands alone.
4773 if (St != ARM_AM::rrx) {
4774 Loc = Parser.getTok().getLoc();
4775 // A '#' and a shift amount.
4776 const AsmToken &HashTok = Parser.getTok();
4777 if (HashTok.isNot(AsmToken::Hash) &&
4778 HashTok.isNot(AsmToken::Dollar))
4779 return Error(HashTok.getLoc(), "'#' expected");
4780 Parser.Lex(); // Eat hash token.
4783 if (getParser().parseExpression(Expr))
4785 // Range check the immediate.
4786 // lsl, ror: 0 <= imm <= 31
4787 // lsr, asr: 0 <= imm <= 32
4788 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4790 return Error(Loc, "shift amount must be an immediate");
4791 int64_t Imm = CE->getValue();
4793 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4794 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4795 return Error(Loc, "immediate shift value out of range");
4796 // If <ShiftTy> #0, turn it into a no_shift.
4799 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4808 /// parseFPImm - A floating point immediate expression operand.
4809 ARMAsmParser::OperandMatchResultTy
4810 ARMAsmParser::parseFPImm(OperandVector &Operands) {
4811 // Anything that can accept a floating point constant as an operand
4812 // needs to go through here, as the regular parseExpression is
4815 // This routine still creates a generic Immediate operand, containing
4816 // a bitcast of the 64-bit floating point value. The various operands
4817 // that accept floats can check whether the value is valid for them
4818 // via the standard is*() predicates.
4820 SMLoc S = Parser.getTok().getLoc();
4822 if (Parser.getTok().isNot(AsmToken::Hash) &&
4823 Parser.getTok().isNot(AsmToken::Dollar))
4824 return MatchOperand_NoMatch;
4826 // Disambiguate the VMOV forms that can accept an FP immediate.
4827 // vmov.f32 <sreg>, #imm
4828 // vmov.f64 <dreg>, #imm
4829 // vmov.f32 <dreg>, #imm @ vector f32x2
4830 // vmov.f32 <qreg>, #imm @ vector f32x4
4832 // There are also the NEON VMOV instructions which expect an
4833 // integer constant. Make sure we don't try to parse an FPImm
4835 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4836 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
4837 bool isVmovf = TyOp.isToken() &&
4838 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
4839 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
4840 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
4841 Mnemonic.getToken() == "fconsts");
4842 if (!(isVmovf || isFconst))
4843 return MatchOperand_NoMatch;
4845 Parser.Lex(); // Eat '#' or '$'.
4847 // Handle negation, as that still comes through as a separate token.
4848 bool isNegative = false;
4849 if (Parser.getTok().is(AsmToken::Minus)) {
4853 const AsmToken &Tok = Parser.getTok();
4854 SMLoc Loc = Tok.getLoc();
4855 if (Tok.is(AsmToken::Real) && isVmovf) {
4856 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4857 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4858 // If we had a '-' in front, toggle the sign bit.
4859 IntVal ^= (uint64_t)isNegative << 31;
4860 Parser.Lex(); // Eat the token.
4861 Operands.push_back(ARMOperand::CreateImm(
4862 MCConstantExpr::Create(IntVal, getContext()),
4863 S, Parser.getTok().getLoc()));
4864 return MatchOperand_Success;
4866 // Also handle plain integers. Instructions which allow floating point
4867 // immediates also allow a raw encoded 8-bit value.
4868 if (Tok.is(AsmToken::Integer) && isFconst) {
4869 int64_t Val = Tok.getIntVal();
4870 Parser.Lex(); // Eat the token.
4871 if (Val > 255 || Val < 0) {
4872 Error(Loc, "encoded floating point value out of range");
4873 return MatchOperand_ParseFail;
4875 float RealVal = ARM_AM::getFPImmFloat(Val);
4876 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
4878 Operands.push_back(ARMOperand::CreateImm(
4879 MCConstantExpr::Create(Val, getContext()), S,
4880 Parser.getTok().getLoc()));
4881 return MatchOperand_Success;
4884 Error(Loc, "invalid floating point immediate");
4885 return MatchOperand_ParseFail;
4888 /// Parse a arm instruction operand. For now this parses the operand regardless
4889 /// of the mnemonic.
4890 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
4893 // Check if the current operand has a custom associated parser, if so, try to
4894 // custom parse the operand, or fallback to the general approach.
4895 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4896 if (ResTy == MatchOperand_Success)
4898 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4899 // there was a match, but an error occurred, in which case, just return that
4900 // the operand parsing failed.
4901 if (ResTy == MatchOperand_ParseFail)
4904 switch (getLexer().getKind()) {
4906 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4908 case AsmToken::Identifier: {
4909 // If we've seen a branch mnemonic, the next operand must be a label. This
4910 // is true even if the label is a register name. So "br r1" means branch to
4912 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4914 if (!tryParseRegisterWithWriteBack(Operands))
4916 int Res = tryParseShiftRegister(Operands);
4917 if (Res == 0) // success
4919 else if (Res == -1) // irrecoverable error
4921 // If this is VMRS, check for the apsr_nzcv operand.
4922 if (Mnemonic == "vmrs" &&
4923 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4924 S = Parser.getTok().getLoc();
4926 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4931 // Fall though for the Identifier case that is not a register or a
4934 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4935 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4936 case AsmToken::String: // quoted label names.
4937 case AsmToken::Dot: { // . as a branch target
4938 // This was not a register so parse other operands that start with an
4939 // identifier (like labels) as expressions and create them as immediates.
4940 const MCExpr *IdVal;
4941 S = Parser.getTok().getLoc();
4942 if (getParser().parseExpression(IdVal))
4944 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4945 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4948 case AsmToken::LBrac:
4949 return parseMemory(Operands);
4950 case AsmToken::LCurly:
4951 return parseRegisterList(Operands);
4952 case AsmToken::Dollar:
4953 case AsmToken::Hash: {
4954 // #42 -> immediate.
4955 S = Parser.getTok().getLoc();
4958 if (Parser.getTok().isNot(AsmToken::Colon)) {
4959 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4960 const MCExpr *ImmVal;
4961 if (getParser().parseExpression(ImmVal))
4963 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4965 int32_t Val = CE->getValue();
4966 if (isNegative && Val == 0)
4967 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4969 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4970 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4972 // There can be a trailing '!' on operands that we want as a separate
4973 // '!' Token operand. Handle that here. For example, the compatibility
4974 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4975 if (Parser.getTok().is(AsmToken::Exclaim)) {
4976 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4977 Parser.getTok().getLoc()));
4978 Parser.Lex(); // Eat exclaim token
4982 // w/ a ':' after the '#', it's just like a plain ':'.
4985 case AsmToken::Colon: {
4986 // ":lower16:" and ":upper16:" expression prefixes
4987 // FIXME: Check it's an expression prefix,
4988 // e.g. (FOO - :lower16:BAR) isn't legal.
4989 ARMMCExpr::VariantKind RefKind;
4990 if (parsePrefix(RefKind))
4993 const MCExpr *SubExprVal;
4994 if (getParser().parseExpression(SubExprVal))
4997 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4999 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5000 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
5003 case AsmToken::Equal: {
5004 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
5005 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
5007 Parser.Lex(); // Eat '='
5008 const MCExpr *SubExprVal;
5009 if (getParser().parseExpression(SubExprVal))
5011 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5013 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
5014 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
5020 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
5021 // :lower16: and :upper16:.
5022 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
5023 RefKind = ARMMCExpr::VK_ARM_None;
5025 // consume an optional '#' (GNU compatibility)
5026 if (getLexer().is(AsmToken::Hash))
5029 // :lower16: and :upper16: modifiers
5030 assert(getLexer().is(AsmToken::Colon) && "expected a :");
5031 Parser.Lex(); // Eat ':'
5033 if (getLexer().isNot(AsmToken::Identifier)) {
5034 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
5038 StringRef IDVal = Parser.getTok().getIdentifier();
5039 if (IDVal == "lower16") {
5040 RefKind = ARMMCExpr::VK_ARM_LO16;
5041 } else if (IDVal == "upper16") {
5042 RefKind = ARMMCExpr::VK_ARM_HI16;
5044 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
5049 if (getLexer().isNot(AsmToken::Colon)) {
5050 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
5053 Parser.Lex(); // Eat the last ':'
5057 /// \brief Given a mnemonic, split out possible predication code and carry
5058 /// setting letters to form a canonical mnemonic and flags.
5060 // FIXME: Would be nice to autogen this.
5061 // FIXME: This is a bit of a maze of special cases.
5062 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
5063 unsigned &PredicationCode,
5065 unsigned &ProcessorIMod,
5066 StringRef &ITMask) {
5067 PredicationCode = ARMCC::AL;
5068 CarrySetting = false;
5071 // Ignore some mnemonics we know aren't predicated forms.
5073 // FIXME: Would be nice to autogen this.
5074 if ((Mnemonic == "movs" && isThumb()) ||
5075 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
5076 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
5077 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
5078 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
5079 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
5080 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
5081 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
5082 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
5083 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
5084 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
5085 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5086 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
5089 // First, split out any predication code. Ignore mnemonics we know aren't
5090 // predicated but do have a carry-set and so weren't caught above.
5091 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5092 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5093 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5094 Mnemonic != "sbcs" && Mnemonic != "rscs") {
5095 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5096 .Case("eq", ARMCC::EQ)
5097 .Case("ne", ARMCC::NE)
5098 .Case("hs", ARMCC::HS)
5099 .Case("cs", ARMCC::HS)
5100 .Case("lo", ARMCC::LO)
5101 .Case("cc", ARMCC::LO)
5102 .Case("mi", ARMCC::MI)
5103 .Case("pl", ARMCC::PL)
5104 .Case("vs", ARMCC::VS)
5105 .Case("vc", ARMCC::VC)
5106 .Case("hi", ARMCC::HI)
5107 .Case("ls", ARMCC::LS)
5108 .Case("ge", ARMCC::GE)
5109 .Case("lt", ARMCC::LT)
5110 .Case("gt", ARMCC::GT)
5111 .Case("le", ARMCC::LE)
5112 .Case("al", ARMCC::AL)
5115 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5116 PredicationCode = CC;
5120 // Next, determine if we have a carry setting bit. We explicitly ignore all
5121 // the instructions we know end in 's'.
5122 if (Mnemonic.endswith("s") &&
5123 !(Mnemonic == "cps" || Mnemonic == "mls" ||
5124 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5125 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5126 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5127 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5128 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5129 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5130 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5131 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5132 (Mnemonic == "movs" && isThumb()))) {
5133 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5134 CarrySetting = true;
5137 // The "cps" instruction can have a interrupt mode operand which is glued into
5138 // the mnemonic. Check if this is the case, split it and parse the imod op
5139 if (Mnemonic.startswith("cps")) {
5140 // Split out any imod code.
5142 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5143 .Case("ie", ARM_PROC::IE)
5144 .Case("id", ARM_PROC::ID)
5147 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5148 ProcessorIMod = IMod;
5152 // The "it" instruction has the condition mask on the end of the mnemonic.
5153 if (Mnemonic.startswith("it")) {
5154 ITMask = Mnemonic.slice(2, Mnemonic.size());
5155 Mnemonic = Mnemonic.slice(0, 2);
5161 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5162 /// inclusion of carry set or predication code operands.
5164 // FIXME: It would be nice to autogen this.
5166 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5167 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
5168 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5169 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5170 Mnemonic == "add" || Mnemonic == "adc" ||
5171 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
5172 Mnemonic == "orr" || Mnemonic == "mvn" ||
5173 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
5174 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
5175 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5176 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5177 Mnemonic == "mla" || Mnemonic == "smlal" ||
5178 Mnemonic == "umlal" || Mnemonic == "umull"))) {
5179 CanAcceptCarrySet = true;
5181 CanAcceptCarrySet = false;
5183 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5184 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5185 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5186 Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5187 Mnemonic.startswith("vsel") ||
5188 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
5189 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
5190 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
5191 Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
5192 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5193 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5194 // These mnemonics are never predicable
5195 CanAcceptPredicationCode = false;
5196 } else if (!isThumb()) {
5197 // Some instructions are only predicable in Thumb mode
5198 CanAcceptPredicationCode
5199 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5200 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5201 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5202 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5203 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5204 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5205 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5206 } else if (isThumbOne()) {
5208 CanAcceptPredicationCode = Mnemonic != "movs";
5210 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5212 CanAcceptPredicationCode = true;
5215 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5216 OperandVector &Operands) {
5217 // FIXME: This is all horribly hacky. We really need a better way to deal
5218 // with optional operands like this in the matcher table.
5220 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5221 // another does not. Specifically, the MOVW instruction does not. So we
5222 // special case it here and remove the defaulted (non-setting) cc_out
5223 // operand if that's the instruction we're trying to match.
5225 // We do this as post-processing of the explicit operands rather than just
5226 // conditionally adding the cc_out in the first place because we need
5227 // to check the type of the parsed immediate operand.
5228 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5229 !static_cast<ARMOperand &>(*Operands[4]).isARMSOImm() &&
5230 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5231 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5234 // Register-register 'add' for thumb does not have a cc_out operand
5235 // when there are only two register operands.
5236 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5237 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5238 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5239 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5241 // Register-register 'add' for thumb does not have a cc_out operand
5242 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5243 // have to check the immediate range here since Thumb2 has a variant
5244 // that can handle a different range and has a cc_out operand.
5245 if (((isThumb() && Mnemonic == "add") ||
5246 (isThumbTwo() && Mnemonic == "sub")) &&
5247 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5248 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5249 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5250 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5251 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5252 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5254 // For Thumb2, add/sub immediate does not have a cc_out operand for the
5255 // imm0_4095 variant. That's the least-preferred variant when
5256 // selecting via the generic "add" mnemonic, so to know that we
5257 // should remove the cc_out operand, we have to explicitly check that
5258 // it's not one of the other variants. Ugh.
5259 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5260 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5261 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5262 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5263 // Nest conditions rather than one big 'if' statement for readability.
5265 // If both registers are low, we're in an IT block, and the immediate is
5266 // in range, we should use encoding T1 instead, which has a cc_out.
5268 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5269 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5270 static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5272 // Check against T3. If the second register is the PC, this is an
5273 // alternate form of ADR, which uses encoding T4, so check for that too.
5274 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5275 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5278 // Otherwise, we use encoding T4, which does not have a cc_out
5283 // The thumb2 multiply instruction doesn't have a CCOut register, so
5284 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5285 // use the 16-bit encoding or not.
5286 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5287 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5288 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5289 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5290 static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5291 // If the registers aren't low regs, the destination reg isn't the
5292 // same as one of the source regs, or the cc_out operand is zero
5293 // outside of an IT block, we have to use the 32-bit encoding, so
5294 // remove the cc_out operand.
5295 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5296 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5297 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5298 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5299 static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5300 static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5301 static_cast<ARMOperand &>(*Operands[4]).getReg())))
5304 // Also check the 'mul' syntax variant that doesn't specify an explicit
5305 // destination register.
5306 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5307 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5308 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5309 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5310 // If the registers aren't low regs or the cc_out operand is zero
5311 // outside of an IT block, we have to use the 32-bit encoding, so
5312 // remove the cc_out operand.
5313 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5314 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5320 // Register-register 'add/sub' for thumb does not have a cc_out operand
5321 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5322 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5323 // right, this will result in better diagnostics (which operand is off)
5325 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5326 (Operands.size() == 5 || Operands.size() == 6) &&
5327 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5328 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5329 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5330 (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5331 (Operands.size() == 6 &&
5332 static_cast<ARMOperand &>(*Operands[5]).isImm())))
5338 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5339 OperandVector &Operands) {
5340 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5341 unsigned RegIdx = 3;
5342 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5343 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") {
5344 if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5345 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32")
5348 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5349 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5350 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5351 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5352 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5358 static bool isDataTypeToken(StringRef Tok) {
5359 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5360 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5361 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5362 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5363 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5364 Tok == ".f" || Tok == ".d";
5367 // FIXME: This bit should probably be handled via an explicit match class
5368 // in the .td files that matches the suffix instead of having it be
5369 // a literal string token the way it is now.
5370 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5371 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5373 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
5374 unsigned VariantID);
5376 static bool RequiresVFPRegListValidation(StringRef Inst,
5377 bool &AcceptSinglePrecisionOnly,
5378 bool &AcceptDoublePrecisionOnly) {
5379 if (Inst.size() < 7)
5382 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5383 StringRef AddressingMode = Inst.substr(4, 2);
5384 if (AddressingMode == "ia" || AddressingMode == "db" ||
5385 AddressingMode == "ea" || AddressingMode == "fd") {
5386 AcceptSinglePrecisionOnly = Inst[6] == 's';
5387 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5395 /// Parse an arm instruction mnemonic followed by its operands.
5396 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5397 SMLoc NameLoc, OperandVector &Operands) {
5398 // FIXME: Can this be done via tablegen in some fashion?
5399 bool RequireVFPRegisterListCheck;
5400 bool AcceptSinglePrecisionOnly;
5401 bool AcceptDoublePrecisionOnly;
5402 RequireVFPRegisterListCheck =
5403 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5404 AcceptDoublePrecisionOnly);
5406 // Apply mnemonic aliases before doing anything else, as the destination
5407 // mnemonic may include suffices and we want to handle them normally.
5408 // The generic tblgen'erated code does this later, at the start of
5409 // MatchInstructionImpl(), but that's too late for aliases that include
5410 // any sort of suffix.
5411 uint64_t AvailableFeatures = getAvailableFeatures();
5412 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5413 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5415 // First check for the ARM-specific .req directive.
5416 if (Parser.getTok().is(AsmToken::Identifier) &&
5417 Parser.getTok().getIdentifier() == ".req") {
5418 parseDirectiveReq(Name, NameLoc);
5419 // We always return 'error' for this, as we're done with this
5420 // statement and don't need to match the 'instruction."
5424 // Create the leading tokens for the mnemonic, split by '.' characters.
5425 size_t Start = 0, Next = Name.find('.');
5426 StringRef Mnemonic = Name.slice(Start, Next);
5428 // Split out the predication code and carry setting flag from the mnemonic.
5429 unsigned PredicationCode;
5430 unsigned ProcessorIMod;
5433 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5434 ProcessorIMod, ITMask);
5436 // In Thumb1, only the branch (B) instruction can be predicated.
5437 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5438 Parser.eatToEndOfStatement();
5439 return Error(NameLoc, "conditional execution not supported in Thumb1");
5442 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5444 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5445 // is the mask as it will be for the IT encoding if the conditional
5446 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5447 // where the conditional bit0 is zero, the instruction post-processing
5448 // will adjust the mask accordingly.
5449 if (Mnemonic == "it") {
5450 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5451 if (ITMask.size() > 3) {
5452 Parser.eatToEndOfStatement();
5453 return Error(Loc, "too many conditions on IT instruction");
5456 for (unsigned i = ITMask.size(); i != 0; --i) {
5457 char pos = ITMask[i - 1];
5458 if (pos != 't' && pos != 'e') {
5459 Parser.eatToEndOfStatement();
5460 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5463 if (ITMask[i - 1] == 't')
5466 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5469 // FIXME: This is all a pretty gross hack. We should automatically handle
5470 // optional operands like this via tblgen.
5472 // Next, add the CCOut and ConditionCode operands, if needed.
5474 // For mnemonics which can ever incorporate a carry setting bit or predication
5475 // code, our matching model involves us always generating CCOut and
5476 // ConditionCode operands to match the mnemonic "as written" and then we let
5477 // the matcher deal with finding the right instruction or generating an
5478 // appropriate error.
5479 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5480 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5482 // If we had a carry-set on an instruction that can't do that, issue an
5484 if (!CanAcceptCarrySet && CarrySetting) {
5485 Parser.eatToEndOfStatement();
5486 return Error(NameLoc, "instruction '" + Mnemonic +
5487 "' can not set flags, but 's' suffix specified");
5489 // If we had a predication code on an instruction that can't do that, issue an
5491 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5492 Parser.eatToEndOfStatement();
5493 return Error(NameLoc, "instruction '" + Mnemonic +
5494 "' is not predicable, but condition code specified");
5497 // Add the carry setting operand, if necessary.
5498 if (CanAcceptCarrySet) {
5499 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5500 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5504 // Add the predication code operand, if necessary.
5505 if (CanAcceptPredicationCode) {
5506 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5508 Operands.push_back(ARMOperand::CreateCondCode(
5509 ARMCC::CondCodes(PredicationCode), Loc));
5512 // Add the processor imod operand, if necessary.
5513 if (ProcessorIMod) {
5514 Operands.push_back(ARMOperand::CreateImm(
5515 MCConstantExpr::Create(ProcessorIMod, getContext()),
5517 } else if (Mnemonic == "cps" && isMClass()) {
5518 return Error(NameLoc, "instruction 'cps' requires effect for M-class");
5521 // Add the remaining tokens in the mnemonic.
5522 while (Next != StringRef::npos) {
5524 Next = Name.find('.', Start + 1);
5525 StringRef ExtraToken = Name.slice(Start, Next);
5527 // Some NEON instructions have an optional datatype suffix that is
5528 // completely ignored. Check for that.
5529 if (isDataTypeToken(ExtraToken) &&
5530 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5533 // For for ARM mode generate an error if the .n qualifier is used.
5534 if (ExtraToken == ".n" && !isThumb()) {
5535 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5536 Parser.eatToEndOfStatement();
5537 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5541 // The .n qualifier is always discarded as that is what the tables
5542 // and matcher expect. In ARM mode the .w qualifier has no effect,
5543 // so discard it to avoid errors that can be caused by the matcher.
5544 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5545 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5546 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5550 // Read the remaining operands.
5551 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5552 // Read the first operand.
5553 if (parseOperand(Operands, Mnemonic)) {
5554 Parser.eatToEndOfStatement();
5558 while (getLexer().is(AsmToken::Comma)) {
5559 Parser.Lex(); // Eat the comma.
5561 // Parse and remember the operand.
5562 if (parseOperand(Operands, Mnemonic)) {
5563 Parser.eatToEndOfStatement();
5569 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5570 SMLoc Loc = getLexer().getLoc();
5571 Parser.eatToEndOfStatement();
5572 return Error(Loc, "unexpected token in argument list");
5575 Parser.Lex(); // Consume the EndOfStatement
5577 if (RequireVFPRegisterListCheck) {
5578 ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
5579 if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
5580 return Error(Op.getStartLoc(),
5581 "VFP/Neon single precision register expected");
5582 if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
5583 return Error(Op.getStartLoc(),
5584 "VFP/Neon double precision register expected");
5587 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5588 // do and don't have a cc_out optional-def operand. With some spot-checks
5589 // of the operand list, we can figure out which variant we're trying to
5590 // parse and adjust accordingly before actually matching. We shouldn't ever
5591 // try to remove a cc_out operand that was explicitly set on the the
5592 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5593 // table driven matcher doesn't fit well with the ARM instruction set.
5594 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
5595 Operands.erase(Operands.begin() + 1);
5597 // Some instructions have the same mnemonic, but don't always
5598 // have a predicate. Distinguish them here and delete the
5599 // predicate if needed.
5600 if (shouldOmitPredicateOperand(Mnemonic, Operands))
5601 Operands.erase(Operands.begin() + 1);
5603 // ARM mode 'blx' need special handling, as the register operand version
5604 // is predicable, but the label operand version is not. So, we can't rely
5605 // on the Mnemonic based checking to correctly figure out when to put
5606 // a k_CondCode operand in the list. If we're trying to match the label
5607 // version, remove the k_CondCode operand here.
5608 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5609 static_cast<ARMOperand &>(*Operands[2]).isImm())
5610 Operands.erase(Operands.begin() + 1);
5612 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5613 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5614 // a single GPRPair reg operand is used in the .td file to replace the two
5615 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5616 // expressed as a GPRPair, so we have to manually merge them.
5617 // FIXME: We would really like to be able to tablegen'erate this.
5618 if (!isThumb() && Operands.size() > 4 &&
5619 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5620 Mnemonic == "stlexd")) {
5621 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5622 unsigned Idx = isLoad ? 2 : 3;
5623 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
5624 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
5626 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5627 // Adjust only if Op1 and Op2 are GPRs.
5628 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
5629 MRC.contains(Op2.getReg())) {
5630 unsigned Reg1 = Op1.getReg();
5631 unsigned Reg2 = Op2.getReg();
5632 unsigned Rt = MRI->getEncodingValue(Reg1);
5633 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5635 // Rt2 must be Rt + 1 and Rt must be even.
5636 if (Rt + 1 != Rt2 || (Rt & 1)) {
5637 Error(Op2.getStartLoc(), isLoad
5638 ? "destination operands must be sequential"
5639 : "source operands must be sequential");
5642 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5643 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5645 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
5646 Operands.erase(Operands.begin() + Idx + 1);
5650 // GNU Assembler extension (compatibility)
5651 if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5652 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5653 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5655 assert(Op2.isReg() && "expected register argument");
5657 unsigned SuperReg = MRI->getMatchingSuperReg(
5658 Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5660 assert(SuperReg && "expected register pair");
5662 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5665 Operands.begin() + 3,
5666 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
5670 // FIXME: As said above, this is all a pretty gross hack. This instruction
5671 // does not fit with other "subs" and tblgen.
5672 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5673 // so the Mnemonic is the original name "subs" and delete the predicate
5674 // operand so it will match the table entry.
5675 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5676 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5677 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
5678 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5679 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
5680 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5681 Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
5682 Operands.erase(Operands.begin() + 1);
5687 // Validate context-sensitive operand constraints.
5689 // return 'true' if register list contains non-low GPR registers,
5690 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5691 // 'containsReg' to true.
5692 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5693 unsigned HiReg, bool &containsReg) {
5694 containsReg = false;
5695 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5696 unsigned OpReg = Inst.getOperand(i).getReg();
5699 // Anything other than a low register isn't legal here.
5700 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5706 // Check if the specified regisgter is in the register list of the inst,
5707 // starting at the indicated operand number.
5708 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5709 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5710 unsigned OpReg = Inst.getOperand(i).getReg();
5717 // Return true if instruction has the interesting property of being
5718 // allowed in IT blocks, but not being predicable.
5719 static bool instIsBreakpoint(const MCInst &Inst) {
5720 return Inst.getOpcode() == ARM::tBKPT ||
5721 Inst.getOpcode() == ARM::BKPT ||
5722 Inst.getOpcode() == ARM::tHLT ||
5723 Inst.getOpcode() == ARM::HLT;
5727 // FIXME: We would really like to be able to tablegen'erate this.
5728 bool ARMAsmParser::validateInstruction(MCInst &Inst,
5729 const OperandVector &Operands) {
5730 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5731 SMLoc Loc = Operands[0]->getStartLoc();
5733 // Check the IT block state first.
5734 // NOTE: BKPT and HLT instructions have the interesting property of being
5735 // allowed in IT blocks, but not being predicable. They just always execute.
5736 if (inITBlock() && !instIsBreakpoint(Inst)) {
5738 if (ITState.FirstCond)
5739 ITState.FirstCond = false;
5741 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5742 // The instruction must be predicable.
5743 if (!MCID.isPredicable())
5744 return Error(Loc, "instructions in IT block must be predicable");
5745 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5746 unsigned ITCond = Bit ? ITState.Cond :
5747 ARMCC::getOppositeCondition(ITState.Cond);
5748 if (Cond != ITCond) {
5749 // Find the condition code Operand to get its SMLoc information.
5751 for (unsigned I = 1; I < Operands.size(); ++I)
5752 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
5753 CondLoc = Operands[I]->getStartLoc();
5754 return Error(CondLoc, "incorrect condition in IT block; got '" +
5755 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5756 "', but expected '" +
5757 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5759 // Check for non-'al' condition codes outside of the IT block.
5760 } else if (isThumbTwo() && MCID.isPredicable() &&
5761 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5762 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5763 Inst.getOpcode() != ARM::t2Bcc)
5764 return Error(Loc, "predicated instructions must be in IT block");
5766 const unsigned Opcode = Inst.getOpcode();
5770 case ARM::LDRD_POST: {
5771 const unsigned RtReg = Inst.getOperand(0).getReg();
5774 if (RtReg == ARM::LR)
5775 return Error(Operands[3]->getStartLoc(),
5778 const unsigned Rt = MRI->getEncodingValue(RtReg);
5779 // Rt must be even-numbered.
5781 return Error(Operands[3]->getStartLoc(),
5782 "Rt must be even-numbered");
5784 // Rt2 must be Rt + 1.
5785 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5787 return Error(Operands[3]->getStartLoc(),
5788 "destination operands must be sequential");
5790 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5791 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5792 // For addressing modes with writeback, the base register needs to be
5793 // different from the destination registers.
5794 if (Rn == Rt || Rn == Rt2)
5795 return Error(Operands[3]->getStartLoc(),
5796 "base register needs to be different from destination "
5803 case ARM::t2LDRD_PRE:
5804 case ARM::t2LDRD_POST: {
5805 // Rt2 must be different from Rt.
5806 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5807 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5809 return Error(Operands[3]->getStartLoc(),
5810 "destination operands can't be identical");
5814 // Rt2 must be Rt + 1.
5815 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5816 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5818 return Error(Operands[3]->getStartLoc(),
5819 "source operands must be sequential");
5823 case ARM::STRD_POST: {
5824 // Rt2 must be Rt + 1.
5825 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5826 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5828 return Error(Operands[3]->getStartLoc(),
5829 "source operands must be sequential");
5832 case ARM::STR_PRE_IMM:
5833 case ARM::STR_PRE_REG:
5834 case ARM::STR_POST_IMM:
5835 case ARM::STR_POST_REG:
5837 case ARM::STRH_POST:
5838 case ARM::STRB_PRE_IMM:
5839 case ARM::STRB_PRE_REG:
5840 case ARM::STRB_POST_IMM:
5841 case ARM::STRB_POST_REG: {
5842 // Rt must be different from Rn.
5843 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5844 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5847 return Error(Operands[3]->getStartLoc(),
5848 "source register and base register can't be identical");
5851 case ARM::LDR_PRE_IMM:
5852 case ARM::LDR_PRE_REG:
5853 case ARM::LDR_POST_IMM:
5854 case ARM::LDR_POST_REG:
5856 case ARM::LDRH_POST:
5857 case ARM::LDRSH_PRE:
5858 case ARM::LDRSH_POST:
5859 case ARM::LDRB_PRE_IMM:
5860 case ARM::LDRB_PRE_REG:
5861 case ARM::LDRB_POST_IMM:
5862 case ARM::LDRB_POST_REG:
5863 case ARM::LDRSB_PRE:
5864 case ARM::LDRSB_POST: {
5865 // Rt must be different from Rn.
5866 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5867 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5870 return Error(Operands[3]->getStartLoc(),
5871 "destination register and base register can't be identical");
5876 // Width must be in range [1, 32-lsb].
5877 unsigned LSB = Inst.getOperand(2).getImm();
5878 unsigned Widthm1 = Inst.getOperand(3).getImm();
5879 if (Widthm1 >= 32 - LSB)
5880 return Error(Operands[5]->getStartLoc(),
5881 "bitfield width must be in range [1,32-lsb]");
5884 // Notionally handles ARM::tLDMIA_UPD too.
5886 // If we're parsing Thumb2, the .w variant is available and handles
5887 // most cases that are normally illegal for a Thumb1 LDM instruction.
5888 // We'll make the transformation in processInstruction() if necessary.
5890 // Thumb LDM instructions are writeback iff the base register is not
5891 // in the register list.
5892 unsigned Rn = Inst.getOperand(0).getReg();
5893 bool HasWritebackToken =
5894 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5895 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
5896 bool ListContainsBase;
5897 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5898 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5899 "registers must be in range r0-r7");
5900 // If we should have writeback, then there should be a '!' token.
5901 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5902 return Error(Operands[2]->getStartLoc(),
5903 "writeback operator '!' expected");
5904 // If we should not have writeback, there must not be a '!'. This is
5905 // true even for the 32-bit wide encodings.
5906 if (ListContainsBase && HasWritebackToken)
5907 return Error(Operands[3]->getStartLoc(),
5908 "writeback operator '!' not allowed when base register "
5909 "in register list");
5913 case ARM::LDMIA_UPD:
5914 case ARM::LDMDB_UPD:
5915 case ARM::LDMIB_UPD:
5916 case ARM::LDMDA_UPD:
5917 // ARM variants loading and updating the same register are only officially
5918 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5922 case ARM::t2LDMIA_UPD:
5923 case ARM::t2LDMDB_UPD:
5924 case ARM::t2STMIA_UPD:
5925 case ARM::t2STMDB_UPD: {
5926 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5927 return Error(Operands.back()->getStartLoc(),
5928 "writeback register not allowed in register list");
5931 case ARM::sysLDMIA_UPD:
5932 case ARM::sysLDMDA_UPD:
5933 case ARM::sysLDMDB_UPD:
5934 case ARM::sysLDMIB_UPD:
5935 if (!listContainsReg(Inst, 3, ARM::PC))
5936 return Error(Operands[4]->getStartLoc(),
5937 "writeback register only allowed on system LDM "
5938 "if PC in register-list");
5940 case ARM::sysSTMIA_UPD:
5941 case ARM::sysSTMDA_UPD:
5942 case ARM::sysSTMDB_UPD:
5943 case ARM::sysSTMIB_UPD:
5944 return Error(Operands[2]->getStartLoc(),
5945 "system STM cannot have writeback register");
5947 // The second source operand must be the same register as the destination
5950 // In this case, we must directly check the parsed operands because the
5951 // cvtThumbMultiply() function is written in such a way that it guarantees
5952 // this first statement is always true for the new Inst. Essentially, the
5953 // destination is unconditionally copied into the second source operand
5954 // without checking to see if it matches what we actually parsed.
5955 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
5956 ((ARMOperand &)*Operands[5]).getReg()) &&
5957 (((ARMOperand &)*Operands[3]).getReg() !=
5958 ((ARMOperand &)*Operands[4]).getReg())) {
5959 return Error(Operands[3]->getStartLoc(),
5960 "destination register must match source register");
5964 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5965 // so only issue a diagnostic for thumb1. The instructions will be
5966 // switched to the t2 encodings in processInstruction() if necessary.
5968 bool ListContainsBase;
5969 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5971 return Error(Operands[2]->getStartLoc(),
5972 "registers must be in range r0-r7 or pc");
5976 bool ListContainsBase;
5977 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5979 return Error(Operands[2]->getStartLoc(),
5980 "registers must be in range r0-r7 or lr");
5983 case ARM::tSTMIA_UPD: {
5984 bool ListContainsBase, InvalidLowList;
5985 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5986 0, ListContainsBase);
5987 if (InvalidLowList && !isThumbTwo())
5988 return Error(Operands[4]->getStartLoc(),
5989 "registers must be in range r0-r7");
5991 // This would be converted to a 32-bit stm, but that's not valid if the
5992 // writeback register is in the list.
5993 if (InvalidLowList && ListContainsBase)
5994 return Error(Operands[4]->getStartLoc(),
5995 "writeback operator '!' not allowed when base register "
5996 "in register list");
5999 case ARM::tADDrSP: {
6000 // If the non-SP source operand and the destination operand are not the
6001 // same, we need thumb2 (for the wide encoding), or we have an error.
6002 if (!isThumbTwo() &&
6003 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
6004 return Error(Operands[4]->getStartLoc(),
6005 "source register must be the same as destination");
6009 // Final range checking for Thumb unconditional branch instructions.
6011 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
6012 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6015 int op = (Operands[2]->isImm()) ? 2 : 3;
6016 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
6017 return Error(Operands[op]->getStartLoc(), "branch target out of range");
6020 // Final range checking for Thumb conditional branch instructions.
6022 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
6023 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6026 int Op = (Operands[2]->isImm()) ? 2 : 3;
6027 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
6028 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
6033 case ARM::t2MOVTi16:
6035 // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
6036 // especially when we turn it into a movw and the expression <symbol> does
6037 // not have a :lower16: or :upper16 as part of the expression. We don't
6038 // want the behavior of silently truncating, which can be unexpected and
6039 // lead to bugs that are difficult to find since this is an easy mistake
6041 int i = (Operands[3]->isImm()) ? 3 : 4;
6042 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
6043 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
6045 const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
6047 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
6048 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
6049 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
6052 "immediate expression for mov requires :lower16: or :upper16");
6060 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
6062 default: llvm_unreachable("unexpected opcode!");
6064 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6065 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6066 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6067 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6068 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6069 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6070 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
6071 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
6072 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
6075 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6076 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6077 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6078 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6079 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6081 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6082 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6083 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6084 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6085 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6087 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
6088 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
6089 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
6090 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
6091 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
6094 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6095 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6096 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6097 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6098 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6099 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6100 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6101 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6102 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6103 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6104 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
6105 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6106 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6107 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6108 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6111 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6112 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6113 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6114 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6115 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6116 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6117 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6118 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6119 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6120 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6121 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6122 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6123 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
6124 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6125 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6126 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
6127 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6128 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6131 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6132 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6133 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6134 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6135 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6136 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6137 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6138 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6139 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6140 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6141 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
6142 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6143 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6144 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6145 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6148 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6149 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6150 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6151 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6152 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6153 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6154 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6155 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6156 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6157 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6158 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6159 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6160 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
6161 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6162 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6163 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
6164 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6165 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6169 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6171 default: llvm_unreachable("unexpected opcode!");
6173 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6174 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6175 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6176 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6177 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6178 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6179 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
6180 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6181 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6184 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6185 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6186 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6187 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6188 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6189 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6190 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6191 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6192 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6193 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6194 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
6195 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6196 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6197 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6198 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6201 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6202 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6203 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6204 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6205 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6206 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6207 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6208 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6209 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6210 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6211 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6212 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6213 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
6214 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6215 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6216 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6217 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6218 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6221 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6222 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6223 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6224 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6225 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6226 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6227 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6228 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6229 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6230 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6231 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
6232 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6233 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6234 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6235 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6238 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6239 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6240 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6241 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6242 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6243 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6244 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6245 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6246 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6247 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6248 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6249 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6250 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
6251 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6252 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6253 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
6254 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6255 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6258 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6259 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6260 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6261 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6262 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6263 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6264 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6265 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6266 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6267 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6268 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
6269 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6270 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6271 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6272 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6275 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6276 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6277 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6278 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6279 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6280 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6281 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6282 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6283 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6284 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6285 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6286 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6287 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
6288 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6289 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6290 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6291 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6292 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6295 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6296 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6297 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6298 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6299 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6300 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6301 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6302 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6303 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6304 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6305 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6306 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6307 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
6308 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6309 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6310 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
6311 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6312 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6316 bool ARMAsmParser::processInstruction(MCInst &Inst,
6317 const OperandVector &Operands) {
6318 switch (Inst.getOpcode()) {
6319 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6320 case ARM::LDRT_POST:
6321 case ARM::LDRBT_POST: {
6322 const unsigned Opcode =
6323 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6324 : ARM::LDRBT_POST_IMM;
6326 TmpInst.setOpcode(Opcode);
6327 TmpInst.addOperand(Inst.getOperand(0));
6328 TmpInst.addOperand(Inst.getOperand(1));
6329 TmpInst.addOperand(Inst.getOperand(1));
6330 TmpInst.addOperand(MCOperand::CreateReg(0));
6331 TmpInst.addOperand(MCOperand::CreateImm(0));
6332 TmpInst.addOperand(Inst.getOperand(2));
6333 TmpInst.addOperand(Inst.getOperand(3));
6337 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6338 case ARM::STRT_POST:
6339 case ARM::STRBT_POST: {
6340 const unsigned Opcode =
6341 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6342 : ARM::STRBT_POST_IMM;
6344 TmpInst.setOpcode(Opcode);
6345 TmpInst.addOperand(Inst.getOperand(1));
6346 TmpInst.addOperand(Inst.getOperand(0));
6347 TmpInst.addOperand(Inst.getOperand(1));
6348 TmpInst.addOperand(MCOperand::CreateReg(0));
6349 TmpInst.addOperand(MCOperand::CreateImm(0));
6350 TmpInst.addOperand(Inst.getOperand(2));
6351 TmpInst.addOperand(Inst.getOperand(3));
6355 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6357 if (Inst.getOperand(1).getReg() != ARM::PC ||
6358 Inst.getOperand(5).getReg() != 0)
6361 TmpInst.setOpcode(ARM::ADR);
6362 TmpInst.addOperand(Inst.getOperand(0));
6363 TmpInst.addOperand(Inst.getOperand(2));
6364 TmpInst.addOperand(Inst.getOperand(3));
6365 TmpInst.addOperand(Inst.getOperand(4));
6369 // Aliases for alternate PC+imm syntax of LDR instructions.
6370 case ARM::t2LDRpcrel:
6371 // Select the narrow version if the immediate will fit.
6372 if (Inst.getOperand(1).getImm() > 0 &&
6373 Inst.getOperand(1).getImm() <= 0xff &&
6374 !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
6375 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
6376 Inst.setOpcode(ARM::tLDRpci);
6378 Inst.setOpcode(ARM::t2LDRpci);
6380 case ARM::t2LDRBpcrel:
6381 Inst.setOpcode(ARM::t2LDRBpci);
6383 case ARM::t2LDRHpcrel:
6384 Inst.setOpcode(ARM::t2LDRHpci);
6386 case ARM::t2LDRSBpcrel:
6387 Inst.setOpcode(ARM::t2LDRSBpci);
6389 case ARM::t2LDRSHpcrel:
6390 Inst.setOpcode(ARM::t2LDRSHpci);
6392 // Handle NEON VST complex aliases.
6393 case ARM::VST1LNdWB_register_Asm_8:
6394 case ARM::VST1LNdWB_register_Asm_16:
6395 case ARM::VST1LNdWB_register_Asm_32: {
6397 // Shuffle the operands around so the lane index operand is in the
6400 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6401 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6402 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6403 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6404 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6405 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6406 TmpInst.addOperand(Inst.getOperand(1)); // lane
6407 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6408 TmpInst.addOperand(Inst.getOperand(6));
6413 case ARM::VST2LNdWB_register_Asm_8:
6414 case ARM::VST2LNdWB_register_Asm_16:
6415 case ARM::VST2LNdWB_register_Asm_32:
6416 case ARM::VST2LNqWB_register_Asm_16:
6417 case ARM::VST2LNqWB_register_Asm_32: {
6419 // Shuffle the operands around so the lane index operand is in the
6422 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6423 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6424 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6425 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6426 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6427 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6428 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6430 TmpInst.addOperand(Inst.getOperand(1)); // lane
6431 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6432 TmpInst.addOperand(Inst.getOperand(6));
6437 case ARM::VST3LNdWB_register_Asm_8:
6438 case ARM::VST3LNdWB_register_Asm_16:
6439 case ARM::VST3LNdWB_register_Asm_32:
6440 case ARM::VST3LNqWB_register_Asm_16:
6441 case ARM::VST3LNqWB_register_Asm_32: {
6443 // Shuffle the operands around so the lane index operand is in the
6446 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6447 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6448 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6449 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6450 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6451 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6452 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6454 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6456 TmpInst.addOperand(Inst.getOperand(1)); // lane
6457 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6458 TmpInst.addOperand(Inst.getOperand(6));
6463 case ARM::VST4LNdWB_register_Asm_8:
6464 case ARM::VST4LNdWB_register_Asm_16:
6465 case ARM::VST4LNdWB_register_Asm_32:
6466 case ARM::VST4LNqWB_register_Asm_16:
6467 case ARM::VST4LNqWB_register_Asm_32: {
6469 // Shuffle the operands around so the lane index operand is in the
6472 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6473 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6474 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6475 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6476 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6477 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6478 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6480 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6482 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6484 TmpInst.addOperand(Inst.getOperand(1)); // lane
6485 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6486 TmpInst.addOperand(Inst.getOperand(6));
6491 case ARM::VST1LNdWB_fixed_Asm_8:
6492 case ARM::VST1LNdWB_fixed_Asm_16:
6493 case ARM::VST1LNdWB_fixed_Asm_32: {
6495 // Shuffle the operands around so the lane index operand is in the
6498 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6499 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6500 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6501 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6502 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6503 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6504 TmpInst.addOperand(Inst.getOperand(1)); // lane
6505 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6506 TmpInst.addOperand(Inst.getOperand(5));
6511 case ARM::VST2LNdWB_fixed_Asm_8:
6512 case ARM::VST2LNdWB_fixed_Asm_16:
6513 case ARM::VST2LNdWB_fixed_Asm_32:
6514 case ARM::VST2LNqWB_fixed_Asm_16:
6515 case ARM::VST2LNqWB_fixed_Asm_32: {
6517 // Shuffle the operands around so the lane index operand is in the
6520 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6521 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6522 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6523 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6524 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6525 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6526 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6528 TmpInst.addOperand(Inst.getOperand(1)); // lane
6529 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6530 TmpInst.addOperand(Inst.getOperand(5));
6535 case ARM::VST3LNdWB_fixed_Asm_8:
6536 case ARM::VST3LNdWB_fixed_Asm_16:
6537 case ARM::VST3LNdWB_fixed_Asm_32:
6538 case ARM::VST3LNqWB_fixed_Asm_16:
6539 case ARM::VST3LNqWB_fixed_Asm_32: {
6541 // Shuffle the operands around so the lane index operand is in the
6544 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6545 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6546 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6547 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6548 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6549 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6550 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6552 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6554 TmpInst.addOperand(Inst.getOperand(1)); // lane
6555 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6556 TmpInst.addOperand(Inst.getOperand(5));
6561 case ARM::VST4LNdWB_fixed_Asm_8:
6562 case ARM::VST4LNdWB_fixed_Asm_16:
6563 case ARM::VST4LNdWB_fixed_Asm_32:
6564 case ARM::VST4LNqWB_fixed_Asm_16:
6565 case ARM::VST4LNqWB_fixed_Asm_32: {
6567 // Shuffle the operands around so the lane index operand is in the
6570 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6571 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6572 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6573 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6574 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6575 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6576 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6578 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6580 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6582 TmpInst.addOperand(Inst.getOperand(1)); // lane
6583 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6584 TmpInst.addOperand(Inst.getOperand(5));
6589 case ARM::VST1LNdAsm_8:
6590 case ARM::VST1LNdAsm_16:
6591 case ARM::VST1LNdAsm_32: {
6593 // Shuffle the operands around so the lane index operand is in the
6596 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6597 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6598 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6599 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6600 TmpInst.addOperand(Inst.getOperand(1)); // lane
6601 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6602 TmpInst.addOperand(Inst.getOperand(5));
6607 case ARM::VST2LNdAsm_8:
6608 case ARM::VST2LNdAsm_16:
6609 case ARM::VST2LNdAsm_32:
6610 case ARM::VST2LNqAsm_16:
6611 case ARM::VST2LNqAsm_32: {
6613 // Shuffle the operands around so the lane index operand is in the
6616 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6617 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6618 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6619 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6620 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6622 TmpInst.addOperand(Inst.getOperand(1)); // lane
6623 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6624 TmpInst.addOperand(Inst.getOperand(5));
6629 case ARM::VST3LNdAsm_8:
6630 case ARM::VST3LNdAsm_16:
6631 case ARM::VST3LNdAsm_32:
6632 case ARM::VST3LNqAsm_16:
6633 case ARM::VST3LNqAsm_32: {
6635 // Shuffle the operands around so the lane index operand is in the
6638 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6639 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6640 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6641 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6642 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6644 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6646 TmpInst.addOperand(Inst.getOperand(1)); // lane
6647 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6648 TmpInst.addOperand(Inst.getOperand(5));
6653 case ARM::VST4LNdAsm_8:
6654 case ARM::VST4LNdAsm_16:
6655 case ARM::VST4LNdAsm_32:
6656 case ARM::VST4LNqAsm_16:
6657 case ARM::VST4LNqAsm_32: {
6659 // Shuffle the operands around so the lane index operand is in the
6662 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6663 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6664 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6665 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6666 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6668 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6670 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6672 TmpInst.addOperand(Inst.getOperand(1)); // lane
6673 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6674 TmpInst.addOperand(Inst.getOperand(5));
6679 // Handle NEON VLD complex aliases.
6680 case ARM::VLD1LNdWB_register_Asm_8:
6681 case ARM::VLD1LNdWB_register_Asm_16:
6682 case ARM::VLD1LNdWB_register_Asm_32: {
6684 // Shuffle the operands around so the lane index operand is in the
6687 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6688 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6689 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6690 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6691 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6692 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6693 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6694 TmpInst.addOperand(Inst.getOperand(1)); // lane
6695 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6696 TmpInst.addOperand(Inst.getOperand(6));
6701 case ARM::VLD2LNdWB_register_Asm_8:
6702 case ARM::VLD2LNdWB_register_Asm_16:
6703 case ARM::VLD2LNdWB_register_Asm_32:
6704 case ARM::VLD2LNqWB_register_Asm_16:
6705 case ARM::VLD2LNqWB_register_Asm_32: {
6707 // Shuffle the operands around so the lane index operand is in the
6710 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6711 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6712 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6714 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6715 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6716 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6717 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6718 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6719 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6721 TmpInst.addOperand(Inst.getOperand(1)); // lane
6722 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6723 TmpInst.addOperand(Inst.getOperand(6));
6728 case ARM::VLD3LNdWB_register_Asm_8:
6729 case ARM::VLD3LNdWB_register_Asm_16:
6730 case ARM::VLD3LNdWB_register_Asm_32:
6731 case ARM::VLD3LNqWB_register_Asm_16:
6732 case ARM::VLD3LNqWB_register_Asm_32: {
6734 // Shuffle the operands around so the lane index operand is in the
6737 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6738 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6739 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6741 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6743 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6744 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6745 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6746 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6747 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6748 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6750 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6752 TmpInst.addOperand(Inst.getOperand(1)); // lane
6753 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6754 TmpInst.addOperand(Inst.getOperand(6));
6759 case ARM::VLD4LNdWB_register_Asm_8:
6760 case ARM::VLD4LNdWB_register_Asm_16:
6761 case ARM::VLD4LNdWB_register_Asm_32:
6762 case ARM::VLD4LNqWB_register_Asm_16:
6763 case ARM::VLD4LNqWB_register_Asm_32: {
6765 // Shuffle the operands around so the lane index operand is in the
6768 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6769 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6770 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6772 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6774 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6776 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6777 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6778 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6779 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6780 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6781 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6783 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6785 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6787 TmpInst.addOperand(Inst.getOperand(1)); // lane
6788 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6789 TmpInst.addOperand(Inst.getOperand(6));
6794 case ARM::VLD1LNdWB_fixed_Asm_8:
6795 case ARM::VLD1LNdWB_fixed_Asm_16:
6796 case ARM::VLD1LNdWB_fixed_Asm_32: {
6798 // Shuffle the operands around so the lane index operand is in the
6801 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6802 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6803 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6804 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6805 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6806 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6807 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6808 TmpInst.addOperand(Inst.getOperand(1)); // lane
6809 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6810 TmpInst.addOperand(Inst.getOperand(5));
6815 case ARM::VLD2LNdWB_fixed_Asm_8:
6816 case ARM::VLD2LNdWB_fixed_Asm_16:
6817 case ARM::VLD2LNdWB_fixed_Asm_32:
6818 case ARM::VLD2LNqWB_fixed_Asm_16:
6819 case ARM::VLD2LNqWB_fixed_Asm_32: {
6821 // Shuffle the operands around so the lane index operand is in the
6824 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6825 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6826 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6828 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6829 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6830 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6831 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6832 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6833 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6835 TmpInst.addOperand(Inst.getOperand(1)); // lane
6836 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6837 TmpInst.addOperand(Inst.getOperand(5));
6842 case ARM::VLD3LNdWB_fixed_Asm_8:
6843 case ARM::VLD3LNdWB_fixed_Asm_16:
6844 case ARM::VLD3LNdWB_fixed_Asm_32:
6845 case ARM::VLD3LNqWB_fixed_Asm_16:
6846 case ARM::VLD3LNqWB_fixed_Asm_32: {
6848 // Shuffle the operands around so the lane index operand is in the
6851 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6852 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6853 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6855 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6857 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6858 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6859 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6860 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6861 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6862 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6864 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6866 TmpInst.addOperand(Inst.getOperand(1)); // lane
6867 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6868 TmpInst.addOperand(Inst.getOperand(5));
6873 case ARM::VLD4LNdWB_fixed_Asm_8:
6874 case ARM::VLD4LNdWB_fixed_Asm_16:
6875 case ARM::VLD4LNdWB_fixed_Asm_32:
6876 case ARM::VLD4LNqWB_fixed_Asm_16:
6877 case ARM::VLD4LNqWB_fixed_Asm_32: {
6879 // Shuffle the operands around so the lane index operand is in the
6882 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6883 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6884 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6886 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6888 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6890 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6891 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6892 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6893 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6894 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6895 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6897 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6899 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6901 TmpInst.addOperand(Inst.getOperand(1)); // lane
6902 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6903 TmpInst.addOperand(Inst.getOperand(5));
6908 case ARM::VLD1LNdAsm_8:
6909 case ARM::VLD1LNdAsm_16:
6910 case ARM::VLD1LNdAsm_32: {
6912 // Shuffle the operands around so the lane index operand is in the
6915 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6916 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6917 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6918 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6919 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6920 TmpInst.addOperand(Inst.getOperand(1)); // lane
6921 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6922 TmpInst.addOperand(Inst.getOperand(5));
6927 case ARM::VLD2LNdAsm_8:
6928 case ARM::VLD2LNdAsm_16:
6929 case ARM::VLD2LNdAsm_32:
6930 case ARM::VLD2LNqAsm_16:
6931 case ARM::VLD2LNqAsm_32: {
6933 // Shuffle the operands around so the lane index operand is in the
6936 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6937 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6938 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6940 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6941 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6942 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6943 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6945 TmpInst.addOperand(Inst.getOperand(1)); // lane
6946 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6947 TmpInst.addOperand(Inst.getOperand(5));
6952 case ARM::VLD3LNdAsm_8:
6953 case ARM::VLD3LNdAsm_16:
6954 case ARM::VLD3LNdAsm_32:
6955 case ARM::VLD3LNqAsm_16:
6956 case ARM::VLD3LNqAsm_32: {
6958 // Shuffle the operands around so the lane index operand is in the
6961 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6962 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6963 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6965 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6967 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6968 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6969 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6970 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6972 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6974 TmpInst.addOperand(Inst.getOperand(1)); // lane
6975 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6976 TmpInst.addOperand(Inst.getOperand(5));
6981 case ARM::VLD4LNdAsm_8:
6982 case ARM::VLD4LNdAsm_16:
6983 case ARM::VLD4LNdAsm_32:
6984 case ARM::VLD4LNqAsm_16:
6985 case ARM::VLD4LNqAsm_32: {
6987 // Shuffle the operands around so the lane index operand is in the
6990 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6991 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6992 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6994 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6996 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6998 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6999 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7000 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7001 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7003 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7005 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7007 TmpInst.addOperand(Inst.getOperand(1)); // lane
7008 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7009 TmpInst.addOperand(Inst.getOperand(5));
7014 // VLD3DUP single 3-element structure to all lanes instructions.
7015 case ARM::VLD3DUPdAsm_8:
7016 case ARM::VLD3DUPdAsm_16:
7017 case ARM::VLD3DUPdAsm_32:
7018 case ARM::VLD3DUPqAsm_8:
7019 case ARM::VLD3DUPqAsm_16:
7020 case ARM::VLD3DUPqAsm_32: {
7023 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7024 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7025 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7027 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7029 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7030 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7031 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7032 TmpInst.addOperand(Inst.getOperand(4));
7037 case ARM::VLD3DUPdWB_fixed_Asm_8:
7038 case ARM::VLD3DUPdWB_fixed_Asm_16:
7039 case ARM::VLD3DUPdWB_fixed_Asm_32:
7040 case ARM::VLD3DUPqWB_fixed_Asm_8:
7041 case ARM::VLD3DUPqWB_fixed_Asm_16:
7042 case ARM::VLD3DUPqWB_fixed_Asm_32: {
7045 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7046 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7047 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7049 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7051 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7052 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7053 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7054 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7055 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7056 TmpInst.addOperand(Inst.getOperand(4));
7061 case ARM::VLD3DUPdWB_register_Asm_8:
7062 case ARM::VLD3DUPdWB_register_Asm_16:
7063 case ARM::VLD3DUPdWB_register_Asm_32:
7064 case ARM::VLD3DUPqWB_register_Asm_8:
7065 case ARM::VLD3DUPqWB_register_Asm_16:
7066 case ARM::VLD3DUPqWB_register_Asm_32: {
7069 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7070 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7071 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7073 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7075 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7076 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7077 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7078 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7079 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7080 TmpInst.addOperand(Inst.getOperand(5));
7085 // VLD3 multiple 3-element structure instructions.
7086 case ARM::VLD3dAsm_8:
7087 case ARM::VLD3dAsm_16:
7088 case ARM::VLD3dAsm_32:
7089 case ARM::VLD3qAsm_8:
7090 case ARM::VLD3qAsm_16:
7091 case ARM::VLD3qAsm_32: {
7094 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7095 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7096 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7098 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7100 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7101 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7102 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7103 TmpInst.addOperand(Inst.getOperand(4));
7108 case ARM::VLD3dWB_fixed_Asm_8:
7109 case ARM::VLD3dWB_fixed_Asm_16:
7110 case ARM::VLD3dWB_fixed_Asm_32:
7111 case ARM::VLD3qWB_fixed_Asm_8:
7112 case ARM::VLD3qWB_fixed_Asm_16:
7113 case ARM::VLD3qWB_fixed_Asm_32: {
7116 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7117 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7118 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7120 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7122 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7123 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7124 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7125 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7126 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7127 TmpInst.addOperand(Inst.getOperand(4));
7132 case ARM::VLD3dWB_register_Asm_8:
7133 case ARM::VLD3dWB_register_Asm_16:
7134 case ARM::VLD3dWB_register_Asm_32:
7135 case ARM::VLD3qWB_register_Asm_8:
7136 case ARM::VLD3qWB_register_Asm_16:
7137 case ARM::VLD3qWB_register_Asm_32: {
7140 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7141 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7142 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7144 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7146 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7147 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7148 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7149 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7150 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7151 TmpInst.addOperand(Inst.getOperand(5));
7156 // VLD4DUP single 3-element structure to all lanes instructions.
7157 case ARM::VLD4DUPdAsm_8:
7158 case ARM::VLD4DUPdAsm_16:
7159 case ARM::VLD4DUPdAsm_32:
7160 case ARM::VLD4DUPqAsm_8:
7161 case ARM::VLD4DUPqAsm_16:
7162 case ARM::VLD4DUPqAsm_32: {
7165 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7166 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7167 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7169 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7171 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7173 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7174 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7175 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7176 TmpInst.addOperand(Inst.getOperand(4));
7181 case ARM::VLD4DUPdWB_fixed_Asm_8:
7182 case ARM::VLD4DUPdWB_fixed_Asm_16:
7183 case ARM::VLD4DUPdWB_fixed_Asm_32:
7184 case ARM::VLD4DUPqWB_fixed_Asm_8:
7185 case ARM::VLD4DUPqWB_fixed_Asm_16:
7186 case ARM::VLD4DUPqWB_fixed_Asm_32: {
7189 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7190 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7191 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7193 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7195 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7197 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7198 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7199 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7200 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7201 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7202 TmpInst.addOperand(Inst.getOperand(4));
7207 case ARM::VLD4DUPdWB_register_Asm_8:
7208 case ARM::VLD4DUPdWB_register_Asm_16:
7209 case ARM::VLD4DUPdWB_register_Asm_32:
7210 case ARM::VLD4DUPqWB_register_Asm_8:
7211 case ARM::VLD4DUPqWB_register_Asm_16:
7212 case ARM::VLD4DUPqWB_register_Asm_32: {
7215 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7216 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7217 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7219 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7221 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7223 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7224 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7225 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7226 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7227 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7228 TmpInst.addOperand(Inst.getOperand(5));
7233 // VLD4 multiple 4-element structure instructions.
7234 case ARM::VLD4dAsm_8:
7235 case ARM::VLD4dAsm_16:
7236 case ARM::VLD4dAsm_32:
7237 case ARM::VLD4qAsm_8:
7238 case ARM::VLD4qAsm_16:
7239 case ARM::VLD4qAsm_32: {
7242 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7243 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7244 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7246 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7248 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7250 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7251 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7252 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7253 TmpInst.addOperand(Inst.getOperand(4));
7258 case ARM::VLD4dWB_fixed_Asm_8:
7259 case ARM::VLD4dWB_fixed_Asm_16:
7260 case ARM::VLD4dWB_fixed_Asm_32:
7261 case ARM::VLD4qWB_fixed_Asm_8:
7262 case ARM::VLD4qWB_fixed_Asm_16:
7263 case ARM::VLD4qWB_fixed_Asm_32: {
7266 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7267 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7268 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7270 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7272 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7274 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7275 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7276 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7277 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7278 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7279 TmpInst.addOperand(Inst.getOperand(4));
7284 case ARM::VLD4dWB_register_Asm_8:
7285 case ARM::VLD4dWB_register_Asm_16:
7286 case ARM::VLD4dWB_register_Asm_32:
7287 case ARM::VLD4qWB_register_Asm_8:
7288 case ARM::VLD4qWB_register_Asm_16:
7289 case ARM::VLD4qWB_register_Asm_32: {
7292 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7293 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7294 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7296 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7298 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7300 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7301 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7302 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7303 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7304 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7305 TmpInst.addOperand(Inst.getOperand(5));
7310 // VST3 multiple 3-element structure instructions.
7311 case ARM::VST3dAsm_8:
7312 case ARM::VST3dAsm_16:
7313 case ARM::VST3dAsm_32:
7314 case ARM::VST3qAsm_8:
7315 case ARM::VST3qAsm_16:
7316 case ARM::VST3qAsm_32: {
7319 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7320 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7321 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7322 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7323 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7325 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7327 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7328 TmpInst.addOperand(Inst.getOperand(4));
7333 case ARM::VST3dWB_fixed_Asm_8:
7334 case ARM::VST3dWB_fixed_Asm_16:
7335 case ARM::VST3dWB_fixed_Asm_32:
7336 case ARM::VST3qWB_fixed_Asm_8:
7337 case ARM::VST3qWB_fixed_Asm_16:
7338 case ARM::VST3qWB_fixed_Asm_32: {
7341 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7342 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7343 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7344 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7345 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7346 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7347 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7349 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7351 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7352 TmpInst.addOperand(Inst.getOperand(4));
7357 case ARM::VST3dWB_register_Asm_8:
7358 case ARM::VST3dWB_register_Asm_16:
7359 case ARM::VST3dWB_register_Asm_32:
7360 case ARM::VST3qWB_register_Asm_8:
7361 case ARM::VST3qWB_register_Asm_16:
7362 case ARM::VST3qWB_register_Asm_32: {
7365 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7366 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7367 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7368 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7369 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7370 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7371 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7373 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7375 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7376 TmpInst.addOperand(Inst.getOperand(5));
7381 // VST4 multiple 3-element structure instructions.
7382 case ARM::VST4dAsm_8:
7383 case ARM::VST4dAsm_16:
7384 case ARM::VST4dAsm_32:
7385 case ARM::VST4qAsm_8:
7386 case ARM::VST4qAsm_16:
7387 case ARM::VST4qAsm_32: {
7390 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7391 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7392 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7393 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7394 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7396 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7398 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7400 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7401 TmpInst.addOperand(Inst.getOperand(4));
7406 case ARM::VST4dWB_fixed_Asm_8:
7407 case ARM::VST4dWB_fixed_Asm_16:
7408 case ARM::VST4dWB_fixed_Asm_32:
7409 case ARM::VST4qWB_fixed_Asm_8:
7410 case ARM::VST4qWB_fixed_Asm_16:
7411 case ARM::VST4qWB_fixed_Asm_32: {
7414 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7415 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7416 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7417 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7418 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7419 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7420 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7422 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7424 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7426 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7427 TmpInst.addOperand(Inst.getOperand(4));
7432 case ARM::VST4dWB_register_Asm_8:
7433 case ARM::VST4dWB_register_Asm_16:
7434 case ARM::VST4dWB_register_Asm_32:
7435 case ARM::VST4qWB_register_Asm_8:
7436 case ARM::VST4qWB_register_Asm_16:
7437 case ARM::VST4qWB_register_Asm_32: {
7440 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7441 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7442 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7443 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7444 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7445 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7446 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7448 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7450 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7452 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7453 TmpInst.addOperand(Inst.getOperand(5));
7458 // Handle encoding choice for the shift-immediate instructions.
7461 case ARM::t2ASRri: {
7462 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7463 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7464 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7465 !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7466 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
7468 switch (Inst.getOpcode()) {
7469 default: llvm_unreachable("unexpected opcode");
7470 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7471 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7472 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7474 // The Thumb1 operands aren't in the same order. Awesome, eh?
7476 TmpInst.setOpcode(NewOpc);
7477 TmpInst.addOperand(Inst.getOperand(0));
7478 TmpInst.addOperand(Inst.getOperand(5));
7479 TmpInst.addOperand(Inst.getOperand(1));
7480 TmpInst.addOperand(Inst.getOperand(2));
7481 TmpInst.addOperand(Inst.getOperand(3));
7482 TmpInst.addOperand(Inst.getOperand(4));
7489 // Handle the Thumb2 mode MOV complex aliases.
7491 case ARM::t2MOVSsr: {
7492 // Which instruction to expand to depends on the CCOut operand and
7493 // whether we're in an IT block if the register operands are low
7495 bool isNarrow = false;
7496 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7497 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7498 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7499 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7500 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7504 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7505 default: llvm_unreachable("unexpected opcode!");
7506 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7507 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7508 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7509 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7511 TmpInst.setOpcode(newOpc);
7512 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7514 TmpInst.addOperand(MCOperand::CreateReg(
7515 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7516 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7517 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7518 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7519 TmpInst.addOperand(Inst.getOperand(5));
7521 TmpInst.addOperand(MCOperand::CreateReg(
7522 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7527 case ARM::t2MOVSsi: {
7528 // Which instruction to expand to depends on the CCOut operand and
7529 // whether we're in an IT block if the register operands are low
7531 bool isNarrow = false;
7532 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7533 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7534 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7538 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7539 default: llvm_unreachable("unexpected opcode!");
7540 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7541 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7542 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7543 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7544 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7546 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7547 if (Amount == 32) Amount = 0;
7548 TmpInst.setOpcode(newOpc);
7549 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7551 TmpInst.addOperand(MCOperand::CreateReg(
7552 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7553 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7554 if (newOpc != ARM::t2RRX)
7555 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7556 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7557 TmpInst.addOperand(Inst.getOperand(4));
7559 TmpInst.addOperand(MCOperand::CreateReg(
7560 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7564 // Handle the ARM mode MOV complex aliases.
7569 ARM_AM::ShiftOpc ShiftTy;
7570 switch(Inst.getOpcode()) {
7571 default: llvm_unreachable("unexpected opcode!");
7572 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7573 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7574 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7575 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7577 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7579 TmpInst.setOpcode(ARM::MOVsr);
7580 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7581 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7582 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7583 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7584 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7585 TmpInst.addOperand(Inst.getOperand(4));
7586 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7594 ARM_AM::ShiftOpc ShiftTy;
7595 switch(Inst.getOpcode()) {
7596 default: llvm_unreachable("unexpected opcode!");
7597 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7598 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7599 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7600 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7602 // A shift by zero is a plain MOVr, not a MOVsi.
7603 unsigned Amt = Inst.getOperand(2).getImm();
7604 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7605 // A shift by 32 should be encoded as 0 when permitted
7606 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7608 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7610 TmpInst.setOpcode(Opc);
7611 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7612 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7613 if (Opc == ARM::MOVsi)
7614 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7615 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7616 TmpInst.addOperand(Inst.getOperand(4));
7617 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7622 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7624 TmpInst.setOpcode(ARM::MOVsi);
7625 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7626 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7627 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7628 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7629 TmpInst.addOperand(Inst.getOperand(3));
7630 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7634 case ARM::t2LDMIA_UPD: {
7635 // If this is a load of a single register, then we should use
7636 // a post-indexed LDR instruction instead, per the ARM ARM.
7637 if (Inst.getNumOperands() != 5)
7640 TmpInst.setOpcode(ARM::t2LDR_POST);
7641 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7642 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7643 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7644 TmpInst.addOperand(MCOperand::CreateImm(4));
7645 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7646 TmpInst.addOperand(Inst.getOperand(3));
7650 case ARM::t2STMDB_UPD: {
7651 // If this is a store of a single register, then we should use
7652 // a pre-indexed STR instruction instead, per the ARM ARM.
7653 if (Inst.getNumOperands() != 5)
7656 TmpInst.setOpcode(ARM::t2STR_PRE);
7657 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7658 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7659 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7660 TmpInst.addOperand(MCOperand::CreateImm(-4));
7661 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7662 TmpInst.addOperand(Inst.getOperand(3));
7666 case ARM::LDMIA_UPD:
7667 // If this is a load of a single register via a 'pop', then we should use
7668 // a post-indexed LDR instruction instead, per the ARM ARM.
7669 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
7670 Inst.getNumOperands() == 5) {
7672 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7673 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7674 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7675 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7676 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7677 TmpInst.addOperand(MCOperand::CreateImm(4));
7678 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7679 TmpInst.addOperand(Inst.getOperand(3));
7684 case ARM::STMDB_UPD:
7685 // If this is a store of a single register via a 'push', then we should use
7686 // a pre-indexed STR instruction instead, per the ARM ARM.
7687 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
7688 Inst.getNumOperands() == 5) {
7690 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7691 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7692 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7693 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7694 TmpInst.addOperand(MCOperand::CreateImm(-4));
7695 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7696 TmpInst.addOperand(Inst.getOperand(3));
7700 case ARM::t2ADDri12:
7701 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7702 // mnemonic was used (not "addw"), encoding T3 is preferred.
7703 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
7704 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7706 Inst.setOpcode(ARM::t2ADDri);
7707 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7709 case ARM::t2SUBri12:
7710 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7711 // mnemonic was used (not "subw"), encoding T3 is preferred.
7712 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
7713 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7715 Inst.setOpcode(ARM::t2SUBri);
7716 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7719 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7720 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7721 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7722 // to encoding T1 if <Rd> is omitted."
7723 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7724 Inst.setOpcode(ARM::tADDi3);
7729 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7730 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7731 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7732 // to encoding T1 if <Rd> is omitted."
7733 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7734 Inst.setOpcode(ARM::tSUBi3);
7739 case ARM::t2SUBri: {
7740 // If the destination and first source operand are the same, and
7741 // the flags are compatible with the current IT status, use encoding T2
7742 // instead of T3. For compatibility with the system 'as'. Make sure the
7743 // wide encoding wasn't explicit.
7744 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7745 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7746 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7747 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7748 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7749 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7750 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
7753 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7754 ARM::tADDi8 : ARM::tSUBi8);
7755 TmpInst.addOperand(Inst.getOperand(0));
7756 TmpInst.addOperand(Inst.getOperand(5));
7757 TmpInst.addOperand(Inst.getOperand(0));
7758 TmpInst.addOperand(Inst.getOperand(2));
7759 TmpInst.addOperand(Inst.getOperand(3));
7760 TmpInst.addOperand(Inst.getOperand(4));
7764 case ARM::t2ADDrr: {
7765 // If the destination and first source operand are the same, and
7766 // there's no setting of the flags, use encoding T2 instead of T3.
7767 // Note that this is only for ADD, not SUB. This mirrors the system
7768 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7769 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7770 Inst.getOperand(5).getReg() != 0 ||
7771 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7772 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
7775 TmpInst.setOpcode(ARM::tADDhirr);
7776 TmpInst.addOperand(Inst.getOperand(0));
7777 TmpInst.addOperand(Inst.getOperand(0));
7778 TmpInst.addOperand(Inst.getOperand(2));
7779 TmpInst.addOperand(Inst.getOperand(3));
7780 TmpInst.addOperand(Inst.getOperand(4));
7784 case ARM::tADDrSP: {
7785 // If the non-SP source operand and the destination operand are not the
7786 // same, we need to use the 32-bit encoding if it's available.
7787 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7788 Inst.setOpcode(ARM::t2ADDrr);
7789 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7795 // A Thumb conditional branch outside of an IT block is a tBcc.
7796 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7797 Inst.setOpcode(ARM::tBcc);
7802 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7803 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7804 Inst.setOpcode(ARM::t2Bcc);
7809 // If the conditional is AL or we're in an IT block, we really want t2B.
7810 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7811 Inst.setOpcode(ARM::t2B);
7816 // If the conditional is AL, we really want tB.
7817 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7818 Inst.setOpcode(ARM::tB);
7823 // If the register list contains any high registers, or if the writeback
7824 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7825 // instead if we're in Thumb2. Otherwise, this should have generated
7826 // an error in validateInstruction().
7827 unsigned Rn = Inst.getOperand(0).getReg();
7828 bool hasWritebackToken =
7829 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7830 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
7831 bool listContainsBase;
7832 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7833 (!listContainsBase && !hasWritebackToken) ||
7834 (listContainsBase && hasWritebackToken)) {
7835 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7836 assert (isThumbTwo());
7837 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7838 // If we're switching to the updating version, we need to insert
7839 // the writeback tied operand.
7840 if (hasWritebackToken)
7841 Inst.insert(Inst.begin(),
7842 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7847 case ARM::tSTMIA_UPD: {
7848 // If the register list contains any high registers, we need to use
7849 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7850 // should have generated an error in validateInstruction().
7851 unsigned Rn = Inst.getOperand(0).getReg();
7852 bool listContainsBase;
7853 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7854 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7855 assert (isThumbTwo());
7856 Inst.setOpcode(ARM::t2STMIA_UPD);
7862 bool listContainsBase;
7863 // If the register list contains any high registers, we need to use
7864 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7865 // should have generated an error in validateInstruction().
7866 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7868 assert (isThumbTwo());
7869 Inst.setOpcode(ARM::t2LDMIA_UPD);
7870 // Add the base register and writeback operands.
7871 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7872 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7876 bool listContainsBase;
7877 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7879 assert (isThumbTwo());
7880 Inst.setOpcode(ARM::t2STMDB_UPD);
7881 // Add the base register and writeback operands.
7882 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7883 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7887 // If we can use the 16-bit encoding and the user didn't explicitly
7888 // request the 32-bit variant, transform it here.
7889 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7890 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7891 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7892 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7893 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7894 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7895 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7896 // The operands aren't in the same order for tMOVi8...
7898 TmpInst.setOpcode(ARM::tMOVi8);
7899 TmpInst.addOperand(Inst.getOperand(0));
7900 TmpInst.addOperand(Inst.getOperand(4));
7901 TmpInst.addOperand(Inst.getOperand(1));
7902 TmpInst.addOperand(Inst.getOperand(2));
7903 TmpInst.addOperand(Inst.getOperand(3));
7910 // If we can use the 16-bit encoding and the user didn't explicitly
7911 // request the 32-bit variant, transform it here.
7912 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7913 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7914 Inst.getOperand(2).getImm() == ARMCC::AL &&
7915 Inst.getOperand(4).getReg() == ARM::CPSR &&
7916 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7917 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7918 // The operands aren't the same for tMOV[S]r... (no cc_out)
7920 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7921 TmpInst.addOperand(Inst.getOperand(0));
7922 TmpInst.addOperand(Inst.getOperand(1));
7923 TmpInst.addOperand(Inst.getOperand(2));
7924 TmpInst.addOperand(Inst.getOperand(3));
7934 // If we can use the 16-bit encoding and the user didn't explicitly
7935 // request the 32-bit variant, transform it here.
7936 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7937 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7938 Inst.getOperand(2).getImm() == 0 &&
7939 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7940 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7942 switch (Inst.getOpcode()) {
7943 default: llvm_unreachable("Illegal opcode!");
7944 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7945 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7946 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7947 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7949 // The operands aren't the same for thumb1 (no rotate operand).
7951 TmpInst.setOpcode(NewOpc);
7952 TmpInst.addOperand(Inst.getOperand(0));
7953 TmpInst.addOperand(Inst.getOperand(1));
7954 TmpInst.addOperand(Inst.getOperand(3));
7955 TmpInst.addOperand(Inst.getOperand(4));
7962 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7963 // rrx shifts and asr/lsr of #32 is encoded as 0
7964 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7966 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7967 // Shifting by zero is accepted as a vanilla 'MOVr'
7969 TmpInst.setOpcode(ARM::MOVr);
7970 TmpInst.addOperand(Inst.getOperand(0));
7971 TmpInst.addOperand(Inst.getOperand(1));
7972 TmpInst.addOperand(Inst.getOperand(3));
7973 TmpInst.addOperand(Inst.getOperand(4));
7974 TmpInst.addOperand(Inst.getOperand(5));
7987 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7988 if (SOpc == ARM_AM::rrx) return false;
7989 switch (Inst.getOpcode()) {
7990 default: llvm_unreachable("unexpected opcode!");
7991 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7992 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7993 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7994 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7995 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7996 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7998 // If the shift is by zero, use the non-shifted instruction definition.
7999 // The exception is for right shifts, where 0 == 32
8000 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8001 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
8003 TmpInst.setOpcode(newOpc);
8004 TmpInst.addOperand(Inst.getOperand(0));
8005 TmpInst.addOperand(Inst.getOperand(1));
8006 TmpInst.addOperand(Inst.getOperand(2));
8007 TmpInst.addOperand(Inst.getOperand(4));
8008 TmpInst.addOperand(Inst.getOperand(5));
8009 TmpInst.addOperand(Inst.getOperand(6));
8017 // The mask bits for all but the first condition are represented as
8018 // the low bit of the condition code value implies 't'. We currently
8019 // always have 1 implies 't', so XOR toggle the bits if the low bit
8020 // of the condition code is zero.
8021 MCOperand &MO = Inst.getOperand(1);
8022 unsigned Mask = MO.getImm();
8023 unsigned OrigMask = Mask;
8024 unsigned TZ = countTrailingZeros(Mask);
8025 if ((Inst.getOperand(0).getImm() & 1) == 0) {
8026 assert(Mask && TZ <= 3 && "illegal IT mask value!");
8027 Mask ^= (0xE << TZ) & 0xF;
8031 // Set up the IT block state according to the IT instruction we just
8033 assert(!inITBlock() && "nested IT blocks?!");
8034 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8035 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
8036 ITState.CurPosition = 0;
8037 ITState.FirstCond = true;
8047 // Assemblers should use the narrow encodings of these instructions when permissible.
8048 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8049 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8050 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8051 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8052 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8053 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8054 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8057 switch (Inst.getOpcode()) {
8058 default: llvm_unreachable("unexpected opcode");
8059 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
8060 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
8061 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
8062 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
8063 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
8064 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
8067 TmpInst.setOpcode(NewOpc);
8068 TmpInst.addOperand(Inst.getOperand(0));
8069 TmpInst.addOperand(Inst.getOperand(5));
8070 TmpInst.addOperand(Inst.getOperand(1));
8071 TmpInst.addOperand(Inst.getOperand(2));
8072 TmpInst.addOperand(Inst.getOperand(3));
8073 TmpInst.addOperand(Inst.getOperand(4));
8084 // Assemblers should use the narrow encodings of these instructions when permissible.
8085 // These instructions are special in that they are commutable, so shorter encodings
8086 // are available more often.
8087 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8088 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8089 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8090 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8091 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8092 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8093 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8094 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8097 switch (Inst.getOpcode()) {
8098 default: llvm_unreachable("unexpected opcode");
8099 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
8100 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
8101 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
8102 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
8105 TmpInst.setOpcode(NewOpc);
8106 TmpInst.addOperand(Inst.getOperand(0));
8107 TmpInst.addOperand(Inst.getOperand(5));
8108 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8109 TmpInst.addOperand(Inst.getOperand(1));
8110 TmpInst.addOperand(Inst.getOperand(2));
8112 TmpInst.addOperand(Inst.getOperand(2));
8113 TmpInst.addOperand(Inst.getOperand(1));
8115 TmpInst.addOperand(Inst.getOperand(3));
8116 TmpInst.addOperand(Inst.getOperand(4));
8126 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8127 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8128 // suffix depending on whether they're in an IT block or not.
8129 unsigned Opc = Inst.getOpcode();
8130 const MCInstrDesc &MCID = MII.get(Opc);
8131 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8132 assert(MCID.hasOptionalDef() &&
8133 "optionally flag setting instruction missing optional def operand");
8134 assert(MCID.NumOperands == Inst.getNumOperands() &&
8135 "operand count mismatch!");
8136 // Find the optional-def operand (cc_out).
8139 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8142 // If we're parsing Thumb1, reject it completely.
8143 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8144 return Match_MnemonicFail;
8145 // If we're parsing Thumb2, which form is legal depends on whether we're
8147 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8149 return Match_RequiresITBlock;
8150 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8152 return Match_RequiresNotITBlock;
8154 // Some high-register supporting Thumb1 encodings only allow both registers
8155 // to be from r0-r7 when in Thumb2.
8156 else if (Opc == ARM::tADDhirr && isThumbOne() &&
8157 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8158 isARMLowRegister(Inst.getOperand(2).getReg()))
8159 return Match_RequiresThumb2;
8160 // Others only require ARMv6 or later.
8161 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
8162 isARMLowRegister(Inst.getOperand(0).getReg()) &&
8163 isARMLowRegister(Inst.getOperand(1).getReg()))
8164 return Match_RequiresV6;
8165 return Match_Success;
8169 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8170 return true; // In an assembly source, no need to second-guess
8174 static const char *getSubtargetFeatureName(uint64_t Val);
8175 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8176 OperandVector &Operands,
8177 MCStreamer &Out, uint64_t &ErrorInfo,
8178 bool MatchingInlineAsm) {
8180 unsigned MatchResult;
8182 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8184 switch (MatchResult) {
8187 // Context sensitive operand constraints aren't handled by the matcher,
8188 // so check them here.
8189 if (validateInstruction(Inst, Operands)) {
8190 // Still progress the IT block, otherwise one wrong condition causes
8191 // nasty cascading errors.
8192 forwardITPosition();
8196 { // processInstruction() updates inITBlock state, we need to save it away
8197 bool wasInITBlock = inITBlock();
8199 // Some instructions need post-processing to, for example, tweak which
8200 // encoding is selected. Loop on it while changes happen so the
8201 // individual transformations can chain off each other. E.g.,
8202 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8203 while (processInstruction(Inst, Operands))
8206 // Only after the instruction is fully processed, we can validate it
8207 if (wasInITBlock && hasV8Ops() && isThumb() &&
8208 !isV8EligibleForIT(&Inst)) {
8209 Warning(IDLoc, "deprecated instruction in IT block");
8213 // Only move forward at the very end so that everything in validate
8214 // and process gets a consistent answer about whether we're in an IT
8216 forwardITPosition();
8218 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8219 // doesn't actually encode.
8220 if (Inst.getOpcode() == ARM::ITasm)
8224 Out.EmitInstruction(Inst, STI);
8226 case Match_MissingFeature: {
8227 assert(ErrorInfo && "Unknown missing feature!");
8228 // Special case the error message for the very common case where only
8229 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8230 std::string Msg = "instruction requires:";
8232 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8233 if (ErrorInfo & Mask) {
8235 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8239 return Error(IDLoc, Msg);
8241 case Match_InvalidOperand: {
8242 SMLoc ErrorLoc = IDLoc;
8243 if (ErrorInfo != ~0ULL) {
8244 if (ErrorInfo >= Operands.size())
8245 return Error(IDLoc, "too few operands for instruction");
8247 ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8248 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8251 return Error(ErrorLoc, "invalid operand for instruction");
8253 case Match_MnemonicFail:
8254 return Error(IDLoc, "invalid instruction",
8255 ((ARMOperand &)*Operands[0]).getLocRange());
8256 case Match_RequiresNotITBlock:
8257 return Error(IDLoc, "flag setting instruction only valid outside IT block");
8258 case Match_RequiresITBlock:
8259 return Error(IDLoc, "instruction only valid inside IT block");
8260 case Match_RequiresV6:
8261 return Error(IDLoc, "instruction variant requires ARMv6 or later");
8262 case Match_RequiresThumb2:
8263 return Error(IDLoc, "instruction variant requires Thumb2");
8264 case Match_ImmRange0_15: {
8265 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8266 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8267 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8269 case Match_ImmRange0_239: {
8270 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8271 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8272 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8274 case Match_AlignedMemoryRequiresNone:
8275 case Match_DupAlignedMemoryRequiresNone:
8276 case Match_AlignedMemoryRequires16:
8277 case Match_DupAlignedMemoryRequires16:
8278 case Match_AlignedMemoryRequires32:
8279 case Match_DupAlignedMemoryRequires32:
8280 case Match_AlignedMemoryRequires64:
8281 case Match_DupAlignedMemoryRequires64:
8282 case Match_AlignedMemoryRequires64or128:
8283 case Match_DupAlignedMemoryRequires64or128:
8284 case Match_AlignedMemoryRequires64or128or256:
8286 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
8287 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8288 switch (MatchResult) {
8290 llvm_unreachable("Missing Match_Aligned type");
8291 case Match_AlignedMemoryRequiresNone:
8292 case Match_DupAlignedMemoryRequiresNone:
8293 return Error(ErrorLoc, "alignment must be omitted");
8294 case Match_AlignedMemoryRequires16:
8295 case Match_DupAlignedMemoryRequires16:
8296 return Error(ErrorLoc, "alignment must be 16 or omitted");
8297 case Match_AlignedMemoryRequires32:
8298 case Match_DupAlignedMemoryRequires32:
8299 return Error(ErrorLoc, "alignment must be 32 or omitted");
8300 case Match_AlignedMemoryRequires64:
8301 case Match_DupAlignedMemoryRequires64:
8302 return Error(ErrorLoc, "alignment must be 64 or omitted");
8303 case Match_AlignedMemoryRequires64or128:
8304 case Match_DupAlignedMemoryRequires64or128:
8305 return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8306 case Match_AlignedMemoryRequires64or128or256:
8307 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8312 llvm_unreachable("Implement any new match types added!");
8315 /// parseDirective parses the arm specific directives
8316 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8317 const MCObjectFileInfo::Environment Format =
8318 getContext().getObjectFileInfo()->getObjectFileType();
8319 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8320 bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
8322 StringRef IDVal = DirectiveID.getIdentifier();
8323 if (IDVal == ".word")
8324 return parseLiteralValues(4, DirectiveID.getLoc());
8325 else if (IDVal == ".short" || IDVal == ".hword")
8326 return parseLiteralValues(2, DirectiveID.getLoc());
8327 else if (IDVal == ".thumb")
8328 return parseDirectiveThumb(DirectiveID.getLoc());
8329 else if (IDVal == ".arm")
8330 return parseDirectiveARM(DirectiveID.getLoc());
8331 else if (IDVal == ".thumb_func")
8332 return parseDirectiveThumbFunc(DirectiveID.getLoc());
8333 else if (IDVal == ".code")
8334 return parseDirectiveCode(DirectiveID.getLoc());
8335 else if (IDVal == ".syntax")
8336 return parseDirectiveSyntax(DirectiveID.getLoc());
8337 else if (IDVal == ".unreq")
8338 return parseDirectiveUnreq(DirectiveID.getLoc());
8339 else if (IDVal == ".fnend")
8340 return parseDirectiveFnEnd(DirectiveID.getLoc());
8341 else if (IDVal == ".cantunwind")
8342 return parseDirectiveCantUnwind(DirectiveID.getLoc());
8343 else if (IDVal == ".personality")
8344 return parseDirectivePersonality(DirectiveID.getLoc());
8345 else if (IDVal == ".handlerdata")
8346 return parseDirectiveHandlerData(DirectiveID.getLoc());
8347 else if (IDVal == ".setfp")
8348 return parseDirectiveSetFP(DirectiveID.getLoc());
8349 else if (IDVal == ".pad")
8350 return parseDirectivePad(DirectiveID.getLoc());
8351 else if (IDVal == ".save")
8352 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8353 else if (IDVal == ".vsave")
8354 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8355 else if (IDVal == ".ltorg" || IDVal == ".pool")
8356 return parseDirectiveLtorg(DirectiveID.getLoc());
8357 else if (IDVal == ".even")
8358 return parseDirectiveEven(DirectiveID.getLoc());
8359 else if (IDVal == ".personalityindex")
8360 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8361 else if (IDVal == ".unwind_raw")
8362 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8363 else if (IDVal == ".movsp")
8364 return parseDirectiveMovSP(DirectiveID.getLoc());
8365 else if (IDVal == ".arch_extension")
8366 return parseDirectiveArchExtension(DirectiveID.getLoc());
8367 else if (IDVal == ".align")
8368 return parseDirectiveAlign(DirectiveID.getLoc());
8369 else if (IDVal == ".thumb_set")
8370 return parseDirectiveThumbSet(DirectiveID.getLoc());
8372 if (!IsMachO && !IsCOFF) {
8373 if (IDVal == ".arch")
8374 return parseDirectiveArch(DirectiveID.getLoc());
8375 else if (IDVal == ".cpu")
8376 return parseDirectiveCPU(DirectiveID.getLoc());
8377 else if (IDVal == ".eabi_attribute")
8378 return parseDirectiveEabiAttr(DirectiveID.getLoc());
8379 else if (IDVal == ".fpu")
8380 return parseDirectiveFPU(DirectiveID.getLoc());
8381 else if (IDVal == ".fnstart")
8382 return parseDirectiveFnStart(DirectiveID.getLoc());
8383 else if (IDVal == ".inst")
8384 return parseDirectiveInst(DirectiveID.getLoc());
8385 else if (IDVal == ".inst.n")
8386 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8387 else if (IDVal == ".inst.w")
8388 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8389 else if (IDVal == ".object_arch")
8390 return parseDirectiveObjectArch(DirectiveID.getLoc());
8391 else if (IDVal == ".tlsdescseq")
8392 return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8398 /// parseLiteralValues
8399 /// ::= .hword expression [, expression]*
8400 /// ::= .short expression [, expression]*
8401 /// ::= .word expression [, expression]*
8402 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8403 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8405 const MCExpr *Value;
8406 if (getParser().parseExpression(Value)) {
8407 Parser.eatToEndOfStatement();
8411 getParser().getStreamer().EmitValue(Value, Size);
8413 if (getLexer().is(AsmToken::EndOfStatement))
8416 // FIXME: Improve diagnostic.
8417 if (getLexer().isNot(AsmToken::Comma)) {
8418 Error(L, "unexpected token in directive");
8429 /// parseDirectiveThumb
8431 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8432 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8433 Error(L, "unexpected token in directive");
8439 Error(L, "target does not support Thumb mode");
8446 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8450 /// parseDirectiveARM
8452 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8453 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8454 Error(L, "unexpected token in directive");
8460 Error(L, "target does not support ARM mode");
8467 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8471 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8472 if (NextSymbolIsThumb) {
8473 getParser().getStreamer().EmitThumbFunc(Symbol);
8474 NextSymbolIsThumb = false;
8478 /// parseDirectiveThumbFunc
8479 /// ::= .thumbfunc symbol_name
8480 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8481 const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
8482 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8484 // Darwin asm has (optionally) function name after .thumb_func direction
8487 const AsmToken &Tok = Parser.getTok();
8488 if (Tok.isNot(AsmToken::EndOfStatement)) {
8489 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8490 Error(L, "unexpected token in .thumb_func directive");
8495 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8496 getParser().getStreamer().EmitThumbFunc(Func);
8497 Parser.Lex(); // Consume the identifier token.
8502 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8503 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8504 Parser.eatToEndOfStatement();
8508 NextSymbolIsThumb = true;
8512 /// parseDirectiveSyntax
8513 /// ::= .syntax unified | divided
8514 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8515 const AsmToken &Tok = Parser.getTok();
8516 if (Tok.isNot(AsmToken::Identifier)) {
8517 Error(L, "unexpected token in .syntax directive");
8521 StringRef Mode = Tok.getString();
8522 if (Mode == "unified" || Mode == "UNIFIED") {
8524 } else if (Mode == "divided" || Mode == "DIVIDED") {
8525 Error(L, "'.syntax divided' arm asssembly not supported");
8528 Error(L, "unrecognized syntax mode in .syntax directive");
8532 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8533 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8538 // TODO tell the MC streamer the mode
8539 // getParser().getStreamer().Emit???();
8543 /// parseDirectiveCode
8544 /// ::= .code 16 | 32
8545 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8546 const AsmToken &Tok = Parser.getTok();
8547 if (Tok.isNot(AsmToken::Integer)) {
8548 Error(L, "unexpected token in .code directive");
8551 int64_t Val = Parser.getTok().getIntVal();
8552 if (Val != 16 && Val != 32) {
8553 Error(L, "invalid operand to .code directive");
8558 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8559 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8566 Error(L, "target does not support Thumb mode");
8572 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8575 Error(L, "target does not support ARM mode");
8581 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8587 /// parseDirectiveReq
8588 /// ::= name .req registername
8589 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8590 Parser.Lex(); // Eat the '.req' token.
8592 SMLoc SRegLoc, ERegLoc;
8593 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8594 Parser.eatToEndOfStatement();
8595 Error(SRegLoc, "register name expected");
8599 // Shouldn't be anything else.
8600 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8601 Parser.eatToEndOfStatement();
8602 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8606 Parser.Lex(); // Consume the EndOfStatement
8608 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8609 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8616 /// parseDirectiveUneq
8617 /// ::= .unreq registername
8618 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8619 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8620 Parser.eatToEndOfStatement();
8621 Error(L, "unexpected input in .unreq directive.");
8624 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
8625 Parser.Lex(); // Eat the identifier.
8629 /// parseDirectiveArch
8631 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8632 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8634 unsigned ID = StringSwitch<unsigned>(Arch)
8635 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8636 .Case(NAME, ARM::ID)
8637 #define ARM_ARCH_ALIAS(NAME, ID) \
8638 .Case(NAME, ARM::ID)
8639 #include "MCTargetDesc/ARMArchName.def"
8640 .Default(ARM::INVALID_ARCH);
8642 if (ID == ARM::INVALID_ARCH) {
8643 Error(L, "Unknown arch name");
8647 getTargetStreamer().emitArch(ID);
8651 /// parseDirectiveEabiAttr
8652 /// ::= .eabi_attribute int, int [, "str"]
8653 /// ::= .eabi_attribute Tag_name, int [, "str"]
8654 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8657 TagLoc = Parser.getTok().getLoc();
8658 if (Parser.getTok().is(AsmToken::Identifier)) {
8659 StringRef Name = Parser.getTok().getIdentifier();
8660 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8662 Error(TagLoc, "attribute name not recognised: " + Name);
8663 Parser.eatToEndOfStatement();
8668 const MCExpr *AttrExpr;
8670 TagLoc = Parser.getTok().getLoc();
8671 if (Parser.parseExpression(AttrExpr)) {
8672 Parser.eatToEndOfStatement();
8676 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8678 Error(TagLoc, "expected numeric constant");
8679 Parser.eatToEndOfStatement();
8683 Tag = CE->getValue();
8686 if (Parser.getTok().isNot(AsmToken::Comma)) {
8687 Error(Parser.getTok().getLoc(), "comma expected");
8688 Parser.eatToEndOfStatement();
8691 Parser.Lex(); // skip comma
8693 StringRef StringValue = "";
8694 bool IsStringValue = false;
8696 int64_t IntegerValue = 0;
8697 bool IsIntegerValue = false;
8699 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8700 IsStringValue = true;
8701 else if (Tag == ARMBuildAttrs::compatibility) {
8702 IsStringValue = true;
8703 IsIntegerValue = true;
8704 } else if (Tag < 32 || Tag % 2 == 0)
8705 IsIntegerValue = true;
8706 else if (Tag % 2 == 1)
8707 IsStringValue = true;
8709 llvm_unreachable("invalid tag type");
8711 if (IsIntegerValue) {
8712 const MCExpr *ValueExpr;
8713 SMLoc ValueExprLoc = Parser.getTok().getLoc();
8714 if (Parser.parseExpression(ValueExpr)) {
8715 Parser.eatToEndOfStatement();
8719 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8721 Error(ValueExprLoc, "expected numeric constant");
8722 Parser.eatToEndOfStatement();
8726 IntegerValue = CE->getValue();
8729 if (Tag == ARMBuildAttrs::compatibility) {
8730 if (Parser.getTok().isNot(AsmToken::Comma))
8731 IsStringValue = false;
8736 if (IsStringValue) {
8737 if (Parser.getTok().isNot(AsmToken::String)) {
8738 Error(Parser.getTok().getLoc(), "bad string constant");
8739 Parser.eatToEndOfStatement();
8743 StringValue = Parser.getTok().getStringContents();
8747 if (IsIntegerValue && IsStringValue) {
8748 assert(Tag == ARMBuildAttrs::compatibility);
8749 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8750 } else if (IsIntegerValue)
8751 getTargetStreamer().emitAttribute(Tag, IntegerValue);
8752 else if (IsStringValue)
8753 getTargetStreamer().emitTextAttribute(Tag, StringValue);
8757 /// parseDirectiveCPU
8759 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8760 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8761 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8765 // FIXME: This is duplicated in getARMFPUFeatures() in
8766 // tools/clang/lib/Driver/Tools.cpp
8767 static const struct {
8769 const uint64_t Enabled;
8770 const uint64_t Disabled;
8772 {ARM::VFP, ARM::FeatureVFP2, ARM::FeatureNEON},
8773 {ARM::VFPV2, ARM::FeatureVFP2, ARM::FeatureNEON},
8774 {ARM::VFPV3, ARM::FeatureVFP3, ARM::FeatureNEON},
8775 {ARM::VFPV3_D16, ARM::FeatureVFP3 | ARM::FeatureD16, ARM::FeatureNEON},
8776 {ARM::VFPV4, ARM::FeatureVFP4, ARM::FeatureNEON},
8777 {ARM::VFPV4_D16, ARM::FeatureVFP4 | ARM::FeatureD16, ARM::FeatureNEON},
8778 {ARM::FP_ARMV8, ARM::FeatureFPARMv8,
8779 ARM::FeatureNEON | ARM::FeatureCrypto},
8780 {ARM::NEON, ARM::FeatureNEON, 0},
8781 {ARM::NEON_VFPV4, ARM::FeatureVFP4 | ARM::FeatureNEON, 0},
8782 {ARM::NEON_FP_ARMV8, ARM::FeatureFPARMv8 | ARM::FeatureNEON,
8783 ARM::FeatureCrypto},
8784 {ARM::CRYPTO_NEON_FP_ARMV8,
8785 ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto, 0},
8786 {ARM::SOFTVFP, 0, 0},
8789 /// parseDirectiveFPU
8791 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8792 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8794 unsigned ID = StringSwitch<unsigned>(FPU)
8795 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8796 #include "ARMFPUName.def"
8797 .Default(ARM::INVALID_FPU);
8799 if (ID == ARM::INVALID_FPU) {
8800 Error(L, "Unknown FPU name");
8804 for (const auto &Fpu : Fpus) {
8808 // Need to toggle features that should be on but are off and that
8809 // should off but are on.
8810 uint64_t Toggle = (Fpu.Enabled & ~STI.getFeatureBits()) |
8811 (Fpu.Disabled & STI.getFeatureBits());
8812 setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle)));
8816 getTargetStreamer().emitFPU(ID);
8820 /// parseDirectiveFnStart
8822 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8823 if (UC.hasFnStart()) {
8824 Error(L, ".fnstart starts before the end of previous one");
8825 UC.emitFnStartLocNotes();
8829 // Reset the unwind directives parser state
8832 getTargetStreamer().emitFnStart();
8834 UC.recordFnStart(L);
8838 /// parseDirectiveFnEnd
8840 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8841 // Check the ordering of unwind directives
8842 if (!UC.hasFnStart()) {
8843 Error(L, ".fnstart must precede .fnend directive");
8847 // Reset the unwind directives parser state
8848 getTargetStreamer().emitFnEnd();
8854 /// parseDirectiveCantUnwind
8856 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8857 UC.recordCantUnwind(L);
8859 // Check the ordering of unwind directives
8860 if (!UC.hasFnStart()) {
8861 Error(L, ".fnstart must precede .cantunwind directive");
8864 if (UC.hasHandlerData()) {
8865 Error(L, ".cantunwind can't be used with .handlerdata directive");
8866 UC.emitHandlerDataLocNotes();
8869 if (UC.hasPersonality()) {
8870 Error(L, ".cantunwind can't be used with .personality directive");
8871 UC.emitPersonalityLocNotes();
8875 getTargetStreamer().emitCantUnwind();
8879 /// parseDirectivePersonality
8880 /// ::= .personality name
8881 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8882 bool HasExistingPersonality = UC.hasPersonality();
8884 UC.recordPersonality(L);
8886 // Check the ordering of unwind directives
8887 if (!UC.hasFnStart()) {
8888 Error(L, ".fnstart must precede .personality directive");
8891 if (UC.cantUnwind()) {
8892 Error(L, ".personality can't be used with .cantunwind directive");
8893 UC.emitCantUnwindLocNotes();
8896 if (UC.hasHandlerData()) {
8897 Error(L, ".personality must precede .handlerdata directive");
8898 UC.emitHandlerDataLocNotes();
8901 if (HasExistingPersonality) {
8902 Parser.eatToEndOfStatement();
8903 Error(L, "multiple personality directives");
8904 UC.emitPersonalityLocNotes();
8908 // Parse the name of the personality routine
8909 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8910 Parser.eatToEndOfStatement();
8911 Error(L, "unexpected input in .personality directive.");
8914 StringRef Name(Parser.getTok().getIdentifier());
8917 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8918 getTargetStreamer().emitPersonality(PR);
8922 /// parseDirectiveHandlerData
8923 /// ::= .handlerdata
8924 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8925 UC.recordHandlerData(L);
8927 // Check the ordering of unwind directives
8928 if (!UC.hasFnStart()) {
8929 Error(L, ".fnstart must precede .personality directive");
8932 if (UC.cantUnwind()) {
8933 Error(L, ".handlerdata can't be used with .cantunwind directive");
8934 UC.emitCantUnwindLocNotes();
8938 getTargetStreamer().emitHandlerData();
8942 /// parseDirectiveSetFP
8943 /// ::= .setfp fpreg, spreg [, offset]
8944 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8945 // Check the ordering of unwind directives
8946 if (!UC.hasFnStart()) {
8947 Error(L, ".fnstart must precede .setfp directive");
8950 if (UC.hasHandlerData()) {
8951 Error(L, ".setfp must precede .handlerdata directive");
8956 SMLoc FPRegLoc = Parser.getTok().getLoc();
8957 int FPReg = tryParseRegister();
8959 Error(FPRegLoc, "frame pointer register expected");
8964 if (Parser.getTok().isNot(AsmToken::Comma)) {
8965 Error(Parser.getTok().getLoc(), "comma expected");
8968 Parser.Lex(); // skip comma
8971 SMLoc SPRegLoc = Parser.getTok().getLoc();
8972 int SPReg = tryParseRegister();
8974 Error(SPRegLoc, "stack pointer register expected");
8978 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
8979 Error(SPRegLoc, "register should be either $sp or the latest fp register");
8983 // Update the frame pointer register
8984 UC.saveFPReg(FPReg);
8988 if (Parser.getTok().is(AsmToken::Comma)) {
8989 Parser.Lex(); // skip comma
8991 if (Parser.getTok().isNot(AsmToken::Hash) &&
8992 Parser.getTok().isNot(AsmToken::Dollar)) {
8993 Error(Parser.getTok().getLoc(), "'#' expected");
8996 Parser.Lex(); // skip hash token.
8998 const MCExpr *OffsetExpr;
8999 SMLoc ExLoc = Parser.getTok().getLoc();
9001 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9002 Error(ExLoc, "malformed setfp offset");
9005 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9007 Error(ExLoc, "setfp offset must be an immediate");
9011 Offset = CE->getValue();
9014 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
9015 static_cast<unsigned>(SPReg), Offset);
9021 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
9022 // Check the ordering of unwind directives
9023 if (!UC.hasFnStart()) {
9024 Error(L, ".fnstart must precede .pad directive");
9027 if (UC.hasHandlerData()) {
9028 Error(L, ".pad must precede .handlerdata directive");
9033 if (Parser.getTok().isNot(AsmToken::Hash) &&
9034 Parser.getTok().isNot(AsmToken::Dollar)) {
9035 Error(Parser.getTok().getLoc(), "'#' expected");
9038 Parser.Lex(); // skip hash token.
9040 const MCExpr *OffsetExpr;
9041 SMLoc ExLoc = Parser.getTok().getLoc();
9043 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9044 Error(ExLoc, "malformed pad offset");
9047 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9049 Error(ExLoc, "pad offset must be an immediate");
9053 getTargetStreamer().emitPad(CE->getValue());
9057 /// parseDirectiveRegSave
9058 /// ::= .save { registers }
9059 /// ::= .vsave { registers }
9060 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
9061 // Check the ordering of unwind directives
9062 if (!UC.hasFnStart()) {
9063 Error(L, ".fnstart must precede .save or .vsave directives");
9066 if (UC.hasHandlerData()) {
9067 Error(L, ".save or .vsave must precede .handlerdata directive");
9071 // RAII object to make sure parsed operands are deleted.
9072 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
9074 // Parse the register list
9075 if (parseRegisterList(Operands))
9077 ARMOperand &Op = (ARMOperand &)*Operands[0];
9078 if (!IsVector && !Op.isRegList()) {
9079 Error(L, ".save expects GPR registers");
9082 if (IsVector && !Op.isDPRRegList()) {
9083 Error(L, ".vsave expects DPR registers");
9087 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
9091 /// parseDirectiveInst
9092 /// ::= .inst opcode [, ...]
9093 /// ::= .inst.n opcode [, ...]
9094 /// ::= .inst.w opcode [, ...]
9095 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
9107 Parser.eatToEndOfStatement();
9108 Error(Loc, "cannot determine Thumb instruction size, "
9109 "use inst.n/inst.w instead");
9114 Parser.eatToEndOfStatement();
9115 Error(Loc, "width suffixes are invalid in ARM mode");
9121 if (getLexer().is(AsmToken::EndOfStatement)) {
9122 Parser.eatToEndOfStatement();
9123 Error(Loc, "expected expression following directive");
9130 if (getParser().parseExpression(Expr)) {
9131 Error(Loc, "expected expression");
9135 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
9137 Error(Loc, "expected constant expression");
9143 if (Value->getValue() > 0xffff) {
9144 Error(Loc, "inst.n operand is too big, use inst.w instead");
9149 if (Value->getValue() > 0xffffffff) {
9151 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
9156 llvm_unreachable("only supported widths are 2 and 4");
9159 getTargetStreamer().emitInst(Value->getValue(), Suffix);
9161 if (getLexer().is(AsmToken::EndOfStatement))
9164 if (getLexer().isNot(AsmToken::Comma)) {
9165 Error(Loc, "unexpected token in directive");
9176 /// parseDirectiveLtorg
9177 /// ::= .ltorg | .pool
9178 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9179 getTargetStreamer().emitCurrentConstantPool();
9183 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9184 const MCSection *Section = getStreamer().getCurrentSection().first;
9186 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9187 TokError("unexpected token in directive");
9192 getStreamer().InitSections();
9193 Section = getStreamer().getCurrentSection().first;
9196 assert(Section && "must have section to emit alignment");
9197 if (Section->UseCodeAlign())
9198 getStreamer().EmitCodeAlignment(2);
9200 getStreamer().EmitValueToAlignment(2);
9205 /// parseDirectivePersonalityIndex
9206 /// ::= .personalityindex index
9207 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9208 bool HasExistingPersonality = UC.hasPersonality();
9210 UC.recordPersonalityIndex(L);
9212 if (!UC.hasFnStart()) {
9213 Parser.eatToEndOfStatement();
9214 Error(L, ".fnstart must precede .personalityindex directive");
9217 if (UC.cantUnwind()) {
9218 Parser.eatToEndOfStatement();
9219 Error(L, ".personalityindex cannot be used with .cantunwind");
9220 UC.emitCantUnwindLocNotes();
9223 if (UC.hasHandlerData()) {
9224 Parser.eatToEndOfStatement();
9225 Error(L, ".personalityindex must precede .handlerdata directive");
9226 UC.emitHandlerDataLocNotes();
9229 if (HasExistingPersonality) {
9230 Parser.eatToEndOfStatement();
9231 Error(L, "multiple personality directives");
9232 UC.emitPersonalityLocNotes();
9236 const MCExpr *IndexExpression;
9237 SMLoc IndexLoc = Parser.getTok().getLoc();
9238 if (Parser.parseExpression(IndexExpression)) {
9239 Parser.eatToEndOfStatement();
9243 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9245 Parser.eatToEndOfStatement();
9246 Error(IndexLoc, "index must be a constant number");
9249 if (CE->getValue() < 0 ||
9250 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9251 Parser.eatToEndOfStatement();
9252 Error(IndexLoc, "personality routine index should be in range [0-3]");
9256 getTargetStreamer().emitPersonalityIndex(CE->getValue());
9260 /// parseDirectiveUnwindRaw
9261 /// ::= .unwind_raw offset, opcode [, opcode...]
9262 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9263 if (!UC.hasFnStart()) {
9264 Parser.eatToEndOfStatement();
9265 Error(L, ".fnstart must precede .unwind_raw directives");
9269 int64_t StackOffset;
9271 const MCExpr *OffsetExpr;
9272 SMLoc OffsetLoc = getLexer().getLoc();
9273 if (getLexer().is(AsmToken::EndOfStatement) ||
9274 getParser().parseExpression(OffsetExpr)) {
9275 Error(OffsetLoc, "expected expression");
9276 Parser.eatToEndOfStatement();
9280 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9282 Error(OffsetLoc, "offset must be a constant");
9283 Parser.eatToEndOfStatement();
9287 StackOffset = CE->getValue();
9289 if (getLexer().isNot(AsmToken::Comma)) {
9290 Error(getLexer().getLoc(), "expected comma");
9291 Parser.eatToEndOfStatement();
9296 SmallVector<uint8_t, 16> Opcodes;
9300 SMLoc OpcodeLoc = getLexer().getLoc();
9301 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9302 Error(OpcodeLoc, "expected opcode expression");
9303 Parser.eatToEndOfStatement();
9307 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9309 Error(OpcodeLoc, "opcode value must be a constant");
9310 Parser.eatToEndOfStatement();
9314 const int64_t Opcode = OC->getValue();
9315 if (Opcode & ~0xff) {
9316 Error(OpcodeLoc, "invalid opcode");
9317 Parser.eatToEndOfStatement();
9321 Opcodes.push_back(uint8_t(Opcode));
9323 if (getLexer().is(AsmToken::EndOfStatement))
9326 if (getLexer().isNot(AsmToken::Comma)) {
9327 Error(getLexer().getLoc(), "unexpected token in directive");
9328 Parser.eatToEndOfStatement();
9335 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9341 /// parseDirectiveTLSDescSeq
9342 /// ::= .tlsdescseq tls-variable
9343 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9344 if (getLexer().isNot(AsmToken::Identifier)) {
9345 TokError("expected variable after '.tlsdescseq' directive");
9346 Parser.eatToEndOfStatement();
9350 const MCSymbolRefExpr *SRE =
9351 MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
9352 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9355 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9356 Error(Parser.getTok().getLoc(), "unexpected token");
9357 Parser.eatToEndOfStatement();
9361 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9365 /// parseDirectiveMovSP
9366 /// ::= .movsp reg [, #offset]
9367 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9368 if (!UC.hasFnStart()) {
9369 Parser.eatToEndOfStatement();
9370 Error(L, ".fnstart must precede .movsp directives");
9373 if (UC.getFPReg() != ARM::SP) {
9374 Parser.eatToEndOfStatement();
9375 Error(L, "unexpected .movsp directive");
9379 SMLoc SPRegLoc = Parser.getTok().getLoc();
9380 int SPReg = tryParseRegister();
9382 Parser.eatToEndOfStatement();
9383 Error(SPRegLoc, "register expected");
9387 if (SPReg == ARM::SP || SPReg == ARM::PC) {
9388 Parser.eatToEndOfStatement();
9389 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9394 if (Parser.getTok().is(AsmToken::Comma)) {
9397 if (Parser.getTok().isNot(AsmToken::Hash)) {
9398 Error(Parser.getTok().getLoc(), "expected #constant");
9399 Parser.eatToEndOfStatement();
9404 const MCExpr *OffsetExpr;
9405 SMLoc OffsetLoc = Parser.getTok().getLoc();
9406 if (Parser.parseExpression(OffsetExpr)) {
9407 Parser.eatToEndOfStatement();
9408 Error(OffsetLoc, "malformed offset expression");
9412 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9414 Parser.eatToEndOfStatement();
9415 Error(OffsetLoc, "offset must be an immediate constant");
9419 Offset = CE->getValue();
9422 getTargetStreamer().emitMovSP(SPReg, Offset);
9423 UC.saveFPReg(SPReg);
9428 /// parseDirectiveObjectArch
9429 /// ::= .object_arch name
9430 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9431 if (getLexer().isNot(AsmToken::Identifier)) {
9432 Error(getLexer().getLoc(), "unexpected token");
9433 Parser.eatToEndOfStatement();
9437 StringRef Arch = Parser.getTok().getString();
9438 SMLoc ArchLoc = Parser.getTok().getLoc();
9441 unsigned ID = StringSwitch<unsigned>(Arch)
9442 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9443 .Case(NAME, ARM::ID)
9444 #define ARM_ARCH_ALIAS(NAME, ID) \
9445 .Case(NAME, ARM::ID)
9446 #include "MCTargetDesc/ARMArchName.def"
9447 #undef ARM_ARCH_NAME
9448 #undef ARM_ARCH_ALIAS
9449 .Default(ARM::INVALID_ARCH);
9451 if (ID == ARM::INVALID_ARCH) {
9452 Error(ArchLoc, "unknown architecture '" + Arch + "'");
9453 Parser.eatToEndOfStatement();
9457 getTargetStreamer().emitObjectArch(ID);
9459 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9460 Error(getLexer().getLoc(), "unexpected token");
9461 Parser.eatToEndOfStatement();
9467 /// parseDirectiveAlign
9469 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9470 // NOTE: if this is not the end of the statement, fall back to the target
9471 // agnostic handling for this directive which will correctly handle this.
9472 if (getLexer().isNot(AsmToken::EndOfStatement))
9475 // '.align' is target specifically handled to mean 2**2 byte alignment.
9476 if (getStreamer().getCurrentSection().first->UseCodeAlign())
9477 getStreamer().EmitCodeAlignment(4, 0);
9479 getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9484 /// parseDirectiveThumbSet
9485 /// ::= .thumb_set name, value
9486 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9488 if (Parser.parseIdentifier(Name)) {
9489 TokError("expected identifier after '.thumb_set'");
9490 Parser.eatToEndOfStatement();
9494 if (getLexer().isNot(AsmToken::Comma)) {
9495 TokError("expected comma after name '" + Name + "'");
9496 Parser.eatToEndOfStatement();
9501 const MCExpr *Value;
9502 if (Parser.parseExpression(Value)) {
9503 TokError("missing expression");
9504 Parser.eatToEndOfStatement();
9508 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9509 TokError("unexpected token");
9510 Parser.eatToEndOfStatement();
9515 MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
9516 getTargetStreamer().emitThumbSet(Alias, Value);
9520 /// Force static initialization.
9521 extern "C" void LLVMInitializeARMAsmParser() {
9522 RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9523 RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9524 RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9525 RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9528 #define GET_REGISTER_MATCHER
9529 #define GET_SUBTARGET_FEATURE_NAME
9530 #define GET_MATCHER_IMPLEMENTATION
9531 #include "ARMGenAsmMatcher.inc"
9533 static const struct {
9535 const unsigned ArchCheck;
9536 const uint64_t Features;
9538 { "crc", Feature_HasV8, ARM::FeatureCRC },
9539 { "crypto", Feature_HasV8,
9540 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9541 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9542 { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9543 ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9544 // FIXME: iWMMXT not supported
9545 { "iwmmxt", Feature_None, 0 },
9546 // FIXME: iWMMXT2 not supported
9547 { "iwmmxt2", Feature_None, 0 },
9548 // FIXME: Maverick not supported
9549 { "maverick", Feature_None, 0 },
9550 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
9551 // FIXME: ARMv6-m OS Extensions feature not checked
9552 { "os", Feature_None, 0 },
9553 // FIXME: Also available in ARMv6-K
9554 { "sec", Feature_HasV7, ARM::FeatureTrustZone },
9555 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9556 // FIXME: Only available in A-class, isel not predicated
9557 { "virt", Feature_HasV7, ARM::FeatureVirtualization },
9558 // FIXME: xscale not supported
9559 { "xscale", Feature_None, 0 },
9562 /// parseDirectiveArchExtension
9563 /// ::= .arch_extension [no]feature
9564 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9565 if (getLexer().isNot(AsmToken::Identifier)) {
9566 Error(getLexer().getLoc(), "unexpected token");
9567 Parser.eatToEndOfStatement();
9571 StringRef Name = Parser.getTok().getString();
9572 SMLoc ExtLoc = Parser.getTok().getLoc();
9575 bool EnableFeature = true;
9576 if (Name.startswith_lower("no")) {
9577 EnableFeature = false;
9578 Name = Name.substr(2);
9581 for (const auto &Extension : Extensions) {
9582 if (Extension.Name != Name)
9585 if (!Extension.Features)
9586 report_fatal_error("unsupported architectural extension: " + Name);
9588 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
9589 Error(ExtLoc, "architectural extension '" + Name + "' is not "
9590 "allowed for the current base architecture");
9594 uint64_t ToggleFeatures = EnableFeature
9595 ? (~STI.getFeatureBits() & Extension.Features)
9596 : ( STI.getFeatureBits() & Extension.Features);
9598 ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
9599 setAvailableFeatures(Features);
9603 Error(ExtLoc, "unknown architectural extension: " + Name);
9604 Parser.eatToEndOfStatement();
9608 // Define this matcher function after the auto-generated include so we
9609 // have the match class enum definitions.
9610 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
9612 ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
9613 // If the kind is a token for a literal immediate, check if our asm
9614 // operand matches. This is for InstAliases which have a fixed-value
9615 // immediate in the syntax.
9620 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
9621 if (CE->getValue() == 0)
9622 return Match_Success;
9626 const MCExpr *SOExpr = Op.getImm();
9628 if (!SOExpr->EvaluateAsAbsolute(Value))
9629 return Match_Success;
9630 assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
9631 "expression value must be representable in 32 bits");
9636 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
9637 return Match_Success;
9640 return Match_InvalidOperand;