1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/ADT/Twine.h"
42 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
44 class ARMAsmParser : public MCTargetAsmParser {
47 const MCRegisterInfo *MRI;
49 // Map of register aliases registers via the .req directive.
50 StringMap<unsigned> RegisterReqs;
53 ARMCC::CondCodes Cond; // Condition for IT block.
54 unsigned Mask:4; // Condition mask for instructions.
55 // Starting at first 1 (from lsb).
56 // '1' condition as indicated in IT.
57 // '0' inverse of condition (else).
58 // Count of instructions in IT block is
59 // 4 - trailingzeroes(mask)
61 bool FirstCond; // Explicit flag for when we're parsing the
62 // First instruction in the IT block. It's
63 // implied in the mask, so needs special
66 unsigned CurPosition; // Current position in parsing of IT
67 // block. In range [0,3]. Initialized
68 // according to count of instructions in block.
69 // ~0U if no active IT block.
71 bool inITBlock() { return ITState.CurPosition != ~0U;}
72 void forwardITPosition() {
73 if (!inITBlock()) return;
74 // Move to the next instruction in the IT block, if there is one. If not,
75 // mark the block as done.
76 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
77 if (++ITState.CurPosition == 5 - TZ)
78 ITState.CurPosition = ~0U; // Done with the IT block after this.
82 MCAsmParser &getParser() const { return Parser; }
83 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
85 bool Warning(SMLoc L, const Twine &Msg,
86 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
87 return Parser.Warning(L, Msg, Ranges);
89 bool Error(SMLoc L, const Twine &Msg,
90 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
91 return Parser.Error(L, Msg, Ranges);
94 int tryParseRegister();
95 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
96 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
97 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
98 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
99 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
100 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
101 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
102 unsigned &ShiftAmount);
103 bool parseDirectiveWord(unsigned Size, SMLoc L);
104 bool parseDirectiveThumb(SMLoc L);
105 bool parseDirectiveARM(SMLoc L);
106 bool parseDirectiveThumbFunc(SMLoc L);
107 bool parseDirectiveCode(SMLoc L);
108 bool parseDirectiveSyntax(SMLoc L);
109 bool parseDirectiveReq(StringRef Name, SMLoc L);
110 bool parseDirectiveUnreq(SMLoc L);
111 bool parseDirectiveArch(SMLoc L);
112 bool parseDirectiveEabiAttr(SMLoc L);
114 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
115 bool &CarrySetting, unsigned &ProcessorIMod,
117 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
118 bool &CanAcceptPredicationCode);
120 bool isThumb() const {
121 // FIXME: Can tablegen auto-generate this?
122 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
124 bool isThumbOne() const {
125 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
127 bool isThumbTwo() const {
128 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
130 bool hasV6Ops() const {
131 return STI.getFeatureBits() & ARM::HasV6Ops;
133 bool hasV7Ops() const {
134 return STI.getFeatureBits() & ARM::HasV7Ops;
137 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
138 setAvailableFeatures(FB);
140 bool isMClass() const {
141 return STI.getFeatureBits() & ARM::FeatureMClass;
144 /// @name Auto-generated Match Functions
147 #define GET_ASSEMBLER_HEADER
148 #include "ARMGenAsmMatcher.inc"
152 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
153 OperandMatchResultTy parseCoprocNumOperand(
154 SmallVectorImpl<MCParsedAsmOperand*>&);
155 OperandMatchResultTy parseCoprocRegOperand(
156 SmallVectorImpl<MCParsedAsmOperand*>&);
157 OperandMatchResultTy parseCoprocOptionOperand(
158 SmallVectorImpl<MCParsedAsmOperand*>&);
159 OperandMatchResultTy parseMemBarrierOptOperand(
160 SmallVectorImpl<MCParsedAsmOperand*>&);
161 OperandMatchResultTy parseProcIFlagsOperand(
162 SmallVectorImpl<MCParsedAsmOperand*>&);
163 OperandMatchResultTy parseMSRMaskOperand(
164 SmallVectorImpl<MCParsedAsmOperand*>&);
165 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
166 StringRef Op, int Low, int High);
167 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
168 return parsePKHImm(O, "lsl", 0, 31);
170 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
171 return parsePKHImm(O, "asr", 1, 32);
173 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
174 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
175 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
176 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
177 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
178 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
179 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
180 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
181 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
183 // Asm Match Converter Methods
184 void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
185 void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
186 void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
187 const SmallVectorImpl<MCParsedAsmOperand*> &);
188 void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
189 const SmallVectorImpl<MCParsedAsmOperand*> &);
190 void cvtLdWriteBackRegAddrMode2(MCInst &Inst,
191 const SmallVectorImpl<MCParsedAsmOperand*> &);
192 void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
193 const SmallVectorImpl<MCParsedAsmOperand*> &);
194 void cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
195 const SmallVectorImpl<MCParsedAsmOperand*> &);
196 void cvtStWriteBackRegAddrMode2(MCInst &Inst,
197 const SmallVectorImpl<MCParsedAsmOperand*> &);
198 void cvtStWriteBackRegAddrMode3(MCInst &Inst,
199 const SmallVectorImpl<MCParsedAsmOperand*> &);
200 void cvtLdExtTWriteBackImm(MCInst &Inst,
201 const SmallVectorImpl<MCParsedAsmOperand*> &);
202 void cvtLdExtTWriteBackReg(MCInst &Inst,
203 const SmallVectorImpl<MCParsedAsmOperand*> &);
204 void cvtStExtTWriteBackImm(MCInst &Inst,
205 const SmallVectorImpl<MCParsedAsmOperand*> &);
206 void cvtStExtTWriteBackReg(MCInst &Inst,
207 const SmallVectorImpl<MCParsedAsmOperand*> &);
208 void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
209 void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
210 void cvtLdWriteBackRegAddrMode3(MCInst &Inst,
211 const SmallVectorImpl<MCParsedAsmOperand*> &);
212 void cvtThumbMultiply(MCInst &Inst,
213 const SmallVectorImpl<MCParsedAsmOperand*> &);
214 void cvtVLDwbFixed(MCInst &Inst,
215 const SmallVectorImpl<MCParsedAsmOperand*> &);
216 void cvtVLDwbRegister(MCInst &Inst,
217 const SmallVectorImpl<MCParsedAsmOperand*> &);
218 void cvtVSTwbFixed(MCInst &Inst,
219 const SmallVectorImpl<MCParsedAsmOperand*> &);
220 void cvtVSTwbRegister(MCInst &Inst,
221 const SmallVectorImpl<MCParsedAsmOperand*> &);
222 bool validateInstruction(MCInst &Inst,
223 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
224 bool processInstruction(MCInst &Inst,
225 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
226 bool shouldOmitCCOutOperand(StringRef Mnemonic,
227 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
230 enum ARMMatchResultTy {
231 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
232 Match_RequiresNotITBlock,
234 Match_RequiresThumb2,
235 #define GET_OPERAND_DIAGNOSTIC_TYPES
236 #include "ARMGenAsmMatcher.inc"
240 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
241 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
242 MCAsmParserExtension::Initialize(_Parser);
244 // Cache the MCRegisterInfo.
245 MRI = &getContext().getRegisterInfo();
247 // Initialize the set of available features.
248 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
250 // Not in an ITBlock to start with.
251 ITState.CurPosition = ~0U;
254 // Implementation of the MCTargetAsmParser interface:
255 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
256 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
257 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
258 bool ParseDirective(AsmToken DirectiveID);
260 unsigned checkTargetMatchPredicate(MCInst &Inst);
262 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
263 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
264 MCStreamer &Out, unsigned &ErrorInfo,
265 bool MatchingInlineAsm);
267 } // end anonymous namespace
271 /// ARMOperand - Instances of this class represent a parsed ARM machine
273 class ARMOperand : public MCParsedAsmOperand {
293 k_VectorListAllLanes,
299 k_BitfieldDescriptor,
303 SMLoc StartLoc, EndLoc;
304 SmallVector<unsigned, 8> Registers;
308 ARMCC::CondCodes Val;
328 ARM_PROC::IFlags Val;
344 // A vector register list is a sequential list of 1 to 4 registers.
360 /// Combined record for all forms of ARM address expressions.
363 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
365 const MCConstantExpr *OffsetImm; // Offset immediate value
366 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
367 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
368 unsigned ShiftImm; // shift for OffsetReg.
369 unsigned Alignment; // 0 = no alignment specified
370 // n = alignment in bytes (2, 4, 8, 16, or 32)
371 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
377 ARM_AM::ShiftOpc ShiftTy;
386 ARM_AM::ShiftOpc ShiftTy;
392 ARM_AM::ShiftOpc ShiftTy;
405 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
407 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
409 StartLoc = o.StartLoc;
426 case k_DPRRegisterList:
427 case k_SPRRegisterList:
428 Registers = o.Registers;
431 case k_VectorListAllLanes:
432 case k_VectorListIndexed:
433 VectorList = o.VectorList;
440 CoprocOption = o.CoprocOption;
445 case k_MemBarrierOpt:
451 case k_PostIndexRegister:
452 PostIdxReg = o.PostIdxReg;
460 case k_ShifterImmediate:
461 ShifterImm = o.ShifterImm;
463 case k_ShiftedRegister:
464 RegShiftedReg = o.RegShiftedReg;
466 case k_ShiftedImmediate:
467 RegShiftedImm = o.RegShiftedImm;
469 case k_RotateImmediate:
472 case k_BitfieldDescriptor:
473 Bitfield = o.Bitfield;
476 VectorIndex = o.VectorIndex;
481 /// getStartLoc - Get the location of the first token of this operand.
482 SMLoc getStartLoc() const { return StartLoc; }
483 /// getEndLoc - Get the location of the last token of this operand.
484 SMLoc getEndLoc() const { return EndLoc; }
485 /// getLocRange - Get the range between the first and last token of this
487 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
489 ARMCC::CondCodes getCondCode() const {
490 assert(Kind == k_CondCode && "Invalid access!");
494 unsigned getCoproc() const {
495 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
499 StringRef getToken() const {
500 assert(Kind == k_Token && "Invalid access!");
501 return StringRef(Tok.Data, Tok.Length);
504 unsigned getReg() const {
505 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
509 const SmallVectorImpl<unsigned> &getRegList() const {
510 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
511 Kind == k_SPRRegisterList) && "Invalid access!");
515 const MCExpr *getImm() const {
516 assert(isImm() && "Invalid access!");
520 unsigned getVectorIndex() const {
521 assert(Kind == k_VectorIndex && "Invalid access!");
522 return VectorIndex.Val;
525 ARM_MB::MemBOpt getMemBarrierOpt() const {
526 assert(Kind == k_MemBarrierOpt && "Invalid access!");
530 ARM_PROC::IFlags getProcIFlags() const {
531 assert(Kind == k_ProcIFlags && "Invalid access!");
535 unsigned getMSRMask() const {
536 assert(Kind == k_MSRMask && "Invalid access!");
540 bool isCoprocNum() const { return Kind == k_CoprocNum; }
541 bool isCoprocReg() const { return Kind == k_CoprocReg; }
542 bool isCoprocOption() const { return Kind == k_CoprocOption; }
543 bool isCondCode() const { return Kind == k_CondCode; }
544 bool isCCOut() const { return Kind == k_CCOut; }
545 bool isITMask() const { return Kind == k_ITCondMask; }
546 bool isITCondCode() const { return Kind == k_CondCode; }
547 bool isImm() const { return Kind == k_Immediate; }
548 bool isFPImm() const {
549 if (!isImm()) return false;
550 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
551 if (!CE) return false;
552 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
555 bool isFBits16() const {
556 if (!isImm()) return false;
557 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
558 if (!CE) return false;
559 int64_t Value = CE->getValue();
560 return Value >= 0 && Value <= 16;
562 bool isFBits32() const {
563 if (!isImm()) return false;
564 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
565 if (!CE) return false;
566 int64_t Value = CE->getValue();
567 return Value >= 1 && Value <= 32;
569 bool isImm8s4() const {
570 if (!isImm()) return false;
571 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
572 if (!CE) return false;
573 int64_t Value = CE->getValue();
574 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
576 bool isImm0_1020s4() const {
577 if (!isImm()) return false;
578 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
579 if (!CE) return false;
580 int64_t Value = CE->getValue();
581 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
583 bool isImm0_508s4() const {
584 if (!isImm()) return false;
585 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
586 if (!CE) return false;
587 int64_t Value = CE->getValue();
588 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
590 bool isImm0_508s4Neg() const {
591 if (!isImm()) return false;
592 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
593 if (!CE) return false;
594 int64_t Value = -CE->getValue();
595 // explicitly exclude zero. we want that to use the normal 0_508 version.
596 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
598 bool isImm0_255() const {
599 if (!isImm()) return false;
600 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
601 if (!CE) return false;
602 int64_t Value = CE->getValue();
603 return Value >= 0 && Value < 256;
605 bool isImm0_4095() const {
606 if (!isImm()) return false;
607 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
608 if (!CE) return false;
609 int64_t Value = CE->getValue();
610 return Value >= 0 && Value < 4096;
612 bool isImm0_4095Neg() const {
613 if (!isImm()) return false;
614 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
615 if (!CE) return false;
616 int64_t Value = -CE->getValue();
617 return Value > 0 && Value < 4096;
619 bool isImm0_1() const {
620 if (!isImm()) return false;
621 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
622 if (!CE) return false;
623 int64_t Value = CE->getValue();
624 return Value >= 0 && Value < 2;
626 bool isImm0_3() const {
627 if (!isImm()) return false;
628 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
629 if (!CE) return false;
630 int64_t Value = CE->getValue();
631 return Value >= 0 && Value < 4;
633 bool isImm0_7() const {
634 if (!isImm()) return false;
635 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
636 if (!CE) return false;
637 int64_t Value = CE->getValue();
638 return Value >= 0 && Value < 8;
640 bool isImm0_15() const {
641 if (!isImm()) return false;
642 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
643 if (!CE) return false;
644 int64_t Value = CE->getValue();
645 return Value >= 0 && Value < 16;
647 bool isImm0_31() const {
648 if (!isImm()) return false;
649 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
650 if (!CE) return false;
651 int64_t Value = CE->getValue();
652 return Value >= 0 && Value < 32;
654 bool isImm0_63() const {
655 if (!isImm()) return false;
656 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
657 if (!CE) return false;
658 int64_t Value = CE->getValue();
659 return Value >= 0 && Value < 64;
661 bool isImm8() const {
662 if (!isImm()) return false;
663 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
664 if (!CE) return false;
665 int64_t Value = CE->getValue();
668 bool isImm16() const {
669 if (!isImm()) return false;
670 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
671 if (!CE) return false;
672 int64_t Value = CE->getValue();
675 bool isImm32() const {
676 if (!isImm()) return false;
677 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
678 if (!CE) return false;
679 int64_t Value = CE->getValue();
682 bool isShrImm8() const {
683 if (!isImm()) return false;
684 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
685 if (!CE) return false;
686 int64_t Value = CE->getValue();
687 return Value > 0 && Value <= 8;
689 bool isShrImm16() const {
690 if (!isImm()) return false;
691 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
692 if (!CE) return false;
693 int64_t Value = CE->getValue();
694 return Value > 0 && Value <= 16;
696 bool isShrImm32() const {
697 if (!isImm()) return false;
698 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
699 if (!CE) return false;
700 int64_t Value = CE->getValue();
701 return Value > 0 && Value <= 32;
703 bool isShrImm64() const {
704 if (!isImm()) return false;
705 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
706 if (!CE) return false;
707 int64_t Value = CE->getValue();
708 return Value > 0 && Value <= 64;
710 bool isImm1_7() const {
711 if (!isImm()) return false;
712 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
713 if (!CE) return false;
714 int64_t Value = CE->getValue();
715 return Value > 0 && Value < 8;
717 bool isImm1_15() const {
718 if (!isImm()) return false;
719 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
720 if (!CE) return false;
721 int64_t Value = CE->getValue();
722 return Value > 0 && Value < 16;
724 bool isImm1_31() const {
725 if (!isImm()) return false;
726 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
727 if (!CE) return false;
728 int64_t Value = CE->getValue();
729 return Value > 0 && Value < 32;
731 bool isImm1_16() const {
732 if (!isImm()) return false;
733 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
734 if (!CE) return false;
735 int64_t Value = CE->getValue();
736 return Value > 0 && Value < 17;
738 bool isImm1_32() const {
739 if (!isImm()) return false;
740 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
741 if (!CE) return false;
742 int64_t Value = CE->getValue();
743 return Value > 0 && Value < 33;
745 bool isImm0_32() const {
746 if (!isImm()) return false;
747 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
748 if (!CE) return false;
749 int64_t Value = CE->getValue();
750 return Value >= 0 && Value < 33;
752 bool isImm0_65535() const {
753 if (!isImm()) return false;
754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
755 if (!CE) return false;
756 int64_t Value = CE->getValue();
757 return Value >= 0 && Value < 65536;
759 bool isImm0_65535Expr() const {
760 if (!isImm()) return false;
761 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
762 // If it's not a constant expression, it'll generate a fixup and be
764 if (!CE) return true;
765 int64_t Value = CE->getValue();
766 return Value >= 0 && Value < 65536;
768 bool isImm24bit() const {
769 if (!isImm()) return false;
770 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
771 if (!CE) return false;
772 int64_t Value = CE->getValue();
773 return Value >= 0 && Value <= 0xffffff;
775 bool isImmThumbSR() const {
776 if (!isImm()) return false;
777 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
778 if (!CE) return false;
779 int64_t Value = CE->getValue();
780 return Value > 0 && Value < 33;
782 bool isPKHLSLImm() const {
783 if (!isImm()) return false;
784 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
785 if (!CE) return false;
786 int64_t Value = CE->getValue();
787 return Value >= 0 && Value < 32;
789 bool isPKHASRImm() const {
790 if (!isImm()) return false;
791 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
792 if (!CE) return false;
793 int64_t Value = CE->getValue();
794 return Value > 0 && Value <= 32;
796 bool isAdrLabel() const {
797 // If we have an immediate that's not a constant, treat it as a label
798 // reference needing a fixup. If it is a constant, but it can't fit
799 // into shift immediate encoding, we reject it.
800 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
801 else return (isARMSOImm() || isARMSOImmNeg());
803 bool isARMSOImm() const {
804 if (!isImm()) return false;
805 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
806 if (!CE) return false;
807 int64_t Value = CE->getValue();
808 return ARM_AM::getSOImmVal(Value) != -1;
810 bool isARMSOImmNot() const {
811 if (!isImm()) return false;
812 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
813 if (!CE) return false;
814 int64_t Value = CE->getValue();
815 return ARM_AM::getSOImmVal(~Value) != -1;
817 bool isARMSOImmNeg() const {
818 if (!isImm()) return false;
819 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
820 if (!CE) return false;
821 int64_t Value = CE->getValue();
822 // Only use this when not representable as a plain so_imm.
823 return ARM_AM::getSOImmVal(Value) == -1 &&
824 ARM_AM::getSOImmVal(-Value) != -1;
826 bool isT2SOImm() const {
827 if (!isImm()) return false;
828 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
829 if (!CE) return false;
830 int64_t Value = CE->getValue();
831 return ARM_AM::getT2SOImmVal(Value) != -1;
833 bool isT2SOImmNot() const {
834 if (!isImm()) return false;
835 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
836 if (!CE) return false;
837 int64_t Value = CE->getValue();
838 return ARM_AM::getT2SOImmVal(~Value) != -1;
840 bool isT2SOImmNeg() const {
841 if (!isImm()) return false;
842 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
843 if (!CE) return false;
844 int64_t Value = CE->getValue();
845 // Only use this when not representable as a plain so_imm.
846 return ARM_AM::getT2SOImmVal(Value) == -1 &&
847 ARM_AM::getT2SOImmVal(-Value) != -1;
849 bool isSetEndImm() const {
850 if (!isImm()) return false;
851 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
852 if (!CE) return false;
853 int64_t Value = CE->getValue();
854 return Value == 1 || Value == 0;
856 bool isReg() const { return Kind == k_Register; }
857 bool isRegList() const { return Kind == k_RegisterList; }
858 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
859 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
860 bool isToken() const { return Kind == k_Token; }
861 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
862 bool isMem() const { return Kind == k_Memory; }
863 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
864 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
865 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
866 bool isRotImm() const { return Kind == k_RotateImmediate; }
867 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
868 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
869 bool isPostIdxReg() const {
870 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
872 bool isMemNoOffset(bool alignOK = false) const {
875 // No offset of any kind.
876 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
877 (alignOK || Memory.Alignment == 0);
879 bool isMemPCRelImm12() const {
880 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
882 // Base register must be PC.
883 if (Memory.BaseRegNum != ARM::PC)
885 // Immediate offset in range [-4095, 4095].
886 if (!Memory.OffsetImm) return true;
887 int64_t Val = Memory.OffsetImm->getValue();
888 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
890 bool isAlignedMemory() const {
891 return isMemNoOffset(true);
893 bool isAddrMode2() const {
894 if (!isMem() || Memory.Alignment != 0) return false;
895 // Check for register offset.
896 if (Memory.OffsetRegNum) return true;
897 // Immediate offset in range [-4095, 4095].
898 if (!Memory.OffsetImm) return true;
899 int64_t Val = Memory.OffsetImm->getValue();
900 return Val > -4096 && Val < 4096;
902 bool isAM2OffsetImm() const {
903 if (!isImm()) return false;
904 // Immediate offset in range [-4095, 4095].
905 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
906 if (!CE) return false;
907 int64_t Val = CE->getValue();
908 return Val > -4096 && Val < 4096;
910 bool isAddrMode3() const {
911 // If we have an immediate that's not a constant, treat it as a label
912 // reference needing a fixup. If it is a constant, it's something else
914 if (isImm() && !isa<MCConstantExpr>(getImm()))
916 if (!isMem() || Memory.Alignment != 0) return false;
917 // No shifts are legal for AM3.
918 if (Memory.ShiftType != ARM_AM::no_shift) return false;
919 // Check for register offset.
920 if (Memory.OffsetRegNum) return true;
921 // Immediate offset in range [-255, 255].
922 if (!Memory.OffsetImm) return true;
923 int64_t Val = Memory.OffsetImm->getValue();
924 // The #-0 offset is encoded as INT32_MIN, and we have to check
926 return (Val > -256 && Val < 256) || Val == INT32_MIN;
928 bool isAM3Offset() const {
929 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
931 if (Kind == k_PostIndexRegister)
932 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
933 // Immediate offset in range [-255, 255].
934 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
935 if (!CE) return false;
936 int64_t Val = CE->getValue();
937 // Special case, #-0 is INT32_MIN.
938 return (Val > -256 && Val < 256) || Val == INT32_MIN;
940 bool isAddrMode5() const {
941 // If we have an immediate that's not a constant, treat it as a label
942 // reference needing a fixup. If it is a constant, it's something else
944 if (isImm() && !isa<MCConstantExpr>(getImm()))
946 if (!isMem() || Memory.Alignment != 0) return false;
947 // Check for register offset.
948 if (Memory.OffsetRegNum) return false;
949 // Immediate offset in range [-1020, 1020] and a multiple of 4.
950 if (!Memory.OffsetImm) return true;
951 int64_t Val = Memory.OffsetImm->getValue();
952 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
955 bool isMemTBB() const {
956 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
957 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
961 bool isMemTBH() const {
962 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
963 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
964 Memory.Alignment != 0 )
968 bool isMemRegOffset() const {
969 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
973 bool isT2MemRegOffset() const {
974 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
975 Memory.Alignment != 0)
977 // Only lsl #{0, 1, 2, 3} allowed.
978 if (Memory.ShiftType == ARM_AM::no_shift)
980 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
984 bool isMemThumbRR() const {
985 // Thumb reg+reg addressing is simple. Just two registers, a base and
986 // an offset. No shifts, negations or any other complicating factors.
987 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
988 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
990 return isARMLowRegister(Memory.BaseRegNum) &&
991 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
993 bool isMemThumbRIs4() const {
994 if (!isMem() || Memory.OffsetRegNum != 0 ||
995 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
997 // Immediate offset, multiple of 4 in range [0, 124].
998 if (!Memory.OffsetImm) return true;
999 int64_t Val = Memory.OffsetImm->getValue();
1000 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1002 bool isMemThumbRIs2() const {
1003 if (!isMem() || Memory.OffsetRegNum != 0 ||
1004 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1006 // Immediate offset, multiple of 4 in range [0, 62].
1007 if (!Memory.OffsetImm) return true;
1008 int64_t Val = Memory.OffsetImm->getValue();
1009 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1011 bool isMemThumbRIs1() const {
1012 if (!isMem() || Memory.OffsetRegNum != 0 ||
1013 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1015 // Immediate offset in range [0, 31].
1016 if (!Memory.OffsetImm) return true;
1017 int64_t Val = Memory.OffsetImm->getValue();
1018 return Val >= 0 && Val <= 31;
1020 bool isMemThumbSPI() const {
1021 if (!isMem() || Memory.OffsetRegNum != 0 ||
1022 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1024 // Immediate offset, multiple of 4 in range [0, 1020].
1025 if (!Memory.OffsetImm) return true;
1026 int64_t Val = Memory.OffsetImm->getValue();
1027 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1029 bool isMemImm8s4Offset() const {
1030 // If we have an immediate that's not a constant, treat it as a label
1031 // reference needing a fixup. If it is a constant, it's something else
1032 // and we reject it.
1033 if (isImm() && !isa<MCConstantExpr>(getImm()))
1035 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1037 // Immediate offset a multiple of 4 in range [-1020, 1020].
1038 if (!Memory.OffsetImm) return true;
1039 int64_t Val = Memory.OffsetImm->getValue();
1040 // Special case, #-0 is INT32_MIN.
1041 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1043 bool isMemImm0_1020s4Offset() const {
1044 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1046 // Immediate offset a multiple of 4 in range [0, 1020].
1047 if (!Memory.OffsetImm) return true;
1048 int64_t Val = Memory.OffsetImm->getValue();
1049 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1051 bool isMemImm8Offset() const {
1052 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1054 // Base reg of PC isn't allowed for these encodings.
1055 if (Memory.BaseRegNum == ARM::PC) return false;
1056 // Immediate offset in range [-255, 255].
1057 if (!Memory.OffsetImm) return true;
1058 int64_t Val = Memory.OffsetImm->getValue();
1059 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1061 bool isMemPosImm8Offset() const {
1062 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1064 // Immediate offset in range [0, 255].
1065 if (!Memory.OffsetImm) return true;
1066 int64_t Val = Memory.OffsetImm->getValue();
1067 return Val >= 0 && Val < 256;
1069 bool isMemNegImm8Offset() const {
1070 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1072 // Base reg of PC isn't allowed for these encodings.
1073 if (Memory.BaseRegNum == ARM::PC) return false;
1074 // Immediate offset in range [-255, -1].
1075 if (!Memory.OffsetImm) return false;
1076 int64_t Val = Memory.OffsetImm->getValue();
1077 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1079 bool isMemUImm12Offset() const {
1080 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1082 // Immediate offset in range [0, 4095].
1083 if (!Memory.OffsetImm) return true;
1084 int64_t Val = Memory.OffsetImm->getValue();
1085 return (Val >= 0 && Val < 4096);
1087 bool isMemImm12Offset() const {
1088 // If we have an immediate that's not a constant, treat it as a label
1089 // reference needing a fixup. If it is a constant, it's something else
1090 // and we reject it.
1091 if (isImm() && !isa<MCConstantExpr>(getImm()))
1094 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1096 // Immediate offset in range [-4095, 4095].
1097 if (!Memory.OffsetImm) return true;
1098 int64_t Val = Memory.OffsetImm->getValue();
1099 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1101 bool isPostIdxImm8() const {
1102 if (!isImm()) return false;
1103 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1104 if (!CE) return false;
1105 int64_t Val = CE->getValue();
1106 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1108 bool isPostIdxImm8s4() const {
1109 if (!isImm()) return false;
1110 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1111 if (!CE) return false;
1112 int64_t Val = CE->getValue();
1113 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1117 bool isMSRMask() const { return Kind == k_MSRMask; }
1118 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1121 bool isSingleSpacedVectorList() const {
1122 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1124 bool isDoubleSpacedVectorList() const {
1125 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1127 bool isVecListOneD() const {
1128 if (!isSingleSpacedVectorList()) return false;
1129 return VectorList.Count == 1;
1132 bool isVecListDPair() const {
1133 if (!isSingleSpacedVectorList()) return false;
1134 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1135 .contains(VectorList.RegNum));
1138 bool isVecListThreeD() const {
1139 if (!isSingleSpacedVectorList()) return false;
1140 return VectorList.Count == 3;
1143 bool isVecListFourD() const {
1144 if (!isSingleSpacedVectorList()) return false;
1145 return VectorList.Count == 4;
1148 bool isVecListDPairSpaced() const {
1149 if (isSingleSpacedVectorList()) return false;
1150 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1151 .contains(VectorList.RegNum));
1154 bool isVecListThreeQ() const {
1155 if (!isDoubleSpacedVectorList()) return false;
1156 return VectorList.Count == 3;
1159 bool isVecListFourQ() const {
1160 if (!isDoubleSpacedVectorList()) return false;
1161 return VectorList.Count == 4;
1164 bool isSingleSpacedVectorAllLanes() const {
1165 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1167 bool isDoubleSpacedVectorAllLanes() const {
1168 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1170 bool isVecListOneDAllLanes() const {
1171 if (!isSingleSpacedVectorAllLanes()) return false;
1172 return VectorList.Count == 1;
1175 bool isVecListDPairAllLanes() const {
1176 if (!isSingleSpacedVectorAllLanes()) return false;
1177 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1178 .contains(VectorList.RegNum));
1181 bool isVecListDPairSpacedAllLanes() const {
1182 if (!isDoubleSpacedVectorAllLanes()) return false;
1183 return VectorList.Count == 2;
1186 bool isVecListThreeDAllLanes() const {
1187 if (!isSingleSpacedVectorAllLanes()) return false;
1188 return VectorList.Count == 3;
1191 bool isVecListThreeQAllLanes() const {
1192 if (!isDoubleSpacedVectorAllLanes()) return false;
1193 return VectorList.Count == 3;
1196 bool isVecListFourDAllLanes() const {
1197 if (!isSingleSpacedVectorAllLanes()) return false;
1198 return VectorList.Count == 4;
1201 bool isVecListFourQAllLanes() const {
1202 if (!isDoubleSpacedVectorAllLanes()) return false;
1203 return VectorList.Count == 4;
1206 bool isSingleSpacedVectorIndexed() const {
1207 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1209 bool isDoubleSpacedVectorIndexed() const {
1210 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1212 bool isVecListOneDByteIndexed() const {
1213 if (!isSingleSpacedVectorIndexed()) return false;
1214 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1217 bool isVecListOneDHWordIndexed() const {
1218 if (!isSingleSpacedVectorIndexed()) return false;
1219 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1222 bool isVecListOneDWordIndexed() const {
1223 if (!isSingleSpacedVectorIndexed()) return false;
1224 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1227 bool isVecListTwoDByteIndexed() const {
1228 if (!isSingleSpacedVectorIndexed()) return false;
1229 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1232 bool isVecListTwoDHWordIndexed() const {
1233 if (!isSingleSpacedVectorIndexed()) return false;
1234 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1237 bool isVecListTwoQWordIndexed() const {
1238 if (!isDoubleSpacedVectorIndexed()) return false;
1239 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1242 bool isVecListTwoQHWordIndexed() const {
1243 if (!isDoubleSpacedVectorIndexed()) return false;
1244 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1247 bool isVecListTwoDWordIndexed() const {
1248 if (!isSingleSpacedVectorIndexed()) return false;
1249 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1252 bool isVecListThreeDByteIndexed() const {
1253 if (!isSingleSpacedVectorIndexed()) return false;
1254 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1257 bool isVecListThreeDHWordIndexed() const {
1258 if (!isSingleSpacedVectorIndexed()) return false;
1259 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1262 bool isVecListThreeQWordIndexed() const {
1263 if (!isDoubleSpacedVectorIndexed()) return false;
1264 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1267 bool isVecListThreeQHWordIndexed() const {
1268 if (!isDoubleSpacedVectorIndexed()) return false;
1269 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1272 bool isVecListThreeDWordIndexed() const {
1273 if (!isSingleSpacedVectorIndexed()) return false;
1274 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1277 bool isVecListFourDByteIndexed() const {
1278 if (!isSingleSpacedVectorIndexed()) return false;
1279 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1282 bool isVecListFourDHWordIndexed() const {
1283 if (!isSingleSpacedVectorIndexed()) return false;
1284 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1287 bool isVecListFourQWordIndexed() const {
1288 if (!isDoubleSpacedVectorIndexed()) return false;
1289 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1292 bool isVecListFourQHWordIndexed() const {
1293 if (!isDoubleSpacedVectorIndexed()) return false;
1294 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1297 bool isVecListFourDWordIndexed() const {
1298 if (!isSingleSpacedVectorIndexed()) return false;
1299 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1302 bool isVectorIndex8() const {
1303 if (Kind != k_VectorIndex) return false;
1304 return VectorIndex.Val < 8;
1306 bool isVectorIndex16() const {
1307 if (Kind != k_VectorIndex) return false;
1308 return VectorIndex.Val < 4;
1310 bool isVectorIndex32() const {
1311 if (Kind != k_VectorIndex) return false;
1312 return VectorIndex.Val < 2;
1315 bool isNEONi8splat() const {
1316 if (!isImm()) return false;
1317 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1318 // Must be a constant.
1319 if (!CE) return false;
1320 int64_t Value = CE->getValue();
1321 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1323 return Value >= 0 && Value < 256;
1326 bool isNEONi16splat() const {
1327 if (!isImm()) return false;
1328 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1329 // Must be a constant.
1330 if (!CE) return false;
1331 int64_t Value = CE->getValue();
1332 // i16 value in the range [0,255] or [0x0100, 0xff00]
1333 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1336 bool isNEONi32splat() const {
1337 if (!isImm()) return false;
1338 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1339 // Must be a constant.
1340 if (!CE) return false;
1341 int64_t Value = CE->getValue();
1342 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1343 return (Value >= 0 && Value < 256) ||
1344 (Value >= 0x0100 && Value <= 0xff00) ||
1345 (Value >= 0x010000 && Value <= 0xff0000) ||
1346 (Value >= 0x01000000 && Value <= 0xff000000);
1349 bool isNEONi32vmov() const {
1350 if (!isImm()) return false;
1351 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1352 // Must be a constant.
1353 if (!CE) return false;
1354 int64_t Value = CE->getValue();
1355 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1356 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1357 return (Value >= 0 && Value < 256) ||
1358 (Value >= 0x0100 && Value <= 0xff00) ||
1359 (Value >= 0x010000 && Value <= 0xff0000) ||
1360 (Value >= 0x01000000 && Value <= 0xff000000) ||
1361 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1362 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1364 bool isNEONi32vmovNeg() const {
1365 if (!isImm()) return false;
1366 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1367 // Must be a constant.
1368 if (!CE) return false;
1369 int64_t Value = ~CE->getValue();
1370 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1371 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1372 return (Value >= 0 && Value < 256) ||
1373 (Value >= 0x0100 && Value <= 0xff00) ||
1374 (Value >= 0x010000 && Value <= 0xff0000) ||
1375 (Value >= 0x01000000 && Value <= 0xff000000) ||
1376 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1377 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1380 bool isNEONi64splat() const {
1381 if (!isImm()) return false;
1382 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1383 // Must be a constant.
1384 if (!CE) return false;
1385 uint64_t Value = CE->getValue();
1386 // i64 value with each byte being either 0 or 0xff.
1387 for (unsigned i = 0; i < 8; ++i)
1388 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1392 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1393 // Add as immediates when possible. Null MCExpr = 0.
1395 Inst.addOperand(MCOperand::CreateImm(0));
1396 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1397 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1399 Inst.addOperand(MCOperand::CreateExpr(Expr));
1402 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1403 assert(N == 2 && "Invalid number of operands!");
1404 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1405 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1406 Inst.addOperand(MCOperand::CreateReg(RegNum));
1409 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1410 assert(N == 1 && "Invalid number of operands!");
1411 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1414 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1415 assert(N == 1 && "Invalid number of operands!");
1416 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1419 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1420 assert(N == 1 && "Invalid number of operands!");
1421 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1424 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1425 assert(N == 1 && "Invalid number of operands!");
1426 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1429 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1430 assert(N == 1 && "Invalid number of operands!");
1431 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1434 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1435 assert(N == 1 && "Invalid number of operands!");
1436 Inst.addOperand(MCOperand::CreateReg(getReg()));
1439 void addRegOperands(MCInst &Inst, unsigned N) const {
1440 assert(N == 1 && "Invalid number of operands!");
1441 Inst.addOperand(MCOperand::CreateReg(getReg()));
1444 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1445 assert(N == 3 && "Invalid number of operands!");
1446 assert(isRegShiftedReg() &&
1447 "addRegShiftedRegOperands() on non RegShiftedReg!");
1448 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1449 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1450 Inst.addOperand(MCOperand::CreateImm(
1451 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1454 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1455 assert(N == 2 && "Invalid number of operands!");
1456 assert(isRegShiftedImm() &&
1457 "addRegShiftedImmOperands() on non RegShiftedImm!");
1458 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1459 // Shift of #32 is encoded as 0 where permitted
1460 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1461 Inst.addOperand(MCOperand::CreateImm(
1462 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1465 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1466 assert(N == 1 && "Invalid number of operands!");
1467 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1471 void addRegListOperands(MCInst &Inst, unsigned N) const {
1472 assert(N == 1 && "Invalid number of operands!");
1473 const SmallVectorImpl<unsigned> &RegList = getRegList();
1474 for (SmallVectorImpl<unsigned>::const_iterator
1475 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1476 Inst.addOperand(MCOperand::CreateReg(*I));
1479 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1480 addRegListOperands(Inst, N);
1483 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1484 addRegListOperands(Inst, N);
1487 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1488 assert(N == 1 && "Invalid number of operands!");
1489 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1490 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1493 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1494 assert(N == 1 && "Invalid number of operands!");
1495 // Munge the lsb/width into a bitfield mask.
1496 unsigned lsb = Bitfield.LSB;
1497 unsigned width = Bitfield.Width;
1498 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1499 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1500 (32 - (lsb + width)));
1501 Inst.addOperand(MCOperand::CreateImm(Mask));
1504 void addImmOperands(MCInst &Inst, unsigned N) const {
1505 assert(N == 1 && "Invalid number of operands!");
1506 addExpr(Inst, getImm());
1509 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1510 assert(N == 1 && "Invalid number of operands!");
1511 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1512 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1515 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1516 assert(N == 1 && "Invalid number of operands!");
1517 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1518 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1521 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1522 assert(N == 1 && "Invalid number of operands!");
1523 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1524 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1525 Inst.addOperand(MCOperand::CreateImm(Val));
1528 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1529 assert(N == 1 && "Invalid number of operands!");
1530 // FIXME: We really want to scale the value here, but the LDRD/STRD
1531 // instruction don't encode operands that way yet.
1532 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1533 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1536 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1537 assert(N == 1 && "Invalid number of operands!");
1538 // The immediate is scaled by four in the encoding and is stored
1539 // in the MCInst as such. Lop off the low two bits here.
1540 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1541 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1544 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1545 assert(N == 1 && "Invalid number of operands!");
1546 // The immediate is scaled by four in the encoding and is stored
1547 // in the MCInst as such. Lop off the low two bits here.
1548 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1549 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1552 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1553 assert(N == 1 && "Invalid number of operands!");
1554 // The immediate is scaled by four in the encoding and is stored
1555 // in the MCInst as such. Lop off the low two bits here.
1556 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1557 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1560 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1561 assert(N == 1 && "Invalid number of operands!");
1562 // The constant encodes as the immediate-1, and we store in the instruction
1563 // the bits as encoded, so subtract off one here.
1564 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1565 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1568 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1569 assert(N == 1 && "Invalid number of operands!");
1570 // The constant encodes as the immediate-1, and we store in the instruction
1571 // the bits as encoded, so subtract off one here.
1572 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1573 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1576 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1577 assert(N == 1 && "Invalid number of operands!");
1578 // The constant encodes as the immediate, except for 32, which encodes as
1580 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1581 unsigned Imm = CE->getValue();
1582 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1585 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1586 assert(N == 1 && "Invalid number of operands!");
1587 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1588 // the instruction as well.
1589 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1590 int Val = CE->getValue();
1591 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1594 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1595 assert(N == 1 && "Invalid number of operands!");
1596 // The operand is actually a t2_so_imm, but we have its bitwise
1597 // negation in the assembly source, so twiddle it here.
1598 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1599 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1602 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1603 assert(N == 1 && "Invalid number of operands!");
1604 // The operand is actually a t2_so_imm, but we have its
1605 // negation in the assembly source, so twiddle it here.
1606 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1607 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1610 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1611 assert(N == 1 && "Invalid number of operands!");
1612 // The operand is actually an imm0_4095, but we have its
1613 // negation in the assembly source, so twiddle it here.
1614 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1615 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1618 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1619 assert(N == 1 && "Invalid number of operands!");
1620 // The operand is actually a so_imm, but we have its bitwise
1621 // negation in the assembly source, so twiddle it here.
1622 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1623 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1626 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1627 assert(N == 1 && "Invalid number of operands!");
1628 // The operand is actually a so_imm, but we have its
1629 // negation in the assembly source, so twiddle it here.
1630 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1631 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1634 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1635 assert(N == 1 && "Invalid number of operands!");
1636 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1639 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1640 assert(N == 1 && "Invalid number of operands!");
1641 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1644 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1645 assert(N == 1 && "Invalid number of operands!");
1646 int32_t Imm = Memory.OffsetImm->getValue();
1647 // FIXME: Handle #-0
1648 if (Imm == INT32_MIN) Imm = 0;
1649 Inst.addOperand(MCOperand::CreateImm(Imm));
1652 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1653 assert(N == 1 && "Invalid number of operands!");
1654 assert(isImm() && "Not an immediate!");
1656 // If we have an immediate that's not a constant, treat it as a label
1657 // reference needing a fixup.
1658 if (!isa<MCConstantExpr>(getImm())) {
1659 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1663 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1664 int Val = CE->getValue();
1665 Inst.addOperand(MCOperand::CreateImm(Val));
1668 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1669 assert(N == 2 && "Invalid number of operands!");
1670 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1671 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1674 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1675 assert(N == 3 && "Invalid number of operands!");
1676 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1677 if (!Memory.OffsetRegNum) {
1678 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1679 // Special case for #-0
1680 if (Val == INT32_MIN) Val = 0;
1681 if (Val < 0) Val = -Val;
1682 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1684 // For register offset, we encode the shift type and negation flag
1686 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1687 Memory.ShiftImm, Memory.ShiftType);
1689 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1690 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1691 Inst.addOperand(MCOperand::CreateImm(Val));
1694 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1695 assert(N == 2 && "Invalid number of operands!");
1696 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1697 assert(CE && "non-constant AM2OffsetImm operand!");
1698 int32_t Val = CE->getValue();
1699 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1700 // Special case for #-0
1701 if (Val == INT32_MIN) Val = 0;
1702 if (Val < 0) Val = -Val;
1703 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1704 Inst.addOperand(MCOperand::CreateReg(0));
1705 Inst.addOperand(MCOperand::CreateImm(Val));
1708 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1709 assert(N == 3 && "Invalid number of operands!");
1710 // If we have an immediate that's not a constant, treat it as a label
1711 // reference needing a fixup. If it is a constant, it's something else
1712 // and we reject it.
1714 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1715 Inst.addOperand(MCOperand::CreateReg(0));
1716 Inst.addOperand(MCOperand::CreateImm(0));
1720 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1721 if (!Memory.OffsetRegNum) {
1722 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1723 // Special case for #-0
1724 if (Val == INT32_MIN) Val = 0;
1725 if (Val < 0) Val = -Val;
1726 Val = ARM_AM::getAM3Opc(AddSub, Val);
1728 // For register offset, we encode the shift type and negation flag
1730 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1732 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1733 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1734 Inst.addOperand(MCOperand::CreateImm(Val));
1737 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1738 assert(N == 2 && "Invalid number of operands!");
1739 if (Kind == k_PostIndexRegister) {
1741 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1742 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1743 Inst.addOperand(MCOperand::CreateImm(Val));
1748 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1749 int32_t Val = CE->getValue();
1750 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1751 // Special case for #-0
1752 if (Val == INT32_MIN) Val = 0;
1753 if (Val < 0) Val = -Val;
1754 Val = ARM_AM::getAM3Opc(AddSub, Val);
1755 Inst.addOperand(MCOperand::CreateReg(0));
1756 Inst.addOperand(MCOperand::CreateImm(Val));
1759 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1760 assert(N == 2 && "Invalid number of operands!");
1761 // If we have an immediate that's not a constant, treat it as a label
1762 // reference needing a fixup. If it is a constant, it's something else
1763 // and we reject it.
1765 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1766 Inst.addOperand(MCOperand::CreateImm(0));
1770 // The lower two bits are always zero and as such are not encoded.
1771 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1772 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1773 // Special case for #-0
1774 if (Val == INT32_MIN) Val = 0;
1775 if (Val < 0) Val = -Val;
1776 Val = ARM_AM::getAM5Opc(AddSub, Val);
1777 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1778 Inst.addOperand(MCOperand::CreateImm(Val));
1781 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1782 assert(N == 2 && "Invalid number of operands!");
1783 // If we have an immediate that's not a constant, treat it as a label
1784 // reference needing a fixup. If it is a constant, it's something else
1785 // and we reject it.
1787 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1788 Inst.addOperand(MCOperand::CreateImm(0));
1792 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1793 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1794 Inst.addOperand(MCOperand::CreateImm(Val));
1797 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1798 assert(N == 2 && "Invalid number of operands!");
1799 // The lower two bits are always zero and as such are not encoded.
1800 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1801 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1802 Inst.addOperand(MCOperand::CreateImm(Val));
1805 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1806 assert(N == 2 && "Invalid number of operands!");
1807 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1808 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1809 Inst.addOperand(MCOperand::CreateImm(Val));
1812 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1813 addMemImm8OffsetOperands(Inst, N);
1816 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1817 addMemImm8OffsetOperands(Inst, N);
1820 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1821 assert(N == 2 && "Invalid number of operands!");
1822 // If this is an immediate, it's a label reference.
1824 addExpr(Inst, getImm());
1825 Inst.addOperand(MCOperand::CreateImm(0));
1829 // Otherwise, it's a normal memory reg+offset.
1830 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1831 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1832 Inst.addOperand(MCOperand::CreateImm(Val));
1835 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1836 assert(N == 2 && "Invalid number of operands!");
1837 // If this is an immediate, it's a label reference.
1839 addExpr(Inst, getImm());
1840 Inst.addOperand(MCOperand::CreateImm(0));
1844 // Otherwise, it's a normal memory reg+offset.
1845 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1846 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1847 Inst.addOperand(MCOperand::CreateImm(Val));
1850 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1851 assert(N == 2 && "Invalid number of operands!");
1852 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1853 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1856 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1857 assert(N == 2 && "Invalid number of operands!");
1858 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1859 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1862 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1863 assert(N == 3 && "Invalid number of operands!");
1865 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1866 Memory.ShiftImm, Memory.ShiftType);
1867 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1868 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1869 Inst.addOperand(MCOperand::CreateImm(Val));
1872 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1873 assert(N == 3 && "Invalid number of operands!");
1874 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1875 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1876 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1879 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1880 assert(N == 2 && "Invalid number of operands!");
1881 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1882 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1885 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1886 assert(N == 2 && "Invalid number of operands!");
1887 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1888 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1889 Inst.addOperand(MCOperand::CreateImm(Val));
1892 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1893 assert(N == 2 && "Invalid number of operands!");
1894 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1895 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1896 Inst.addOperand(MCOperand::CreateImm(Val));
1899 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1900 assert(N == 2 && "Invalid number of operands!");
1901 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1902 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1903 Inst.addOperand(MCOperand::CreateImm(Val));
1906 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1907 assert(N == 2 && "Invalid number of operands!");
1908 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1909 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1910 Inst.addOperand(MCOperand::CreateImm(Val));
1913 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1914 assert(N == 1 && "Invalid number of operands!");
1915 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1916 assert(CE && "non-constant post-idx-imm8 operand!");
1917 int Imm = CE->getValue();
1918 bool isAdd = Imm >= 0;
1919 if (Imm == INT32_MIN) Imm = 0;
1920 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1921 Inst.addOperand(MCOperand::CreateImm(Imm));
1924 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1925 assert(N == 1 && "Invalid number of operands!");
1926 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1927 assert(CE && "non-constant post-idx-imm8s4 operand!");
1928 int Imm = CE->getValue();
1929 bool isAdd = Imm >= 0;
1930 if (Imm == INT32_MIN) Imm = 0;
1931 // Immediate is scaled by 4.
1932 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1933 Inst.addOperand(MCOperand::CreateImm(Imm));
1936 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1937 assert(N == 2 && "Invalid number of operands!");
1938 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1939 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1942 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1943 assert(N == 2 && "Invalid number of operands!");
1944 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1945 // The sign, shift type, and shift amount are encoded in a single operand
1946 // using the AM2 encoding helpers.
1947 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1948 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1949 PostIdxReg.ShiftTy);
1950 Inst.addOperand(MCOperand::CreateImm(Imm));
1953 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1954 assert(N == 1 && "Invalid number of operands!");
1955 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1958 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1959 assert(N == 1 && "Invalid number of operands!");
1960 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1963 void addVecListOperands(MCInst &Inst, unsigned N) const {
1964 assert(N == 1 && "Invalid number of operands!");
1965 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1968 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1969 assert(N == 2 && "Invalid number of operands!");
1970 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1971 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1974 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1975 assert(N == 1 && "Invalid number of operands!");
1976 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1979 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1980 assert(N == 1 && "Invalid number of operands!");
1981 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1984 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1985 assert(N == 1 && "Invalid number of operands!");
1986 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1989 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1990 assert(N == 1 && "Invalid number of operands!");
1991 // The immediate encodes the type of constant as well as the value.
1992 // Mask in that this is an i8 splat.
1993 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1994 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1997 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1998 assert(N == 1 && "Invalid number of operands!");
1999 // The immediate encodes the type of constant as well as the value.
2000 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2001 unsigned Value = CE->getValue();
2003 Value = (Value >> 8) | 0xa00;
2006 Inst.addOperand(MCOperand::CreateImm(Value));
2009 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2010 assert(N == 1 && "Invalid number of operands!");
2011 // The immediate encodes the type of constant as well as the value.
2012 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2013 unsigned Value = CE->getValue();
2014 if (Value >= 256 && Value <= 0xff00)
2015 Value = (Value >> 8) | 0x200;
2016 else if (Value > 0xffff && Value <= 0xff0000)
2017 Value = (Value >> 16) | 0x400;
2018 else if (Value > 0xffffff)
2019 Value = (Value >> 24) | 0x600;
2020 Inst.addOperand(MCOperand::CreateImm(Value));
2023 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2024 assert(N == 1 && "Invalid number of operands!");
2025 // The immediate encodes the type of constant as well as the value.
2026 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2027 unsigned Value = CE->getValue();
2028 if (Value >= 256 && Value <= 0xffff)
2029 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2030 else if (Value > 0xffff && Value <= 0xffffff)
2031 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2032 else if (Value > 0xffffff)
2033 Value = (Value >> 24) | 0x600;
2034 Inst.addOperand(MCOperand::CreateImm(Value));
2037 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2038 assert(N == 1 && "Invalid number of operands!");
2039 // The immediate encodes the type of constant as well as the value.
2040 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2041 unsigned Value = ~CE->getValue();
2042 if (Value >= 256 && Value <= 0xffff)
2043 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2044 else if (Value > 0xffff && Value <= 0xffffff)
2045 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2046 else if (Value > 0xffffff)
2047 Value = (Value >> 24) | 0x600;
2048 Inst.addOperand(MCOperand::CreateImm(Value));
2051 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2052 assert(N == 1 && "Invalid number of operands!");
2053 // The immediate encodes the type of constant as well as the value.
2054 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2055 uint64_t Value = CE->getValue();
2057 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2058 Imm |= (Value & 1) << i;
2060 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2063 virtual void print(raw_ostream &OS) const;
2065 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2066 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2067 Op->ITMask.Mask = Mask;
2073 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2074 ARMOperand *Op = new ARMOperand(k_CondCode);
2081 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2082 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2083 Op->Cop.Val = CopVal;
2089 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2090 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2091 Op->Cop.Val = CopVal;
2097 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2098 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2105 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2106 ARMOperand *Op = new ARMOperand(k_CCOut);
2107 Op->Reg.RegNum = RegNum;
2113 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2114 ARMOperand *Op = new ARMOperand(k_Token);
2115 Op->Tok.Data = Str.data();
2116 Op->Tok.Length = Str.size();
2122 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2123 ARMOperand *Op = new ARMOperand(k_Register);
2124 Op->Reg.RegNum = RegNum;
2130 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2135 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2136 Op->RegShiftedReg.ShiftTy = ShTy;
2137 Op->RegShiftedReg.SrcReg = SrcReg;
2138 Op->RegShiftedReg.ShiftReg = ShiftReg;
2139 Op->RegShiftedReg.ShiftImm = ShiftImm;
2145 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2149 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2150 Op->RegShiftedImm.ShiftTy = ShTy;
2151 Op->RegShiftedImm.SrcReg = SrcReg;
2152 Op->RegShiftedImm.ShiftImm = ShiftImm;
2158 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2160 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2161 Op->ShifterImm.isASR = isASR;
2162 Op->ShifterImm.Imm = Imm;
2168 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2169 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2170 Op->RotImm.Imm = Imm;
2176 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2178 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2179 Op->Bitfield.LSB = LSB;
2180 Op->Bitfield.Width = Width;
2187 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
2188 SMLoc StartLoc, SMLoc EndLoc) {
2189 KindTy Kind = k_RegisterList;
2191 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2192 Kind = k_DPRRegisterList;
2193 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2194 contains(Regs.front().first))
2195 Kind = k_SPRRegisterList;
2197 ARMOperand *Op = new ARMOperand(Kind);
2198 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
2199 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2200 Op->Registers.push_back(I->first);
2201 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
2202 Op->StartLoc = StartLoc;
2203 Op->EndLoc = EndLoc;
2207 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2208 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2209 ARMOperand *Op = new ARMOperand(k_VectorList);
2210 Op->VectorList.RegNum = RegNum;
2211 Op->VectorList.Count = Count;
2212 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2218 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2219 bool isDoubleSpaced,
2221 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2222 Op->VectorList.RegNum = RegNum;
2223 Op->VectorList.Count = Count;
2224 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2230 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2232 bool isDoubleSpaced,
2234 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2235 Op->VectorList.RegNum = RegNum;
2236 Op->VectorList.Count = Count;
2237 Op->VectorList.LaneIndex = Index;
2238 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2244 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2246 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2247 Op->VectorIndex.Val = Idx;
2253 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2254 ARMOperand *Op = new ARMOperand(k_Immediate);
2261 static ARMOperand *CreateMem(unsigned BaseRegNum,
2262 const MCConstantExpr *OffsetImm,
2263 unsigned OffsetRegNum,
2264 ARM_AM::ShiftOpc ShiftType,
2269 ARMOperand *Op = new ARMOperand(k_Memory);
2270 Op->Memory.BaseRegNum = BaseRegNum;
2271 Op->Memory.OffsetImm = OffsetImm;
2272 Op->Memory.OffsetRegNum = OffsetRegNum;
2273 Op->Memory.ShiftType = ShiftType;
2274 Op->Memory.ShiftImm = ShiftImm;
2275 Op->Memory.Alignment = Alignment;
2276 Op->Memory.isNegative = isNegative;
2282 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2283 ARM_AM::ShiftOpc ShiftTy,
2286 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2287 Op->PostIdxReg.RegNum = RegNum;
2288 Op->PostIdxReg.isAdd = isAdd;
2289 Op->PostIdxReg.ShiftTy = ShiftTy;
2290 Op->PostIdxReg.ShiftImm = ShiftImm;
2296 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2297 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2298 Op->MBOpt.Val = Opt;
2304 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2305 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2306 Op->IFlags.Val = IFlags;
2312 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2313 ARMOperand *Op = new ARMOperand(k_MSRMask);
2314 Op->MMask.Val = MMask;
2321 } // end anonymous namespace.
2323 void ARMOperand::print(raw_ostream &OS) const {
2326 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2329 OS << "<ccout " << getReg() << ">";
2331 case k_ITCondMask: {
2332 static const char *const MaskStr[] = {
2333 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2334 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2336 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2337 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2341 OS << "<coprocessor number: " << getCoproc() << ">";
2344 OS << "<coprocessor register: " << getCoproc() << ">";
2346 case k_CoprocOption:
2347 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2350 OS << "<mask: " << getMSRMask() << ">";
2353 getImm()->print(OS);
2355 case k_MemBarrierOpt:
2356 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2360 << " base:" << Memory.BaseRegNum;
2363 case k_PostIndexRegister:
2364 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2365 << PostIdxReg.RegNum;
2366 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2367 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2368 << PostIdxReg.ShiftImm;
2371 case k_ProcIFlags: {
2372 OS << "<ARM_PROC::";
2373 unsigned IFlags = getProcIFlags();
2374 for (int i=2; i >= 0; --i)
2375 if (IFlags & (1 << i))
2376 OS << ARM_PROC::IFlagsToString(1 << i);
2381 OS << "<register " << getReg() << ">";
2383 case k_ShifterImmediate:
2384 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2385 << " #" << ShifterImm.Imm << ">";
2387 case k_ShiftedRegister:
2388 OS << "<so_reg_reg "
2389 << RegShiftedReg.SrcReg << " "
2390 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2391 << " " << RegShiftedReg.ShiftReg << ">";
2393 case k_ShiftedImmediate:
2394 OS << "<so_reg_imm "
2395 << RegShiftedImm.SrcReg << " "
2396 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2397 << " #" << RegShiftedImm.ShiftImm << ">";
2399 case k_RotateImmediate:
2400 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2402 case k_BitfieldDescriptor:
2403 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2404 << ", width: " << Bitfield.Width << ">";
2406 case k_RegisterList:
2407 case k_DPRRegisterList:
2408 case k_SPRRegisterList: {
2409 OS << "<register_list ";
2411 const SmallVectorImpl<unsigned> &RegList = getRegList();
2412 for (SmallVectorImpl<unsigned>::const_iterator
2413 I = RegList.begin(), E = RegList.end(); I != E; ) {
2415 if (++I < E) OS << ", ";
2422 OS << "<vector_list " << VectorList.Count << " * "
2423 << VectorList.RegNum << ">";
2425 case k_VectorListAllLanes:
2426 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2427 << VectorList.RegNum << ">";
2429 case k_VectorListIndexed:
2430 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2431 << VectorList.Count << " * " << VectorList.RegNum << ">";
2434 OS << "'" << getToken() << "'";
2437 OS << "<vectorindex " << getVectorIndex() << ">";
2442 /// @name Auto-generated Match Functions
2445 static unsigned MatchRegisterName(StringRef Name);
2449 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2450 SMLoc &StartLoc, SMLoc &EndLoc) {
2451 StartLoc = Parser.getTok().getLoc();
2452 RegNo = tryParseRegister();
2453 EndLoc = Parser.getTok().getLoc();
2455 return (RegNo == (unsigned)-1);
2458 /// Try to parse a register name. The token must be an Identifier when called,
2459 /// and if it is a register name the token is eaten and the register number is
2460 /// returned. Otherwise return -1.
2462 int ARMAsmParser::tryParseRegister() {
2463 const AsmToken &Tok = Parser.getTok();
2464 if (Tok.isNot(AsmToken::Identifier)) return -1;
2466 std::string lowerCase = Tok.getString().lower();
2467 unsigned RegNum = MatchRegisterName(lowerCase);
2469 RegNum = StringSwitch<unsigned>(lowerCase)
2470 .Case("r13", ARM::SP)
2471 .Case("r14", ARM::LR)
2472 .Case("r15", ARM::PC)
2473 .Case("ip", ARM::R12)
2474 // Additional register name aliases for 'gas' compatibility.
2475 .Case("a1", ARM::R0)
2476 .Case("a2", ARM::R1)
2477 .Case("a3", ARM::R2)
2478 .Case("a4", ARM::R3)
2479 .Case("v1", ARM::R4)
2480 .Case("v2", ARM::R5)
2481 .Case("v3", ARM::R6)
2482 .Case("v4", ARM::R7)
2483 .Case("v5", ARM::R8)
2484 .Case("v6", ARM::R9)
2485 .Case("v7", ARM::R10)
2486 .Case("v8", ARM::R11)
2487 .Case("sb", ARM::R9)
2488 .Case("sl", ARM::R10)
2489 .Case("fp", ARM::R11)
2493 // Check for aliases registered via .req. Canonicalize to lower case.
2494 // That's more consistent since register names are case insensitive, and
2495 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2496 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2497 // If no match, return failure.
2498 if (Entry == RegisterReqs.end())
2500 Parser.Lex(); // Eat identifier token.
2501 return Entry->getValue();
2504 Parser.Lex(); // Eat identifier token.
2509 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2510 // If a recoverable error occurs, return 1. If an irrecoverable error
2511 // occurs, return -1. An irrecoverable error is one where tokens have been
2512 // consumed in the process of trying to parse the shifter (i.e., when it is
2513 // indeed a shifter operand, but malformed).
2514 int ARMAsmParser::tryParseShiftRegister(
2515 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2516 SMLoc S = Parser.getTok().getLoc();
2517 const AsmToken &Tok = Parser.getTok();
2518 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2520 std::string lowerCase = Tok.getString().lower();
2521 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2522 .Case("asl", ARM_AM::lsl)
2523 .Case("lsl", ARM_AM::lsl)
2524 .Case("lsr", ARM_AM::lsr)
2525 .Case("asr", ARM_AM::asr)
2526 .Case("ror", ARM_AM::ror)
2527 .Case("rrx", ARM_AM::rrx)
2528 .Default(ARM_AM::no_shift);
2530 if (ShiftTy == ARM_AM::no_shift)
2533 Parser.Lex(); // Eat the operator.
2535 // The source register for the shift has already been added to the
2536 // operand list, so we need to pop it off and combine it into the shifted
2537 // register operand instead.
2538 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2539 if (!PrevOp->isReg())
2540 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2541 int SrcReg = PrevOp->getReg();
2544 if (ShiftTy == ARM_AM::rrx) {
2545 // RRX Doesn't have an explicit shift amount. The encoder expects
2546 // the shift register to be the same as the source register. Seems odd,
2550 // Figure out if this is shifted by a constant or a register (for non-RRX).
2551 if (Parser.getTok().is(AsmToken::Hash) ||
2552 Parser.getTok().is(AsmToken::Dollar)) {
2553 Parser.Lex(); // Eat hash.
2554 SMLoc ImmLoc = Parser.getTok().getLoc();
2555 const MCExpr *ShiftExpr = 0;
2556 if (getParser().ParseExpression(ShiftExpr)) {
2557 Error(ImmLoc, "invalid immediate shift value");
2560 // The expression must be evaluatable as an immediate.
2561 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2563 Error(ImmLoc, "invalid immediate shift value");
2566 // Range check the immediate.
2567 // lsl, ror: 0 <= imm <= 31
2568 // lsr, asr: 0 <= imm <= 32
2569 Imm = CE->getValue();
2571 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2572 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2573 Error(ImmLoc, "immediate shift value out of range");
2576 // shift by zero is a nop. Always send it through as lsl.
2577 // ('as' compatibility)
2579 ShiftTy = ARM_AM::lsl;
2580 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2581 ShiftReg = tryParseRegister();
2582 SMLoc L = Parser.getTok().getLoc();
2583 if (ShiftReg == -1) {
2584 Error (L, "expected immediate or register in shift operand");
2588 Error (Parser.getTok().getLoc(),
2589 "expected immediate or register in shift operand");
2594 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2595 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2597 S, Parser.getTok().getLoc()));
2599 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2600 S, Parser.getTok().getLoc()));
2606 /// Try to parse a register name. The token must be an Identifier when called.
2607 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2608 /// if there is a "writeback". 'true' if it's not a register.
2610 /// TODO this is likely to change to allow different register types and or to
2611 /// parse for a specific register type.
2613 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2614 SMLoc S = Parser.getTok().getLoc();
2615 int RegNo = tryParseRegister();
2619 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2621 const AsmToken &ExclaimTok = Parser.getTok();
2622 if (ExclaimTok.is(AsmToken::Exclaim)) {
2623 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2624 ExclaimTok.getLoc()));
2625 Parser.Lex(); // Eat exclaim token
2629 // Also check for an index operand. This is only legal for vector registers,
2630 // but that'll get caught OK in operand matching, so we don't need to
2631 // explicitly filter everything else out here.
2632 if (Parser.getTok().is(AsmToken::LBrac)) {
2633 SMLoc SIdx = Parser.getTok().getLoc();
2634 Parser.Lex(); // Eat left bracket token.
2636 const MCExpr *ImmVal;
2637 if (getParser().ParseExpression(ImmVal))
2639 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2641 return TokError("immediate value expected for vector index");
2643 SMLoc E = Parser.getTok().getLoc();
2644 if (Parser.getTok().isNot(AsmToken::RBrac))
2645 return Error(E, "']' expected");
2647 Parser.Lex(); // Eat right bracket token.
2649 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2657 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2658 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2660 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2661 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2663 switch (Name.size()) {
2666 if (Name[0] != CoprocOp)
2682 if (Name[0] != CoprocOp || Name[1] != '1')
2686 case '0': return 10;
2687 case '1': return 11;
2688 case '2': return 12;
2689 case '3': return 13;
2690 case '4': return 14;
2691 case '5': return 15;
2696 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2697 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2698 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2699 SMLoc S = Parser.getTok().getLoc();
2700 const AsmToken &Tok = Parser.getTok();
2701 if (!Tok.is(AsmToken::Identifier))
2702 return MatchOperand_NoMatch;
2703 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2704 .Case("eq", ARMCC::EQ)
2705 .Case("ne", ARMCC::NE)
2706 .Case("hs", ARMCC::HS)
2707 .Case("cs", ARMCC::HS)
2708 .Case("lo", ARMCC::LO)
2709 .Case("cc", ARMCC::LO)
2710 .Case("mi", ARMCC::MI)
2711 .Case("pl", ARMCC::PL)
2712 .Case("vs", ARMCC::VS)
2713 .Case("vc", ARMCC::VC)
2714 .Case("hi", ARMCC::HI)
2715 .Case("ls", ARMCC::LS)
2716 .Case("ge", ARMCC::GE)
2717 .Case("lt", ARMCC::LT)
2718 .Case("gt", ARMCC::GT)
2719 .Case("le", ARMCC::LE)
2720 .Case("al", ARMCC::AL)
2723 return MatchOperand_NoMatch;
2724 Parser.Lex(); // Eat the token.
2726 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2728 return MatchOperand_Success;
2731 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2732 /// token must be an Identifier when called, and if it is a coprocessor
2733 /// number, the token is eaten and the operand is added to the operand list.
2734 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2735 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2736 SMLoc S = Parser.getTok().getLoc();
2737 const AsmToken &Tok = Parser.getTok();
2738 if (Tok.isNot(AsmToken::Identifier))
2739 return MatchOperand_NoMatch;
2741 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2743 return MatchOperand_NoMatch;
2745 Parser.Lex(); // Eat identifier token.
2746 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2747 return MatchOperand_Success;
2750 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2751 /// token must be an Identifier when called, and if it is a coprocessor
2752 /// number, the token is eaten and the operand is added to the operand list.
2753 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2754 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2755 SMLoc S = Parser.getTok().getLoc();
2756 const AsmToken &Tok = Parser.getTok();
2757 if (Tok.isNot(AsmToken::Identifier))
2758 return MatchOperand_NoMatch;
2760 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2762 return MatchOperand_NoMatch;
2764 Parser.Lex(); // Eat identifier token.
2765 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2766 return MatchOperand_Success;
2769 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2770 /// coproc_option : '{' imm0_255 '}'
2771 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2772 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2773 SMLoc S = Parser.getTok().getLoc();
2775 // If this isn't a '{', this isn't a coprocessor immediate operand.
2776 if (Parser.getTok().isNot(AsmToken::LCurly))
2777 return MatchOperand_NoMatch;
2778 Parser.Lex(); // Eat the '{'
2781 SMLoc Loc = Parser.getTok().getLoc();
2782 if (getParser().ParseExpression(Expr)) {
2783 Error(Loc, "illegal expression");
2784 return MatchOperand_ParseFail;
2786 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2787 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2788 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2789 return MatchOperand_ParseFail;
2791 int Val = CE->getValue();
2793 // Check for and consume the closing '}'
2794 if (Parser.getTok().isNot(AsmToken::RCurly))
2795 return MatchOperand_ParseFail;
2796 SMLoc E = Parser.getTok().getLoc();
2797 Parser.Lex(); // Eat the '}'
2799 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2800 return MatchOperand_Success;
2803 // For register list parsing, we need to map from raw GPR register numbering
2804 // to the enumeration values. The enumeration values aren't sorted by
2805 // register number due to our using "sp", "lr" and "pc" as canonical names.
2806 static unsigned getNextRegister(unsigned Reg) {
2807 // If this is a GPR, we need to do it manually, otherwise we can rely
2808 // on the sort ordering of the enumeration since the other reg-classes
2810 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2813 default: llvm_unreachable("Invalid GPR number!");
2814 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2815 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2816 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2817 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2818 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2819 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2820 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2821 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2825 // Return the low-subreg of a given Q register.
2826 static unsigned getDRegFromQReg(unsigned QReg) {
2828 default: llvm_unreachable("expected a Q register!");
2829 case ARM::Q0: return ARM::D0;
2830 case ARM::Q1: return ARM::D2;
2831 case ARM::Q2: return ARM::D4;
2832 case ARM::Q3: return ARM::D6;
2833 case ARM::Q4: return ARM::D8;
2834 case ARM::Q5: return ARM::D10;
2835 case ARM::Q6: return ARM::D12;
2836 case ARM::Q7: return ARM::D14;
2837 case ARM::Q8: return ARM::D16;
2838 case ARM::Q9: return ARM::D18;
2839 case ARM::Q10: return ARM::D20;
2840 case ARM::Q11: return ARM::D22;
2841 case ARM::Q12: return ARM::D24;
2842 case ARM::Q13: return ARM::D26;
2843 case ARM::Q14: return ARM::D28;
2844 case ARM::Q15: return ARM::D30;
2848 /// Parse a register list.
2850 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2851 assert(Parser.getTok().is(AsmToken::LCurly) &&
2852 "Token is not a Left Curly Brace");
2853 SMLoc S = Parser.getTok().getLoc();
2854 Parser.Lex(); // Eat '{' token.
2855 SMLoc RegLoc = Parser.getTok().getLoc();
2857 // Check the first register in the list to see what register class
2858 // this is a list of.
2859 int Reg = tryParseRegister();
2861 return Error(RegLoc, "register expected");
2863 // The reglist instructions have at most 16 registers, so reserve
2864 // space for that many.
2865 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2867 // Allow Q regs and just interpret them as the two D sub-registers.
2868 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2869 Reg = getDRegFromQReg(Reg);
2870 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2873 const MCRegisterClass *RC;
2874 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2875 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2876 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2877 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2878 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2879 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2881 return Error(RegLoc, "invalid register in register list");
2883 // Store the register.
2884 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2886 // This starts immediately after the first register token in the list,
2887 // so we can see either a comma or a minus (range separator) as a legal
2889 while (Parser.getTok().is(AsmToken::Comma) ||
2890 Parser.getTok().is(AsmToken::Minus)) {
2891 if (Parser.getTok().is(AsmToken::Minus)) {
2892 Parser.Lex(); // Eat the minus.
2893 SMLoc EndLoc = Parser.getTok().getLoc();
2894 int EndReg = tryParseRegister();
2896 return Error(EndLoc, "register expected");
2897 // Allow Q regs and just interpret them as the two D sub-registers.
2898 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2899 EndReg = getDRegFromQReg(EndReg) + 1;
2900 // If the register is the same as the start reg, there's nothing
2904 // The register must be in the same register class as the first.
2905 if (!RC->contains(EndReg))
2906 return Error(EndLoc, "invalid register in register list");
2907 // Ranges must go from low to high.
2908 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
2909 return Error(EndLoc, "bad range in register list");
2911 // Add all the registers in the range to the register list.
2912 while (Reg != EndReg) {
2913 Reg = getNextRegister(Reg);
2914 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2918 Parser.Lex(); // Eat the comma.
2919 RegLoc = Parser.getTok().getLoc();
2921 const AsmToken RegTok = Parser.getTok();
2922 Reg = tryParseRegister();
2924 return Error(RegLoc, "register expected");
2925 // Allow Q regs and just interpret them as the two D sub-registers.
2926 bool isQReg = false;
2927 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2928 Reg = getDRegFromQReg(Reg);
2931 // The register must be in the same register class as the first.
2932 if (!RC->contains(Reg))
2933 return Error(RegLoc, "invalid register in register list");
2934 // List must be monotonically increasing.
2935 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
2936 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2937 Warning(RegLoc, "register list not in ascending order");
2939 return Error(RegLoc, "register list not in ascending order");
2941 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
2942 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2943 ") in register list");
2946 // VFP register lists must also be contiguous.
2947 // It's OK to use the enumeration values directly here rather, as the
2948 // VFP register classes have the enum sorted properly.
2949 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2951 return Error(RegLoc, "non-contiguous register range");
2952 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2954 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2957 SMLoc E = Parser.getTok().getLoc();
2958 if (Parser.getTok().isNot(AsmToken::RCurly))
2959 return Error(E, "'}' expected");
2960 Parser.Lex(); // Eat '}' token.
2962 // Push the register list operand.
2963 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2965 // The ARM system instruction variants for LDM/STM have a '^' token here.
2966 if (Parser.getTok().is(AsmToken::Caret)) {
2967 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
2968 Parser.Lex(); // Eat '^' token.
2974 // Helper function to parse the lane index for vector lists.
2975 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2976 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) {
2977 Index = 0; // Always return a defined index value.
2978 if (Parser.getTok().is(AsmToken::LBrac)) {
2979 Parser.Lex(); // Eat the '['.
2980 if (Parser.getTok().is(AsmToken::RBrac)) {
2981 // "Dn[]" is the 'all lanes' syntax.
2982 LaneKind = AllLanes;
2983 Parser.Lex(); // Eat the ']'.
2984 return MatchOperand_Success;
2987 // There's an optional '#' token here. Normally there wouldn't be, but
2988 // inline assemble puts one in, and it's friendly to accept that.
2989 if (Parser.getTok().is(AsmToken::Hash))
2990 Parser.Lex(); // Eat the '#'
2992 const MCExpr *LaneIndex;
2993 SMLoc Loc = Parser.getTok().getLoc();
2994 if (getParser().ParseExpression(LaneIndex)) {
2995 Error(Loc, "illegal expression");
2996 return MatchOperand_ParseFail;
2998 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3000 Error(Loc, "lane index must be empty or an integer");
3001 return MatchOperand_ParseFail;
3003 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3004 Error(Parser.getTok().getLoc(), "']' expected");
3005 return MatchOperand_ParseFail;
3007 Parser.Lex(); // Eat the ']'.
3008 int64_t Val = CE->getValue();
3010 // FIXME: Make this range check context sensitive for .8, .16, .32.
3011 if (Val < 0 || Val > 7) {
3012 Error(Parser.getTok().getLoc(), "lane index out of range");
3013 return MatchOperand_ParseFail;
3016 LaneKind = IndexedLane;
3017 return MatchOperand_Success;
3020 return MatchOperand_Success;
3023 // parse a vector register list
3024 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3025 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3026 VectorLaneTy LaneKind;
3028 SMLoc S = Parser.getTok().getLoc();
3029 // As an extension (to match gas), support a plain D register or Q register
3030 // (without encosing curly braces) as a single or double entry list,
3032 if (Parser.getTok().is(AsmToken::Identifier)) {
3033 int Reg = tryParseRegister();
3035 return MatchOperand_NoMatch;
3036 SMLoc E = Parser.getTok().getLoc();
3037 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3038 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
3039 if (Res != MatchOperand_Success)
3043 E = Parser.getTok().getLoc();
3044 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3047 E = Parser.getTok().getLoc();
3048 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3052 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3057 return MatchOperand_Success;
3059 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3060 Reg = getDRegFromQReg(Reg);
3061 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
3062 if (Res != MatchOperand_Success)
3066 E = Parser.getTok().getLoc();
3067 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3068 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3069 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3072 E = Parser.getTok().getLoc();
3073 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3074 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3075 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3079 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3084 return MatchOperand_Success;
3086 Error(S, "vector register expected");
3087 return MatchOperand_ParseFail;
3090 if (Parser.getTok().isNot(AsmToken::LCurly))
3091 return MatchOperand_NoMatch;
3093 Parser.Lex(); // Eat '{' token.
3094 SMLoc RegLoc = Parser.getTok().getLoc();
3096 int Reg = tryParseRegister();
3098 Error(RegLoc, "register expected");
3099 return MatchOperand_ParseFail;
3103 unsigned FirstReg = Reg;
3104 // The list is of D registers, but we also allow Q regs and just interpret
3105 // them as the two D sub-registers.
3106 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3107 FirstReg = Reg = getDRegFromQReg(Reg);
3108 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3109 // it's ambiguous with four-register single spaced.
3113 if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success)
3114 return MatchOperand_ParseFail;
3116 while (Parser.getTok().is(AsmToken::Comma) ||
3117 Parser.getTok().is(AsmToken::Minus)) {
3118 if (Parser.getTok().is(AsmToken::Minus)) {
3120 Spacing = 1; // Register range implies a single spaced list.
3121 else if (Spacing == 2) {
3122 Error(Parser.getTok().getLoc(),
3123 "sequential registers in double spaced list");
3124 return MatchOperand_ParseFail;
3126 Parser.Lex(); // Eat the minus.
3127 SMLoc EndLoc = Parser.getTok().getLoc();
3128 int EndReg = tryParseRegister();
3130 Error(EndLoc, "register expected");
3131 return MatchOperand_ParseFail;
3133 // Allow Q regs and just interpret them as the two D sub-registers.
3134 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3135 EndReg = getDRegFromQReg(EndReg) + 1;
3136 // If the register is the same as the start reg, there's nothing
3140 // The register must be in the same register class as the first.
3141 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3142 Error(EndLoc, "invalid register in register list");
3143 return MatchOperand_ParseFail;
3145 // Ranges must go from low to high.
3147 Error(EndLoc, "bad range in register list");
3148 return MatchOperand_ParseFail;
3150 // Parse the lane specifier if present.
3151 VectorLaneTy NextLaneKind;
3152 unsigned NextLaneIndex;
3153 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3154 return MatchOperand_ParseFail;
3155 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3156 Error(EndLoc, "mismatched lane index in register list");
3157 return MatchOperand_ParseFail;
3159 EndLoc = Parser.getTok().getLoc();
3161 // Add all the registers in the range to the register list.
3162 Count += EndReg - Reg;
3166 Parser.Lex(); // Eat the comma.
3167 RegLoc = Parser.getTok().getLoc();
3169 Reg = tryParseRegister();
3171 Error(RegLoc, "register expected");
3172 return MatchOperand_ParseFail;
3174 // vector register lists must be contiguous.
3175 // It's OK to use the enumeration values directly here rather, as the
3176 // VFP register classes have the enum sorted properly.
3178 // The list is of D registers, but we also allow Q regs and just interpret
3179 // them as the two D sub-registers.
3180 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3182 Spacing = 1; // Register range implies a single spaced list.
3183 else if (Spacing == 2) {
3185 "invalid register in double-spaced list (must be 'D' register')");
3186 return MatchOperand_ParseFail;
3188 Reg = getDRegFromQReg(Reg);
3189 if (Reg != OldReg + 1) {
3190 Error(RegLoc, "non-contiguous register range");
3191 return MatchOperand_ParseFail;
3195 // Parse the lane specifier if present.
3196 VectorLaneTy NextLaneKind;
3197 unsigned NextLaneIndex;
3198 SMLoc EndLoc = Parser.getTok().getLoc();
3199 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3200 return MatchOperand_ParseFail;
3201 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3202 Error(EndLoc, "mismatched lane index in register list");
3203 return MatchOperand_ParseFail;
3207 // Normal D register.
3208 // Figure out the register spacing (single or double) of the list if
3209 // we don't know it already.
3211 Spacing = 1 + (Reg == OldReg + 2);
3213 // Just check that it's contiguous and keep going.
3214 if (Reg != OldReg + Spacing) {
3215 Error(RegLoc, "non-contiguous register range");
3216 return MatchOperand_ParseFail;
3219 // Parse the lane specifier if present.
3220 VectorLaneTy NextLaneKind;
3221 unsigned NextLaneIndex;
3222 SMLoc EndLoc = Parser.getTok().getLoc();
3223 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3224 return MatchOperand_ParseFail;
3225 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3226 Error(EndLoc, "mismatched lane index in register list");
3227 return MatchOperand_ParseFail;
3231 SMLoc E = Parser.getTok().getLoc();
3232 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3233 Error(E, "'}' expected");
3234 return MatchOperand_ParseFail;
3236 Parser.Lex(); // Eat '}' token.
3240 // Two-register operands have been converted to the
3241 // composite register classes.
3243 const MCRegisterClass *RC = (Spacing == 1) ?
3244 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3245 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3246 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3249 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3250 (Spacing == 2), S, E));
3253 // Two-register operands have been converted to the
3254 // composite register classes.
3256 const MCRegisterClass *RC = (Spacing == 1) ?
3257 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3258 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3259 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3261 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3266 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3272 return MatchOperand_Success;
3275 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3276 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3277 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3278 SMLoc S = Parser.getTok().getLoc();
3279 const AsmToken &Tok = Parser.getTok();
3282 if (Tok.is(AsmToken::Identifier)) {
3283 StringRef OptStr = Tok.getString();
3285 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3286 .Case("sy", ARM_MB::SY)
3287 .Case("st", ARM_MB::ST)
3288 .Case("sh", ARM_MB::ISH)
3289 .Case("ish", ARM_MB::ISH)
3290 .Case("shst", ARM_MB::ISHST)
3291 .Case("ishst", ARM_MB::ISHST)
3292 .Case("nsh", ARM_MB::NSH)
3293 .Case("un", ARM_MB::NSH)
3294 .Case("nshst", ARM_MB::NSHST)
3295 .Case("unst", ARM_MB::NSHST)
3296 .Case("osh", ARM_MB::OSH)
3297 .Case("oshst", ARM_MB::OSHST)
3301 return MatchOperand_NoMatch;
3303 Parser.Lex(); // Eat identifier token.
3304 } else if (Tok.is(AsmToken::Hash) ||
3305 Tok.is(AsmToken::Dollar) ||
3306 Tok.is(AsmToken::Integer)) {
3307 if (Parser.getTok().isNot(AsmToken::Integer))
3308 Parser.Lex(); // Eat the '#'.
3309 SMLoc Loc = Parser.getTok().getLoc();
3311 const MCExpr *MemBarrierID;
3312 if (getParser().ParseExpression(MemBarrierID)) {
3313 Error(Loc, "illegal expression");
3314 return MatchOperand_ParseFail;
3317 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3319 Error(Loc, "constant expression expected");
3320 return MatchOperand_ParseFail;
3323 int Val = CE->getValue();
3325 Error(Loc, "immediate value out of range");
3326 return MatchOperand_ParseFail;
3329 Opt = ARM_MB::RESERVED_0 + Val;
3331 return MatchOperand_ParseFail;
3333 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3334 return MatchOperand_Success;
3337 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3338 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3339 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3340 SMLoc S = Parser.getTok().getLoc();
3341 const AsmToken &Tok = Parser.getTok();
3342 if (!Tok.is(AsmToken::Identifier))
3343 return MatchOperand_NoMatch;
3344 StringRef IFlagsStr = Tok.getString();
3346 // An iflags string of "none" is interpreted to mean that none of the AIF
3347 // bits are set. Not a terribly useful instruction, but a valid encoding.
3348 unsigned IFlags = 0;
3349 if (IFlagsStr != "none") {
3350 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3351 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3352 .Case("a", ARM_PROC::A)
3353 .Case("i", ARM_PROC::I)
3354 .Case("f", ARM_PROC::F)
3357 // If some specific iflag is already set, it means that some letter is
3358 // present more than once, this is not acceptable.
3359 if (Flag == ~0U || (IFlags & Flag))
3360 return MatchOperand_NoMatch;
3366 Parser.Lex(); // Eat identifier token.
3367 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3368 return MatchOperand_Success;
3371 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3372 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3373 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3374 SMLoc S = Parser.getTok().getLoc();
3375 const AsmToken &Tok = Parser.getTok();
3376 if (!Tok.is(AsmToken::Identifier))
3377 return MatchOperand_NoMatch;
3378 StringRef Mask = Tok.getString();
3381 // See ARMv6-M 10.1.1
3382 std::string Name = Mask.lower();
3383 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3384 // Note: in the documentation:
3385 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3386 // for MSR APSR_nzcvq.
3387 // but we do make it an alias here. This is so to get the "mask encoding"
3388 // bits correct on MSR APSR writes.
3390 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3391 // should really only be allowed when writing a special register. Note
3392 // they get dropped in the MRS instruction reading a special register as
3393 // the SYSm field is only 8 bits.
3395 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3396 // includes the DSP extension but that is not checked.
3397 .Case("apsr", 0x800)
3398 .Case("apsr_nzcvq", 0x800)
3399 .Case("apsr_g", 0x400)
3400 .Case("apsr_nzcvqg", 0xc00)
3401 .Case("iapsr", 0x801)
3402 .Case("iapsr_nzcvq", 0x801)
3403 .Case("iapsr_g", 0x401)
3404 .Case("iapsr_nzcvqg", 0xc01)
3405 .Case("eapsr", 0x802)
3406 .Case("eapsr_nzcvq", 0x802)
3407 .Case("eapsr_g", 0x402)
3408 .Case("eapsr_nzcvqg", 0xc02)
3409 .Case("xpsr", 0x803)
3410 .Case("xpsr_nzcvq", 0x803)
3411 .Case("xpsr_g", 0x403)
3412 .Case("xpsr_nzcvqg", 0xc03)
3413 .Case("ipsr", 0x805)
3414 .Case("epsr", 0x806)
3415 .Case("iepsr", 0x807)
3418 .Case("primask", 0x810)
3419 .Case("basepri", 0x811)
3420 .Case("basepri_max", 0x812)
3421 .Case("faultmask", 0x813)
3422 .Case("control", 0x814)
3425 if (FlagsVal == ~0U)
3426 return MatchOperand_NoMatch;
3428 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3429 // basepri, basepri_max and faultmask only valid for V7m.
3430 return MatchOperand_NoMatch;
3432 Parser.Lex(); // Eat identifier token.
3433 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3434 return MatchOperand_Success;
3437 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3438 size_t Start = 0, Next = Mask.find('_');
3439 StringRef Flags = "";
3440 std::string SpecReg = Mask.slice(Start, Next).lower();
3441 if (Next != StringRef::npos)
3442 Flags = Mask.slice(Next+1, Mask.size());
3444 // FlagsVal contains the complete mask:
3446 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3447 unsigned FlagsVal = 0;
3449 if (SpecReg == "apsr") {
3450 FlagsVal = StringSwitch<unsigned>(Flags)
3451 .Case("nzcvq", 0x8) // same as CPSR_f
3452 .Case("g", 0x4) // same as CPSR_s
3453 .Case("nzcvqg", 0xc) // same as CPSR_fs
3456 if (FlagsVal == ~0U) {
3458 return MatchOperand_NoMatch;
3460 FlagsVal = 8; // No flag
3462 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3463 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3464 if (Flags == "all" || Flags == "")
3466 for (int i = 0, e = Flags.size(); i != e; ++i) {
3467 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3474 // If some specific flag is already set, it means that some letter is
3475 // present more than once, this is not acceptable.
3476 if (FlagsVal == ~0U || (FlagsVal & Flag))
3477 return MatchOperand_NoMatch;
3480 } else // No match for special register.
3481 return MatchOperand_NoMatch;
3483 // Special register without flags is NOT equivalent to "fc" flags.
3484 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3485 // two lines would enable gas compatibility at the expense of breaking
3491 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3492 if (SpecReg == "spsr")
3495 Parser.Lex(); // Eat identifier token.
3496 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3497 return MatchOperand_Success;
3500 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3501 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3502 int Low, int High) {
3503 const AsmToken &Tok = Parser.getTok();
3504 if (Tok.isNot(AsmToken::Identifier)) {
3505 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3506 return MatchOperand_ParseFail;
3508 StringRef ShiftName = Tok.getString();
3509 std::string LowerOp = Op.lower();
3510 std::string UpperOp = Op.upper();
3511 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3512 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3513 return MatchOperand_ParseFail;
3515 Parser.Lex(); // Eat shift type token.
3517 // There must be a '#' and a shift amount.
3518 if (Parser.getTok().isNot(AsmToken::Hash) &&
3519 Parser.getTok().isNot(AsmToken::Dollar)) {
3520 Error(Parser.getTok().getLoc(), "'#' expected");
3521 return MatchOperand_ParseFail;
3523 Parser.Lex(); // Eat hash token.
3525 const MCExpr *ShiftAmount;
3526 SMLoc Loc = Parser.getTok().getLoc();
3527 if (getParser().ParseExpression(ShiftAmount)) {
3528 Error(Loc, "illegal expression");
3529 return MatchOperand_ParseFail;
3531 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3533 Error(Loc, "constant expression expected");
3534 return MatchOperand_ParseFail;
3536 int Val = CE->getValue();
3537 if (Val < Low || Val > High) {
3538 Error(Loc, "immediate value out of range");
3539 return MatchOperand_ParseFail;
3542 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
3544 return MatchOperand_Success;
3547 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3548 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3549 const AsmToken &Tok = Parser.getTok();
3550 SMLoc S = Tok.getLoc();
3551 if (Tok.isNot(AsmToken::Identifier)) {
3552 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3553 return MatchOperand_ParseFail;
3555 int Val = StringSwitch<int>(Tok.getString())
3559 Parser.Lex(); // Eat the token.
3562 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3563 return MatchOperand_ParseFail;
3565 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3567 S, Parser.getTok().getLoc()));
3568 return MatchOperand_Success;
3571 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3572 /// instructions. Legal values are:
3573 /// lsl #n 'n' in [0,31]
3574 /// asr #n 'n' in [1,32]
3575 /// n == 32 encoded as n == 0.
3576 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3577 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3578 const AsmToken &Tok = Parser.getTok();
3579 SMLoc S = Tok.getLoc();
3580 if (Tok.isNot(AsmToken::Identifier)) {
3581 Error(S, "shift operator 'asr' or 'lsl' expected");
3582 return MatchOperand_ParseFail;
3584 StringRef ShiftName = Tok.getString();
3586 if (ShiftName == "lsl" || ShiftName == "LSL")
3588 else if (ShiftName == "asr" || ShiftName == "ASR")
3591 Error(S, "shift operator 'asr' or 'lsl' expected");
3592 return MatchOperand_ParseFail;
3594 Parser.Lex(); // Eat the operator.
3596 // A '#' and a shift amount.
3597 if (Parser.getTok().isNot(AsmToken::Hash) &&
3598 Parser.getTok().isNot(AsmToken::Dollar)) {
3599 Error(Parser.getTok().getLoc(), "'#' expected");
3600 return MatchOperand_ParseFail;
3602 Parser.Lex(); // Eat hash token.
3604 const MCExpr *ShiftAmount;
3605 SMLoc E = Parser.getTok().getLoc();
3606 if (getParser().ParseExpression(ShiftAmount)) {
3607 Error(E, "malformed shift expression");
3608 return MatchOperand_ParseFail;
3610 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3612 Error(E, "shift amount must be an immediate");
3613 return MatchOperand_ParseFail;
3616 int64_t Val = CE->getValue();
3618 // Shift amount must be in [1,32]
3619 if (Val < 1 || Val > 32) {
3620 Error(E, "'asr' shift amount must be in range [1,32]");
3621 return MatchOperand_ParseFail;
3623 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3624 if (isThumb() && Val == 32) {
3625 Error(E, "'asr #32' shift amount not allowed in Thumb mode");
3626 return MatchOperand_ParseFail;
3628 if (Val == 32) Val = 0;
3630 // Shift amount must be in [1,32]
3631 if (Val < 0 || Val > 31) {
3632 Error(E, "'lsr' shift amount must be in range [0,31]");
3633 return MatchOperand_ParseFail;
3637 E = Parser.getTok().getLoc();
3638 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
3640 return MatchOperand_Success;
3643 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3644 /// of instructions. Legal values are:
3645 /// ror #n 'n' in {0, 8, 16, 24}
3646 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3647 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3648 const AsmToken &Tok = Parser.getTok();
3649 SMLoc S = Tok.getLoc();
3650 if (Tok.isNot(AsmToken::Identifier))
3651 return MatchOperand_NoMatch;
3652 StringRef ShiftName = Tok.getString();
3653 if (ShiftName != "ror" && ShiftName != "ROR")
3654 return MatchOperand_NoMatch;
3655 Parser.Lex(); // Eat the operator.
3657 // A '#' and a rotate amount.
3658 if (Parser.getTok().isNot(AsmToken::Hash) &&
3659 Parser.getTok().isNot(AsmToken::Dollar)) {
3660 Error(Parser.getTok().getLoc(), "'#' expected");
3661 return MatchOperand_ParseFail;
3663 Parser.Lex(); // Eat hash token.
3665 const MCExpr *ShiftAmount;
3666 SMLoc E = Parser.getTok().getLoc();
3667 if (getParser().ParseExpression(ShiftAmount)) {
3668 Error(E, "malformed rotate expression");
3669 return MatchOperand_ParseFail;
3671 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3673 Error(E, "rotate amount must be an immediate");
3674 return MatchOperand_ParseFail;
3677 int64_t Val = CE->getValue();
3678 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3679 // normally, zero is represented in asm by omitting the rotate operand
3681 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3682 Error(E, "'ror' rotate amount must be 8, 16, or 24");
3683 return MatchOperand_ParseFail;
3686 E = Parser.getTok().getLoc();
3687 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
3689 return MatchOperand_Success;
3692 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3693 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3694 SMLoc S = Parser.getTok().getLoc();
3695 // The bitfield descriptor is really two operands, the LSB and the width.
3696 if (Parser.getTok().isNot(AsmToken::Hash) &&
3697 Parser.getTok().isNot(AsmToken::Dollar)) {
3698 Error(Parser.getTok().getLoc(), "'#' expected");
3699 return MatchOperand_ParseFail;
3701 Parser.Lex(); // Eat hash token.
3703 const MCExpr *LSBExpr;
3704 SMLoc E = Parser.getTok().getLoc();
3705 if (getParser().ParseExpression(LSBExpr)) {
3706 Error(E, "malformed immediate expression");
3707 return MatchOperand_ParseFail;
3709 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3711 Error(E, "'lsb' operand must be an immediate");
3712 return MatchOperand_ParseFail;
3715 int64_t LSB = CE->getValue();
3716 // The LSB must be in the range [0,31]
3717 if (LSB < 0 || LSB > 31) {
3718 Error(E, "'lsb' operand must be in the range [0,31]");
3719 return MatchOperand_ParseFail;
3721 E = Parser.getTok().getLoc();
3723 // Expect another immediate operand.
3724 if (Parser.getTok().isNot(AsmToken::Comma)) {
3725 Error(Parser.getTok().getLoc(), "too few operands");
3726 return MatchOperand_ParseFail;
3728 Parser.Lex(); // Eat hash token.
3729 if (Parser.getTok().isNot(AsmToken::Hash) &&
3730 Parser.getTok().isNot(AsmToken::Dollar)) {
3731 Error(Parser.getTok().getLoc(), "'#' expected");
3732 return MatchOperand_ParseFail;
3734 Parser.Lex(); // Eat hash token.
3736 const MCExpr *WidthExpr;
3737 if (getParser().ParseExpression(WidthExpr)) {
3738 Error(E, "malformed immediate expression");
3739 return MatchOperand_ParseFail;
3741 CE = dyn_cast<MCConstantExpr>(WidthExpr);
3743 Error(E, "'width' operand must be an immediate");
3744 return MatchOperand_ParseFail;
3747 int64_t Width = CE->getValue();
3748 // The LSB must be in the range [1,32-lsb]
3749 if (Width < 1 || Width > 32 - LSB) {
3750 Error(E, "'width' operand must be in the range [1,32-lsb]");
3751 return MatchOperand_ParseFail;
3753 E = Parser.getTok().getLoc();
3755 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3757 return MatchOperand_Success;
3760 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3761 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3762 // Check for a post-index addressing register operand. Specifically:
3763 // postidx_reg := '+' register {, shift}
3764 // | '-' register {, shift}
3765 // | register {, shift}
3767 // This method must return MatchOperand_NoMatch without consuming any tokens
3768 // in the case where there is no match, as other alternatives take other
3770 AsmToken Tok = Parser.getTok();
3771 SMLoc S = Tok.getLoc();
3772 bool haveEaten = false;
3775 if (Tok.is(AsmToken::Plus)) {
3776 Parser.Lex(); // Eat the '+' token.
3778 } else if (Tok.is(AsmToken::Minus)) {
3779 Parser.Lex(); // Eat the '-' token.
3783 if (Parser.getTok().is(AsmToken::Identifier))
3784 Reg = tryParseRegister();
3787 return MatchOperand_NoMatch;
3788 Error(Parser.getTok().getLoc(), "register expected");
3789 return MatchOperand_ParseFail;
3791 SMLoc E = Parser.getTok().getLoc();
3793 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3794 unsigned ShiftImm = 0;
3795 if (Parser.getTok().is(AsmToken::Comma)) {
3796 Parser.Lex(); // Eat the ','.
3797 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3798 return MatchOperand_ParseFail;
3801 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3804 return MatchOperand_Success;
3807 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3808 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3809 // Check for a post-index addressing register operand. Specifically:
3810 // am3offset := '+' register
3817 // This method must return MatchOperand_NoMatch without consuming any tokens
3818 // in the case where there is no match, as other alternatives take other
3820 AsmToken Tok = Parser.getTok();
3821 SMLoc S = Tok.getLoc();
3823 // Do immediates first, as we always parse those if we have a '#'.
3824 if (Parser.getTok().is(AsmToken::Hash) ||
3825 Parser.getTok().is(AsmToken::Dollar)) {
3826 Parser.Lex(); // Eat the '#'.
3827 // Explicitly look for a '-', as we need to encode negative zero
3829 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3830 const MCExpr *Offset;
3831 if (getParser().ParseExpression(Offset))
3832 return MatchOperand_ParseFail;
3833 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3835 Error(S, "constant expression expected");
3836 return MatchOperand_ParseFail;
3838 SMLoc E = Tok.getLoc();
3839 // Negative zero is encoded as the flag value INT32_MIN.
3840 int32_t Val = CE->getValue();
3841 if (isNegative && Val == 0)
3845 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3847 return MatchOperand_Success;
3851 bool haveEaten = false;
3854 if (Tok.is(AsmToken::Plus)) {
3855 Parser.Lex(); // Eat the '+' token.
3857 } else if (Tok.is(AsmToken::Minus)) {
3858 Parser.Lex(); // Eat the '-' token.
3862 if (Parser.getTok().is(AsmToken::Identifier))
3863 Reg = tryParseRegister();
3866 return MatchOperand_NoMatch;
3867 Error(Parser.getTok().getLoc(), "register expected");
3868 return MatchOperand_ParseFail;
3870 SMLoc E = Parser.getTok().getLoc();
3872 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3875 return MatchOperand_Success;
3878 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
3879 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3880 /// when they refer multiple MIOperands inside a single one.
3882 cvtT2LdrdPre(MCInst &Inst,
3883 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3885 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3886 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3887 // Create a writeback register dummy placeholder.
3888 Inst.addOperand(MCOperand::CreateReg(0));
3890 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3892 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3895 /// cvtT2StrdPre - Convert parsed operands to MCInst.
3896 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3897 /// when they refer multiple MIOperands inside a single one.
3899 cvtT2StrdPre(MCInst &Inst,
3900 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3901 // Create a writeback register dummy placeholder.
3902 Inst.addOperand(MCOperand::CreateReg(0));
3904 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3905 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3907 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3909 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3912 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3913 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3914 /// when they refer multiple MIOperands inside a single one.
3916 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
3917 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3918 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3920 // Create a writeback register dummy placeholder.
3921 Inst.addOperand(MCOperand::CreateImm(0));
3923 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3924 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3927 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3928 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3929 /// when they refer multiple MIOperands inside a single one.
3931 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
3932 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3933 // Create a writeback register dummy placeholder.
3934 Inst.addOperand(MCOperand::CreateImm(0));
3935 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3936 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3937 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3940 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3941 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3942 /// when they refer multiple MIOperands inside a single one.
3944 cvtLdWriteBackRegAddrMode2(MCInst &Inst,
3945 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3946 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3948 // Create a writeback register dummy placeholder.
3949 Inst.addOperand(MCOperand::CreateImm(0));
3951 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3952 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3955 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3956 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3957 /// when they refer multiple MIOperands inside a single one.
3959 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
3960 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3961 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3963 // Create a writeback register dummy placeholder.
3964 Inst.addOperand(MCOperand::CreateImm(0));
3966 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3967 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3971 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3972 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3973 /// when they refer multiple MIOperands inside a single one.
3975 cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
3976 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3977 // Create a writeback register dummy placeholder.
3978 Inst.addOperand(MCOperand::CreateImm(0));
3979 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3980 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3981 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3984 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3985 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3986 /// when they refer multiple MIOperands inside a single one.
3988 cvtStWriteBackRegAddrMode2(MCInst &Inst,
3989 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3990 // Create a writeback register dummy placeholder.
3991 Inst.addOperand(MCOperand::CreateImm(0));
3992 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3993 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3994 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3997 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3998 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3999 /// when they refer multiple MIOperands inside a single one.
4001 cvtStWriteBackRegAddrMode3(MCInst &Inst,
4002 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4003 // Create a writeback register dummy placeholder.
4004 Inst.addOperand(MCOperand::CreateImm(0));
4005 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4006 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4007 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4010 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
4011 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4012 /// when they refer multiple MIOperands inside a single one.
4014 cvtLdExtTWriteBackImm(MCInst &Inst,
4015 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4017 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4018 // Create a writeback register dummy placeholder.
4019 Inst.addOperand(MCOperand::CreateImm(0));
4021 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4023 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4025 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4028 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
4029 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4030 /// when they refer multiple MIOperands inside a single one.
4032 cvtLdExtTWriteBackReg(MCInst &Inst,
4033 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4035 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4036 // Create a writeback register dummy placeholder.
4037 Inst.addOperand(MCOperand::CreateImm(0));
4039 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4041 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4043 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4046 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
4047 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4048 /// when they refer multiple MIOperands inside a single one.
4050 cvtStExtTWriteBackImm(MCInst &Inst,
4051 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4052 // Create a writeback register dummy placeholder.
4053 Inst.addOperand(MCOperand::CreateImm(0));
4055 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4057 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4059 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4061 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4064 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
4065 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4066 /// when they refer multiple MIOperands inside a single one.
4068 cvtStExtTWriteBackReg(MCInst &Inst,
4069 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4070 // Create a writeback register dummy placeholder.
4071 Inst.addOperand(MCOperand::CreateImm(0));
4073 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4075 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4077 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4079 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4082 /// cvtLdrdPre - Convert parsed operands to MCInst.
4083 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4084 /// when they refer multiple MIOperands inside a single one.
4086 cvtLdrdPre(MCInst &Inst,
4087 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4089 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4090 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4091 // Create a writeback register dummy placeholder.
4092 Inst.addOperand(MCOperand::CreateImm(0));
4094 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4096 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4099 /// cvtStrdPre - Convert parsed operands to MCInst.
4100 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4101 /// when they refer multiple MIOperands inside a single one.
4103 cvtStrdPre(MCInst &Inst,
4104 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4105 // Create a writeback register dummy placeholder.
4106 Inst.addOperand(MCOperand::CreateImm(0));
4108 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4109 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4111 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4113 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4116 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4117 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4118 /// when they refer multiple MIOperands inside a single one.
4120 cvtLdWriteBackRegAddrMode3(MCInst &Inst,
4121 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4122 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4123 // Create a writeback register dummy placeholder.
4124 Inst.addOperand(MCOperand::CreateImm(0));
4125 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4126 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4129 /// cvtThumbMultiply - Convert parsed operands to MCInst.
4130 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4131 /// when they refer multiple MIOperands inside a single one.
4133 cvtThumbMultiply(MCInst &Inst,
4134 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4135 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4136 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4137 // If we have a three-operand form, make sure to set Rn to be the operand
4138 // that isn't the same as Rd.
4140 if (Operands.size() == 6 &&
4141 ((ARMOperand*)Operands[4])->getReg() ==
4142 ((ARMOperand*)Operands[3])->getReg())
4144 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4145 Inst.addOperand(Inst.getOperand(0));
4146 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4150 cvtVLDwbFixed(MCInst &Inst,
4151 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4153 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4154 // Create a writeback register dummy placeholder.
4155 Inst.addOperand(MCOperand::CreateImm(0));
4157 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4159 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4163 cvtVLDwbRegister(MCInst &Inst,
4164 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4166 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4167 // Create a writeback register dummy placeholder.
4168 Inst.addOperand(MCOperand::CreateImm(0));
4170 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4172 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4174 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4178 cvtVSTwbFixed(MCInst &Inst,
4179 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4180 // Create a writeback register dummy placeholder.
4181 Inst.addOperand(MCOperand::CreateImm(0));
4183 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4185 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4187 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4191 cvtVSTwbRegister(MCInst &Inst,
4192 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4193 // Create a writeback register dummy placeholder.
4194 Inst.addOperand(MCOperand::CreateImm(0));
4196 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4198 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4200 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4202 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4205 /// Parse an ARM memory expression, return false if successful else return true
4206 /// or an error. The first token must be a '[' when called.
4208 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4210 assert(Parser.getTok().is(AsmToken::LBrac) &&
4211 "Token is not a Left Bracket");
4212 S = Parser.getTok().getLoc();
4213 Parser.Lex(); // Eat left bracket token.
4215 const AsmToken &BaseRegTok = Parser.getTok();
4216 int BaseRegNum = tryParseRegister();
4217 if (BaseRegNum == -1)
4218 return Error(BaseRegTok.getLoc(), "register expected");
4220 // The next token must either be a comma or a closing bracket.
4221 const AsmToken &Tok = Parser.getTok();
4222 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
4223 return Error(Tok.getLoc(), "malformed memory operand");
4225 if (Tok.is(AsmToken::RBrac)) {
4227 Parser.Lex(); // Eat right bracket token.
4229 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4230 0, 0, false, S, E));
4232 // If there's a pre-indexing writeback marker, '!', just add it as a token
4233 // operand. It's rather odd, but syntactically valid.
4234 if (Parser.getTok().is(AsmToken::Exclaim)) {
4235 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4236 Parser.Lex(); // Eat the '!'.
4242 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
4243 Parser.Lex(); // Eat the comma.
4245 // If we have a ':', it's an alignment specifier.
4246 if (Parser.getTok().is(AsmToken::Colon)) {
4247 Parser.Lex(); // Eat the ':'.
4248 E = Parser.getTok().getLoc();
4251 if (getParser().ParseExpression(Expr))
4254 // The expression has to be a constant. Memory references with relocations
4255 // don't come through here, as they use the <label> forms of the relevant
4257 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4259 return Error (E, "constant expression expected");
4262 switch (CE->getValue()) {
4265 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4266 case 16: Align = 2; break;
4267 case 32: Align = 4; break;
4268 case 64: Align = 8; break;
4269 case 128: Align = 16; break;
4270 case 256: Align = 32; break;
4273 // Now we should have the closing ']'
4274 E = Parser.getTok().getLoc();
4275 if (Parser.getTok().isNot(AsmToken::RBrac))
4276 return Error(E, "']' expected");
4277 Parser.Lex(); // Eat right bracket token.
4279 // Don't worry about range checking the value here. That's handled by
4280 // the is*() predicates.
4281 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4282 ARM_AM::no_shift, 0, Align,
4285 // If there's a pre-indexing writeback marker, '!', just add it as a token
4287 if (Parser.getTok().is(AsmToken::Exclaim)) {
4288 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4289 Parser.Lex(); // Eat the '!'.
4295 // If we have a '#', it's an immediate offset, else assume it's a register
4296 // offset. Be friendly and also accept a plain integer (without a leading
4297 // hash) for gas compatibility.
4298 if (Parser.getTok().is(AsmToken::Hash) ||
4299 Parser.getTok().is(AsmToken::Dollar) ||
4300 Parser.getTok().is(AsmToken::Integer)) {
4301 if (Parser.getTok().isNot(AsmToken::Integer))
4302 Parser.Lex(); // Eat the '#'.
4303 E = Parser.getTok().getLoc();
4305 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4306 const MCExpr *Offset;
4307 if (getParser().ParseExpression(Offset))
4310 // The expression has to be a constant. Memory references with relocations
4311 // don't come through here, as they use the <label> forms of the relevant
4313 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4315 return Error (E, "constant expression expected");
4317 // If the constant was #-0, represent it as INT32_MIN.
4318 int32_t Val = CE->getValue();
4319 if (isNegative && Val == 0)
4320 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4322 // Now we should have the closing ']'
4323 E = Parser.getTok().getLoc();
4324 if (Parser.getTok().isNot(AsmToken::RBrac))
4325 return Error(E, "']' expected");
4326 Parser.Lex(); // Eat right bracket token.
4328 // Don't worry about range checking the value here. That's handled by
4329 // the is*() predicates.
4330 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4331 ARM_AM::no_shift, 0, 0,
4334 // If there's a pre-indexing writeback marker, '!', just add it as a token
4336 if (Parser.getTok().is(AsmToken::Exclaim)) {
4337 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4338 Parser.Lex(); // Eat the '!'.
4344 // The register offset is optionally preceded by a '+' or '-'
4345 bool isNegative = false;
4346 if (Parser.getTok().is(AsmToken::Minus)) {
4348 Parser.Lex(); // Eat the '-'.
4349 } else if (Parser.getTok().is(AsmToken::Plus)) {
4351 Parser.Lex(); // Eat the '+'.
4354 E = Parser.getTok().getLoc();
4355 int OffsetRegNum = tryParseRegister();
4356 if (OffsetRegNum == -1)
4357 return Error(E, "register expected");
4359 // If there's a shift operator, handle it.
4360 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4361 unsigned ShiftImm = 0;
4362 if (Parser.getTok().is(AsmToken::Comma)) {
4363 Parser.Lex(); // Eat the ','.
4364 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4368 // Now we should have the closing ']'
4369 E = Parser.getTok().getLoc();
4370 if (Parser.getTok().isNot(AsmToken::RBrac))
4371 return Error(E, "']' expected");
4372 Parser.Lex(); // Eat right bracket token.
4374 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4375 ShiftType, ShiftImm, 0, isNegative,
4378 // If there's a pre-indexing writeback marker, '!', just add it as a token
4380 if (Parser.getTok().is(AsmToken::Exclaim)) {
4381 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4382 Parser.Lex(); // Eat the '!'.
4388 /// parseMemRegOffsetShift - one of these two:
4389 /// ( lsl | lsr | asr | ror ) , # shift_amount
4391 /// return true if it parses a shift otherwise it returns false.
4392 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4394 SMLoc Loc = Parser.getTok().getLoc();
4395 const AsmToken &Tok = Parser.getTok();
4396 if (Tok.isNot(AsmToken::Identifier))
4398 StringRef ShiftName = Tok.getString();
4399 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4400 ShiftName == "asl" || ShiftName == "ASL")
4402 else if (ShiftName == "lsr" || ShiftName == "LSR")
4404 else if (ShiftName == "asr" || ShiftName == "ASR")
4406 else if (ShiftName == "ror" || ShiftName == "ROR")
4408 else if (ShiftName == "rrx" || ShiftName == "RRX")
4411 return Error(Loc, "illegal shift operator");
4412 Parser.Lex(); // Eat shift type token.
4414 // rrx stands alone.
4416 if (St != ARM_AM::rrx) {
4417 Loc = Parser.getTok().getLoc();
4418 // A '#' and a shift amount.
4419 const AsmToken &HashTok = Parser.getTok();
4420 if (HashTok.isNot(AsmToken::Hash) &&
4421 HashTok.isNot(AsmToken::Dollar))
4422 return Error(HashTok.getLoc(), "'#' expected");
4423 Parser.Lex(); // Eat hash token.
4426 if (getParser().ParseExpression(Expr))
4428 // Range check the immediate.
4429 // lsl, ror: 0 <= imm <= 31
4430 // lsr, asr: 0 <= imm <= 32
4431 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4433 return Error(Loc, "shift amount must be an immediate");
4434 int64_t Imm = CE->getValue();
4436 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4437 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4438 return Error(Loc, "immediate shift value out of range");
4439 // If <ShiftTy> #0, turn it into a no_shift.
4442 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4451 /// parseFPImm - A floating point immediate expression operand.
4452 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4453 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4454 // Anything that can accept a floating point constant as an operand
4455 // needs to go through here, as the regular ParseExpression is
4458 // This routine still creates a generic Immediate operand, containing
4459 // a bitcast of the 64-bit floating point value. The various operands
4460 // that accept floats can check whether the value is valid for them
4461 // via the standard is*() predicates.
4463 SMLoc S = Parser.getTok().getLoc();
4465 if (Parser.getTok().isNot(AsmToken::Hash) &&
4466 Parser.getTok().isNot(AsmToken::Dollar))
4467 return MatchOperand_NoMatch;
4469 // Disambiguate the VMOV forms that can accept an FP immediate.
4470 // vmov.f32 <sreg>, #imm
4471 // vmov.f64 <dreg>, #imm
4472 // vmov.f32 <dreg>, #imm @ vector f32x2
4473 // vmov.f32 <qreg>, #imm @ vector f32x4
4475 // There are also the NEON VMOV instructions which expect an
4476 // integer constant. Make sure we don't try to parse an FPImm
4478 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4479 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4480 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4481 TyOp->getToken() != ".f64"))
4482 return MatchOperand_NoMatch;
4484 Parser.Lex(); // Eat the '#'.
4486 // Handle negation, as that still comes through as a separate token.
4487 bool isNegative = false;
4488 if (Parser.getTok().is(AsmToken::Minus)) {
4492 const AsmToken &Tok = Parser.getTok();
4493 SMLoc Loc = Tok.getLoc();
4494 if (Tok.is(AsmToken::Real)) {
4495 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4496 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4497 // If we had a '-' in front, toggle the sign bit.
4498 IntVal ^= (uint64_t)isNegative << 31;
4499 Parser.Lex(); // Eat the token.
4500 Operands.push_back(ARMOperand::CreateImm(
4501 MCConstantExpr::Create(IntVal, getContext()),
4502 S, Parser.getTok().getLoc()));
4503 return MatchOperand_Success;
4505 // Also handle plain integers. Instructions which allow floating point
4506 // immediates also allow a raw encoded 8-bit value.
4507 if (Tok.is(AsmToken::Integer)) {
4508 int64_t Val = Tok.getIntVal();
4509 Parser.Lex(); // Eat the token.
4510 if (Val > 255 || Val < 0) {
4511 Error(Loc, "encoded floating point value out of range");
4512 return MatchOperand_ParseFail;
4514 double RealVal = ARM_AM::getFPImmFloat(Val);
4515 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4516 Operands.push_back(ARMOperand::CreateImm(
4517 MCConstantExpr::Create(Val, getContext()), S,
4518 Parser.getTok().getLoc()));
4519 return MatchOperand_Success;
4522 Error(Loc, "invalid floating point immediate");
4523 return MatchOperand_ParseFail;
4526 /// Parse a arm instruction operand. For now this parses the operand regardless
4527 /// of the mnemonic.
4528 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4529 StringRef Mnemonic) {
4532 // Check if the current operand has a custom associated parser, if so, try to
4533 // custom parse the operand, or fallback to the general approach.
4534 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4535 if (ResTy == MatchOperand_Success)
4537 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4538 // there was a match, but an error occurred, in which case, just return that
4539 // the operand parsing failed.
4540 if (ResTy == MatchOperand_ParseFail)
4543 switch (getLexer().getKind()) {
4545 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4547 case AsmToken::Identifier: {
4548 if (!tryParseRegisterWithWriteBack(Operands))
4550 int Res = tryParseShiftRegister(Operands);
4551 if (Res == 0) // success
4553 else if (Res == -1) // irrecoverable error
4555 // If this is VMRS, check for the apsr_nzcv operand.
4556 if (Mnemonic == "vmrs" &&
4557 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4558 S = Parser.getTok().getLoc();
4560 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4564 // Fall though for the Identifier case that is not a register or a
4567 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4568 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4569 case AsmToken::String: // quoted label names.
4570 case AsmToken::Dot: { // . as a branch target
4571 // This was not a register so parse other operands that start with an
4572 // identifier (like labels) as expressions and create them as immediates.
4573 const MCExpr *IdVal;
4574 S = Parser.getTok().getLoc();
4575 if (getParser().ParseExpression(IdVal))
4577 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4578 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4581 case AsmToken::LBrac:
4582 return parseMemory(Operands);
4583 case AsmToken::LCurly:
4584 return parseRegisterList(Operands);
4585 case AsmToken::Dollar:
4586 case AsmToken::Hash: {
4587 // #42 -> immediate.
4588 S = Parser.getTok().getLoc();
4591 if (Parser.getTok().isNot(AsmToken::Colon)) {
4592 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4593 const MCExpr *ImmVal;
4594 if (getParser().ParseExpression(ImmVal))
4596 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4598 int32_t Val = CE->getValue();
4599 if (isNegative && Val == 0)
4600 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4602 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4603 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4606 // w/ a ':' after the '#', it's just like a plain ':'.
4609 case AsmToken::Colon: {
4610 // ":lower16:" and ":upper16:" expression prefixes
4611 // FIXME: Check it's an expression prefix,
4612 // e.g. (FOO - :lower16:BAR) isn't legal.
4613 ARMMCExpr::VariantKind RefKind;
4614 if (parsePrefix(RefKind))
4617 const MCExpr *SubExprVal;
4618 if (getParser().ParseExpression(SubExprVal))
4621 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4623 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4624 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4630 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4631 // :lower16: and :upper16:.
4632 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4633 RefKind = ARMMCExpr::VK_ARM_None;
4635 // :lower16: and :upper16: modifiers
4636 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4637 Parser.Lex(); // Eat ':'
4639 if (getLexer().isNot(AsmToken::Identifier)) {
4640 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4644 StringRef IDVal = Parser.getTok().getIdentifier();
4645 if (IDVal == "lower16") {
4646 RefKind = ARMMCExpr::VK_ARM_LO16;
4647 } else if (IDVal == "upper16") {
4648 RefKind = ARMMCExpr::VK_ARM_HI16;
4650 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4655 if (getLexer().isNot(AsmToken::Colon)) {
4656 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4659 Parser.Lex(); // Eat the last ':'
4663 /// \brief Given a mnemonic, split out possible predication code and carry
4664 /// setting letters to form a canonical mnemonic and flags.
4666 // FIXME: Would be nice to autogen this.
4667 // FIXME: This is a bit of a maze of special cases.
4668 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4669 unsigned &PredicationCode,
4671 unsigned &ProcessorIMod,
4672 StringRef &ITMask) {
4673 PredicationCode = ARMCC::AL;
4674 CarrySetting = false;
4677 // Ignore some mnemonics we know aren't predicated forms.
4679 // FIXME: Would be nice to autogen this.
4680 if ((Mnemonic == "movs" && isThumb()) ||
4681 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4682 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4683 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4684 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4685 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4686 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4687 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4688 Mnemonic == "fmuls")
4691 // First, split out any predication code. Ignore mnemonics we know aren't
4692 // predicated but do have a carry-set and so weren't caught above.
4693 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4694 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4695 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4696 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4697 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4698 .Case("eq", ARMCC::EQ)
4699 .Case("ne", ARMCC::NE)
4700 .Case("hs", ARMCC::HS)
4701 .Case("cs", ARMCC::HS)
4702 .Case("lo", ARMCC::LO)
4703 .Case("cc", ARMCC::LO)
4704 .Case("mi", ARMCC::MI)
4705 .Case("pl", ARMCC::PL)
4706 .Case("vs", ARMCC::VS)
4707 .Case("vc", ARMCC::VC)
4708 .Case("hi", ARMCC::HI)
4709 .Case("ls", ARMCC::LS)
4710 .Case("ge", ARMCC::GE)
4711 .Case("lt", ARMCC::LT)
4712 .Case("gt", ARMCC::GT)
4713 .Case("le", ARMCC::LE)
4714 .Case("al", ARMCC::AL)
4717 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4718 PredicationCode = CC;
4722 // Next, determine if we have a carry setting bit. We explicitly ignore all
4723 // the instructions we know end in 's'.
4724 if (Mnemonic.endswith("s") &&
4725 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4726 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4727 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4728 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4729 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4730 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4731 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4732 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4733 Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4734 (Mnemonic == "movs" && isThumb()))) {
4735 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4736 CarrySetting = true;
4739 // The "cps" instruction can have a interrupt mode operand which is glued into
4740 // the mnemonic. Check if this is the case, split it and parse the imod op
4741 if (Mnemonic.startswith("cps")) {
4742 // Split out any imod code.
4744 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4745 .Case("ie", ARM_PROC::IE)
4746 .Case("id", ARM_PROC::ID)
4749 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4750 ProcessorIMod = IMod;
4754 // The "it" instruction has the condition mask on the end of the mnemonic.
4755 if (Mnemonic.startswith("it")) {
4756 ITMask = Mnemonic.slice(2, Mnemonic.size());
4757 Mnemonic = Mnemonic.slice(0, 2);
4763 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4764 /// inclusion of carry set or predication code operands.
4766 // FIXME: It would be nice to autogen this.
4768 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4769 bool &CanAcceptPredicationCode) {
4770 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4771 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4772 Mnemonic == "add" || Mnemonic == "adc" ||
4773 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4774 Mnemonic == "orr" || Mnemonic == "mvn" ||
4775 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4776 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4777 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4778 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4779 Mnemonic == "mla" || Mnemonic == "smlal" ||
4780 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4781 CanAcceptCarrySet = true;
4783 CanAcceptCarrySet = false;
4785 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4786 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4787 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4788 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4789 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4790 (Mnemonic == "clrex" && !isThumb()) ||
4791 (Mnemonic == "nop" && isThumbOne()) ||
4792 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4793 Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4794 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4795 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4797 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4798 CanAcceptPredicationCode = false;
4800 CanAcceptPredicationCode = true;
4803 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4804 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4805 CanAcceptPredicationCode = false;
4809 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4810 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4811 // FIXME: This is all horribly hacky. We really need a better way to deal
4812 // with optional operands like this in the matcher table.
4814 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4815 // another does not. Specifically, the MOVW instruction does not. So we
4816 // special case it here and remove the defaulted (non-setting) cc_out
4817 // operand if that's the instruction we're trying to match.
4819 // We do this as post-processing of the explicit operands rather than just
4820 // conditionally adding the cc_out in the first place because we need
4821 // to check the type of the parsed immediate operand.
4822 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4823 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4824 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4825 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4828 // Register-register 'add' for thumb does not have a cc_out operand
4829 // when there are only two register operands.
4830 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4831 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4832 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4833 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4835 // Register-register 'add' for thumb does not have a cc_out operand
4836 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4837 // have to check the immediate range here since Thumb2 has a variant
4838 // that can handle a different range and has a cc_out operand.
4839 if (((isThumb() && Mnemonic == "add") ||
4840 (isThumbTwo() && Mnemonic == "sub")) &&
4841 Operands.size() == 6 &&
4842 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4843 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4844 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4845 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4846 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4847 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4849 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4850 // imm0_4095 variant. That's the least-preferred variant when
4851 // selecting via the generic "add" mnemonic, so to know that we
4852 // should remove the cc_out operand, we have to explicitly check that
4853 // it's not one of the other variants. Ugh.
4854 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4855 Operands.size() == 6 &&
4856 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4857 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4858 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4859 // Nest conditions rather than one big 'if' statement for readability.
4861 // If either register is a high reg, it's either one of the SP
4862 // variants (handled above) or a 32-bit encoding, so we just
4863 // check against T3. If the second register is the PC, this is an
4864 // alternate form of ADR, which uses encoding T4, so check for that too.
4865 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4866 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4867 static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4868 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4870 // If both registers are low, we're in an IT block, and the immediate is
4871 // in range, we should use encoding T1 instead, which has a cc_out.
4873 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4874 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4875 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4878 // Otherwise, we use encoding T4, which does not have a cc_out
4883 // The thumb2 multiply instruction doesn't have a CCOut register, so
4884 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4885 // use the 16-bit encoding or not.
4886 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4887 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4888 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4889 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4890 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4891 // If the registers aren't low regs, the destination reg isn't the
4892 // same as one of the source regs, or the cc_out operand is zero
4893 // outside of an IT block, we have to use the 32-bit encoding, so
4894 // remove the cc_out operand.
4895 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4896 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4897 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4899 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4900 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4901 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4902 static_cast<ARMOperand*>(Operands[4])->getReg())))
4905 // Also check the 'mul' syntax variant that doesn't specify an explicit
4906 // destination register.
4907 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4908 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4909 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4910 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4911 // If the registers aren't low regs or the cc_out operand is zero
4912 // outside of an IT block, we have to use the 32-bit encoding, so
4913 // remove the cc_out operand.
4914 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4915 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4921 // Register-register 'add/sub' for thumb does not have a cc_out operand
4922 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4923 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4924 // right, this will result in better diagnostics (which operand is off)
4926 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4927 (Operands.size() == 5 || Operands.size() == 6) &&
4928 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4929 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4930 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4931 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4932 (Operands.size() == 6 &&
4933 static_cast<ARMOperand*>(Operands[5])->isImm())))
4939 static bool isDataTypeToken(StringRef Tok) {
4940 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4941 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4942 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4943 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4944 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4945 Tok == ".f" || Tok == ".d";
4948 // FIXME: This bit should probably be handled via an explicit match class
4949 // in the .td files that matches the suffix instead of having it be
4950 // a literal string token the way it is now.
4951 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4952 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4955 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
4956 /// Parse an arm instruction mnemonic followed by its operands.
4957 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4958 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4959 // Apply mnemonic aliases before doing anything else, as the destination
4960 // mnemnonic may include suffices and we want to handle them normally.
4961 // The generic tblgen'erated code does this later, at the start of
4962 // MatchInstructionImpl(), but that's too late for aliases that include
4963 // any sort of suffix.
4964 unsigned AvailableFeatures = getAvailableFeatures();
4965 applyMnemonicAliases(Name, AvailableFeatures);
4967 // First check for the ARM-specific .req directive.
4968 if (Parser.getTok().is(AsmToken::Identifier) &&
4969 Parser.getTok().getIdentifier() == ".req") {
4970 parseDirectiveReq(Name, NameLoc);
4971 // We always return 'error' for this, as we're done with this
4972 // statement and don't need to match the 'instruction."
4976 // Create the leading tokens for the mnemonic, split by '.' characters.
4977 size_t Start = 0, Next = Name.find('.');
4978 StringRef Mnemonic = Name.slice(Start, Next);
4980 // Split out the predication code and carry setting flag from the mnemonic.
4981 unsigned PredicationCode;
4982 unsigned ProcessorIMod;
4985 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4986 ProcessorIMod, ITMask);
4988 // In Thumb1, only the branch (B) instruction can be predicated.
4989 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4990 Parser.EatToEndOfStatement();
4991 return Error(NameLoc, "conditional execution not supported in Thumb1");
4994 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4996 // Handle the IT instruction ITMask. Convert it to a bitmask. This
4997 // is the mask as it will be for the IT encoding if the conditional
4998 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4999 // where the conditional bit0 is zero, the instruction post-processing
5000 // will adjust the mask accordingly.
5001 if (Mnemonic == "it") {
5002 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5003 if (ITMask.size() > 3) {
5004 Parser.EatToEndOfStatement();
5005 return Error(Loc, "too many conditions on IT instruction");
5008 for (unsigned i = ITMask.size(); i != 0; --i) {
5009 char pos = ITMask[i - 1];
5010 if (pos != 't' && pos != 'e') {
5011 Parser.EatToEndOfStatement();
5012 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5015 if (ITMask[i - 1] == 't')
5018 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5021 // FIXME: This is all a pretty gross hack. We should automatically handle
5022 // optional operands like this via tblgen.
5024 // Next, add the CCOut and ConditionCode operands, if needed.
5026 // For mnemonics which can ever incorporate a carry setting bit or predication
5027 // code, our matching model involves us always generating CCOut and
5028 // ConditionCode operands to match the mnemonic "as written" and then we let
5029 // the matcher deal with finding the right instruction or generating an
5030 // appropriate error.
5031 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5032 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5034 // If we had a carry-set on an instruction that can't do that, issue an
5036 if (!CanAcceptCarrySet && CarrySetting) {
5037 Parser.EatToEndOfStatement();
5038 return Error(NameLoc, "instruction '" + Mnemonic +
5039 "' can not set flags, but 's' suffix specified");
5041 // If we had a predication code on an instruction that can't do that, issue an
5043 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5044 Parser.EatToEndOfStatement();
5045 return Error(NameLoc, "instruction '" + Mnemonic +
5046 "' is not predicable, but condition code specified");
5049 // Add the carry setting operand, if necessary.
5050 if (CanAcceptCarrySet) {
5051 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5052 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5056 // Add the predication code operand, if necessary.
5057 if (CanAcceptPredicationCode) {
5058 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5060 Operands.push_back(ARMOperand::CreateCondCode(
5061 ARMCC::CondCodes(PredicationCode), Loc));
5064 // Add the processor imod operand, if necessary.
5065 if (ProcessorIMod) {
5066 Operands.push_back(ARMOperand::CreateImm(
5067 MCConstantExpr::Create(ProcessorIMod, getContext()),
5071 // Add the remaining tokens in the mnemonic.
5072 while (Next != StringRef::npos) {
5074 Next = Name.find('.', Start + 1);
5075 StringRef ExtraToken = Name.slice(Start, Next);
5077 // Some NEON instructions have an optional datatype suffix that is
5078 // completely ignored. Check for that.
5079 if (isDataTypeToken(ExtraToken) &&
5080 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5083 if (ExtraToken != ".n") {
5084 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5085 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5089 // Read the remaining operands.
5090 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5091 // Read the first operand.
5092 if (parseOperand(Operands, Mnemonic)) {
5093 Parser.EatToEndOfStatement();
5097 while (getLexer().is(AsmToken::Comma)) {
5098 Parser.Lex(); // Eat the comma.
5100 // Parse and remember the operand.
5101 if (parseOperand(Operands, Mnemonic)) {
5102 Parser.EatToEndOfStatement();
5108 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5109 SMLoc Loc = getLexer().getLoc();
5110 Parser.EatToEndOfStatement();
5111 return Error(Loc, "unexpected token in argument list");
5114 Parser.Lex(); // Consume the EndOfStatement
5116 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5117 // do and don't have a cc_out optional-def operand. With some spot-checks
5118 // of the operand list, we can figure out which variant we're trying to
5119 // parse and adjust accordingly before actually matching. We shouldn't ever
5120 // try to remove a cc_out operand that was explicitly set on the the
5121 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5122 // table driven matcher doesn't fit well with the ARM instruction set.
5123 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5124 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5125 Operands.erase(Operands.begin() + 1);
5129 // ARM mode 'blx' need special handling, as the register operand version
5130 // is predicable, but the label operand version is not. So, we can't rely
5131 // on the Mnemonic based checking to correctly figure out when to put
5132 // a k_CondCode operand in the list. If we're trying to match the label
5133 // version, remove the k_CondCode operand here.
5134 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5135 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5136 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5137 Operands.erase(Operands.begin() + 1);
5141 // The vector-compare-to-zero instructions have a literal token "#0" at
5142 // the end that comes to here as an immediate operand. Convert it to a
5143 // token to play nicely with the matcher.
5144 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
5145 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
5146 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5147 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5148 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5149 if (CE && CE->getValue() == 0) {
5150 Operands.erase(Operands.begin() + 5);
5151 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5155 // VCMP{E} does the same thing, but with a different operand count.
5156 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
5157 static_cast<ARMOperand*>(Operands[4])->isImm()) {
5158 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
5159 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5160 if (CE && CE->getValue() == 0) {
5161 Operands.erase(Operands.begin() + 4);
5162 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5166 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
5167 // end. Convert it to a token here. Take care not to convert those
5168 // that should hit the Thumb2 encoding.
5169 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
5170 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5171 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5172 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5173 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5174 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5175 if (CE && CE->getValue() == 0 &&
5177 // The cc_out operand matches the IT block.
5178 ((inITBlock() != CarrySetting) &&
5179 // Neither register operand is a high register.
5180 (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5181 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){
5182 Operands.erase(Operands.begin() + 5);
5183 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5191 // Validate context-sensitive operand constraints.
5193 // return 'true' if register list contains non-low GPR registers,
5194 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5195 // 'containsReg' to true.
5196 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5197 unsigned HiReg, bool &containsReg) {
5198 containsReg = false;
5199 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5200 unsigned OpReg = Inst.getOperand(i).getReg();
5203 // Anything other than a low register isn't legal here.
5204 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5210 // Check if the specified regisgter is in the register list of the inst,
5211 // starting at the indicated operand number.
5212 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5213 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5214 unsigned OpReg = Inst.getOperand(i).getReg();
5221 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5222 // the ARMInsts array) instead. Getting that here requires awkward
5223 // API changes, though. Better way?
5225 extern const MCInstrDesc ARMInsts[];
5227 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5228 return ARMInsts[Opcode];
5231 // FIXME: We would really like to be able to tablegen'erate this.
5233 validateInstruction(MCInst &Inst,
5234 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5235 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5236 SMLoc Loc = Operands[0]->getStartLoc();
5237 // Check the IT block state first.
5238 // NOTE: BKPT instruction has the interesting property of being
5239 // allowed in IT blocks, but not being predicable. It just always
5241 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5242 Inst.getOpcode() != ARM::BKPT) {
5244 if (ITState.FirstCond)
5245 ITState.FirstCond = false;
5247 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5248 // The instruction must be predicable.
5249 if (!MCID.isPredicable())
5250 return Error(Loc, "instructions in IT block must be predicable");
5251 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5252 unsigned ITCond = bit ? ITState.Cond :
5253 ARMCC::getOppositeCondition(ITState.Cond);
5254 if (Cond != ITCond) {
5255 // Find the condition code Operand to get its SMLoc information.
5257 for (unsigned i = 1; i < Operands.size(); ++i)
5258 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5259 CondLoc = Operands[i]->getStartLoc();
5260 return Error(CondLoc, "incorrect condition in IT block; got '" +
5261 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5262 "', but expected '" +
5263 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5265 // Check for non-'al' condition codes outside of the IT block.
5266 } else if (isThumbTwo() && MCID.isPredicable() &&
5267 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5268 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5269 Inst.getOpcode() != ARM::t2B)
5270 return Error(Loc, "predicated instructions must be in IT block");
5272 switch (Inst.getOpcode()) {
5275 case ARM::LDRD_POST:
5277 // Rt2 must be Rt + 1.
5278 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5279 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5281 return Error(Operands[3]->getStartLoc(),
5282 "destination operands must be sequential");
5286 // Rt2 must be Rt + 1.
5287 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5288 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5290 return Error(Operands[3]->getStartLoc(),
5291 "source operands must be sequential");
5295 case ARM::STRD_POST:
5297 // Rt2 must be Rt + 1.
5298 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5299 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5301 return Error(Operands[3]->getStartLoc(),
5302 "source operands must be sequential");
5307 // width must be in range [1, 32-lsb]
5308 unsigned lsb = Inst.getOperand(2).getImm();
5309 unsigned widthm1 = Inst.getOperand(3).getImm();
5310 if (widthm1 >= 32 - lsb)
5311 return Error(Operands[5]->getStartLoc(),
5312 "bitfield width must be in range [1,32-lsb]");
5316 // If we're parsing Thumb2, the .w variant is available and handles
5317 // most cases that are normally illegal for a Thumb1 LDM
5318 // instruction. We'll make the transformation in processInstruction()
5321 // Thumb LDM instructions are writeback iff the base register is not
5322 // in the register list.
5323 unsigned Rn = Inst.getOperand(0).getReg();
5324 bool hasWritebackToken =
5325 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5326 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5327 bool listContainsBase;
5328 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5329 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5330 "registers must be in range r0-r7");
5331 // If we should have writeback, then there should be a '!' token.
5332 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5333 return Error(Operands[2]->getStartLoc(),
5334 "writeback operator '!' expected");
5335 // If we should not have writeback, there must not be a '!'. This is
5336 // true even for the 32-bit wide encodings.
5337 if (listContainsBase && hasWritebackToken)
5338 return Error(Operands[3]->getStartLoc(),
5339 "writeback operator '!' not allowed when base register "
5340 "in register list");
5344 case ARM::t2LDMIA_UPD: {
5345 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5346 return Error(Operands[4]->getStartLoc(),
5347 "writeback operator '!' not allowed when base register "
5348 "in register list");
5352 // The second source operand must be the same register as the destination
5355 // In this case, we must directly check the parsed operands because the
5356 // cvtThumbMultiply() function is written in such a way that it guarantees
5357 // this first statement is always true for the new Inst. Essentially, the
5358 // destination is unconditionally copied into the second source operand
5359 // without checking to see if it matches what we actually parsed.
5360 if (Operands.size() == 6 &&
5361 (((ARMOperand*)Operands[3])->getReg() !=
5362 ((ARMOperand*)Operands[5])->getReg()) &&
5363 (((ARMOperand*)Operands[3])->getReg() !=
5364 ((ARMOperand*)Operands[4])->getReg())) {
5365 return Error(Operands[3]->getStartLoc(),
5366 "destination register must match source register");
5370 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5371 // so only issue a diagnostic for thumb1. The instructions will be
5372 // switched to the t2 encodings in processInstruction() if necessary.
5374 bool listContainsBase;
5375 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5377 return Error(Operands[2]->getStartLoc(),
5378 "registers must be in range r0-r7 or pc");
5382 bool listContainsBase;
5383 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5385 return Error(Operands[2]->getStartLoc(),
5386 "registers must be in range r0-r7 or lr");
5389 case ARM::tSTMIA_UPD: {
5390 bool listContainsBase;
5391 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5392 return Error(Operands[4]->getStartLoc(),
5393 "registers must be in range r0-r7");
5396 case ARM::tADDrSP: {
5397 // If the non-SP source operand and the destination operand are not the
5398 // same, we need thumb2 (for the wide encoding), or we have an error.
5399 if (!isThumbTwo() &&
5400 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5401 return Error(Operands[4]->getStartLoc(),
5402 "source register must be the same as destination");
5411 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5413 default: llvm_unreachable("unexpected opcode!");
5415 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5416 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5417 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5418 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5419 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5420 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5421 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5422 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5423 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5426 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5427 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5428 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5429 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5430 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5432 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5433 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5434 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5435 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5436 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5438 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5439 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5440 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5441 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5442 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5445 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5446 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5447 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5448 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5449 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5450 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5451 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5452 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5453 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5454 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5455 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5456 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5457 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5458 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5459 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5462 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5463 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5464 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5465 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5466 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5467 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5468 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5469 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5470 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5471 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5472 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5473 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5474 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5475 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5476 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5477 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5478 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5479 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5482 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5483 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5484 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5485 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5486 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5487 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5488 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5489 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5490 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5491 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5492 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5493 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5494 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5495 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5496 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5499 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5500 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5501 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5502 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5503 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5504 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5505 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5506 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5507 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5508 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5509 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5510 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5511 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5512 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5513 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5514 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5515 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5516 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5520 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5522 default: llvm_unreachable("unexpected opcode!");
5524 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5525 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5526 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5527 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5528 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5529 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5530 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5531 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5532 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5535 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5536 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5537 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5538 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5539 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5540 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5541 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5542 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5543 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5544 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5545 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5546 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5547 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5548 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5549 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5552 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5553 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5554 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5555 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5556 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5557 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5558 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5559 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5560 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5561 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5562 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5563 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5564 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5565 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5566 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5567 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5568 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5569 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5572 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5573 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5574 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5575 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5576 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5577 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5578 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5579 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5580 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5581 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5582 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5583 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5584 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5585 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5586 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5589 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5590 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5591 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5592 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5593 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5594 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5595 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5596 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5597 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5598 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5599 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5600 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5601 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5602 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5603 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5604 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5605 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5606 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5609 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5610 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5611 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5612 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5613 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5614 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5615 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5616 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5617 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5618 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5619 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5620 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5621 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5622 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5623 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5626 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5627 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5628 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5629 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5630 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5631 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5632 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5633 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5634 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5635 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5636 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5637 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5638 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5639 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5640 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5641 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5642 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5643 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5646 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5647 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5648 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5649 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5650 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5651 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5652 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5653 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5654 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5655 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5656 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5657 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5658 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5659 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5660 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5661 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5662 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5663 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5668 processInstruction(MCInst &Inst,
5669 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5670 switch (Inst.getOpcode()) {
5671 // Alias for alternate form of 'ADR Rd, #imm' instruction.
5673 if (Inst.getOperand(1).getReg() != ARM::PC ||
5674 Inst.getOperand(5).getReg() != 0)
5677 TmpInst.setOpcode(ARM::ADR);
5678 TmpInst.addOperand(Inst.getOperand(0));
5679 TmpInst.addOperand(Inst.getOperand(2));
5680 TmpInst.addOperand(Inst.getOperand(3));
5681 TmpInst.addOperand(Inst.getOperand(4));
5685 // Aliases for alternate PC+imm syntax of LDR instructions.
5686 case ARM::t2LDRpcrel:
5687 Inst.setOpcode(ARM::t2LDRpci);
5689 case ARM::t2LDRBpcrel:
5690 Inst.setOpcode(ARM::t2LDRBpci);
5692 case ARM::t2LDRHpcrel:
5693 Inst.setOpcode(ARM::t2LDRHpci);
5695 case ARM::t2LDRSBpcrel:
5696 Inst.setOpcode(ARM::t2LDRSBpci);
5698 case ARM::t2LDRSHpcrel:
5699 Inst.setOpcode(ARM::t2LDRSHpci);
5701 // Handle NEON VST complex aliases.
5702 case ARM::VST1LNdWB_register_Asm_8:
5703 case ARM::VST1LNdWB_register_Asm_16:
5704 case ARM::VST1LNdWB_register_Asm_32: {
5706 // Shuffle the operands around so the lane index operand is in the
5709 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5710 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5711 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5712 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5713 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5714 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5715 TmpInst.addOperand(Inst.getOperand(1)); // lane
5716 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5717 TmpInst.addOperand(Inst.getOperand(6));
5722 case ARM::VST2LNdWB_register_Asm_8:
5723 case ARM::VST2LNdWB_register_Asm_16:
5724 case ARM::VST2LNdWB_register_Asm_32:
5725 case ARM::VST2LNqWB_register_Asm_16:
5726 case ARM::VST2LNqWB_register_Asm_32: {
5728 // Shuffle the operands around so the lane index operand is in the
5731 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5732 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5733 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5734 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5735 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5736 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5737 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5739 TmpInst.addOperand(Inst.getOperand(1)); // lane
5740 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5741 TmpInst.addOperand(Inst.getOperand(6));
5746 case ARM::VST3LNdWB_register_Asm_8:
5747 case ARM::VST3LNdWB_register_Asm_16:
5748 case ARM::VST3LNdWB_register_Asm_32:
5749 case ARM::VST3LNqWB_register_Asm_16:
5750 case ARM::VST3LNqWB_register_Asm_32: {
5752 // Shuffle the operands around so the lane index operand is in the
5755 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5756 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5757 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5758 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5759 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5760 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5761 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5763 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5765 TmpInst.addOperand(Inst.getOperand(1)); // lane
5766 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5767 TmpInst.addOperand(Inst.getOperand(6));
5772 case ARM::VST4LNdWB_register_Asm_8:
5773 case ARM::VST4LNdWB_register_Asm_16:
5774 case ARM::VST4LNdWB_register_Asm_32:
5775 case ARM::VST4LNqWB_register_Asm_16:
5776 case ARM::VST4LNqWB_register_Asm_32: {
5778 // Shuffle the operands around so the lane index operand is in the
5781 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5782 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5783 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5784 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5785 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5786 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5787 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5789 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5791 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5793 TmpInst.addOperand(Inst.getOperand(1)); // lane
5794 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5795 TmpInst.addOperand(Inst.getOperand(6));
5800 case ARM::VST1LNdWB_fixed_Asm_8:
5801 case ARM::VST1LNdWB_fixed_Asm_16:
5802 case ARM::VST1LNdWB_fixed_Asm_32: {
5804 // Shuffle the operands around so the lane index operand is in the
5807 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5808 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5809 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5810 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5811 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5812 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5813 TmpInst.addOperand(Inst.getOperand(1)); // lane
5814 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5815 TmpInst.addOperand(Inst.getOperand(5));
5820 case ARM::VST2LNdWB_fixed_Asm_8:
5821 case ARM::VST2LNdWB_fixed_Asm_16:
5822 case ARM::VST2LNdWB_fixed_Asm_32:
5823 case ARM::VST2LNqWB_fixed_Asm_16:
5824 case ARM::VST2LNqWB_fixed_Asm_32: {
5826 // Shuffle the operands around so the lane index operand is in the
5829 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5830 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5831 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5832 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5833 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5834 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5835 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5837 TmpInst.addOperand(Inst.getOperand(1)); // lane
5838 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5839 TmpInst.addOperand(Inst.getOperand(5));
5844 case ARM::VST3LNdWB_fixed_Asm_8:
5845 case ARM::VST3LNdWB_fixed_Asm_16:
5846 case ARM::VST3LNdWB_fixed_Asm_32:
5847 case ARM::VST3LNqWB_fixed_Asm_16:
5848 case ARM::VST3LNqWB_fixed_Asm_32: {
5850 // Shuffle the operands around so the lane index operand is in the
5853 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5854 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5855 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5856 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5857 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5858 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5859 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5861 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5863 TmpInst.addOperand(Inst.getOperand(1)); // lane
5864 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5865 TmpInst.addOperand(Inst.getOperand(5));
5870 case ARM::VST4LNdWB_fixed_Asm_8:
5871 case ARM::VST4LNdWB_fixed_Asm_16:
5872 case ARM::VST4LNdWB_fixed_Asm_32:
5873 case ARM::VST4LNqWB_fixed_Asm_16:
5874 case ARM::VST4LNqWB_fixed_Asm_32: {
5876 // Shuffle the operands around so the lane index operand is in the
5879 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5880 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5881 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5882 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5883 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5884 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5885 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5887 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5889 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5891 TmpInst.addOperand(Inst.getOperand(1)); // lane
5892 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5893 TmpInst.addOperand(Inst.getOperand(5));
5898 case ARM::VST1LNdAsm_8:
5899 case ARM::VST1LNdAsm_16:
5900 case ARM::VST1LNdAsm_32: {
5902 // Shuffle the operands around so the lane index operand is in the
5905 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5906 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5907 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5908 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5909 TmpInst.addOperand(Inst.getOperand(1)); // lane
5910 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5911 TmpInst.addOperand(Inst.getOperand(5));
5916 case ARM::VST2LNdAsm_8:
5917 case ARM::VST2LNdAsm_16:
5918 case ARM::VST2LNdAsm_32:
5919 case ARM::VST2LNqAsm_16:
5920 case ARM::VST2LNqAsm_32: {
5922 // Shuffle the operands around so the lane index operand is in the
5925 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5926 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5927 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5928 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5929 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5931 TmpInst.addOperand(Inst.getOperand(1)); // lane
5932 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5933 TmpInst.addOperand(Inst.getOperand(5));
5938 case ARM::VST3LNdAsm_8:
5939 case ARM::VST3LNdAsm_16:
5940 case ARM::VST3LNdAsm_32:
5941 case ARM::VST3LNqAsm_16:
5942 case ARM::VST3LNqAsm_32: {
5944 // Shuffle the operands around so the lane index operand is in the
5947 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5948 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5949 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5950 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5951 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5953 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5955 TmpInst.addOperand(Inst.getOperand(1)); // lane
5956 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5957 TmpInst.addOperand(Inst.getOperand(5));
5962 case ARM::VST4LNdAsm_8:
5963 case ARM::VST4LNdAsm_16:
5964 case ARM::VST4LNdAsm_32:
5965 case ARM::VST4LNqAsm_16:
5966 case ARM::VST4LNqAsm_32: {
5968 // Shuffle the operands around so the lane index operand is in the
5971 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5972 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5973 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5974 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5975 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5977 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5979 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5981 TmpInst.addOperand(Inst.getOperand(1)); // lane
5982 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5983 TmpInst.addOperand(Inst.getOperand(5));
5988 // Handle NEON VLD complex aliases.
5989 case ARM::VLD1LNdWB_register_Asm_8:
5990 case ARM::VLD1LNdWB_register_Asm_16:
5991 case ARM::VLD1LNdWB_register_Asm_32: {
5993 // Shuffle the operands around so the lane index operand is in the
5996 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5997 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5998 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5999 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6000 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6001 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6002 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6003 TmpInst.addOperand(Inst.getOperand(1)); // lane
6004 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6005 TmpInst.addOperand(Inst.getOperand(6));
6010 case ARM::VLD2LNdWB_register_Asm_8:
6011 case ARM::VLD2LNdWB_register_Asm_16:
6012 case ARM::VLD2LNdWB_register_Asm_32:
6013 case ARM::VLD2LNqWB_register_Asm_16:
6014 case ARM::VLD2LNqWB_register_Asm_32: {
6016 // Shuffle the operands around so the lane index operand is in the
6019 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6020 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6021 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6023 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6024 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6025 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6026 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6027 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6028 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6030 TmpInst.addOperand(Inst.getOperand(1)); // lane
6031 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6032 TmpInst.addOperand(Inst.getOperand(6));
6037 case ARM::VLD3LNdWB_register_Asm_8:
6038 case ARM::VLD3LNdWB_register_Asm_16:
6039 case ARM::VLD3LNdWB_register_Asm_32:
6040 case ARM::VLD3LNqWB_register_Asm_16:
6041 case ARM::VLD3LNqWB_register_Asm_32: {
6043 // Shuffle the operands around so the lane index operand is in the
6046 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6047 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6048 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6050 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6052 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6053 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6054 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6055 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6056 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6057 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6059 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6061 TmpInst.addOperand(Inst.getOperand(1)); // lane
6062 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6063 TmpInst.addOperand(Inst.getOperand(6));
6068 case ARM::VLD4LNdWB_register_Asm_8:
6069 case ARM::VLD4LNdWB_register_Asm_16:
6070 case ARM::VLD4LNdWB_register_Asm_32:
6071 case ARM::VLD4LNqWB_register_Asm_16:
6072 case ARM::VLD4LNqWB_register_Asm_32: {
6074 // Shuffle the operands around so the lane index operand is in the
6077 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6078 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6079 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6081 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6083 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6085 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6086 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6087 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6088 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6089 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6090 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6092 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6094 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6096 TmpInst.addOperand(Inst.getOperand(1)); // lane
6097 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6098 TmpInst.addOperand(Inst.getOperand(6));
6103 case ARM::VLD1LNdWB_fixed_Asm_8:
6104 case ARM::VLD1LNdWB_fixed_Asm_16:
6105 case ARM::VLD1LNdWB_fixed_Asm_32: {
6107 // Shuffle the operands around so the lane index operand is in the
6110 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6111 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6112 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6113 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6114 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6115 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6116 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6117 TmpInst.addOperand(Inst.getOperand(1)); // lane
6118 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6119 TmpInst.addOperand(Inst.getOperand(5));
6124 case ARM::VLD2LNdWB_fixed_Asm_8:
6125 case ARM::VLD2LNdWB_fixed_Asm_16:
6126 case ARM::VLD2LNdWB_fixed_Asm_32:
6127 case ARM::VLD2LNqWB_fixed_Asm_16:
6128 case ARM::VLD2LNqWB_fixed_Asm_32: {
6130 // Shuffle the operands around so the lane index operand is in the
6133 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6134 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6135 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6137 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6138 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6139 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6140 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6141 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6142 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6144 TmpInst.addOperand(Inst.getOperand(1)); // lane
6145 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6146 TmpInst.addOperand(Inst.getOperand(5));
6151 case ARM::VLD3LNdWB_fixed_Asm_8:
6152 case ARM::VLD3LNdWB_fixed_Asm_16:
6153 case ARM::VLD3LNdWB_fixed_Asm_32:
6154 case ARM::VLD3LNqWB_fixed_Asm_16:
6155 case ARM::VLD3LNqWB_fixed_Asm_32: {
6157 // Shuffle the operands around so the lane index operand is in the
6160 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6161 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6162 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6164 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6166 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6167 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6168 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6169 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6170 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6171 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6173 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6175 TmpInst.addOperand(Inst.getOperand(1)); // lane
6176 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6177 TmpInst.addOperand(Inst.getOperand(5));
6182 case ARM::VLD4LNdWB_fixed_Asm_8:
6183 case ARM::VLD4LNdWB_fixed_Asm_16:
6184 case ARM::VLD4LNdWB_fixed_Asm_32:
6185 case ARM::VLD4LNqWB_fixed_Asm_16:
6186 case ARM::VLD4LNqWB_fixed_Asm_32: {
6188 // Shuffle the operands around so the lane index operand is in the
6191 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6192 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6193 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6195 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6197 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6199 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6200 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6201 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6202 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6203 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6204 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6206 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6208 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6210 TmpInst.addOperand(Inst.getOperand(1)); // lane
6211 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6212 TmpInst.addOperand(Inst.getOperand(5));
6217 case ARM::VLD1LNdAsm_8:
6218 case ARM::VLD1LNdAsm_16:
6219 case ARM::VLD1LNdAsm_32: {
6221 // Shuffle the operands around so the lane index operand is in the
6224 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6225 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6226 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6227 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6228 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6229 TmpInst.addOperand(Inst.getOperand(1)); // lane
6230 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6231 TmpInst.addOperand(Inst.getOperand(5));
6236 case ARM::VLD2LNdAsm_8:
6237 case ARM::VLD2LNdAsm_16:
6238 case ARM::VLD2LNdAsm_32:
6239 case ARM::VLD2LNqAsm_16:
6240 case ARM::VLD2LNqAsm_32: {
6242 // Shuffle the operands around so the lane index operand is in the
6245 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6246 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6247 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6249 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6250 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6251 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6252 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6254 TmpInst.addOperand(Inst.getOperand(1)); // lane
6255 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6256 TmpInst.addOperand(Inst.getOperand(5));
6261 case ARM::VLD3LNdAsm_8:
6262 case ARM::VLD3LNdAsm_16:
6263 case ARM::VLD3LNdAsm_32:
6264 case ARM::VLD3LNqAsm_16:
6265 case ARM::VLD3LNqAsm_32: {
6267 // Shuffle the operands around so the lane index operand is in the
6270 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6271 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6272 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6274 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6276 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6277 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6278 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6279 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6281 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6283 TmpInst.addOperand(Inst.getOperand(1)); // lane
6284 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6285 TmpInst.addOperand(Inst.getOperand(5));
6290 case ARM::VLD4LNdAsm_8:
6291 case ARM::VLD4LNdAsm_16:
6292 case ARM::VLD4LNdAsm_32:
6293 case ARM::VLD4LNqAsm_16:
6294 case ARM::VLD4LNqAsm_32: {
6296 // Shuffle the operands around so the lane index operand is in the
6299 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6300 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6301 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6303 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6305 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6307 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6308 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6309 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6310 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6312 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6314 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6316 TmpInst.addOperand(Inst.getOperand(1)); // lane
6317 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6318 TmpInst.addOperand(Inst.getOperand(5));
6323 // VLD3DUP single 3-element structure to all lanes instructions.
6324 case ARM::VLD3DUPdAsm_8:
6325 case ARM::VLD3DUPdAsm_16:
6326 case ARM::VLD3DUPdAsm_32:
6327 case ARM::VLD3DUPqAsm_8:
6328 case ARM::VLD3DUPqAsm_16:
6329 case ARM::VLD3DUPqAsm_32: {
6332 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6333 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6334 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6336 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6338 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6339 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6340 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6341 TmpInst.addOperand(Inst.getOperand(4));
6346 case ARM::VLD3DUPdWB_fixed_Asm_8:
6347 case ARM::VLD3DUPdWB_fixed_Asm_16:
6348 case ARM::VLD3DUPdWB_fixed_Asm_32:
6349 case ARM::VLD3DUPqWB_fixed_Asm_8:
6350 case ARM::VLD3DUPqWB_fixed_Asm_16:
6351 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6354 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6355 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6356 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6358 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6360 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6361 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6362 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6363 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6364 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6365 TmpInst.addOperand(Inst.getOperand(4));
6370 case ARM::VLD3DUPdWB_register_Asm_8:
6371 case ARM::VLD3DUPdWB_register_Asm_16:
6372 case ARM::VLD3DUPdWB_register_Asm_32:
6373 case ARM::VLD3DUPqWB_register_Asm_8:
6374 case ARM::VLD3DUPqWB_register_Asm_16:
6375 case ARM::VLD3DUPqWB_register_Asm_32: {
6378 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6379 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6380 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6382 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6384 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6385 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6386 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6387 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6388 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6389 TmpInst.addOperand(Inst.getOperand(5));
6394 // VLD3 multiple 3-element structure instructions.
6395 case ARM::VLD3dAsm_8:
6396 case ARM::VLD3dAsm_16:
6397 case ARM::VLD3dAsm_32:
6398 case ARM::VLD3qAsm_8:
6399 case ARM::VLD3qAsm_16:
6400 case ARM::VLD3qAsm_32: {
6403 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6404 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6405 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6407 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6409 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6410 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6411 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6412 TmpInst.addOperand(Inst.getOperand(4));
6417 case ARM::VLD3dWB_fixed_Asm_8:
6418 case ARM::VLD3dWB_fixed_Asm_16:
6419 case ARM::VLD3dWB_fixed_Asm_32:
6420 case ARM::VLD3qWB_fixed_Asm_8:
6421 case ARM::VLD3qWB_fixed_Asm_16:
6422 case ARM::VLD3qWB_fixed_Asm_32: {
6425 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6426 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6427 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6429 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6431 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6432 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6433 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6434 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6435 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6436 TmpInst.addOperand(Inst.getOperand(4));
6441 case ARM::VLD3dWB_register_Asm_8:
6442 case ARM::VLD3dWB_register_Asm_16:
6443 case ARM::VLD3dWB_register_Asm_32:
6444 case ARM::VLD3qWB_register_Asm_8:
6445 case ARM::VLD3qWB_register_Asm_16:
6446 case ARM::VLD3qWB_register_Asm_32: {
6449 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6450 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6451 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6453 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6455 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6456 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6457 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6458 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6459 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6460 TmpInst.addOperand(Inst.getOperand(5));
6465 // VLD4DUP single 3-element structure to all lanes instructions.
6466 case ARM::VLD4DUPdAsm_8:
6467 case ARM::VLD4DUPdAsm_16:
6468 case ARM::VLD4DUPdAsm_32:
6469 case ARM::VLD4DUPqAsm_8:
6470 case ARM::VLD4DUPqAsm_16:
6471 case ARM::VLD4DUPqAsm_32: {
6474 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6475 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6476 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6478 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6480 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6482 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6483 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6484 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6485 TmpInst.addOperand(Inst.getOperand(4));
6490 case ARM::VLD4DUPdWB_fixed_Asm_8:
6491 case ARM::VLD4DUPdWB_fixed_Asm_16:
6492 case ARM::VLD4DUPdWB_fixed_Asm_32:
6493 case ARM::VLD4DUPqWB_fixed_Asm_8:
6494 case ARM::VLD4DUPqWB_fixed_Asm_16:
6495 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6498 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6499 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6500 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6502 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6504 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6506 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6507 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6508 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6509 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6510 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6511 TmpInst.addOperand(Inst.getOperand(4));
6516 case ARM::VLD4DUPdWB_register_Asm_8:
6517 case ARM::VLD4DUPdWB_register_Asm_16:
6518 case ARM::VLD4DUPdWB_register_Asm_32:
6519 case ARM::VLD4DUPqWB_register_Asm_8:
6520 case ARM::VLD4DUPqWB_register_Asm_16:
6521 case ARM::VLD4DUPqWB_register_Asm_32: {
6524 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6525 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6526 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6528 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6530 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6532 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6533 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6534 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6535 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6536 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6537 TmpInst.addOperand(Inst.getOperand(5));
6542 // VLD4 multiple 4-element structure instructions.
6543 case ARM::VLD4dAsm_8:
6544 case ARM::VLD4dAsm_16:
6545 case ARM::VLD4dAsm_32:
6546 case ARM::VLD4qAsm_8:
6547 case ARM::VLD4qAsm_16:
6548 case ARM::VLD4qAsm_32: {
6551 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6552 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6553 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6555 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6557 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6559 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6560 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6561 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6562 TmpInst.addOperand(Inst.getOperand(4));
6567 case ARM::VLD4dWB_fixed_Asm_8:
6568 case ARM::VLD4dWB_fixed_Asm_16:
6569 case ARM::VLD4dWB_fixed_Asm_32:
6570 case ARM::VLD4qWB_fixed_Asm_8:
6571 case ARM::VLD4qWB_fixed_Asm_16:
6572 case ARM::VLD4qWB_fixed_Asm_32: {
6575 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6576 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6577 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6579 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6581 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6583 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6584 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6585 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6586 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6587 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6588 TmpInst.addOperand(Inst.getOperand(4));
6593 case ARM::VLD4dWB_register_Asm_8:
6594 case ARM::VLD4dWB_register_Asm_16:
6595 case ARM::VLD4dWB_register_Asm_32:
6596 case ARM::VLD4qWB_register_Asm_8:
6597 case ARM::VLD4qWB_register_Asm_16:
6598 case ARM::VLD4qWB_register_Asm_32: {
6601 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6602 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6603 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6605 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6607 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6609 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6610 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6611 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6612 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6613 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6614 TmpInst.addOperand(Inst.getOperand(5));
6619 // VST3 multiple 3-element structure instructions.
6620 case ARM::VST3dAsm_8:
6621 case ARM::VST3dAsm_16:
6622 case ARM::VST3dAsm_32:
6623 case ARM::VST3qAsm_8:
6624 case ARM::VST3qAsm_16:
6625 case ARM::VST3qAsm_32: {
6628 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6629 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6630 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6631 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6632 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6634 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6636 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6637 TmpInst.addOperand(Inst.getOperand(4));
6642 case ARM::VST3dWB_fixed_Asm_8:
6643 case ARM::VST3dWB_fixed_Asm_16:
6644 case ARM::VST3dWB_fixed_Asm_32:
6645 case ARM::VST3qWB_fixed_Asm_8:
6646 case ARM::VST3qWB_fixed_Asm_16:
6647 case ARM::VST3qWB_fixed_Asm_32: {
6650 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6651 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6652 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6653 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6654 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6655 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6656 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6658 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6660 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6661 TmpInst.addOperand(Inst.getOperand(4));
6666 case ARM::VST3dWB_register_Asm_8:
6667 case ARM::VST3dWB_register_Asm_16:
6668 case ARM::VST3dWB_register_Asm_32:
6669 case ARM::VST3qWB_register_Asm_8:
6670 case ARM::VST3qWB_register_Asm_16:
6671 case ARM::VST3qWB_register_Asm_32: {
6674 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6675 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6676 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6677 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6678 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6679 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6680 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6682 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6684 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6685 TmpInst.addOperand(Inst.getOperand(5));
6690 // VST4 multiple 3-element structure instructions.
6691 case ARM::VST4dAsm_8:
6692 case ARM::VST4dAsm_16:
6693 case ARM::VST4dAsm_32:
6694 case ARM::VST4qAsm_8:
6695 case ARM::VST4qAsm_16:
6696 case ARM::VST4qAsm_32: {
6699 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6700 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6701 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6702 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6703 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6705 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6707 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6709 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6710 TmpInst.addOperand(Inst.getOperand(4));
6715 case ARM::VST4dWB_fixed_Asm_8:
6716 case ARM::VST4dWB_fixed_Asm_16:
6717 case ARM::VST4dWB_fixed_Asm_32:
6718 case ARM::VST4qWB_fixed_Asm_8:
6719 case ARM::VST4qWB_fixed_Asm_16:
6720 case ARM::VST4qWB_fixed_Asm_32: {
6723 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6724 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6725 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6726 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6727 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6728 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6729 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6731 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6733 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6735 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6736 TmpInst.addOperand(Inst.getOperand(4));
6741 case ARM::VST4dWB_register_Asm_8:
6742 case ARM::VST4dWB_register_Asm_16:
6743 case ARM::VST4dWB_register_Asm_32:
6744 case ARM::VST4qWB_register_Asm_8:
6745 case ARM::VST4qWB_register_Asm_16:
6746 case ARM::VST4qWB_register_Asm_32: {
6749 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6750 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6751 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6752 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6753 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6754 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6755 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6757 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6759 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6761 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6762 TmpInst.addOperand(Inst.getOperand(5));
6767 // Handle encoding choice for the shift-immediate instructions.
6770 case ARM::t2ASRri: {
6771 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6772 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6773 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6774 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6775 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6777 switch (Inst.getOpcode()) {
6778 default: llvm_unreachable("unexpected opcode");
6779 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6780 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6781 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6783 // The Thumb1 operands aren't in the same order. Awesome, eh?
6785 TmpInst.setOpcode(NewOpc);
6786 TmpInst.addOperand(Inst.getOperand(0));
6787 TmpInst.addOperand(Inst.getOperand(5));
6788 TmpInst.addOperand(Inst.getOperand(1));
6789 TmpInst.addOperand(Inst.getOperand(2));
6790 TmpInst.addOperand(Inst.getOperand(3));
6791 TmpInst.addOperand(Inst.getOperand(4));
6798 // Handle the Thumb2 mode MOV complex aliases.
6800 case ARM::t2MOVSsr: {
6801 // Which instruction to expand to depends on the CCOut operand and
6802 // whether we're in an IT block if the register operands are low
6804 bool isNarrow = false;
6805 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6806 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6807 isARMLowRegister(Inst.getOperand(2).getReg()) &&
6808 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6809 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6813 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6814 default: llvm_unreachable("unexpected opcode!");
6815 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6816 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6817 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6818 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
6820 TmpInst.setOpcode(newOpc);
6821 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6823 TmpInst.addOperand(MCOperand::CreateReg(
6824 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6825 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6826 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6827 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6828 TmpInst.addOperand(Inst.getOperand(5));
6830 TmpInst.addOperand(MCOperand::CreateReg(
6831 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6836 case ARM::t2MOVSsi: {
6837 // Which instruction to expand to depends on the CCOut operand and
6838 // whether we're in an IT block if the register operands are low
6840 bool isNarrow = false;
6841 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6842 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6843 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6847 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6848 default: llvm_unreachable("unexpected opcode!");
6849 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6850 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6851 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6852 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6853 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6855 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6856 if (Amount == 32) Amount = 0;
6857 TmpInst.setOpcode(newOpc);
6858 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6860 TmpInst.addOperand(MCOperand::CreateReg(
6861 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6862 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6863 if (newOpc != ARM::t2RRX)
6864 TmpInst.addOperand(MCOperand::CreateImm(Amount));
6865 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6866 TmpInst.addOperand(Inst.getOperand(4));
6868 TmpInst.addOperand(MCOperand::CreateReg(
6869 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6873 // Handle the ARM mode MOV complex aliases.
6878 ARM_AM::ShiftOpc ShiftTy;
6879 switch(Inst.getOpcode()) {
6880 default: llvm_unreachable("unexpected opcode!");
6881 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6882 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6883 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6884 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6886 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6888 TmpInst.setOpcode(ARM::MOVsr);
6889 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6890 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6891 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6892 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6893 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6894 TmpInst.addOperand(Inst.getOperand(4));
6895 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6903 ARM_AM::ShiftOpc ShiftTy;
6904 switch(Inst.getOpcode()) {
6905 default: llvm_unreachable("unexpected opcode!");
6906 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6907 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6908 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6909 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6911 // A shift by zero is a plain MOVr, not a MOVsi.
6912 unsigned Amt = Inst.getOperand(2).getImm();
6913 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6914 // A shift by 32 should be encoded as 0 when permitted
6915 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
6917 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
6919 TmpInst.setOpcode(Opc);
6920 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6921 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6922 if (Opc == ARM::MOVsi)
6923 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6924 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6925 TmpInst.addOperand(Inst.getOperand(4));
6926 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6931 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
6933 TmpInst.setOpcode(ARM::MOVsi);
6934 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6935 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6936 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6937 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6938 TmpInst.addOperand(Inst.getOperand(3));
6939 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
6943 case ARM::t2LDMIA_UPD: {
6944 // If this is a load of a single register, then we should use
6945 // a post-indexed LDR instruction instead, per the ARM ARM.
6946 if (Inst.getNumOperands() != 5)
6949 TmpInst.setOpcode(ARM::t2LDR_POST);
6950 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6951 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6952 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6953 TmpInst.addOperand(MCOperand::CreateImm(4));
6954 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6955 TmpInst.addOperand(Inst.getOperand(3));
6959 case ARM::t2STMDB_UPD: {
6960 // If this is a store of a single register, then we should use
6961 // a pre-indexed STR instruction instead, per the ARM ARM.
6962 if (Inst.getNumOperands() != 5)
6965 TmpInst.setOpcode(ARM::t2STR_PRE);
6966 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6967 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6968 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6969 TmpInst.addOperand(MCOperand::CreateImm(-4));
6970 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6971 TmpInst.addOperand(Inst.getOperand(3));
6975 case ARM::LDMIA_UPD:
6976 // If this is a load of a single register via a 'pop', then we should use
6977 // a post-indexed LDR instruction instead, per the ARM ARM.
6978 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
6979 Inst.getNumOperands() == 5) {
6981 TmpInst.setOpcode(ARM::LDR_POST_IMM);
6982 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6983 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6984 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6985 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
6986 TmpInst.addOperand(MCOperand::CreateImm(4));
6987 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6988 TmpInst.addOperand(Inst.getOperand(3));
6993 case ARM::STMDB_UPD:
6994 // If this is a store of a single register via a 'push', then we should use
6995 // a pre-indexed STR instruction instead, per the ARM ARM.
6996 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
6997 Inst.getNumOperands() == 5) {
6999 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7000 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7001 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7002 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7003 TmpInst.addOperand(MCOperand::CreateImm(-4));
7004 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7005 TmpInst.addOperand(Inst.getOperand(3));
7009 case ARM::t2ADDri12:
7010 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7011 // mnemonic was used (not "addw"), encoding T3 is preferred.
7012 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7013 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7015 Inst.setOpcode(ARM::t2ADDri);
7016 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7018 case ARM::t2SUBri12:
7019 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7020 // mnemonic was used (not "subw"), encoding T3 is preferred.
7021 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7022 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7024 Inst.setOpcode(ARM::t2SUBri);
7025 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7028 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7029 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7030 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7031 // to encoding T1 if <Rd> is omitted."
7032 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7033 Inst.setOpcode(ARM::tADDi3);
7038 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7039 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7040 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7041 // to encoding T1 if <Rd> is omitted."
7042 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7043 Inst.setOpcode(ARM::tSUBi3);
7048 case ARM::t2SUBri: {
7049 // If the destination and first source operand are the same, and
7050 // the flags are compatible with the current IT status, use encoding T2
7051 // instead of T3. For compatibility with the system 'as'. Make sure the
7052 // wide encoding wasn't explicit.
7053 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7054 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7055 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7056 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7057 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7058 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7059 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7062 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7063 ARM::tADDi8 : ARM::tSUBi8);
7064 TmpInst.addOperand(Inst.getOperand(0));
7065 TmpInst.addOperand(Inst.getOperand(5));
7066 TmpInst.addOperand(Inst.getOperand(0));
7067 TmpInst.addOperand(Inst.getOperand(2));
7068 TmpInst.addOperand(Inst.getOperand(3));
7069 TmpInst.addOperand(Inst.getOperand(4));
7073 case ARM::t2ADDrr: {
7074 // If the destination and first source operand are the same, and
7075 // there's no setting of the flags, use encoding T2 instead of T3.
7076 // Note that this is only for ADD, not SUB. This mirrors the system
7077 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7078 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7079 Inst.getOperand(5).getReg() != 0 ||
7080 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7081 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7084 TmpInst.setOpcode(ARM::tADDhirr);
7085 TmpInst.addOperand(Inst.getOperand(0));
7086 TmpInst.addOperand(Inst.getOperand(0));
7087 TmpInst.addOperand(Inst.getOperand(2));
7088 TmpInst.addOperand(Inst.getOperand(3));
7089 TmpInst.addOperand(Inst.getOperand(4));
7093 case ARM::tADDrSP: {
7094 // If the non-SP source operand and the destination operand are not the
7095 // same, we need to use the 32-bit encoding if it's available.
7096 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7097 Inst.setOpcode(ARM::t2ADDrr);
7098 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7104 // A Thumb conditional branch outside of an IT block is a tBcc.
7105 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7106 Inst.setOpcode(ARM::tBcc);
7111 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7112 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7113 Inst.setOpcode(ARM::t2Bcc);
7118 // If the conditional is AL or we're in an IT block, we really want t2B.
7119 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7120 Inst.setOpcode(ARM::t2B);
7125 // If the conditional is AL, we really want tB.
7126 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7127 Inst.setOpcode(ARM::tB);
7132 // If the register list contains any high registers, or if the writeback
7133 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7134 // instead if we're in Thumb2. Otherwise, this should have generated
7135 // an error in validateInstruction().
7136 unsigned Rn = Inst.getOperand(0).getReg();
7137 bool hasWritebackToken =
7138 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7139 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7140 bool listContainsBase;
7141 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7142 (!listContainsBase && !hasWritebackToken) ||
7143 (listContainsBase && hasWritebackToken)) {
7144 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7145 assert (isThumbTwo());
7146 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7147 // If we're switching to the updating version, we need to insert
7148 // the writeback tied operand.
7149 if (hasWritebackToken)
7150 Inst.insert(Inst.begin(),
7151 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7156 case ARM::tSTMIA_UPD: {
7157 // If the register list contains any high registers, we need to use
7158 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7159 // should have generated an error in validateInstruction().
7160 unsigned Rn = Inst.getOperand(0).getReg();
7161 bool listContainsBase;
7162 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7163 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7164 assert (isThumbTwo());
7165 Inst.setOpcode(ARM::t2STMIA_UPD);
7171 bool listContainsBase;
7172 // If the register list contains any high registers, we need to use
7173 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7174 // should have generated an error in validateInstruction().
7175 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7177 assert (isThumbTwo());
7178 Inst.setOpcode(ARM::t2LDMIA_UPD);
7179 // Add the base register and writeback operands.
7180 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7181 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7185 bool listContainsBase;
7186 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7188 assert (isThumbTwo());
7189 Inst.setOpcode(ARM::t2STMDB_UPD);
7190 // Add the base register and writeback operands.
7191 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7192 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7196 // If we can use the 16-bit encoding and the user didn't explicitly
7197 // request the 32-bit variant, transform it here.
7198 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7199 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7200 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7201 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7202 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7203 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7204 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7205 // The operands aren't in the same order for tMOVi8...
7207 TmpInst.setOpcode(ARM::tMOVi8);
7208 TmpInst.addOperand(Inst.getOperand(0));
7209 TmpInst.addOperand(Inst.getOperand(4));
7210 TmpInst.addOperand(Inst.getOperand(1));
7211 TmpInst.addOperand(Inst.getOperand(2));
7212 TmpInst.addOperand(Inst.getOperand(3));
7219 // If we can use the 16-bit encoding and the user didn't explicitly
7220 // request the 32-bit variant, transform it here.
7221 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7222 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7223 Inst.getOperand(2).getImm() == ARMCC::AL &&
7224 Inst.getOperand(4).getReg() == ARM::CPSR &&
7225 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7226 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7227 // The operands aren't the same for tMOV[S]r... (no cc_out)
7229 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7230 TmpInst.addOperand(Inst.getOperand(0));
7231 TmpInst.addOperand(Inst.getOperand(1));
7232 TmpInst.addOperand(Inst.getOperand(2));
7233 TmpInst.addOperand(Inst.getOperand(3));
7243 // If we can use the 16-bit encoding and the user didn't explicitly
7244 // request the 32-bit variant, transform it here.
7245 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7246 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7247 Inst.getOperand(2).getImm() == 0 &&
7248 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7249 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7251 switch (Inst.getOpcode()) {
7252 default: llvm_unreachable("Illegal opcode!");
7253 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7254 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7255 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7256 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7258 // The operands aren't the same for thumb1 (no rotate operand).
7260 TmpInst.setOpcode(NewOpc);
7261 TmpInst.addOperand(Inst.getOperand(0));
7262 TmpInst.addOperand(Inst.getOperand(1));
7263 TmpInst.addOperand(Inst.getOperand(3));
7264 TmpInst.addOperand(Inst.getOperand(4));
7271 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7272 // rrx shifts and asr/lsr of #32 is encoded as 0
7273 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7275 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7276 // Shifting by zero is accepted as a vanilla 'MOVr'
7278 TmpInst.setOpcode(ARM::MOVr);
7279 TmpInst.addOperand(Inst.getOperand(0));
7280 TmpInst.addOperand(Inst.getOperand(1));
7281 TmpInst.addOperand(Inst.getOperand(3));
7282 TmpInst.addOperand(Inst.getOperand(4));
7283 TmpInst.addOperand(Inst.getOperand(5));
7296 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7297 if (SOpc == ARM_AM::rrx) return false;
7298 switch (Inst.getOpcode()) {
7299 default: llvm_unreachable("unexpected opcode!");
7300 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7301 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7302 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7303 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7304 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7305 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7307 // If the shift is by zero, use the non-shifted instruction definition.
7308 // The exception is for right shifts, where 0 == 32
7309 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7310 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7312 TmpInst.setOpcode(newOpc);
7313 TmpInst.addOperand(Inst.getOperand(0));
7314 TmpInst.addOperand(Inst.getOperand(1));
7315 TmpInst.addOperand(Inst.getOperand(2));
7316 TmpInst.addOperand(Inst.getOperand(4));
7317 TmpInst.addOperand(Inst.getOperand(5));
7318 TmpInst.addOperand(Inst.getOperand(6));
7326 // The mask bits for all but the first condition are represented as
7327 // the low bit of the condition code value implies 't'. We currently
7328 // always have 1 implies 't', so XOR toggle the bits if the low bit
7329 // of the condition code is zero.
7330 MCOperand &MO = Inst.getOperand(1);
7331 unsigned Mask = MO.getImm();
7332 unsigned OrigMask = Mask;
7333 unsigned TZ = CountTrailingZeros_32(Mask);
7334 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7335 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7336 for (unsigned i = 3; i != TZ; --i)
7341 // Set up the IT block state according to the IT instruction we just
7343 assert(!inITBlock() && "nested IT blocks?!");
7344 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7345 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7346 ITState.CurPosition = 0;
7347 ITState.FirstCond = true;
7357 // Assemblers should use the narrow encodings of these instructions when permissible.
7358 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7359 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7360 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7361 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7362 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7363 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7364 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7366 switch (Inst.getOpcode()) {
7367 default: llvm_unreachable("unexpected opcode");
7368 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7369 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7370 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7371 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7372 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7373 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7376 TmpInst.setOpcode(NewOpc);
7377 TmpInst.addOperand(Inst.getOperand(0));
7378 TmpInst.addOperand(Inst.getOperand(5));
7379 TmpInst.addOperand(Inst.getOperand(1));
7380 TmpInst.addOperand(Inst.getOperand(2));
7381 TmpInst.addOperand(Inst.getOperand(3));
7382 TmpInst.addOperand(Inst.getOperand(4));
7393 // Assemblers should use the narrow encodings of these instructions when permissible.
7394 // These instructions are special in that they are commutable, so shorter encodings
7395 // are available more often.
7396 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7397 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7398 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7399 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7400 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7401 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7402 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7403 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7405 switch (Inst.getOpcode()) {
7406 default: llvm_unreachable("unexpected opcode");
7407 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7408 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7409 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7410 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7413 TmpInst.setOpcode(NewOpc);
7414 TmpInst.addOperand(Inst.getOperand(0));
7415 TmpInst.addOperand(Inst.getOperand(5));
7416 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7417 TmpInst.addOperand(Inst.getOperand(1));
7418 TmpInst.addOperand(Inst.getOperand(2));
7420 TmpInst.addOperand(Inst.getOperand(2));
7421 TmpInst.addOperand(Inst.getOperand(1));
7423 TmpInst.addOperand(Inst.getOperand(3));
7424 TmpInst.addOperand(Inst.getOperand(4));
7434 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7435 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7436 // suffix depending on whether they're in an IT block or not.
7437 unsigned Opc = Inst.getOpcode();
7438 const MCInstrDesc &MCID = getInstDesc(Opc);
7439 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7440 assert(MCID.hasOptionalDef() &&
7441 "optionally flag setting instruction missing optional def operand");
7442 assert(MCID.NumOperands == Inst.getNumOperands() &&
7443 "operand count mismatch!");
7444 // Find the optional-def operand (cc_out).
7447 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7450 // If we're parsing Thumb1, reject it completely.
7451 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7452 return Match_MnemonicFail;
7453 // If we're parsing Thumb2, which form is legal depends on whether we're
7455 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7457 return Match_RequiresITBlock;
7458 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7460 return Match_RequiresNotITBlock;
7462 // Some high-register supporting Thumb1 encodings only allow both registers
7463 // to be from r0-r7 when in Thumb2.
7464 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7465 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7466 isARMLowRegister(Inst.getOperand(2).getReg()))
7467 return Match_RequiresThumb2;
7468 // Others only require ARMv6 or later.
7469 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7470 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7471 isARMLowRegister(Inst.getOperand(1).getReg()))
7472 return Match_RequiresV6;
7473 return Match_Success;
7476 static const char *getSubtargetFeatureName(unsigned Val);
7478 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7479 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7480 MCStreamer &Out, unsigned &ErrorInfo,
7481 bool MatchingInlineAsm) {
7483 unsigned MatchResult;
7484 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7486 switch (MatchResult) {
7489 // Context sensitive operand constraints aren't handled by the matcher,
7490 // so check them here.
7491 if (validateInstruction(Inst, Operands)) {
7492 // Still progress the IT block, otherwise one wrong condition causes
7493 // nasty cascading errors.
7494 forwardITPosition();
7498 // Some instructions need post-processing to, for example, tweak which
7499 // encoding is selected. Loop on it while changes happen so the
7500 // individual transformations can chain off each other. E.g.,
7501 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7502 while (processInstruction(Inst, Operands))
7505 // Only move forward at the very end so that everything in validate
7506 // and process gets a consistent answer about whether we're in an IT
7508 forwardITPosition();
7510 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7511 // doesn't actually encode.
7512 if (Inst.getOpcode() == ARM::ITasm)
7516 Out.EmitInstruction(Inst);
7518 case Match_MissingFeature: {
7519 assert(ErrorInfo && "Unknown missing feature!");
7520 // Special case the error message for the very common case where only
7521 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7522 std::string Msg = "instruction requires:";
7524 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7525 if (ErrorInfo & Mask) {
7527 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7531 return Error(IDLoc, Msg);
7533 case Match_InvalidOperand: {
7534 SMLoc ErrorLoc = IDLoc;
7535 if (ErrorInfo != ~0U) {
7536 if (ErrorInfo >= Operands.size())
7537 return Error(IDLoc, "too few operands for instruction");
7539 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7540 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7543 return Error(ErrorLoc, "invalid operand for instruction");
7545 case Match_MnemonicFail:
7546 return Error(IDLoc, "invalid instruction",
7547 ((ARMOperand*)Operands[0])->getLocRange());
7548 case Match_RequiresNotITBlock:
7549 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7550 case Match_RequiresITBlock:
7551 return Error(IDLoc, "instruction only valid inside IT block");
7552 case Match_RequiresV6:
7553 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7554 case Match_RequiresThumb2:
7555 return Error(IDLoc, "instruction variant requires Thumb2");
7556 case Match_ImmRange0_15: {
7557 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7558 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7559 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7563 llvm_unreachable("Implement any new match types added!");
7566 /// parseDirective parses the arm specific directives
7567 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7568 StringRef IDVal = DirectiveID.getIdentifier();
7569 if (IDVal == ".word")
7570 return parseDirectiveWord(4, DirectiveID.getLoc());
7571 else if (IDVal == ".thumb")
7572 return parseDirectiveThumb(DirectiveID.getLoc());
7573 else if (IDVal == ".arm")
7574 return parseDirectiveARM(DirectiveID.getLoc());
7575 else if (IDVal == ".thumb_func")
7576 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7577 else if (IDVal == ".code")
7578 return parseDirectiveCode(DirectiveID.getLoc());
7579 else if (IDVal == ".syntax")
7580 return parseDirectiveSyntax(DirectiveID.getLoc());
7581 else if (IDVal == ".unreq")
7582 return parseDirectiveUnreq(DirectiveID.getLoc());
7583 else if (IDVal == ".arch")
7584 return parseDirectiveArch(DirectiveID.getLoc());
7585 else if (IDVal == ".eabi_attribute")
7586 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7590 /// parseDirectiveWord
7591 /// ::= .word [ expression (, expression)* ]
7592 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7593 if (getLexer().isNot(AsmToken::EndOfStatement)) {
7595 const MCExpr *Value;
7596 if (getParser().ParseExpression(Value))
7599 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
7601 if (getLexer().is(AsmToken::EndOfStatement))
7604 // FIXME: Improve diagnostic.
7605 if (getLexer().isNot(AsmToken::Comma))
7606 return Error(L, "unexpected token in directive");
7615 /// parseDirectiveThumb
7617 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7618 if (getLexer().isNot(AsmToken::EndOfStatement))
7619 return Error(L, "unexpected token in directive");
7624 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7628 /// parseDirectiveARM
7630 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7631 if (getLexer().isNot(AsmToken::EndOfStatement))
7632 return Error(L, "unexpected token in directive");
7637 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7641 /// parseDirectiveThumbFunc
7642 /// ::= .thumbfunc symbol_name
7643 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7644 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
7645 bool isMachO = MAI.hasSubsectionsViaSymbols();
7647 bool needFuncName = true;
7649 // Darwin asm has (optionally) function name after .thumb_func direction
7652 const AsmToken &Tok = Parser.getTok();
7653 if (Tok.isNot(AsmToken::EndOfStatement)) {
7654 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7655 return Error(L, "unexpected token in .thumb_func directive");
7656 Name = Tok.getIdentifier();
7657 Parser.Lex(); // Consume the identifier token.
7658 needFuncName = false;
7662 if (getLexer().isNot(AsmToken::EndOfStatement))
7663 return Error(L, "unexpected token in directive");
7665 // Eat the end of statement and any blank lines that follow.
7666 while (getLexer().is(AsmToken::EndOfStatement))
7669 // FIXME: assuming function name will be the line following .thumb_func
7670 // We really should be checking the next symbol definition even if there's
7671 // stuff in between.
7673 Name = Parser.getTok().getIdentifier();
7676 // Mark symbol as a thumb symbol.
7677 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7678 getParser().getStreamer().EmitThumbFunc(Func);
7682 /// parseDirectiveSyntax
7683 /// ::= .syntax unified | divided
7684 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7685 const AsmToken &Tok = Parser.getTok();
7686 if (Tok.isNot(AsmToken::Identifier))
7687 return Error(L, "unexpected token in .syntax directive");
7688 StringRef Mode = Tok.getString();
7689 if (Mode == "unified" || Mode == "UNIFIED")
7691 else if (Mode == "divided" || Mode == "DIVIDED")
7692 return Error(L, "'.syntax divided' arm asssembly not supported");
7694 return Error(L, "unrecognized syntax mode in .syntax directive");
7696 if (getLexer().isNot(AsmToken::EndOfStatement))
7697 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7700 // TODO tell the MC streamer the mode
7701 // getParser().getStreamer().Emit???();
7705 /// parseDirectiveCode
7706 /// ::= .code 16 | 32
7707 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7708 const AsmToken &Tok = Parser.getTok();
7709 if (Tok.isNot(AsmToken::Integer))
7710 return Error(L, "unexpected token in .code directive");
7711 int64_t Val = Parser.getTok().getIntVal();
7717 return Error(L, "invalid operand to .code directive");
7719 if (getLexer().isNot(AsmToken::EndOfStatement))
7720 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7726 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7730 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7736 /// parseDirectiveReq
7737 /// ::= name .req registername
7738 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7739 Parser.Lex(); // Eat the '.req' token.
7741 SMLoc SRegLoc, ERegLoc;
7742 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7743 Parser.EatToEndOfStatement();
7744 return Error(SRegLoc, "register name expected");
7747 // Shouldn't be anything else.
7748 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7749 Parser.EatToEndOfStatement();
7750 return Error(Parser.getTok().getLoc(),
7751 "unexpected input in .req directive.");
7754 Parser.Lex(); // Consume the EndOfStatement
7756 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7757 return Error(SRegLoc, "redefinition of '" + Name +
7758 "' does not match original.");
7763 /// parseDirectiveUneq
7764 /// ::= .unreq registername
7765 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7766 if (Parser.getTok().isNot(AsmToken::Identifier)) {
7767 Parser.EatToEndOfStatement();
7768 return Error(L, "unexpected input in .unreq directive.");
7770 RegisterReqs.erase(Parser.getTok().getIdentifier());
7771 Parser.Lex(); // Eat the identifier.
7775 /// parseDirectiveArch
7777 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7781 /// parseDirectiveEabiAttr
7782 /// ::= .eabi_attribute int, int
7783 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7787 extern "C" void LLVMInitializeARMAsmLexer();
7789 /// Force static initialization.
7790 extern "C" void LLVMInitializeARMAsmParser() {
7791 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
7792 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
7793 LLVMInitializeARMAsmLexer();
7796 #define GET_REGISTER_MATCHER
7797 #define GET_SUBTARGET_FEATURE_NAME
7798 #define GET_MATCHER_IMPLEMENTATION
7799 #include "ARMGenAsmMatcher.inc"