1 //===-- ARMTargetTransformInfo.cpp - ARM specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// ARM target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "armtti"
19 #include "ARMTargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/CostTable.h"
23 #include "llvm/Target/TargetLowering.h"
26 // Declare the pass initialization routine locally as target-specific passes
27 // don't havve a target-wide initialization entry point, and so we rely on the
28 // pass constructor initialization.
30 void initializeARMTTIPass(PassRegistry &);
35 class ARMTTI final : public ImmutablePass, public TargetTransformInfo {
36 const ARMBaseTargetMachine *TM;
37 const ARMSubtarget *ST;
38 const ARMTargetLowering *TLI;
40 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
41 /// are set if the result needs to be inserted and/or extracted from vectors.
42 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
45 ARMTTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
46 llvm_unreachable("This pass cannot be directly constructed");
49 ARMTTI(const ARMBaseTargetMachine *TM)
50 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
51 TLI(TM->getTargetLowering()) {
52 initializeARMTTIPass(*PassRegistry::getPassRegistry());
55 void initializePass() override {
59 virtual void finalizePass() {
63 void getAnalysisUsage(AnalysisUsage &AU) const override {
64 TargetTransformInfo::getAnalysisUsage(AU);
67 /// Pass identification.
70 /// Provide necessary pointer adjustments for the two base classes.
71 void *getAdjustedAnalysisPointer(const void *ID) override {
72 if (ID == &TargetTransformInfo::ID)
73 return (TargetTransformInfo*)this;
77 /// \name Scalar TTI Implementations
79 using TargetTransformInfo::getIntImmCost;
80 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
85 /// \name Vector TTI Implementations
88 unsigned getNumberOfRegisters(bool Vector) const override {
95 if (ST->isThumb1Only())
100 unsigned getRegisterBitWidth(bool Vector) const override {
110 unsigned getMaximumUnrollFactor() const override {
111 // These are out of order CPUs:
112 if (ST->isCortexA15() || ST->isSwift())
117 unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
118 int Index, Type *SubTp) const override;
120 unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
121 Type *Src) const override;
123 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
124 Type *CondTy) const override;
126 unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
127 unsigned Index) const override;
129 unsigned getAddressComputationCost(Type *Val,
130 bool IsComplex) const override;
133 getArithmeticInstrCost(unsigned Opcode, Type *Ty,
134 OperandValueKind Op1Info = OK_AnyValue,
135 OperandValueKind Op2Info = OK_AnyValue) const override;
137 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
138 unsigned AddressSpace) const override;
142 } // end anonymous namespace
144 INITIALIZE_AG_PASS(ARMTTI, TargetTransformInfo, "armtti",
145 "ARM Target Transform Info", true, true, false)
149 llvm::createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM) {
150 return new ARMTTI(TM);
154 unsigned ARMTTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
155 assert(Ty->isIntegerTy());
157 unsigned Bits = Ty->getPrimitiveSizeInBits();
158 if (Bits == 0 || Bits > 32)
161 int32_t SImmVal = Imm.getSExtValue();
162 uint32_t ZImmVal = Imm.getZExtValue();
163 if (!ST->isThumb()) {
164 if ((SImmVal >= 0 && SImmVal < 65536) ||
165 (ARM_AM::getSOImmVal(ZImmVal) != -1) ||
166 (ARM_AM::getSOImmVal(~ZImmVal) != -1))
168 return ST->hasV6T2Ops() ? 2 : 3;
170 if (ST->isThumb2()) {
171 if ((SImmVal >= 0 && SImmVal < 65536) ||
172 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
173 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
175 return ST->hasV6T2Ops() ? 2 : 3;
178 if (SImmVal >= 0 && SImmVal < 256)
180 if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
182 // Load from constantpool.
186 unsigned ARMTTI::getCastInstrCost(unsigned Opcode, Type *Dst,
188 int ISD = TLI->InstructionOpcodeToISD(Opcode);
189 assert(ISD && "Invalid opcode");
191 // Single to/from double precision conversions.
192 static const CostTblEntry<MVT::SimpleValueType> NEONFltDblTbl[] = {
193 // Vector fptrunc/fpext conversions.
194 { ISD::FP_ROUND, MVT::v2f64, 2 },
195 { ISD::FP_EXTEND, MVT::v2f32, 2 },
196 { ISD::FP_EXTEND, MVT::v4f32, 4 }
199 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
200 ISD == ISD::FP_EXTEND)) {
201 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
202 int Idx = CostTableLookup(NEONFltDblTbl, ISD, LT.second);
204 return LT.first * NEONFltDblTbl[Idx].Cost;
207 EVT SrcTy = TLI->getValueType(Src);
208 EVT DstTy = TLI->getValueType(Dst);
210 if (!SrcTy.isSimple() || !DstTy.isSimple())
211 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
213 // Some arithmetic, load and store operations have specific instructions
214 // to cast up/down their types automatically at no extra cost.
215 // TODO: Get these tables to know at least what the related operations are.
216 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
217 NEONVectorConversionTbl[] = {
218 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
219 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
220 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
221 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
222 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
223 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
225 // The number of vmovl instructions for the extension.
226 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
227 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
228 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
229 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
230 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
231 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
232 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
233 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
234 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
235 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
237 // Operations that we legalize using splitting.
238 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
239 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
241 // Vector float <-> i32 conversions.
242 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
243 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
245 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
246 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
247 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
248 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
249 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
250 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
251 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
252 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
253 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
254 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
255 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
256 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
257 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
258 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
259 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
260 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
261 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
262 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
263 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
264 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
266 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
267 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
268 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
269 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 },
270 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
271 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
273 // Vector double <-> i32 conversions.
274 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
275 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
277 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
278 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
279 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
280 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
281 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
282 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
284 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
285 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
286 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
287 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 },
288 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
289 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 }
292 if (SrcTy.isVector() && ST->hasNEON()) {
293 int Idx = ConvertCostTableLookup(NEONVectorConversionTbl, ISD,
294 DstTy.getSimpleVT(), SrcTy.getSimpleVT());
296 return NEONVectorConversionTbl[Idx].Cost;
299 // Scalar float to integer conversions.
300 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
301 NEONFloatConversionTbl[] = {
302 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
303 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
304 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
305 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 },
306 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
307 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
308 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 },
309 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 },
310 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
311 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
312 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 },
313 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 },
314 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 },
315 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 },
316 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 },
317 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 2 },
318 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 },
319 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 },
320 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 10 },
321 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 10 }
323 if (SrcTy.isFloatingPoint() && ST->hasNEON()) {
324 int Idx = ConvertCostTableLookup(NEONFloatConversionTbl, ISD,
325 DstTy.getSimpleVT(), SrcTy.getSimpleVT());
327 return NEONFloatConversionTbl[Idx].Cost;
330 // Scalar integer to float conversions.
331 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
332 NEONIntegerConversionTbl[] = {
333 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 },
334 { ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 },
335 { ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 },
336 { ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 },
337 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 },
338 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 },
339 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 },
340 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 },
341 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 },
342 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 },
343 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 },
344 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 },
345 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 },
346 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 },
347 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 },
348 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 },
349 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 },
350 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 },
351 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 10 },
352 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 10 }
355 if (SrcTy.isInteger() && ST->hasNEON()) {
356 int Idx = ConvertCostTableLookup(NEONIntegerConversionTbl, ISD,
357 DstTy.getSimpleVT(), SrcTy.getSimpleVT());
359 return NEONIntegerConversionTbl[Idx].Cost;
362 // Scalar integer conversion costs.
363 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
364 ARMIntegerConversionTbl[] = {
365 // i16 -> i64 requires two dependent operations.
366 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 },
368 // Truncates on i64 are assumed to be free.
369 { ISD::TRUNCATE, MVT::i32, MVT::i64, 0 },
370 { ISD::TRUNCATE, MVT::i16, MVT::i64, 0 },
371 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 },
372 { ISD::TRUNCATE, MVT::i1, MVT::i64, 0 }
375 if (SrcTy.isInteger()) {
376 int Idx = ConvertCostTableLookup(ARMIntegerConversionTbl, ISD,
377 DstTy.getSimpleVT(), SrcTy.getSimpleVT());
379 return ARMIntegerConversionTbl[Idx].Cost;
382 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
385 unsigned ARMTTI::getVectorInstrCost(unsigned Opcode, Type *ValTy,
386 unsigned Index) const {
387 // Penalize inserting into an D-subregister. We end up with a three times
388 // lower estimated throughput on swift.
390 Opcode == Instruction::InsertElement &&
391 ValTy->isVectorTy() &&
392 ValTy->getScalarSizeInBits() <= 32)
395 return TargetTransformInfo::getVectorInstrCost(Opcode, ValTy, Index);
398 unsigned ARMTTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
399 Type *CondTy) const {
401 int ISD = TLI->InstructionOpcodeToISD(Opcode);
402 // On NEON a a vector select gets lowered to vbsl.
403 if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
404 // Lowering of some vector selects is currently far from perfect.
405 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
406 NEONVectorSelectTbl[] = {
407 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 2*16 + 1 + 3*1 + 4*1 },
408 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 },
409 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 },
410 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
411 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
412 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 }
415 EVT SelCondTy = TLI->getValueType(CondTy);
416 EVT SelValTy = TLI->getValueType(ValTy);
417 if (SelCondTy.isSimple() && SelValTy.isSimple()) {
418 int Idx = ConvertCostTableLookup(NEONVectorSelectTbl, ISD,
419 SelCondTy.getSimpleVT(),
420 SelValTy.getSimpleVT());
422 return NEONVectorSelectTbl[Idx].Cost;
425 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
429 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
432 unsigned ARMTTI::getAddressComputationCost(Type *Ty, bool IsComplex) const {
433 // Address computations in vectorized code with non-consecutive addresses will
434 // likely result in more instructions compared to scalar code where the
435 // computation can more often be merged into the index mode. The resulting
436 // extra micro-ops can significantly decrease throughput.
437 unsigned NumVectorInstToHideOverhead = 10;
439 if (Ty->isVectorTy() && IsComplex)
440 return NumVectorInstToHideOverhead;
442 // In many cases the address computation is not merged into the instruction
447 unsigned ARMTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
449 // We only handle costs of reverse shuffles for now.
450 if (Kind != SK_Reverse)
451 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
453 static const CostTblEntry<MVT::SimpleValueType> NEONShuffleTbl[] = {
454 // Reverse shuffle cost one instruction if we are shuffling within a double
455 // word (vrev) or two if we shuffle a quad word (vrev, vext).
456 { ISD::VECTOR_SHUFFLE, MVT::v2i32, 1 },
457 { ISD::VECTOR_SHUFFLE, MVT::v2f32, 1 },
458 { ISD::VECTOR_SHUFFLE, MVT::v2i64, 1 },
459 { ISD::VECTOR_SHUFFLE, MVT::v2f64, 1 },
461 { ISD::VECTOR_SHUFFLE, MVT::v4i32, 2 },
462 { ISD::VECTOR_SHUFFLE, MVT::v4f32, 2 },
463 { ISD::VECTOR_SHUFFLE, MVT::v8i16, 2 },
464 { ISD::VECTOR_SHUFFLE, MVT::v16i8, 2 }
467 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
469 int Idx = CostTableLookup(NEONShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
471 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
473 return LT.first * NEONShuffleTbl[Idx].Cost;
476 unsigned ARMTTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
477 OperandValueKind Op1Info,
478 OperandValueKind Op2Info) const {
480 int ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
481 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
483 const unsigned FunctionCallDivCost = 20;
484 const unsigned ReciprocalDivCost = 10;
485 static const CostTblEntry<MVT::SimpleValueType> CostTbl[] = {
487 // These costs are somewhat random. Choose a cost of 20 to indicate that
488 // vectorizing devision (added function call) is going to be very expensive.
489 // Double registers types.
490 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost},
491 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost},
492 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost},
493 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost},
494 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost},
495 { ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost},
496 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost},
497 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost},
498 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost},
499 { ISD::UDIV, MVT::v4i16, ReciprocalDivCost},
500 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost},
501 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost},
502 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost},
503 { ISD::UDIV, MVT::v8i8, ReciprocalDivCost},
504 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost},
505 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost},
506 // Quad register types.
507 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
508 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost},
509 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
510 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost},
511 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost},
512 { ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost},
513 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost},
514 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost},
515 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost},
516 { ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost},
517 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost},
518 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost},
519 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
520 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost},
521 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost},
522 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
529 Idx = CostTableLookup(CostTbl, ISDOpcode, LT.second);
532 return LT.first * CostTbl[Idx].Cost;
535 TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info);
537 // This is somewhat of a hack. The problem that we are facing is that SROA
538 // creates a sequence of shift, and, or instructions to construct values.
539 // These sequences are recognized by the ISel and have zero-cost. Not so for
540 // the vectorized code. Because we have support for v2i64 but not i64 those
541 // sequences look particularly beneficial to vectorize.
542 // To work around this we increase the cost of v2i64 operations to make them
543 // seem less beneficial.
544 if (LT.second == MVT::v2i64 &&
545 Op2Info == TargetTransformInfo::OK_UniformConstantValue)
551 unsigned ARMTTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
552 unsigned AddressSpace) const {
553 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
555 if (Src->isVectorTy() && Alignment != 16 &&
556 Src->getVectorElementType()->isDoubleTy()) {
557 // Unaligned loads/stores are extremely inefficient.
558 // We need 4 uops for vst.1/vld.1 vs 1uop for vldr/vstr.