1 //===-- ARMTargetTransformInfo.cpp - ARM specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// ARM target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
18 #include "ARMTargetMachine.h"
19 #include "llvm/Analysis/TargetTransformInfo.h"
20 #include "llvm/CodeGen/BasicTTIImpl.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/CostTable.h"
23 #include "llvm/Target/TargetLowering.h"
26 #define DEBUG_TYPE "armtti"
30 class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
31 typedef BasicTTIImplBase<ARMTTIImpl> BaseT;
32 typedef TargetTransformInfo TTI;
34 const ARMSubtarget *ST;
35 const ARMTargetLowering *TLI;
37 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
38 /// are set if the result needs to be inserted and/or extracted from vectors.
39 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
42 explicit ARMTTIImpl(const ARMBaseTargetMachine *TM = nullptr)
43 : BaseT(TM), ST(TM ? TM->getSubtargetImpl() : nullptr),
44 TLI(ST ? ST->getTargetLowering() : nullptr) {}
46 // Provide value semantics. MSVC requires that we spell all of these out.
47 ARMTTIImpl(const ARMTTIImpl &Arg)
48 : BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
49 ARMTTIImpl(ARMTTIImpl &&Arg)
50 : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
51 TLI(std::move(Arg.TLI)) {}
52 ARMTTIImpl &operator=(const ARMTTIImpl &RHS) {
53 BaseT::operator=(static_cast<const BaseT &>(RHS));
58 ARMTTIImpl &operator=(ARMTTIImpl &&RHS) {
59 BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
60 ST = std::move(RHS.ST);
61 TLI = std::move(RHS.TLI);
65 /// \name Scalar TTI Implementations
68 using BaseT::getIntImmCost;
69 unsigned getIntImmCost(const APInt &Imm, Type *Ty);
74 /// \name Vector TTI Implementations
77 unsigned getNumberOfRegisters(bool Vector) {
84 if (ST->isThumb1Only())
89 unsigned getRegisterBitWidth(bool Vector) {
99 unsigned getMaxInterleaveFactor() {
100 // These are out of order CPUs:
101 if (ST->isCortexA15() || ST->isSwift())
106 unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
109 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
111 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
113 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
115 unsigned getAddressComputationCost(Type *Val, bool IsComplex);
117 unsigned getArithmeticInstrCost(
118 unsigned Opcode, Type *Ty,
119 TTI::OperandValueKind Op1Info = TTI::OK_AnyValue,
120 TTI::OperandValueKind Op2Info = TTI::OK_AnyValue,
121 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
122 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
124 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
125 unsigned AddressSpace);
130 } // end anonymous namespace
133 llvm::createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM) {
134 return new TargetTransformInfoWrapperPass(ARMTTIImpl(TM));
137 unsigned ARMTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
138 assert(Ty->isIntegerTy());
140 unsigned Bits = Ty->getPrimitiveSizeInBits();
141 if (Bits == 0 || Bits > 32)
144 int32_t SImmVal = Imm.getSExtValue();
145 uint32_t ZImmVal = Imm.getZExtValue();
146 if (!ST->isThumb()) {
147 if ((SImmVal >= 0 && SImmVal < 65536) ||
148 (ARM_AM::getSOImmVal(ZImmVal) != -1) ||
149 (ARM_AM::getSOImmVal(~ZImmVal) != -1))
151 return ST->hasV6T2Ops() ? 2 : 3;
153 if (ST->isThumb2()) {
154 if ((SImmVal >= 0 && SImmVal < 65536) ||
155 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
156 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
158 return ST->hasV6T2Ops() ? 2 : 3;
161 if (SImmVal >= 0 && SImmVal < 256)
163 if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
165 // Load from constantpool.
169 unsigned ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) {
170 int ISD = TLI->InstructionOpcodeToISD(Opcode);
171 assert(ISD && "Invalid opcode");
173 // Single to/from double precision conversions.
174 static const CostTblEntry<MVT::SimpleValueType> NEONFltDblTbl[] = {
175 // Vector fptrunc/fpext conversions.
176 { ISD::FP_ROUND, MVT::v2f64, 2 },
177 { ISD::FP_EXTEND, MVT::v2f32, 2 },
178 { ISD::FP_EXTEND, MVT::v4f32, 4 }
181 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
182 ISD == ISD::FP_EXTEND)) {
183 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
184 int Idx = CostTableLookup(NEONFltDblTbl, ISD, LT.second);
186 return LT.first * NEONFltDblTbl[Idx].Cost;
189 EVT SrcTy = TLI->getValueType(Src);
190 EVT DstTy = TLI->getValueType(Dst);
192 if (!SrcTy.isSimple() || !DstTy.isSimple())
193 return BaseT::getCastInstrCost(Opcode, Dst, Src);
195 // Some arithmetic, load and store operations have specific instructions
196 // to cast up/down their types automatically at no extra cost.
197 // TODO: Get these tables to know at least what the related operations are.
198 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
199 NEONVectorConversionTbl[] = {
200 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
201 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
202 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
203 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
204 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
205 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
207 // The number of vmovl instructions for the extension.
208 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
209 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
210 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
211 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
212 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
213 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
214 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
215 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
216 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
217 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
219 // Operations that we legalize using splitting.
220 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
221 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
223 // Vector float <-> i32 conversions.
224 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
225 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
227 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
228 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
229 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
230 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
231 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
232 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
233 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
234 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
235 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
236 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
237 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
238 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
239 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
240 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
241 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
242 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
243 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
244 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
245 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
246 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
248 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
249 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
250 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
251 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 },
252 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
253 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
255 // Vector double <-> i32 conversions.
256 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
257 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
259 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
260 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
261 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
262 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
263 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
264 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
266 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
267 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
268 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
269 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 },
270 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
271 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 }
274 if (SrcTy.isVector() && ST->hasNEON()) {
275 int Idx = ConvertCostTableLookup(NEONVectorConversionTbl, ISD,
276 DstTy.getSimpleVT(), SrcTy.getSimpleVT());
278 return NEONVectorConversionTbl[Idx].Cost;
281 // Scalar float to integer conversions.
282 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
283 NEONFloatConversionTbl[] = {
284 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
285 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
286 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
287 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 },
288 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
289 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
290 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 },
291 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 },
292 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
293 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
294 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 },
295 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 },
296 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 },
297 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 },
298 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 },
299 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 2 },
300 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 },
301 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 },
302 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 10 },
303 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 10 }
305 if (SrcTy.isFloatingPoint() && ST->hasNEON()) {
306 int Idx = ConvertCostTableLookup(NEONFloatConversionTbl, ISD,
307 DstTy.getSimpleVT(), SrcTy.getSimpleVT());
309 return NEONFloatConversionTbl[Idx].Cost;
312 // Scalar integer to float conversions.
313 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
314 NEONIntegerConversionTbl[] = {
315 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 },
316 { ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 },
317 { ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 },
318 { ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 },
319 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 },
320 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 },
321 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 },
322 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 },
323 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 },
324 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 },
325 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 },
326 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 },
327 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 },
328 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 },
329 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 },
330 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 },
331 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 },
332 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 },
333 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 10 },
334 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 10 }
337 if (SrcTy.isInteger() && ST->hasNEON()) {
338 int Idx = ConvertCostTableLookup(NEONIntegerConversionTbl, ISD,
339 DstTy.getSimpleVT(), SrcTy.getSimpleVT());
341 return NEONIntegerConversionTbl[Idx].Cost;
344 // Scalar integer conversion costs.
345 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
346 ARMIntegerConversionTbl[] = {
347 // i16 -> i64 requires two dependent operations.
348 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 },
350 // Truncates on i64 are assumed to be free.
351 { ISD::TRUNCATE, MVT::i32, MVT::i64, 0 },
352 { ISD::TRUNCATE, MVT::i16, MVT::i64, 0 },
353 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 },
354 { ISD::TRUNCATE, MVT::i1, MVT::i64, 0 }
357 if (SrcTy.isInteger()) {
358 int Idx = ConvertCostTableLookup(ARMIntegerConversionTbl, ISD,
359 DstTy.getSimpleVT(), SrcTy.getSimpleVT());
361 return ARMIntegerConversionTbl[Idx].Cost;
364 return BaseT::getCastInstrCost(Opcode, Dst, Src);
367 unsigned ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
369 // Penalize inserting into an D-subregister. We end up with a three times
370 // lower estimated throughput on swift.
372 Opcode == Instruction::InsertElement &&
373 ValTy->isVectorTy() &&
374 ValTy->getScalarSizeInBits() <= 32)
377 // Cross-class copies are expensive on many microarchitectures,
378 // so assume they are expensive by default.
379 if ((Opcode == Instruction::InsertElement ||
380 Opcode == Instruction::ExtractElement) &&
381 ValTy->getVectorElementType()->isIntegerTy())
384 return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
387 unsigned ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
390 int ISD = TLI->InstructionOpcodeToISD(Opcode);
391 // On NEON a a vector select gets lowered to vbsl.
392 if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
393 // Lowering of some vector selects is currently far from perfect.
394 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
395 NEONVectorSelectTbl[] = {
396 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 2*16 + 1 + 3*1 + 4*1 },
397 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 },
398 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 },
399 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
400 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
401 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 }
404 EVT SelCondTy = TLI->getValueType(CondTy);
405 EVT SelValTy = TLI->getValueType(ValTy);
406 if (SelCondTy.isSimple() && SelValTy.isSimple()) {
407 int Idx = ConvertCostTableLookup(NEONVectorSelectTbl, ISD,
408 SelCondTy.getSimpleVT(),
409 SelValTy.getSimpleVT());
411 return NEONVectorSelectTbl[Idx].Cost;
414 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
418 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy);
421 unsigned ARMTTIImpl::getAddressComputationCost(Type *Ty, bool IsComplex) {
422 // Address computations in vectorized code with non-consecutive addresses will
423 // likely result in more instructions compared to scalar code where the
424 // computation can more often be merged into the index mode. The resulting
425 // extra micro-ops can significantly decrease throughput.
426 unsigned NumVectorInstToHideOverhead = 10;
428 if (Ty->isVectorTy() && IsComplex)
429 return NumVectorInstToHideOverhead;
431 // In many cases the address computation is not merged into the instruction
436 unsigned ARMTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
438 // We only handle costs of reverse and alternate shuffles for now.
439 if (Kind != TTI::SK_Reverse && Kind != TTI::SK_Alternate)
440 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
442 if (Kind == TTI::SK_Reverse) {
443 static const CostTblEntry<MVT::SimpleValueType> NEONShuffleTbl[] = {
444 // Reverse shuffle cost one instruction if we are shuffling within a
445 // double word (vrev) or two if we shuffle a quad word (vrev, vext).
446 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1},
447 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
448 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
449 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1},
451 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2},
452 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
453 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 2},
454 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 2}};
456 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
458 int Idx = CostTableLookup(NEONShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
460 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
462 return LT.first * NEONShuffleTbl[Idx].Cost;
464 if (Kind == TTI::SK_Alternate) {
465 static const CostTblEntry<MVT::SimpleValueType> NEONAltShuffleTbl[] = {
466 // Alt shuffle cost table for ARM. Cost is the number of instructions
467 // required to create the shuffled vector.
469 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
470 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
471 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1},
472 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1},
474 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2},
475 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
476 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 2},
478 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 16},
480 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 32}};
482 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
484 CostTableLookup(NEONAltShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
486 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
487 return LT.first * NEONAltShuffleTbl[Idx].Cost;
489 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
492 unsigned ARMTTIImpl::getArithmeticInstrCost(
493 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info,
494 TTI::OperandValueKind Op2Info, TTI::OperandValueProperties Opd1PropInfo,
495 TTI::OperandValueProperties Opd2PropInfo) {
497 int ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
498 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
500 const unsigned FunctionCallDivCost = 20;
501 const unsigned ReciprocalDivCost = 10;
502 static const CostTblEntry<MVT::SimpleValueType> CostTbl[] = {
504 // These costs are somewhat random. Choose a cost of 20 to indicate that
505 // vectorizing devision (added function call) is going to be very expensive.
506 // Double registers types.
507 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost},
508 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost},
509 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost},
510 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost},
511 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost},
512 { ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost},
513 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost},
514 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost},
515 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost},
516 { ISD::UDIV, MVT::v4i16, ReciprocalDivCost},
517 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost},
518 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost},
519 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost},
520 { ISD::UDIV, MVT::v8i8, ReciprocalDivCost},
521 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost},
522 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost},
523 // Quad register types.
524 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
525 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost},
526 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
527 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost},
528 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost},
529 { ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost},
530 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost},
531 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost},
532 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost},
533 { ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost},
534 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost},
535 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost},
536 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
537 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost},
538 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost},
539 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
546 Idx = CostTableLookup(CostTbl, ISDOpcode, LT.second);
549 return LT.first * CostTbl[Idx].Cost;
551 unsigned Cost = BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info,
552 Opd1PropInfo, Opd2PropInfo);
554 // This is somewhat of a hack. The problem that we are facing is that SROA
555 // creates a sequence of shift, and, or instructions to construct values.
556 // These sequences are recognized by the ISel and have zero-cost. Not so for
557 // the vectorized code. Because we have support for v2i64 but not i64 those
558 // sequences look particularly beneficial to vectorize.
559 // To work around this we increase the cost of v2i64 operations to make them
560 // seem less beneficial.
561 if (LT.second == MVT::v2i64 &&
562 Op2Info == TargetTransformInfo::OK_UniformConstantValue)
568 unsigned ARMTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
570 unsigned AddressSpace) {
571 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
573 if (Src->isVectorTy() && Alignment != 16 &&
574 Src->getVectorElementType()->isDoubleTy()) {
575 // Unaligned loads/stores are extremely inefficient.
576 // We need 4 uops for vst.1/vld.1 vs 1uop for vldr/vstr.