1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
17 #include "ARMFrameLowering.h"
18 #include "ARMISelLowering.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMJITInfo.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "ARMSubtarget.h"
23 #include "Thumb1FrameLowering.h"
24 #include "Thumb1InstrInfo.h"
25 #include "Thumb2InstrInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/Target/TargetMachine.h"
32 class ARMBaseTargetMachine : public LLVMTargetMachine {
34 ARMSubtarget Subtarget;
40 ARMBaseTargetMachine(const Target &T, StringRef TT,
41 StringRef CPU, StringRef FS,
42 const TargetOptions &Options,
43 Reloc::Model RM, CodeModel::Model CM,
47 ARMJITInfo *getJITInfo() override { return &JITInfo; }
48 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
49 const ARMTargetLowering *getTargetLowering() const override {
50 // Implemented by derived classes
51 llvm_unreachable("getTargetLowering not implemented");
53 const InstrItineraryData *getInstrItineraryData() const override {
54 return &getSubtargetImpl()->getInstrItineraryData();
56 const DataLayout *getDataLayout() const override {
57 return getSubtargetImpl()->getDataLayout();
59 /// \brief Register ARM analysis passes with a pass manager.
60 void addAnalysisPasses(PassManagerBase &PM) override;
62 // Pass Pipeline Configuration
63 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
65 bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE) override;
68 /// ARMTargetMachine - ARM target machine.
70 class ARMTargetMachine : public ARMBaseTargetMachine {
71 virtual void anchor();
72 ARMInstrInfo InstrInfo;
73 ARMTargetLowering TLInfo;
74 ARMFrameLowering FrameLowering;
76 ARMTargetMachine(const Target &T, StringRef TT,
77 StringRef CPU, StringRef FS,
78 const TargetOptions &Options,
79 Reloc::Model RM, CodeModel::Model CM,
83 const ARMRegisterInfo *getRegisterInfo() const override {
84 return &InstrInfo.getRegisterInfo();
87 const ARMTargetLowering *getTargetLowering() const override {
91 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
92 return getSubtargetImpl()->getSelectionDAGInfo();
94 const ARMFrameLowering *getFrameLowering() const override {
95 return &FrameLowering;
97 const ARMInstrInfo *getInstrInfo() const override { return &InstrInfo; }
100 /// ARMLETargetMachine - ARM little endian target machine.
102 class ARMLETargetMachine : public ARMTargetMachine {
103 void anchor() override;
105 ARMLETargetMachine(const Target &T, StringRef TT,
106 StringRef CPU, StringRef FS, const TargetOptions &Options,
107 Reloc::Model RM, CodeModel::Model CM,
108 CodeGenOpt::Level OL);
111 /// ARMBETargetMachine - ARM big endian target machine.
113 class ARMBETargetMachine : public ARMTargetMachine {
114 void anchor() override;
116 ARMBETargetMachine(const Target &T, StringRef TT,
117 StringRef CPU, StringRef FS, const TargetOptions &Options,
118 Reloc::Model RM, CodeModel::Model CM,
119 CodeGenOpt::Level OL);
122 /// ThumbTargetMachine - Thumb target machine.
123 /// Due to the way architectures are handled, this represents both
124 /// Thumb-1 and Thumb-2.
126 class ThumbTargetMachine : public ARMBaseTargetMachine {
127 virtual void anchor();
128 // Either Thumb1InstrInfo or Thumb2InstrInfo.
129 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
130 ARMTargetLowering TLInfo;
131 // Either Thumb1FrameLowering or ARMFrameLowering.
132 std::unique_ptr<ARMFrameLowering> FrameLowering;
134 ThumbTargetMachine(const Target &T, StringRef TT,
135 StringRef CPU, StringRef FS,
136 const TargetOptions &Options,
137 Reloc::Model RM, CodeModel::Model CM,
138 CodeGenOpt::Level OL,
141 /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
142 const ARMBaseRegisterInfo *getRegisterInfo() const override {
143 return &InstrInfo->getRegisterInfo();
146 const ARMTargetLowering *getTargetLowering() const override {
150 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
151 return getSubtargetImpl()->getSelectionDAGInfo();
154 /// returns either Thumb1InstrInfo or Thumb2InstrInfo
155 const ARMBaseInstrInfo *getInstrInfo() const override {
156 return InstrInfo.get();
158 /// returns either Thumb1FrameLowering or ARMFrameLowering
159 const ARMFrameLowering *getFrameLowering() const override {
160 return FrameLowering.get();
164 /// ThumbLETargetMachine - Thumb little endian target machine.
166 class ThumbLETargetMachine : public ThumbTargetMachine {
167 void anchor() override;
169 ThumbLETargetMachine(const Target &T, StringRef TT,
170 StringRef CPU, StringRef FS, const TargetOptions &Options,
171 Reloc::Model RM, CodeModel::Model CM,
172 CodeGenOpt::Level OL);
175 /// ThumbBETargetMachine - Thumb big endian target machine.
177 class ThumbBETargetMachine : public ThumbTargetMachine {
178 void anchor() override;
180 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
181 StringRef FS, const TargetOptions &Options,
182 Reloc::Model RM, CodeModel::Model CM,
183 CodeGenOpt::Level OL);
186 } // end namespace llvm