1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "ARMTargetMachine.h"
15 #include "ARMFrameLowering.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Transforms/Scalar.h"
27 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
28 cl::desc("Inhibit optimization of S->D register accesses on A15"),
32 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
33 cl::desc("Run SimplifyCFG after expanding atomic operations"
34 " to make use of cmpxchg flow-based information"),
37 extern "C" void LLVMInitializeARMTarget() {
38 // Register the target.
39 RegisterTargetMachine<ARMLETargetMachine> X(TheARMLETarget);
40 RegisterTargetMachine<ARMBETargetMachine> Y(TheARMBETarget);
41 RegisterTargetMachine<ThumbLETargetMachine> A(TheThumbLETarget);
42 RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);
46 /// TargetMachine ctor - Create an ARM architecture model.
48 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
49 StringRef CPU, StringRef FS,
50 const TargetOptions &Options,
51 Reloc::Model RM, CodeModel::Model CM,
54 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
55 Subtarget(TT, CPU, FS, isLittle, Options),
56 InstrItins(Subtarget.getInstrItineraryData()) {
58 // Default to triple-appropriate float ABI
59 if (Options.FloatABIType == FloatABI::Default)
60 this->Options.FloatABIType =
61 Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
64 void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
65 // Add first the target-independent BasicTTI pass, then our ARM pass. This
66 // allows the ARM pass to delegate to the target independent layer when
68 PM.add(createBasicTargetTransformInfoPass(this));
69 PM.add(createARMTargetTransformInfoPass(this));
73 void ARMTargetMachine::anchor() { }
75 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
76 StringRef CPU, StringRef FS,
77 const TargetOptions &Options,
78 Reloc::Model RM, CodeModel::Model CM,
81 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle),
84 FrameLowering(Subtarget) {
86 if (!Subtarget.hasARMOps())
87 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
88 "support ARM mode execution!");
91 void ARMLETargetMachine::anchor() { }
94 ARMLETargetMachine(const Target &T, StringRef TT,
95 StringRef CPU, StringRef FS, const TargetOptions &Options,
96 Reloc::Model RM, CodeModel::Model CM,
98 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
100 void ARMBETargetMachine::anchor() { }
103 ARMBETargetMachine(const Target &T, StringRef TT,
104 StringRef CPU, StringRef FS, const TargetOptions &Options,
105 Reloc::Model RM, CodeModel::Model CM,
106 CodeGenOpt::Level OL)
107 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
109 void ThumbTargetMachine::anchor() { }
111 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
112 StringRef CPU, StringRef FS,
113 const TargetOptions &Options,
114 Reloc::Model RM, CodeModel::Model CM,
115 CodeGenOpt::Level OL,
117 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle),
118 InstrInfo(Subtarget.hasThumb2()
119 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
120 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
122 FrameLowering(Subtarget.hasThumb2()
123 ? new ARMFrameLowering(Subtarget)
124 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
128 void ThumbLETargetMachine::anchor() { }
130 ThumbLETargetMachine::
131 ThumbLETargetMachine(const Target &T, StringRef TT,
132 StringRef CPU, StringRef FS, const TargetOptions &Options,
133 Reloc::Model RM, CodeModel::Model CM,
134 CodeGenOpt::Level OL)
135 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
137 void ThumbBETargetMachine::anchor() { }
139 ThumbBETargetMachine::
140 ThumbBETargetMachine(const Target &T, StringRef TT,
141 StringRef CPU, StringRef FS, const TargetOptions &Options,
142 Reloc::Model RM, CodeModel::Model CM,
143 CodeGenOpt::Level OL)
144 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
147 /// ARM Code Generator Pass Configuration Options.
148 class ARMPassConfig : public TargetPassConfig {
150 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
151 : TargetPassConfig(TM, PM) {}
153 ARMBaseTargetMachine &getARMTargetMachine() const {
154 return getTM<ARMBaseTargetMachine>();
157 const ARMSubtarget &getARMSubtarget() const {
158 return *getARMTargetMachine().getSubtargetImpl();
161 void addIRPasses() override;
162 bool addPreISel() override;
163 bool addInstSelector() override;
164 bool addPreRegAlloc() override;
165 bool addPreSched2() override;
166 bool addPreEmitPass() override;
170 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
171 return new ARMPassConfig(this, PM);
174 void ARMPassConfig::addIRPasses() {
175 const ARMSubtarget *Subtarget = &getARMSubtarget();
176 if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
177 addPass(createAtomicExpandLoadLinkedPass(TM));
179 // Cmpxchg instructions are often used with a subsequent comparison to
180 // determine whether it succeeded. We can exploit existing control-flow in
181 // ldrex/strex loops to simplify this, but it needs tidying up.
182 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
183 addPass(createCFGSimplificationPass());
186 TargetPassConfig::addIRPasses();
189 bool ARMPassConfig::addPreISel() {
190 if (TM->getOptLevel() != CodeGenOpt::None)
191 addPass(createGlobalMergePass(TM));
196 bool ARMPassConfig::addInstSelector() {
197 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
199 const ARMSubtarget *Subtarget = &getARMSubtarget();
200 if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() &&
201 TM->Options.EnableFastISel)
202 addPass(createARMGlobalBaseRegPass());
206 bool ARMPassConfig::addPreRegAlloc() {
207 // FIXME: Temporarily disabling Thumb-1 pre-RA Load/Store optimization pass
208 if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
209 addPass(createARMLoadStoreOptimizationPass(true));
210 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
211 addPass(createMLxExpansionPass());
212 // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
213 // enabled when NEON is available.
214 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
215 getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
216 addPass(createA15SDOptimizerPass());
221 bool ARMPassConfig::addPreSched2() {
222 if (getOptLevel() != CodeGenOpt::None) {
223 // FIXME: Temporarily disabling Thumb-1 post-RA Load/Store optimization pass
224 if (!getARMSubtarget().isThumb1Only()) {
225 addPass(createARMLoadStoreOptimizationPass());
226 printAndVerify("After ARM load / store optimizer");
229 if (getARMSubtarget().hasNEON())
230 addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
233 // Expand some pseudo instructions into multiple instructions to allow
234 // proper scheduling.
235 addPass(createARMExpandPseudoPass());
237 if (getOptLevel() != CodeGenOpt::None) {
238 if (!getARMSubtarget().isThumb1Only()) {
239 // in v8, IfConversion depends on Thumb instruction widths
240 if (getARMSubtarget().restrictIT() &&
241 !getARMSubtarget().prefers32BitThumb())
242 addPass(createThumb2SizeReductionPass());
243 addPass(&IfConverterID);
246 if (getARMSubtarget().isThumb2())
247 addPass(createThumb2ITBlockPass());
252 bool ARMPassConfig::addPreEmitPass() {
253 if (getARMSubtarget().isThumb2()) {
254 if (!getARMSubtarget().prefers32BitThumb())
255 addPass(createThumb2SizeReductionPass());
257 // Constant island pass work on unbundled instructions.
258 addPass(&UnpackMachineBundlesID);
261 addPass(createARMOptimizeBarriersPass());
262 addPass(createARMConstantIslandPass());
267 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
268 JITCodeEmitter &JCE) {
269 // Machine code emitter pass for ARM.
270 PM.add(createARMJITCodeEmitterPass(*this, JCE));