1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "MCTargetDesc/ARMMCTargetDesc.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCInstrItineraries.h"
20 #include "llvm/Target/TargetSubtargetInfo.h"
23 #define GET_SUBTARGETINFO_HEADER
24 #include "ARMGenSubtargetInfo.inc"
30 class ARMSubtarget : public ARMGenSubtargetInfo {
32 enum ARMProcFamilyEnum {
33 Others, CortexA5, CortexA8, CortexA9, CortexA15, CortexR5, Swift
36 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
37 ARMProcFamilyEnum ARMProcFamily;
39 /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
40 /// Specify whether target support specific ARM ISA variants.
48 /// HasVFPv2, HasVFPv3, HasVFPv4, HasNEON - Specify what
49 /// floating point ISAs are supported.
55 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
56 /// specified. Use the method useNEONForSinglePrecisionFP() to
57 /// determine if NEON should actually be used.
58 bool UseNEONForSinglePrecisionFP;
60 /// UseMulOps - True if non-microcoded fused integer multiply-add and
61 /// multiply-subtract instructions should be used.
64 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
65 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
68 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
69 /// forwarding to allow mul + mla being issued back to back.
70 bool HasVMLxForwarding;
72 /// SlowFPBrcc - True if floating point compare + branch is slow.
75 /// InThumbMode - True if compiling for Thumb, false for ARM.
78 /// HasThumb2 - True if Thumb2 instructions are supported.
81 /// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs -
82 /// v6m, v7m for example.
85 /// NoARM - True if subtarget does not support ARM mode execution.
88 /// PostRAScheduler - True if using post-register-allocation scheduler.
91 /// IsR9Reserved - True if R9 is a not available as general purpose register.
94 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
95 /// imms (including global addresses).
98 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
99 /// must be able to synthesize call stubs for interworking between ARM and
101 bool SupportsTailCall;
103 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
107 /// HasD16 - True if subtarget is limited to 16 double precision
108 /// FP registers for VFPv3.
111 /// HasHardwareDivide - True if subtarget supports [su]div
112 bool HasHardwareDivide;
114 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
115 bool HasHardwareDivideInARM;
117 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
119 bool HasT2ExtractPack;
121 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
125 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
126 /// over 16-bit ones.
129 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
130 /// that partially update CPSR and add false dependency on the previous
131 /// CPSR setting instruction.
132 bool AvoidCPSRPartialUpdate;
134 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
135 /// movs with shifter operand (i.e. asr, lsl, lsr).
136 bool AvoidMOVsShifterOperand;
138 /// HasRAS - Some processors perform return stack prediction. CodeGen should
139 /// avoid issue "normal" call instructions to callees which do not return.
142 /// HasMPExtension - True if the subtarget supports Multiprocessing
143 /// extension (ARMv7 only).
146 /// FPOnlySP - If true, the floating point unit only supports single
150 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
151 /// accesses for some types. For details, see
152 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
153 bool AllowsUnalignedMem;
155 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
156 /// and such) instructions in Thumb2 code.
159 /// NaCl TRAP instruction is generated instead of the regular TRAP.
162 /// stackAlignment - The minimum alignment known to hold of the stack frame on
163 /// entry to the function and which must be maintained by every function.
164 unsigned stackAlignment;
166 /// CPUString - String name of used CPU.
167 std::string CPUString;
169 /// TargetTriple - What processor and OS we're targeting.
172 /// SchedModel - Processor specific instruction costs.
173 const MCSchedModel *SchedModel;
175 /// Selected instruction itineraries (one entry per itinerary class.)
176 InstrItineraryData InstrItins;
185 ARM_ABI_AAPCS // ARM EABI
188 /// This constructor initializes the data members to match that
189 /// of the specified triple.
191 ARMSubtarget(const std::string &TT, const std::string &CPU,
192 const std::string &FS);
194 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
195 /// that still makes it profitable to inline the call.
196 unsigned getMaxInlineSizeThreshold() const {
197 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
198 // Change this once Thumb1 ldmia / stmia support is added.
199 return isThumb1Only() ? 0 : 64;
201 /// ParseSubtargetFeatures - Parses features string setting specified
202 /// subtarget options. Definition of function is auto generated by tblgen.
203 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
205 /// \brief Reset the features for the ARM target.
206 virtual void resetSubtargetFeatures(const MachineFunction *MF);
208 void initializeEnvironment();
209 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
211 void computeIssueWidth();
213 bool hasV4TOps() const { return HasV4TOps; }
214 bool hasV5TOps() const { return HasV5TOps; }
215 bool hasV5TEOps() const { return HasV5TEOps; }
216 bool hasV6Ops() const { return HasV6Ops; }
217 bool hasV6T2Ops() const { return HasV6T2Ops; }
218 bool hasV7Ops() const { return HasV7Ops; }
220 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
221 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
222 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
223 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
224 bool isSwift() const { return ARMProcFamily == Swift; }
225 bool isCortexM3() const { return CPUString == "cortex-m3"; }
226 bool isLikeA9() const { return isCortexA9() || isCortexA15(); }
227 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
229 bool hasARMOps() const { return !NoARM; }
231 bool hasVFP2() const { return HasVFPv2; }
232 bool hasVFP3() const { return HasVFPv3; }
233 bool hasVFP4() const { return HasVFPv4; }
234 bool hasNEON() const { return HasNEON; }
235 bool useNEONForSinglePrecisionFP() const {
236 return hasNEON() && UseNEONForSinglePrecisionFP; }
238 bool hasDivide() const { return HasHardwareDivide; }
239 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
240 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
241 bool hasDataBarrier() const { return HasDataBarrier; }
242 bool useMulOps() const { return UseMulOps; }
243 bool useFPVMLx() const { return !SlowFPVMLx; }
244 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
245 bool isFPBrccSlow() const { return SlowFPBrcc; }
246 bool isFPOnlySP() const { return FPOnlySP; }
247 bool prefers32BitThumb() const { return Pref32BitThumb; }
248 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
249 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
250 bool hasRAS() const { return HasRAS; }
251 bool hasMPExtension() const { return HasMPExtension; }
252 bool hasThumb2DSP() const { return Thumb2DSP; }
253 bool useNaClTrap() const { return UseNaClTrap; }
255 bool hasFP16() const { return HasFP16; }
256 bool hasD16() const { return HasD16; }
258 const Triple &getTargetTriple() const { return TargetTriple; }
260 bool isTargetIOS() const { return TargetTriple.getOS() == Triple::IOS; }
261 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
262 bool isTargetNaCl() const {
263 return TargetTriple.getOS() == Triple::NaCl;
265 bool isTargetELF() const { return !isTargetDarwin(); }
267 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
268 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
270 bool isThumb() const { return InThumbMode; }
271 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
272 bool isThumb2() const { return InThumbMode && HasThumb2; }
273 bool hasThumb2() const { return HasThumb2; }
274 bool isMClass() const { return IsMClass; }
275 bool isARClass() const { return !IsMClass; }
277 bool isR9Reserved() const { return IsR9Reserved; }
279 bool useMovt() const { return UseMovt && hasV6T2Ops(); }
280 bool supportsTailCall() const { return SupportsTailCall; }
282 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
284 const std::string & getCPUString() const { return CPUString; }
286 unsigned getMispredictionPenalty() const;
288 /// enablePostRAScheduler - True at 'More' optimization.
289 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
290 TargetSubtargetInfo::AntiDepBreakMode& Mode,
291 RegClassVector& CriticalPathRCs) const;
293 /// getInstrItins - Return the instruction itineraies based on subtarget
295 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
297 /// getStackAlignment - Returns the minimum alignment known to hold of the
298 /// stack frame on entry to the function and which must be maintained by every
299 /// function for this subtarget.
300 unsigned getStackAlignment() const { return stackAlignment; }
302 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
304 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
306 } // End llvm namespace
308 #endif // ARMSUBTARGET_H