1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "MCTargetDesc/ARMMCTargetDesc.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCInstrItineraries.h"
20 #include "llvm/Target/TargetSubtargetInfo.h"
23 #define GET_SUBTARGETINFO_HEADER
24 #include "ARMGenSubtargetInfo.inc"
31 class ARMSubtarget : public ARMGenSubtargetInfo {
33 enum ARMProcFamilyEnum {
34 Others, CortexA5, CortexA8, CortexA9, CortexA15, CortexR5, Swift, CortexA53, CortexA57
36 enum ARMProcClassEnum {
37 None, AClass, RClass, MClass
40 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
41 ARMProcFamilyEnum ARMProcFamily;
43 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
44 ARMProcClassEnum ARMProcClass;
46 /// HasV4TOps, HasV5TOps, HasV5TEOps,
47 /// HasV6Ops, HasV6MOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
48 /// Specify whether target support specific ARM ISA variants.
58 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
59 /// floating point ISAs are supported.
66 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
67 /// specified. Use the method useNEONForSinglePrecisionFP() to
68 /// determine if NEON should actually be used.
69 bool UseNEONForSinglePrecisionFP;
71 /// UseMulOps - True if non-microcoded fused integer multiply-add and
72 /// multiply-subtract instructions should be used.
75 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
76 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
79 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
80 /// forwarding to allow mul + mla being issued back to back.
81 bool HasVMLxForwarding;
83 /// SlowFPBrcc - True if floating point compare + branch is slow.
86 /// InThumbMode - True if compiling for Thumb, false for ARM.
89 /// HasThumb2 - True if Thumb2 instructions are supported.
92 /// NoARM - True if subtarget does not support ARM mode execution.
95 /// PostRAScheduler - True if using post-register-allocation scheduler.
98 /// IsR9Reserved - True if R9 is a not available as general purpose register.
101 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
102 /// imms (including global addresses).
105 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
106 /// must be able to synthesize call stubs for interworking between ARM and
108 bool SupportsTailCall;
110 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
114 /// HasD16 - True if subtarget is limited to 16 double precision
115 /// FP registers for VFPv3.
118 /// HasHardwareDivide - True if subtarget supports [su]div
119 bool HasHardwareDivide;
121 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
122 bool HasHardwareDivideInARM;
124 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
126 bool HasT2ExtractPack;
128 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
132 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
133 /// over 16-bit ones.
136 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
137 /// that partially update CPSR and add false dependency on the previous
138 /// CPSR setting instruction.
139 bool AvoidCPSRPartialUpdate;
141 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
142 /// movs with shifter operand (i.e. asr, lsl, lsr).
143 bool AvoidMOVsShifterOperand;
145 /// HasRAS - Some processors perform return stack prediction. CodeGen should
146 /// avoid issue "normal" call instructions to callees which do not return.
149 /// HasMPExtension - True if the subtarget supports Multiprocessing
150 /// extension (ARMv7 only).
153 /// FPOnlySP - If true, the floating point unit only supports single
157 /// If true, the processor supports the Performance Monitor Extensions. These
158 /// include a generic cycle-counter as well as more fine-grained (often
159 /// implementation-specific) events.
162 /// HasTrustZone - if true, processor supports TrustZone security extensions
165 /// HasCrypto - if true, processor supports Cryptography extensions
168 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
169 /// accesses for some types. For details, see
170 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
171 bool AllowsUnalignedMem;
173 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
174 /// and such) instructions in Thumb2 code.
177 /// NaCl TRAP instruction is generated instead of the regular TRAP.
180 /// Target machine allowed unsafe FP math (such as use of NEON fp)
183 /// stackAlignment - The minimum alignment known to hold of the stack frame on
184 /// entry to the function and which must be maintained by every function.
185 unsigned stackAlignment;
187 /// CPUString - String name of used CPU.
188 std::string CPUString;
190 /// TargetTriple - What processor and OS we're targeting.
193 /// SchedModel - Processor specific instruction costs.
194 const MCSchedModel *SchedModel;
196 /// Selected instruction itineraries (one entry per itinerary class.)
197 InstrItineraryData InstrItins;
199 /// Options passed via command line that could influence the target
200 const TargetOptions &Options;
205 ARM_ABI_AAPCS // ARM EABI
208 /// This constructor initializes the data members to match that
209 /// of the specified triple.
211 ARMSubtarget(const std::string &TT, const std::string &CPU,
212 const std::string &FS, const TargetOptions &Options);
214 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
215 /// that still makes it profitable to inline the call.
216 unsigned getMaxInlineSizeThreshold() const {
217 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
218 // Change this once Thumb1 ldmia / stmia support is added.
219 return isThumb1Only() ? 0 : 64;
221 /// ParseSubtargetFeatures - Parses features string setting specified
222 /// subtarget options. Definition of function is auto generated by tblgen.
223 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
225 /// \brief Reset the features for the ARM target.
226 virtual void resetSubtargetFeatures(const MachineFunction *MF);
228 void initializeEnvironment();
229 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
231 void computeIssueWidth();
233 bool hasV4TOps() const { return HasV4TOps; }
234 bool hasV5TOps() const { return HasV5TOps; }
235 bool hasV5TEOps() const { return HasV5TEOps; }
236 bool hasV6Ops() const { return HasV6Ops; }
237 bool hasV6MOps() const { return HasV6MOps; }
238 bool hasV6T2Ops() const { return HasV6T2Ops; }
239 bool hasV7Ops() const { return HasV7Ops; }
240 bool hasV8Ops() const { return HasV8Ops; }
242 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
243 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
244 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
245 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
246 bool isSwift() const { return ARMProcFamily == Swift; }
247 bool isCortexM3() const { return CPUString == "cortex-m3"; }
248 bool isLikeA9() const { return isCortexA9() || isCortexA15(); }
249 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
251 bool hasARMOps() const { return !NoARM; }
253 bool hasVFP2() const { return HasVFPv2; }
254 bool hasVFP3() const { return HasVFPv3; }
255 bool hasVFP4() const { return HasVFPv4; }
256 bool hasFPARMv8() const { return HasFPARMv8; }
257 bool hasNEON() const { return HasNEON; }
258 bool hasCrypto() const { return HasCrypto; }
259 bool useNEONForSinglePrecisionFP() const {
260 return hasNEON() && UseNEONForSinglePrecisionFP; }
262 bool hasDivide() const { return HasHardwareDivide; }
263 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
264 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
265 bool hasDataBarrier() const { return HasDataBarrier; }
266 bool useMulOps() const { return UseMulOps; }
267 bool useFPVMLx() const { return !SlowFPVMLx; }
268 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
269 bool isFPBrccSlow() const { return SlowFPBrcc; }
270 bool isFPOnlySP() const { return FPOnlySP; }
271 bool hasPerfMon() const { return HasPerfMon; }
272 bool hasTrustZone() const { return HasTrustZone; }
273 bool prefers32BitThumb() const { return Pref32BitThumb; }
274 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
275 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
276 bool hasRAS() const { return HasRAS; }
277 bool hasMPExtension() const { return HasMPExtension; }
278 bool hasThumb2DSP() const { return Thumb2DSP; }
279 bool useNaClTrap() const { return UseNaClTrap; }
281 bool hasFP16() const { return HasFP16; }
282 bool hasD16() const { return HasD16; }
284 const Triple &getTargetTriple() const { return TargetTriple; }
286 bool isTargetIOS() const { return TargetTriple.isiOS(); }
287 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
288 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
289 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
290 bool isTargetELF() const { return !isTargetDarwin(); }
291 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
292 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
293 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
294 // even for GNUEABI, so we can make a distinction here and still conform to
295 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
296 bool isTargetAEABI() const {
297 return TargetTriple.getEnvironment() == Triple::EABI;
300 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
301 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
303 bool isThumb() const { return InThumbMode; }
304 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
305 bool isThumb2() const { return InThumbMode && HasThumb2; }
306 bool hasThumb2() const { return HasThumb2; }
307 bool isMClass() const { return ARMProcClass == MClass; }
308 bool isRClass() const { return ARMProcClass == RClass; }
309 bool isAClass() const { return ARMProcClass == AClass; }
311 bool isR9Reserved() const { return IsR9Reserved; }
313 bool useMovt() const { return UseMovt && hasV6T2Ops(); }
314 bool supportsTailCall() const { return SupportsTailCall; }
316 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
318 const std::string & getCPUString() const { return CPUString; }
320 unsigned getMispredictionPenalty() const;
322 /// enablePostRAScheduler - True at 'More' optimization.
323 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
324 TargetSubtargetInfo::AntiDepBreakMode& Mode,
325 RegClassVector& CriticalPathRCs) const;
327 /// getInstrItins - Return the instruction itineraies based on subtarget
329 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
331 /// getStackAlignment - Returns the minimum alignment known to hold of the
332 /// stack frame on entry to the function and which must be maintained by every
333 /// function for this subtarget.
334 unsigned getStackAlignment() const { return stackAlignment; }
336 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
338 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
340 } // End llvm namespace
342 #endif // ARMSUBTARGET_H