1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "ARMSelectionDAGInfo.h"
18 #include "MCTargetDesc/ARMMCTargetDesc.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/IR/DataLayout.h"
21 #include "llvm/MC/MCInstrItineraries.h"
22 #include "llvm/Target/TargetSubtargetInfo.h"
25 #define GET_SUBTARGETINFO_HEADER
26 #include "ARMGenSubtargetInfo.inc"
33 class ARMSubtarget : public ARMGenSubtargetInfo {
35 enum ARMProcFamilyEnum {
36 Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
37 CortexR5, Swift, CortexA53, CortexA57, Krait
39 enum ARMProcClassEnum {
40 None, AClass, RClass, MClass
43 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
44 ARMProcFamilyEnum ARMProcFamily;
46 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
47 ARMProcClassEnum ARMProcClass;
49 /// HasV4TOps, HasV5TOps, HasV5TEOps,
50 /// HasV6Ops, HasV6MOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
51 /// Specify whether target support specific ARM ISA variants.
61 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
62 /// floating point ISAs are supported.
69 /// MinSize - True if the function being compiled has the "minsize" attribute
70 /// and should be optimised for size at the expense of speed.
73 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
74 /// specified. Use the method useNEONForSinglePrecisionFP() to
75 /// determine if NEON should actually be used.
76 bool UseNEONForSinglePrecisionFP;
78 /// UseMulOps - True if non-microcoded fused integer multiply-add and
79 /// multiply-subtract instructions should be used.
82 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
83 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
86 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
87 /// forwarding to allow mul + mla being issued back to back.
88 bool HasVMLxForwarding;
90 /// SlowFPBrcc - True if floating point compare + branch is slow.
93 /// InThumbMode - True if compiling for Thumb, false for ARM.
96 /// HasThumb2 - True if Thumb2 instructions are supported.
99 /// NoARM - True if subtarget does not support ARM mode execution.
102 /// PostRAScheduler - True if using post-register-allocation scheduler.
103 bool PostRAScheduler;
105 /// IsR9Reserved - True if R9 is a not available as general purpose register.
108 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
109 /// imms (including global addresses).
112 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
113 /// must be able to synthesize call stubs for interworking between ARM and
115 bool SupportsTailCall;
117 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
121 /// HasD16 - True if subtarget is limited to 16 double precision
122 /// FP registers for VFPv3.
125 /// HasHardwareDivide - True if subtarget supports [su]div
126 bool HasHardwareDivide;
128 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
129 bool HasHardwareDivideInARM;
131 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
133 bool HasT2ExtractPack;
135 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
139 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
140 /// over 16-bit ones.
143 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
144 /// that partially update CPSR and add false dependency on the previous
145 /// CPSR setting instruction.
146 bool AvoidCPSRPartialUpdate;
148 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
149 /// movs with shifter operand (i.e. asr, lsl, lsr).
150 bool AvoidMOVsShifterOperand;
152 /// HasRAS - Some processors perform return stack prediction. CodeGen should
153 /// avoid issue "normal" call instructions to callees which do not return.
156 /// HasMPExtension - True if the subtarget supports Multiprocessing
157 /// extension (ARMv7 only).
160 /// HasVirtualization - True if the subtarget supports the Virtualization
162 bool HasVirtualization;
164 /// FPOnlySP - If true, the floating point unit only supports single
168 /// If true, the processor supports the Performance Monitor Extensions. These
169 /// include a generic cycle-counter as well as more fine-grained (often
170 /// implementation-specific) events.
173 /// HasTrustZone - if true, processor supports TrustZone security extensions
176 /// HasCrypto - if true, processor supports Cryptography extensions
179 /// HasCRC - if true, processor supports CRC instructions
182 /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
183 /// particularly effective at zeroing a VFP register.
184 bool HasZeroCycleZeroing;
186 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
187 /// accesses for some types. For details, see
188 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
189 bool AllowsUnalignedMem;
191 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
192 /// blocks to conform to ARMv8 rule.
195 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
196 /// and such) instructions in Thumb2 code.
199 /// NaCl TRAP instruction is generated instead of the regular TRAP.
202 /// Target machine allowed unsafe FP math (such as use of NEON fp)
205 /// stackAlignment - The minimum alignment known to hold of the stack frame on
206 /// entry to the function and which must be maintained by every function.
207 unsigned stackAlignment;
209 /// CPUString - String name of used CPU.
210 std::string CPUString;
212 /// IsLittle - The target is Little Endian
215 /// TargetTriple - What processor and OS we're targeting.
218 /// SchedModel - Processor specific instruction costs.
219 const MCSchedModel *SchedModel;
221 /// Selected instruction itineraries (one entry per itinerary class.)
222 InstrItineraryData InstrItins;
224 /// Options passed via command line that could influence the target
225 const TargetOptions &Options;
231 ARM_ABI_AAPCS // ARM EABI
234 /// This constructor initializes the data members to match that
235 /// of the specified triple.
237 ARMSubtarget(const std::string &TT, const std::string &CPU,
238 const std::string &FS, bool IsLittle,
239 const TargetOptions &Options);
241 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
242 /// that still makes it profitable to inline the call.
243 unsigned getMaxInlineSizeThreshold() const {
246 /// ParseSubtargetFeatures - Parses features string setting specified
247 /// subtarget options. Definition of function is auto generated by tblgen.
248 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
250 /// \brief Reset the features for the ARM target.
251 void resetSubtargetFeatures(const MachineFunction *MF) override;
253 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
254 /// so that we can use initializer lists for subtarget initialization.
255 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
257 const DataLayout *getDataLayout() const { return &DL; }
258 const ARMSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; }
262 ARMSelectionDAGInfo TSInfo;
264 void initializeEnvironment();
265 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
267 void computeIssueWidth();
269 bool hasV4TOps() const { return HasV4TOps; }
270 bool hasV5TOps() const { return HasV5TOps; }
271 bool hasV5TEOps() const { return HasV5TEOps; }
272 bool hasV6Ops() const { return HasV6Ops; }
273 bool hasV6MOps() const { return HasV6MOps; }
274 bool hasV6T2Ops() const { return HasV6T2Ops; }
275 bool hasV7Ops() const { return HasV7Ops; }
276 bool hasV8Ops() const { return HasV8Ops; }
278 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
279 bool isCortexA7() const { return ARMProcFamily == CortexA7; }
280 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
281 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
282 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
283 bool isSwift() const { return ARMProcFamily == Swift; }
284 bool isCortexM3() const { return CPUString == "cortex-m3"; }
285 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
286 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
287 bool isKrait() const { return ARMProcFamily == Krait; }
289 bool hasARMOps() const { return !NoARM; }
291 bool hasVFP2() const { return HasVFPv2; }
292 bool hasVFP3() const { return HasVFPv3; }
293 bool hasVFP4() const { return HasVFPv4; }
294 bool hasFPARMv8() const { return HasFPARMv8; }
295 bool hasNEON() const { return HasNEON; }
296 bool hasCrypto() const { return HasCrypto; }
297 bool hasCRC() const { return HasCRC; }
298 bool hasVirtualization() const { return HasVirtualization; }
299 bool isMinSize() const { return MinSize; }
300 bool useNEONForSinglePrecisionFP() const {
301 return hasNEON() && UseNEONForSinglePrecisionFP; }
303 bool hasDivide() const { return HasHardwareDivide; }
304 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
305 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
306 bool hasDataBarrier() const { return HasDataBarrier; }
307 bool hasAnyDataBarrier() const {
308 return HasDataBarrier || (hasV6Ops() && !isThumb());
310 bool useMulOps() const { return UseMulOps; }
311 bool useFPVMLx() const { return !SlowFPVMLx; }
312 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
313 bool isFPBrccSlow() const { return SlowFPBrcc; }
314 bool isFPOnlySP() const { return FPOnlySP; }
315 bool hasPerfMon() const { return HasPerfMon; }
316 bool hasTrustZone() const { return HasTrustZone; }
317 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
318 bool prefers32BitThumb() const { return Pref32BitThumb; }
319 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
320 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
321 bool hasRAS() const { return HasRAS; }
322 bool hasMPExtension() const { return HasMPExtension; }
323 bool hasThumb2DSP() const { return Thumb2DSP; }
324 bool useNaClTrap() const { return UseNaClTrap; }
326 bool hasFP16() const { return HasFP16; }
327 bool hasD16() const { return HasD16; }
329 const Triple &getTargetTriple() const { return TargetTriple; }
331 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
332 bool isTargetIOS() const { return TargetTriple.isiOS(); }
333 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
334 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
335 bool isTargetNetBSD() const { return TargetTriple.getOS() == Triple::NetBSD; }
336 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
338 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
339 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
340 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
342 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
343 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
344 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
345 // even for GNUEABI, so we can make a distinction here and still conform to
346 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
347 // FIXME: The Darwin exception is temporary, while we move users to
348 // "*-*-*-macho" triples as quickly as possible.
349 bool isTargetAEABI() const {
350 return (TargetTriple.getEnvironment() == Triple::EABI ||
351 TargetTriple.getEnvironment() == Triple::EABIHF) &&
352 !isTargetDarwin() && !isTargetWindows();
355 // ARM Targets that support EHABI exception handling standard
356 // Darwin uses SjLj. Other targets might need more checks.
357 bool isTargetEHABICompatible() const {
358 return (TargetTriple.getEnvironment() == Triple::EABI ||
359 TargetTriple.getEnvironment() == Triple::GNUEABI ||
360 TargetTriple.getEnvironment() == Triple::EABIHF ||
361 TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
362 TargetTriple.getEnvironment() == Triple::Android) &&
363 !isTargetDarwin() && !isTargetWindows();
366 bool isTargetHardFloat() const {
367 // FIXME: this is invalid for WindowsCE
368 return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
369 TargetTriple.getEnvironment() == Triple::EABIHF ||
372 bool isTargetAndroid() const {
373 return TargetTriple.getEnvironment() == Triple::Android;
376 bool isAPCS_ABI() const {
377 assert(TargetABI != ARM_ABI_UNKNOWN);
378 return TargetABI == ARM_ABI_APCS;
380 bool isAAPCS_ABI() const {
381 assert(TargetABI != ARM_ABI_UNKNOWN);
382 return TargetABI == ARM_ABI_AAPCS;
385 bool isThumb() const { return InThumbMode; }
386 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
387 bool isThumb2() const { return InThumbMode && HasThumb2; }
388 bool hasThumb2() const { return HasThumb2; }
389 bool isMClass() const { return ARMProcClass == MClass; }
390 bool isRClass() const { return ARMProcClass == RClass; }
391 bool isAClass() const { return ARMProcClass == AClass; }
393 bool isR9Reserved() const { return IsR9Reserved; }
395 bool useMovt() const {
396 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
397 // immediates as it is inherently position independent, and may be out of
399 return UseMovt && (isTargetWindows() || !isMinSize());
401 bool supportsTailCall() const { return SupportsTailCall; }
403 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
405 bool restrictIT() const { return RestrictIT; }
407 const std::string & getCPUString() const { return CPUString; }
409 bool isLittle() const { return IsLittle; }
411 unsigned getMispredictionPenalty() const;
413 /// This function returns true if the target has sincos() routine in its
414 /// compiler runtime or math libraries.
415 bool hasSinCos() const;
417 /// True for some subtargets at > -O0.
418 bool enablePostMachineScheduler() const;
420 /// enablePostRAScheduler - True at 'More' optimization.
421 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
422 TargetSubtargetInfo::AntiDepBreakMode& Mode,
423 RegClassVector& CriticalPathRCs) const override;
425 /// getInstrItins - Return the instruction itineraies based on subtarget
427 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
429 /// getStackAlignment - Returns the minimum alignment known to hold of the
430 /// stack frame on entry to the function and which must be maintained by every
431 /// function for this subtarget.
432 unsigned getStackAlignment() const { return stackAlignment; }
434 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
436 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
438 } // End llvm namespace
440 #endif // ARMSUBTARGET_H