1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
18 #include "ARMFrameLowering.h"
19 #include "ARMISelLowering.h"
20 #include "ARMInstrInfo.h"
21 #include "ARMJITInfo.h"
22 #include "ARMSelectionDAGInfo.h"
23 #include "ARMSubtarget.h"
24 #include "Thumb1FrameLowering.h"
25 #include "Thumb1InstrInfo.h"
26 #include "Thumb2InstrInfo.h"
27 #include "ARMJITInfo.h"
28 #include "MCTargetDesc/ARMMCTargetDesc.h"
29 #include "llvm/ADT/Triple.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/MC/MCInstrItineraries.h"
32 #include "llvm/Target/TargetSubtargetInfo.h"
35 #define GET_SUBTARGETINFO_HEADER
36 #include "ARMGenSubtargetInfo.inc"
43 class ARMSubtarget : public ARMGenSubtargetInfo {
45 enum ARMProcFamilyEnum {
46 Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
47 CortexR5, Swift, CortexA53, CortexA57, Krait
49 enum ARMProcClassEnum {
50 None, AClass, RClass, MClass
53 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
54 ARMProcFamilyEnum ARMProcFamily;
56 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
57 ARMProcClassEnum ARMProcClass;
59 /// HasV4TOps, HasV5TOps, HasV5TEOps,
60 /// HasV6Ops, HasV6MOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
61 /// Specify whether target support specific ARM ISA variants.
71 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
72 /// floating point ISAs are supported.
79 /// MinSize - True if the function being compiled has the "minsize" attribute
80 /// and should be optimised for size at the expense of speed.
83 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
84 /// specified. Use the method useNEONForSinglePrecisionFP() to
85 /// determine if NEON should actually be used.
86 bool UseNEONForSinglePrecisionFP;
88 /// UseMulOps - True if non-microcoded fused integer multiply-add and
89 /// multiply-subtract instructions should be used.
92 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
93 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
96 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
97 /// forwarding to allow mul + mla being issued back to back.
98 bool HasVMLxForwarding;
100 /// SlowFPBrcc - True if floating point compare + branch is slow.
103 /// InThumbMode - True if compiling for Thumb, false for ARM.
106 /// HasThumb2 - True if Thumb2 instructions are supported.
109 /// NoARM - True if subtarget does not support ARM mode execution.
112 /// PostRAScheduler - True if using post-register-allocation scheduler.
113 bool PostRAScheduler;
115 /// IsR9Reserved - True if R9 is a not available as general purpose register.
118 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
119 /// imms (including global addresses).
122 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
123 /// must be able to synthesize call stubs for interworking between ARM and
125 bool SupportsTailCall;
127 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
131 /// HasD16 - True if subtarget is limited to 16 double precision
132 /// FP registers for VFPv3.
135 /// HasHardwareDivide - True if subtarget supports [su]div
136 bool HasHardwareDivide;
138 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
139 bool HasHardwareDivideInARM;
141 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
143 bool HasT2ExtractPack;
145 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
149 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
150 /// over 16-bit ones.
153 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
154 /// that partially update CPSR and add false dependency on the previous
155 /// CPSR setting instruction.
156 bool AvoidCPSRPartialUpdate;
158 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
159 /// movs with shifter operand (i.e. asr, lsl, lsr).
160 bool AvoidMOVsShifterOperand;
162 /// HasRAS - Some processors perform return stack prediction. CodeGen should
163 /// avoid issue "normal" call instructions to callees which do not return.
166 /// HasMPExtension - True if the subtarget supports Multiprocessing
167 /// extension (ARMv7 only).
170 /// HasVirtualization - True if the subtarget supports the Virtualization
172 bool HasVirtualization;
174 /// FPOnlySP - If true, the floating point unit only supports single
178 /// If true, the processor supports the Performance Monitor Extensions. These
179 /// include a generic cycle-counter as well as more fine-grained (often
180 /// implementation-specific) events.
183 /// HasTrustZone - if true, processor supports TrustZone security extensions
186 /// HasCrypto - if true, processor supports Cryptography extensions
189 /// HasCRC - if true, processor supports CRC instructions
192 /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
193 /// particularly effective at zeroing a VFP register.
194 bool HasZeroCycleZeroing;
196 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
197 /// accesses for some types. For details, see
198 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
199 bool AllowsUnalignedMem;
201 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
202 /// blocks to conform to ARMv8 rule.
205 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
206 /// and such) instructions in Thumb2 code.
209 /// NaCl TRAP instruction is generated instead of the regular TRAP.
212 /// Target machine allowed unsafe FP math (such as use of NEON fp)
215 /// stackAlignment - The minimum alignment known to hold of the stack frame on
216 /// entry to the function and which must be maintained by every function.
217 unsigned stackAlignment;
219 /// CPUString - String name of used CPU.
220 std::string CPUString;
222 /// IsLittle - The target is Little Endian
225 /// TargetTriple - What processor and OS we're targeting.
228 /// SchedModel - Processor specific instruction costs.
229 const MCSchedModel *SchedModel;
231 /// Selected instruction itineraries (one entry per itinerary class.)
232 InstrItineraryData InstrItins;
234 /// Options passed via command line that could influence the target
235 const TargetOptions &Options;
241 ARM_ABI_AAPCS // ARM EABI
244 /// This constructor initializes the data members to match that
245 /// of the specified triple.
247 ARMSubtarget(const std::string &TT, const std::string &CPU,
248 const std::string &FS, TargetMachine &TM, bool IsLittle,
249 const TargetOptions &Options);
251 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
252 /// that still makes it profitable to inline the call.
253 unsigned getMaxInlineSizeThreshold() const {
256 /// ParseSubtargetFeatures - Parses features string setting specified
257 /// subtarget options. Definition of function is auto generated by tblgen.
258 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
260 /// \brief Reset the features for the ARM target.
261 void resetSubtargetFeatures(const MachineFunction *MF) override;
263 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
264 /// so that we can use initializer lists for subtarget initialization.
265 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
267 const DataLayout *getDataLayout() const { return &DL; }
268 const ARMSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; }
269 ARMJITInfo *getJITInfo() { return &JITInfo; }
270 const ARMBaseInstrInfo *getInstrInfo() const { return InstrInfo.get(); }
271 const ARMTargetLowering *getTargetLowering() const { return &TLInfo; }
272 const ARMFrameLowering *getFrameLowering() const { return FrameLowering.get(); }
273 const ARMBaseRegisterInfo *getRegisterInfo() const {
274 return &InstrInfo->getRegisterInfo();
279 ARMSelectionDAGInfo TSInfo;
281 // Either Thumb1InstrInfo or Thumb2InstrInfo.
282 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
283 ARMTargetLowering TLInfo;
284 // Either Thumb1FrameLowering or ARMFrameLowering.
285 std::unique_ptr<ARMFrameLowering> FrameLowering;
287 void initializeEnvironment();
288 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
290 void computeIssueWidth();
292 bool hasV4TOps() const { return HasV4TOps; }
293 bool hasV5TOps() const { return HasV5TOps; }
294 bool hasV5TEOps() const { return HasV5TEOps; }
295 bool hasV6Ops() const { return HasV6Ops; }
296 bool hasV6MOps() const { return HasV6MOps; }
297 bool hasV6T2Ops() const { return HasV6T2Ops; }
298 bool hasV7Ops() const { return HasV7Ops; }
299 bool hasV8Ops() const { return HasV8Ops; }
301 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
302 bool isCortexA7() const { return ARMProcFamily == CortexA7; }
303 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
304 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
305 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
306 bool isSwift() const { return ARMProcFamily == Swift; }
307 bool isCortexM3() const { return CPUString == "cortex-m3"; }
308 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
309 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
310 bool isKrait() const { return ARMProcFamily == Krait; }
312 bool hasARMOps() const { return !NoARM; }
314 bool hasVFP2() const { return HasVFPv2; }
315 bool hasVFP3() const { return HasVFPv3; }
316 bool hasVFP4() const { return HasVFPv4; }
317 bool hasFPARMv8() const { return HasFPARMv8; }
318 bool hasNEON() const { return HasNEON; }
319 bool hasCrypto() const { return HasCrypto; }
320 bool hasCRC() const { return HasCRC; }
321 bool hasVirtualization() const { return HasVirtualization; }
322 bool isMinSize() const { return MinSize; }
323 bool useNEONForSinglePrecisionFP() const {
324 return hasNEON() && UseNEONForSinglePrecisionFP; }
326 bool hasDivide() const { return HasHardwareDivide; }
327 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
328 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
329 bool hasDataBarrier() const { return HasDataBarrier; }
330 bool hasAnyDataBarrier() const {
331 return HasDataBarrier || (hasV6Ops() && !isThumb());
333 bool useMulOps() const { return UseMulOps; }
334 bool useFPVMLx() const { return !SlowFPVMLx; }
335 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
336 bool isFPBrccSlow() const { return SlowFPBrcc; }
337 bool isFPOnlySP() const { return FPOnlySP; }
338 bool hasPerfMon() const { return HasPerfMon; }
339 bool hasTrustZone() const { return HasTrustZone; }
340 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
341 bool prefers32BitThumb() const { return Pref32BitThumb; }
342 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
343 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
344 bool hasRAS() const { return HasRAS; }
345 bool hasMPExtension() const { return HasMPExtension; }
346 bool hasThumb2DSP() const { return Thumb2DSP; }
347 bool useNaClTrap() const { return UseNaClTrap; }
349 bool hasFP16() const { return HasFP16; }
350 bool hasD16() const { return HasD16; }
352 const Triple &getTargetTriple() const { return TargetTriple; }
354 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
355 bool isTargetIOS() const { return TargetTriple.isiOS(); }
356 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
357 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
358 bool isTargetNetBSD() const { return TargetTriple.getOS() == Triple::NetBSD; }
359 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
361 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
362 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
363 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
365 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
366 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
367 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
368 // even for GNUEABI, so we can make a distinction here and still conform to
369 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
370 // FIXME: The Darwin exception is temporary, while we move users to
371 // "*-*-*-macho" triples as quickly as possible.
372 bool isTargetAEABI() const {
373 return (TargetTriple.getEnvironment() == Triple::EABI ||
374 TargetTriple.getEnvironment() == Triple::EABIHF) &&
375 !isTargetDarwin() && !isTargetWindows();
378 // ARM Targets that support EHABI exception handling standard
379 // Darwin uses SjLj. Other targets might need more checks.
380 bool isTargetEHABICompatible() const {
381 return (TargetTriple.getEnvironment() == Triple::EABI ||
382 TargetTriple.getEnvironment() == Triple::GNUEABI ||
383 TargetTriple.getEnvironment() == Triple::EABIHF ||
384 TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
385 TargetTriple.getEnvironment() == Triple::Android) &&
386 !isTargetDarwin() && !isTargetWindows();
389 bool isTargetHardFloat() const {
390 // FIXME: this is invalid for WindowsCE
391 return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
392 TargetTriple.getEnvironment() == Triple::EABIHF ||
395 bool isTargetAndroid() const {
396 return TargetTriple.getEnvironment() == Triple::Android;
399 bool isAPCS_ABI() const {
400 assert(TargetABI != ARM_ABI_UNKNOWN);
401 return TargetABI == ARM_ABI_APCS;
403 bool isAAPCS_ABI() const {
404 assert(TargetABI != ARM_ABI_UNKNOWN);
405 return TargetABI == ARM_ABI_AAPCS;
408 bool isThumb() const { return InThumbMode; }
409 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
410 bool isThumb2() const { return InThumbMode && HasThumb2; }
411 bool hasThumb2() const { return HasThumb2; }
412 bool isMClass() const { return ARMProcClass == MClass; }
413 bool isRClass() const { return ARMProcClass == RClass; }
414 bool isAClass() const { return ARMProcClass == AClass; }
416 bool isR9Reserved() const { return IsR9Reserved; }
418 bool useMovt() const {
419 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
420 // immediates as it is inherently position independent, and may be out of
422 return UseMovt && (isTargetWindows() || !isMinSize());
424 bool supportsTailCall() const { return SupportsTailCall; }
426 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
428 bool restrictIT() const { return RestrictIT; }
430 const std::string & getCPUString() const { return CPUString; }
432 bool isLittle() const { return IsLittle; }
434 unsigned getMispredictionPenalty() const;
436 /// This function returns true if the target has sincos() routine in its
437 /// compiler runtime or math libraries.
438 bool hasSinCos() const;
440 /// True for some subtargets at > -O0.
441 bool enablePostMachineScheduler() const;
443 /// enablePostRAScheduler - True at 'More' optimization.
444 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
445 TargetSubtargetInfo::AntiDepBreakMode& Mode,
446 RegClassVector& CriticalPathRCs) const override;
448 // enableAtomicExpandLoadLinked - True if we need to expand our atomics.
449 bool enableAtomicExpandLoadLinked() const override;
451 /// getInstrItins - Return the instruction itineraies based on subtarget
453 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
455 /// getStackAlignment - Returns the minimum alignment known to hold of the
456 /// stack frame on entry to the function and which must be maintained by every
457 /// function for this subtarget.
458 unsigned getStackAlignment() const { return stackAlignment; }
460 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
462 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
464 } // End llvm namespace
466 #endif // ARMSUBTARGET_H