1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "llvm/IR/GlobalValue.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Target/TargetInstrInfo.h"
21 #define GET_SUBTARGETINFO_TARGET_DESC
22 #define GET_SUBTARGETINFO_CTOR
23 #include "ARMGenSubtargetInfo.inc"
28 ReserveR9("arm-reserve-r9", cl::Hidden,
29 cl::desc("Reserve R9, making it unavailable as GPR"));
32 DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden);
35 UseFusedMulOps("arm-use-mulops",
36 cl::init(true), cl::Hidden);
39 StrictAlign("arm-strict-align", cl::Hidden,
40 cl::desc("Disallow all unaligned memory accesses"));
42 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
43 const std::string &FS)
44 : ARMGenSubtargetInfo(TT, CPU, FS)
45 , ARMProcFamily(Others)
56 , UseNEONForSinglePrecisionFP(false)
57 , UseMulOps(UseFusedMulOps)
59 , HasVMLxForwarding(false)
65 , PostRAScheduler(false)
66 , IsR9Reserved(ReserveR9)
68 , SupportsTailCall(false)
71 , HasHardwareDivide(false)
72 , HasHardwareDivideInARM(false)
73 , HasT2ExtractPack(false)
74 , HasDataBarrier(false)
75 , Pref32BitThumb(false)
76 , AvoidCPSRPartialUpdate(false)
77 , AvoidMOVsShifterOperand(false)
79 , HasMPExtension(false)
81 , AllowsUnalignedMem(false)
86 , TargetABI(ARM_ABI_APCS) {
87 // Determine default and user specified characteristics
88 if (CPUString.empty())
89 CPUString = "generic";
91 // Insert the architecture feature derived from the target triple into the
92 // feature string. This is important for setting features that are implied
93 // based on the architecture version.
94 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPUString);
97 ArchFS = ArchFS + "," + FS;
101 ParseSubtargetFeatures(CPUString, ArchFS);
103 // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
104 // ARM version or CPU and then remove this.
105 if (!HasV6T2Ops && hasThumb2())
106 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
108 // Keep a pointer to static instruction cost data for the specified CPU.
109 SchedModel = getSchedModelForCPU(CPUString);
111 // Initialize scheduling itinerary for the specified CPU.
112 InstrItins = getInstrItineraryForCPU(CPUString);
114 if ((TT.find("eabi") != std::string::npos) || (isTargetIOS() && isMClass()))
115 // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g.
116 // Darwin-EABI conforms to AACPS but not the rest of EABI.
117 TargetABI = ARM_ABI_AAPCS;
123 UseMovt = hasV6T2Ops();
125 IsR9Reserved = ReserveR9 | !HasV6Ops;
126 UseMovt = DarwinUseMOVT && hasV6T2Ops();
127 SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0);
130 if (!isThumb() || hasThumb2())
131 PostRAScheduler = true;
133 // v6+ may or may not support unaligned mem access depending on the system
135 if (!StrictAlign && hasV6Ops() && isTargetDarwin())
136 AllowsUnalignedMem = true;
139 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
141 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
142 Reloc::Model RelocM) const {
143 if (RelocM == Reloc::Static)
146 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
148 bool isDecl = GV->hasAvailableExternallyLinkage();
149 if (GV->isDeclaration() && !GV->isMaterializable())
152 if (!isTargetDarwin()) {
153 // Extra load is needed for all externally visible.
154 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
158 if (RelocM == Reloc::PIC_) {
159 // If this is a strong reference to a definition, it is definitely not
161 if (!isDecl && !GV->isWeakForLinker())
164 // Unless we have a symbol with hidden visibility, we have to go through a
165 // normal $non_lazy_ptr stub because this symbol might be resolved late.
166 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
169 // If symbol visibility is hidden, we have a stub for common symbol
170 // references and external declarations.
171 if (isDecl || GV->hasCommonLinkage())
172 // Hidden $non_lazy_ptr reference.
177 // If this is a strong reference to a definition, it is definitely not
179 if (!isDecl && !GV->isWeakForLinker())
182 // Unless we have a symbol with hidden visibility, we have to go through a
183 // normal $non_lazy_ptr stub because this symbol might be resolved late.
184 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
192 unsigned ARMSubtarget::getMispredictionPenalty() const {
193 return SchedModel->MispredictPenalty;
196 bool ARMSubtarget::enablePostRAScheduler(
197 CodeGenOpt::Level OptLevel,
198 TargetSubtargetInfo::AntiDepBreakMode& Mode,
199 RegClassVector& CriticalPathRCs) const {
200 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
201 CriticalPathRCs.clear();
202 CriticalPathRCs.push_back(&ARM::GPRRegClass);
203 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;