1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMBaseRegisterInfo.h"
16 #include "llvm/GlobalValue.h"
17 #include "llvm/Target/TargetSubtargetInfo.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/ADT/SmallVector.h"
21 #define GET_SUBTARGETINFO_CTOR
22 #define GET_SUBTARGETINFO_MC_DESC
23 #define GET_SUBTARGETINFO_TARGET_DESC
24 #include "ARMGenSubtargetInfo.inc"
29 ReserveR9("arm-reserve-r9", cl::Hidden,
30 cl::desc("Reserve R9, making it unavailable as GPR"));
33 DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden);
36 StrictAlign("arm-strict-align", cl::Hidden,
37 cl::desc("Disallow all unaligned memory accesses"));
39 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
40 const std::string &FS)
41 : ARMGenSubtargetInfo()
43 , ARMProcFamily(Others)
45 , UseNEONForSinglePrecisionFP(false)
47 , HasVMLxForwarding(false)
52 , PostRAScheduler(false)
53 , IsR9Reserved(ReserveR9)
57 , HasHardwareDivide(false)
58 , HasT2ExtractPack(false)
59 , HasDataBarrier(false)
60 , Pref32BitThumb(false)
61 , AvoidCPSRPartialUpdate(false)
62 , HasMPExtension(false)
64 , AllowsUnalignedMem(false)
69 , TargetABI(ARM_ABI_APCS) {
70 // Determine default and user specified characteristics
71 if (CPUString.empty())
72 CPUString = "generic";
74 if (TT.find("eabi") != std::string::npos)
75 TargetABI = ARM_ABI_AAPCS;
77 // Insert the architecture feature derived from the target triple into the
78 // feature string. This is important for setting features that are implied
79 // based on the architecture version.
80 std::string ArchFS = ARM_MC::ParseARMTriple(TT, IsThumb);
83 ArchFS = ArchFS + "," + FS;
88 ParseSubtargetFeatures(ArchFS, CPUString);
90 // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
91 // ARM version or CPU and then remove this.
92 if (ARMArchVersion < V6T2 && hasThumb2())
93 ARMArchVersion = V6T2;
95 // Initialize scheduling itinerary for the specified CPU.
96 InstrItins = getInstrItineraryForCPU(CPUString);
98 // After parsing Itineraries, set ItinData.IssueWidth.
104 if (!isTargetDarwin())
105 UseMovt = hasV6T2Ops();
107 IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
108 UseMovt = DarwinUseMOVT && hasV6T2Ops();
111 if (!isThumb() || hasThumb2())
112 PostRAScheduler = true;
114 // v6+ may or may not support unaligned mem access depending on the system
116 if (!StrictAlign && hasV6Ops() && isTargetDarwin())
117 AllowsUnalignedMem = true;
120 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
122 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
123 Reloc::Model RelocM) const {
124 if (RelocM == Reloc::Static)
127 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
129 bool isDecl = GV->hasAvailableExternallyLinkage();
130 if (GV->isDeclaration() && !GV->isMaterializable())
133 if (!isTargetDarwin()) {
134 // Extra load is needed for all externally visible.
135 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
139 if (RelocM == Reloc::PIC_) {
140 // If this is a strong reference to a definition, it is definitely not
142 if (!isDecl && !GV->isWeakForLinker())
145 // Unless we have a symbol with hidden visibility, we have to go through a
146 // normal $non_lazy_ptr stub because this symbol might be resolved late.
147 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
150 // If symbol visibility is hidden, we have a stub for common symbol
151 // references and external declarations.
152 if (isDecl || GV->hasCommonLinkage())
153 // Hidden $non_lazy_ptr reference.
158 // If this is a strong reference to a definition, it is definitely not
160 if (!isDecl && !GV->isWeakForLinker())
163 // Unless we have a symbol with hidden visibility, we have to go through a
164 // normal $non_lazy_ptr stub because this symbol might be resolved late.
165 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
173 unsigned ARMSubtarget::getMispredictionPenalty() const {
174 // If we have a reasonable estimate of the pipeline depth, then we can
175 // estimate the penalty of a misprediction based on that.
178 else if (isCortexA9())
181 // Otherwise, just return a sensible default.
185 void ARMSubtarget::computeIssueWidth() {
186 unsigned allStage1Units = 0;
187 for (const InstrItinerary *itin = InstrItins.Itineraries;
188 itin->FirstStage != ~0U; ++itin) {
189 const InstrStage *IS = InstrItins.Stages + itin->FirstStage;
190 allStage1Units |= IS->getUnits();
192 InstrItins.IssueWidth = 0;
193 while (allStage1Units) {
194 ++InstrItins.IssueWidth;
195 // clear the lowest bit
196 allStage1Units ^= allStage1Units & ~(allStage1Units - 1);
198 assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units");
201 bool ARMSubtarget::enablePostRAScheduler(
202 CodeGenOpt::Level OptLevel,
203 TargetSubtargetInfo::AntiDepBreakMode& Mode,
204 RegClassVector& CriticalPathRCs) const {
205 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
206 CriticalPathRCs.clear();
207 CriticalPathRCs.push_back(&ARM::GPRRegClass);
208 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;