1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "llvm/IR/Attributes.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetOptions.h"
24 #define GET_SUBTARGETINFO_TARGET_DESC
25 #define GET_SUBTARGETINFO_CTOR
26 #include "ARMGenSubtargetInfo.inc"
31 ReserveR9("arm-reserve-r9", cl::Hidden,
32 cl::desc("Reserve R9, making it unavailable as GPR"));
35 ArmUseMOVT("arm-use-movt", cl::init(true), cl::Hidden);
38 UseFusedMulOps("arm-use-mulops",
39 cl::init(true), cl::Hidden);
47 static cl::opt<AlignMode>
48 Align(cl::desc("Load/store alignment support"),
49 cl::Hidden, cl::init(DefaultAlign),
51 clEnumValN(DefaultAlign, "arm-default-align",
52 "Generate unaligned accesses only on hardware/OS "
53 "combinations that are known to support them"),
54 clEnumValN(StrictAlign, "arm-strict-align",
55 "Disallow all unaligned memory accesses"),
56 clEnumValN(NoStrictAlign, "arm-no-strict-align",
57 "Allow unaligned memory accesses"),
66 static cl::opt<ITMode>
67 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
69 cl::values(clEnumValN(DefaultIT, "arm-default-it",
70 "Generate IT block based on arch"),
71 clEnumValN(RestrictedIT, "arm-restrict-it",
72 "Disallow deprecated IT based on ARMv8"),
73 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
74 "Allow IT blocks based on ARMv7"),
77 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
78 const std::string &FS, const TargetOptions &Options)
79 : ARMGenSubtargetInfo(TT, CPU, FS)
80 , ARMProcFamily(Others)
86 , TargetABI(ARM_ABI_UNKNOWN) {
87 initializeEnvironment();
88 resetSubtargetFeatures(CPU, FS);
91 void ARMSubtarget::initializeEnvironment() {
106 UseNEONForSinglePrecisionFP = false;
107 UseMulOps = UseFusedMulOps;
109 HasVMLxForwarding = false;
114 PostRAScheduler = false;
115 IsR9Reserved = ReserveR9;
117 SupportsTailCall = false;
120 HasHardwareDivide = false;
121 HasHardwareDivideInARM = false;
122 HasT2ExtractPack = false;
123 HasDataBarrier = false;
124 Pref32BitThumb = false;
125 AvoidCPSRPartialUpdate = false;
126 AvoidMOVsShifterOperand = false;
128 HasMPExtension = false;
129 HasVirtualization = false;
132 HasTrustZone = false;
135 AllowsUnalignedMem = false;
138 UnsafeFPMath = false;
141 void ARMSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
142 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
143 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
145 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
148 !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
150 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
152 initializeEnvironment();
153 resetSubtargetFeatures(CPU, FS);
157 FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
160 void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
161 if (CPUString.empty()) {
162 if (isTargetIOS() && TargetTriple.getArchName().endswith("v7s"))
163 // Default to the Swift CPU when targeting armv7s/thumbv7s.
166 CPUString = "generic";
169 // Insert the architecture feature derived from the target triple into the
170 // feature string. This is important for setting features that are implied
171 // based on the architecture version.
172 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple.getTriple(),
176 ArchFS = ArchFS + "," + FS.str();
180 ParseSubtargetFeatures(CPUString, ArchFS);
182 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
183 // Assert this for now to make the change obvious.
184 assert(hasV6T2Ops() || !hasThumb2());
186 // Keep a pointer to static instruction cost data for the specified CPU.
187 SchedModel = getSchedModelForCPU(CPUString);
189 // Initialize scheduling itinerary for the specified CPU.
190 InstrItins = getInstrItineraryForCPU(CPUString);
192 if (TargetABI == ARM_ABI_UNKNOWN) {
193 switch (TargetTriple.getEnvironment()) {
194 case Triple::Android:
197 case Triple::GNUEABI:
198 case Triple::GNUEABIHF:
199 TargetABI = ARM_ABI_AAPCS;
202 if ((isTargetIOS() && isMClass()) ||
203 (TargetTriple.isOSBinFormatMachO() &&
204 TargetTriple.getOS() == Triple::UnknownOS))
205 TargetABI = ARM_ABI_AAPCS;
207 TargetABI = ARM_ABI_APCS;
217 UseMovt = hasV6T2Ops() && ArmUseMOVT;
219 if (isTargetMachO()) {
220 IsR9Reserved = ReserveR9 | !HasV6Ops;
221 SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
223 IsR9Reserved = ReserveR9;
225 if (!isThumb() || hasThumb2())
226 PostRAScheduler = true;
230 // Assume pre-ARMv6 doesn't support unaligned accesses.
232 // ARMv6 may or may not support unaligned accesses depending on the
233 // SCTLR.U bit, which is architecture-specific. We assume ARMv6
234 // Darwin targets support unaligned accesses, and others don't.
236 // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
237 // which raises an alignment fault on unaligned accesses. Linux
238 // defaults this bit to 0 and handles it as a system-wide (not
239 // per-process) setting. It is therefore safe to assume that ARMv7+
240 // Linux targets support unaligned accesses. The same goes for NaCl.
242 // The above behavior is consistent with GCC.
244 (hasV7Ops() && (isTargetLinux() || isTargetNaCl() ||
245 isTargetNetBSD())) ||
246 (hasV6Ops() && (isTargetMachO() || isTargetNetBSD()));
249 AllowsUnalignedMem = false;
252 AllowsUnalignedMem = true;
258 RestrictIT = hasV8Ops() ? true : false;
268 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
269 uint64_t Bits = getFeatureBits();
270 if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
271 (Options.UnsafeFPMath || isTargetDarwin()))
272 UseNEONForSinglePrecisionFP = true;
275 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
277 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
278 Reloc::Model RelocM) const {
279 if (RelocM == Reloc::Static)
282 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
284 bool isDecl = GV->hasAvailableExternallyLinkage();
285 if (GV->isDeclaration() && !GV->isMaterializable())
288 if (!isTargetMachO()) {
289 // Extra load is needed for all externally visible.
290 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
294 if (RelocM == Reloc::PIC_) {
295 // If this is a strong reference to a definition, it is definitely not
297 if (!isDecl && !GV->isWeakForLinker())
300 // Unless we have a symbol with hidden visibility, we have to go through a
301 // normal $non_lazy_ptr stub because this symbol might be resolved late.
302 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
305 // If symbol visibility is hidden, we have a stub for common symbol
306 // references and external declarations.
307 if (isDecl || GV->hasCommonLinkage())
308 // Hidden $non_lazy_ptr reference.
313 // If this is a strong reference to a definition, it is definitely not
315 if (!isDecl && !GV->isWeakForLinker())
318 // Unless we have a symbol with hidden visibility, we have to go through a
319 // normal $non_lazy_ptr stub because this symbol might be resolved late.
320 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
328 unsigned ARMSubtarget::getMispredictionPenalty() const {
329 return SchedModel->MispredictPenalty;
332 bool ARMSubtarget::hasSinCos() const {
333 return getTargetTriple().getOS() == Triple::IOS &&
334 !getTargetTriple().isOSVersionLT(7, 0);
337 bool ARMSubtarget::enablePostRAScheduler(
338 CodeGenOpt::Level OptLevel,
339 TargetSubtargetInfo::AntiDepBreakMode& Mode,
340 RegClassVector& CriticalPathRCs) const {
341 Mode = TargetSubtargetInfo::ANTIDEP_NONE;
342 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;