1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
36 #define DEBUG_TYPE "arm-subtarget"
38 #define GET_SUBTARGETINFO_TARGET_DESC
39 #define GET_SUBTARGETINFO_CTOR
40 #include "ARMGenSubtargetInfo.inc"
43 ReserveR9("arm-reserve-r9", cl::Hidden,
44 cl::desc("Reserve R9, making it unavailable as GPR"));
47 ArmUseMOVT("arm-use-movt", cl::init(true), cl::Hidden);
50 UseFusedMulOps("arm-use-mulops",
51 cl::init(true), cl::Hidden);
61 static cl::opt<AlignMode>
62 Align(cl::desc("Load/store alignment support"),
63 cl::Hidden, cl::init(DefaultAlign),
65 clEnumValN(DefaultAlign, "arm-default-align",
66 "Generate unaligned accesses only on hardware/OS "
67 "combinations that are known to support them"),
68 clEnumValN(StrictAlign, "arm-strict-align",
69 "Disallow all unaligned memory accesses"),
70 clEnumValN(NoStrictAlign, "arm-no-strict-align",
71 "Allow unaligned memory accesses"),
80 static cl::opt<ITMode>
81 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
83 cl::values(clEnumValN(DefaultIT, "arm-default-it",
84 "Generate IT block based on arch"),
85 clEnumValN(RestrictedIT, "arm-restrict-it",
86 "Disallow deprecated IT based on ARMv8"),
87 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
88 "Allow IT blocks based on ARMv7"),
91 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
92 /// so that we can use initializer lists for subtarget initialization.
93 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
95 initializeEnvironment();
96 initSubtargetFeatures(CPU, FS);
100 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
102 ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
103 if (STI.isThumb1Only())
104 return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
106 return new ARMFrameLowering(STI);
109 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
110 const std::string &FS,
111 const ARMBaseTargetMachine &TM, bool IsLittle)
112 : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
113 ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
114 TargetTriple(TT), Options(TM.Options), TM(TM),
115 TSInfo(*TM.getDataLayout()),
116 FrameLowering(initializeFrameLowering(CPU, FS)),
117 // At this point initializeSubtargetDependencies has been called so
118 // we can query directly.
119 InstrInfo(isThumb1Only()
120 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
122 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
123 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
126 void ARMSubtarget::initializeEnvironment() {
141 UseNEONForSinglePrecisionFP = false;
142 UseMulOps = UseFusedMulOps;
144 HasVMLxForwarding = false;
149 IsR9Reserved = ReserveR9;
151 SupportsTailCall = false;
154 HasHardwareDivide = false;
155 HasHardwareDivideInARM = false;
156 HasT2ExtractPack = false;
157 HasDataBarrier = false;
158 Pref32BitThumb = false;
159 AvoidCPSRPartialUpdate = false;
160 AvoidMOVsShifterOperand = false;
162 HasMPExtension = false;
163 HasVirtualization = false;
166 HasTrustZone = false;
169 HasZeroCycleZeroing = false;
170 AllowsUnalignedMem = false;
173 UnsafeFPMath = false;
176 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
177 if (CPUString.empty()) {
178 if (isTargetDarwin() && TargetTriple.getArchName().endswith("v7s"))
179 // Default to the Swift CPU when targeting armv7s/thumbv7s.
182 CPUString = "generic";
185 // Insert the architecture feature derived from the target triple into the
186 // feature string. This is important for setting features that are implied
187 // based on the architecture version.
189 ARM_MC::ParseARMTriple(TargetTriple.getTriple(), CPUString);
192 ArchFS = ArchFS + "," + FS.str();
196 ParseSubtargetFeatures(CPUString, ArchFS);
198 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
199 // Assert this for now to make the change obvious.
200 assert(hasV6T2Ops() || !hasThumb2());
202 // Keep a pointer to static instruction cost data for the specified CPU.
203 SchedModel = getSchedModelForCPU(CPUString);
205 // Initialize scheduling itinerary for the specified CPU.
206 InstrItins = getInstrItineraryForCPU(CPUString);
208 // FIXME: this is invalid for WindowsCE
209 if (isTargetWindows())
217 UseMovt = hasV6T2Ops() && ArmUseMOVT;
219 if (isTargetMachO()) {
220 IsR9Reserved = ReserveR9 || !HasV6Ops;
221 SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
223 IsR9Reserved = ReserveR9;
224 SupportsTailCall = !isThumb1Only();
227 if (Align == DefaultAlign) {
228 // Assume pre-ARMv6 doesn't support unaligned accesses.
230 // ARMv6 may or may not support unaligned accesses depending on the
231 // SCTLR.U bit, which is architecture-specific. We assume ARMv6
232 // Darwin and NetBSD targets support unaligned accesses, and others don't.
234 // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
235 // which raises an alignment fault on unaligned accesses. Linux
236 // defaults this bit to 0 and handles it as a system-wide (not
237 // per-process) setting. It is therefore safe to assume that ARMv7+
238 // Linux targets support unaligned accesses. The same goes for NaCl.
240 // The above behavior is consistent with GCC.
242 (hasV7Ops() && (isTargetLinux() || isTargetNaCl() ||
243 isTargetNetBSD())) ||
244 (hasV6Ops() && (isTargetMachO() || isTargetNetBSD()));
246 AllowsUnalignedMem = !(Align == StrictAlign);
249 // No v6M core supports unaligned memory access (v6M ARM ARM A3.2)
251 AllowsUnalignedMem = false;
255 RestrictIT = hasV8Ops() ? true : false;
265 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
266 uint64_t Bits = getFeatureBits();
267 if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
268 (Options.UnsafeFPMath || isTargetDarwin()))
269 UseNEONForSinglePrecisionFP = true;
272 bool ARMSubtarget::isAPCS_ABI() const {
273 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
274 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
276 bool ARMSubtarget::isAAPCS_ABI() const {
277 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
278 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS;
281 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
283 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
284 Reloc::Model RelocM) const {
285 if (RelocM == Reloc::Static)
288 bool isDecl = GV->isDeclarationForLinker();
290 if (!isTargetMachO()) {
291 // Extra load is needed for all externally visible.
292 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
296 if (RelocM == Reloc::PIC_) {
297 // If this is a strong reference to a definition, it is definitely not
299 if (!isDecl && !GV->isWeakForLinker())
302 // Unless we have a symbol with hidden visibility, we have to go through a
303 // normal $non_lazy_ptr stub because this symbol might be resolved late.
304 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
307 // If symbol visibility is hidden, we have a stub for common symbol
308 // references and external declarations.
309 if (isDecl || GV->hasCommonLinkage())
310 // Hidden $non_lazy_ptr reference.
315 // If this is a strong reference to a definition, it is definitely not
317 if (!isDecl && !GV->isWeakForLinker())
320 // Unless we have a symbol with hidden visibility, we have to go through a
321 // normal $non_lazy_ptr stub because this symbol might be resolved late.
322 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
330 unsigned ARMSubtarget::getMispredictionPenalty() const {
331 return SchedModel.MispredictPenalty;
334 bool ARMSubtarget::hasSinCos() const {
335 return getTargetTriple().isiOS() && !getTargetTriple().isOSVersionLT(7, 0);
338 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
339 bool ARMSubtarget::enablePostMachineScheduler() const {
340 return (!isThumb() || hasThumb2());
343 bool ARMSubtarget::enableAtomicExpand() const {
344 return hasAnyDataBarrier() && !isThumb1Only();
347 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
348 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
349 // immediates as it is inherently position independent, and may be out of
351 return UseMovt && (isTargetWindows() ||
352 !MF.getFunction()->hasFnAttribute(Attribute::MinSize));