1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
36 #define DEBUG_TYPE "arm-subtarget"
38 #define GET_SUBTARGETINFO_TARGET_DESC
39 #define GET_SUBTARGETINFO_CTOR
40 #include "ARMGenSubtargetInfo.inc"
43 ReserveR9("arm-reserve-r9", cl::Hidden,
44 cl::desc("Reserve R9, making it unavailable as GPR"));
47 UseFusedMulOps("arm-use-mulops",
48 cl::init(true), cl::Hidden);
58 static cl::opt<AlignMode>
59 Align(cl::desc("Load/store alignment support"),
60 cl::Hidden, cl::init(DefaultAlign),
62 clEnumValN(DefaultAlign, "arm-default-align",
63 "Generate unaligned accesses only on hardware/OS "
64 "combinations that are known to support them"),
65 clEnumValN(StrictAlign, "arm-strict-align",
66 "Disallow all unaligned memory accesses"),
67 clEnumValN(NoStrictAlign, "arm-no-strict-align",
68 "Allow unaligned memory accesses"),
77 static cl::opt<ITMode>
78 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
80 cl::values(clEnumValN(DefaultIT, "arm-default-it",
81 "Generate IT block based on arch"),
82 clEnumValN(RestrictedIT, "arm-restrict-it",
83 "Disallow deprecated IT based on ARMv8"),
84 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
85 "Allow IT blocks based on ARMv7"),
88 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
89 /// so that we can use initializer lists for subtarget initialization.
90 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
92 initializeEnvironment();
93 initSubtargetFeatures(CPU, FS);
97 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
99 ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
100 if (STI.isThumb1Only())
101 return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
103 return new ARMFrameLowering(STI);
106 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
107 const std::string &FS,
108 const ARMBaseTargetMachine &TM, bool IsLittle)
109 : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
110 ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
111 TargetTriple(TT), Options(TM.Options), TM(TM),
112 FrameLowering(initializeFrameLowering(CPU, FS)),
113 // At this point initializeSubtargetDependencies has been called so
114 // we can query directly.
115 InstrInfo(isThumb1Only()
116 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
118 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
119 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
122 void ARMSubtarget::initializeEnvironment() {
138 UseNEONForSinglePrecisionFP = false;
139 UseMulOps = UseFusedMulOps;
141 HasVMLxForwarding = false;
144 UseSoftFloat = false;
147 IsR9Reserved = ReserveR9;
149 SupportsTailCall = false;
152 HasHardwareDivide = false;
153 HasHardwareDivideInARM = false;
154 HasT2ExtractPack = false;
155 HasDataBarrier = false;
156 Pref32BitThumb = false;
157 AvoidCPSRPartialUpdate = false;
158 AvoidMOVsShifterOperand = false;
160 HasMPExtension = false;
161 HasVirtualization = false;
164 HasTrustZone = false;
167 HasZeroCycleZeroing = false;
168 AllowsUnalignedMem = false;
171 GenLongCalls = false;
172 UnsafeFPMath = false;
175 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
176 if (CPUString.empty()) {
177 if (isTargetDarwin() && TargetTriple.getArchName().endswith("v7s"))
178 // Default to the Swift CPU when targeting armv7s/thumbv7s.
181 CPUString = "generic";
184 // Insert the architecture feature derived from the target triple into the
185 // feature string. This is important for setting features that are implied
186 // based on the architecture version.
187 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
190 ArchFS = (Twine(ArchFS) + "," + FS).str();
194 ParseSubtargetFeatures(CPUString, ArchFS);
196 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
197 // Assert this for now to make the change obvious.
198 assert(hasV6T2Ops() || !hasThumb2());
200 // Keep a pointer to static instruction cost data for the specified CPU.
201 SchedModel = getSchedModelForCPU(CPUString);
203 // Initialize scheduling itinerary for the specified CPU.
204 InstrItins = getInstrItineraryForCPU(CPUString);
206 // FIXME: this is invalid for WindowsCE
207 if (isTargetWindows())
215 if (isTargetMachO()) {
216 IsR9Reserved = ReserveR9 || !HasV6Ops;
217 SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
219 IsR9Reserved = ReserveR9;
220 SupportsTailCall = !isThumb1Only();
223 if (Align == DefaultAlign) {
224 // Assume pre-ARMv6 doesn't support unaligned accesses.
226 // ARMv6 may or may not support unaligned accesses depending on the
227 // SCTLR.U bit, which is architecture-specific. We assume ARMv6
228 // Darwin and NetBSD targets support unaligned accesses, and others don't.
230 // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
231 // which raises an alignment fault on unaligned accesses. Linux
232 // defaults this bit to 0 and handles it as a system-wide (not
233 // per-process) setting. It is therefore safe to assume that ARMv7+
234 // Linux targets support unaligned accesses. The same goes for NaCl.
236 // The above behavior is consistent with GCC.
238 (hasV7Ops() && (isTargetLinux() || isTargetNaCl() ||
239 isTargetNetBSD())) ||
240 (hasV6Ops() && (isTargetMachO() || isTargetNetBSD()));
242 AllowsUnalignedMem = !(Align == StrictAlign);
245 // No v6M core supports unaligned memory access (v6M ARM ARM A3.2)
247 AllowsUnalignedMem = false;
251 RestrictIT = hasV8Ops();
261 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
262 const FeatureBitset &Bits = getFeatureBits();
263 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
264 (Options.UnsafeFPMath || isTargetDarwin()))
265 UseNEONForSinglePrecisionFP = true;
268 bool ARMSubtarget::isAPCS_ABI() const {
269 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
270 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
272 bool ARMSubtarget::isAAPCS_ABI() const {
273 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
274 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS;
277 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
279 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
280 Reloc::Model RelocM) const {
281 if (RelocM == Reloc::Static)
284 bool isDef = GV->isStrongDefinitionForLinker();
286 if (!isTargetMachO()) {
287 // Extra load is needed for all externally visible.
288 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
292 // If this is a strong reference to a definition, it is definitely not
297 // Unless we have a symbol with hidden visibility, we have to go through a
298 // normal $non_lazy_ptr stub because this symbol might be resolved late.
299 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
302 if (RelocM == Reloc::PIC_) {
303 // If symbol visibility is hidden, we have a stub for common symbol
304 // references and external declarations.
305 if (GV->isDeclarationForLinker() || GV->hasCommonLinkage())
306 // Hidden $non_lazy_ptr reference.
314 unsigned ARMSubtarget::getMispredictionPenalty() const {
315 return SchedModel.MispredictPenalty;
318 bool ARMSubtarget::hasSinCos() const {
319 return getTargetTriple().isiOS() && !getTargetTriple().isOSVersionLT(7, 0);
322 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
323 bool ARMSubtarget::enablePostRAScheduler() const {
324 return (!isThumb() || hasThumb2());
327 bool ARMSubtarget::enableAtomicExpand() const {
328 return hasAnyDataBarrier() && !isThumb1Only();
331 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
332 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
333 // immediates as it is inherently position independent, and may be out of
335 return !NoMovt && hasV6T2Ops() &&
336 (isTargetWindows() ||
337 !MF.getFunction()->hasFnAttribute(Attribute::MinSize));
340 bool ARMSubtarget::useFastISel() const {
341 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
342 return TM.Options.EnableFastISel &&
343 ((isTargetMachO() && !isThumb1Only()) ||
344 (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));