1 //===- ARMScheduleV7.td - ARM v7 Scheduling Definitions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the ARM v7 processors.
12 //===----------------------------------------------------------------------===//
15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
17 // Dual issue pipeline represented by FU_Pipe0 | FU_Pipe1
19 def CortexA8Itineraries : ProcessorItineraries<[
21 // Two fully-pipelined integer ALU pipelines
24 InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
26 // Binary Instructions that produce a result
27 InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
28 InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 2]>,
29 InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1]>,
30 InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1, 1]>,
32 // Unary Instructions that produce a result
33 InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
34 InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
35 InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
37 // Compare instructions
38 InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
39 InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
40 InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
41 InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
43 // Move instructions, unconditional
44 InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1]>,
45 InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
46 InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
47 InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1, 1]>,
49 // Move instructions, conditional
50 InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
51 InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
52 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
53 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
55 // Integer multiply pipeline
56 // Result written in E5, but that is relative to the last cycle of multicycle,
57 // so we use 6 for those cases
59 InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>], [5, 1, 1]>,
60 InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe1], 0>,
61 InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
62 InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe1], 0>,
63 InstrStage<2, [FU_Pipe0]>], [6, 1, 1]>,
64 InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe1], 0>,
65 InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
66 InstrItinData<IIC_iMUL64 , [InstrStage<2, [FU_Pipe1], 0>,
67 InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
68 InstrItinData<IIC_iMAC64 , [InstrStage<2, [FU_Pipe1], 0>,
69 InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
71 // Integer load pipeline
73 // loads have an extra cycle of latency, but are fully pipelined
74 // use FU_Issue to enforce the 1 load/store per cycle limit
77 InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Issue], 0>,
78 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
79 InstrStage<1, [FU_LdSt0]>], [3, 1]>,
82 InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Issue], 0>,
83 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
84 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
86 // Scaled register offset, issues over 2 cycles
87 InstrItinData<IIC_iLoadsi , [InstrStage<2, [FU_Issue], 0>,
88 InstrStage<1, [FU_Pipe0], 0>,
89 InstrStage<1, [FU_Pipe1]>,
90 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
91 InstrStage<1, [FU_LdSt0]>], [4, 1, 1]>,
93 // Immediate offset with update
94 InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Issue], 0>,
95 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
96 InstrStage<1, [FU_LdSt0]>], [3, 2, 1]>,
98 // Register offset with update
99 InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Issue], 0>,
100 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
101 InstrStage<1, [FU_LdSt0]>], [3, 2, 1, 1]>,
103 // Scaled register offset with update, issues over 2 cycles
104 InstrItinData<IIC_iLoadsiu , [InstrStage<2, [FU_Issue], 0>,
105 InstrStage<1, [FU_Pipe0], 0>,
106 InstrStage<1, [FU_Pipe1]>,
107 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
108 InstrStage<1, [FU_LdSt0]>], [4, 3, 1, 1]>,
111 InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Issue], 0>,
112 InstrStage<2, [FU_Pipe0], 0>,
113 InstrStage<2, [FU_Pipe1]>,
114 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
115 InstrStage<1, [FU_LdSt0]>]>,
117 // Integer store pipeline
119 // use FU_Issue to enforce the 1 load/store per cycle limit
122 InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Issue], 0>,
123 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
124 InstrStage<1, [FU_LdSt0]>], [3, 1]>,
127 InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Issue], 0>,
128 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
129 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
131 // Scaled register offset, issues over 2 cycles
132 InstrItinData<IIC_iStoresi , [InstrStage<2, [FU_Issue], 0>,
133 InstrStage<1, [FU_Pipe0], 0>,
134 InstrStage<1, [FU_Pipe1]>,
135 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
136 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
138 // Immediate offset with update
139 InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Issue], 0>,
140 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
141 InstrStage<1, [FU_LdSt0]>], [2, 3, 1]>,
143 // Register offset with update
144 InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Issue], 0>,
145 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
146 InstrStage<1, [FU_LdSt0]>], [2, 3, 1, 1]>,
148 // Scaled register offset with update, issues over 2 cycles
149 InstrItinData<IIC_iStoresiu, [InstrStage<2, [FU_Issue], 0>,
150 InstrStage<1, [FU_Pipe0], 0>,
151 InstrStage<1, [FU_Pipe1]>,
152 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
153 InstrStage<1, [FU_LdSt0]>], [3, 3, 1, 1]>,
156 InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Issue], 0>,
157 InstrStage<2, [FU_Pipe0], 0>,
158 InstrStage<2, [FU_Pipe1]>,
159 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
160 InstrStage<1, [FU_LdSt0]>]>,
164 // no delay slots, so the latency of a branch is unimportant
165 InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
168 // Issue through integer pipeline, and execute in NEON unit. We assume
169 // RunFast mode so that NFP pipeline is used for single-precision when
172 // FP Special Register to Integer Register File Move
173 InstrItinData<IIC_fpSTAT , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
174 InstrStage<1, [FU_NLSPipe]>]>,
176 // Single-precision FP Unary
177 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
178 InstrStage<1, [FU_NPipe]>], [7, 1]>,
180 // Double-precision FP Unary
181 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
182 InstrStage<4, [FU_NPipe], 0>,
183 InstrStage<4, [FU_NLSPipe]>], [4, 1]>,
185 // Single-precision FP Compare
186 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
187 InstrStage<1, [FU_NPipe]>], [1, 1]>,
189 // Double-precision FP Compare
190 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
191 InstrStage<4, [FU_NPipe], 0>,
192 InstrStage<4, [FU_NLSPipe]>], [4, 1]>,
194 // Single to Double FP Convert
195 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
196 InstrStage<7, [FU_NPipe], 0>,
197 InstrStage<7, [FU_NLSPipe]>], [7, 1]>,
199 // Double to Single FP Convert
200 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
201 InstrStage<5, [FU_NPipe], 0>,
202 InstrStage<5, [FU_NLSPipe]>], [5, 1]>,
204 // Single-Precision FP to Integer Convert
205 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
206 InstrStage<1, [FU_NPipe]>], [7, 1]>,
208 // Double-Precision FP to Integer Convert
209 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
210 InstrStage<8, [FU_NPipe], 0>,
211 InstrStage<8, [FU_NLSPipe]>], [8, 1]>,
213 // Integer to Single-Precision FP Convert
214 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
215 InstrStage<1, [FU_NPipe]>], [7, 1]>,
217 // Integer to Double-Precision FP Convert
218 InstrItinData<IIC_fpCVTID , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
219 InstrStage<8, [FU_NPipe], 0>,
220 InstrStage<8, [FU_NLSPipe]>], [8, 1]>,
222 // Single-precision FP ALU
223 InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
224 InstrStage<1, [FU_NPipe]>], [7, 1, 1]>,
226 // Double-precision FP ALU
227 InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
228 InstrStage<9, [FU_NPipe], 0>,
229 InstrStage<9, [FU_NLSPipe]>], [9, 1, 1]>,
231 // Single-precision FP Multiply
232 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
233 InstrStage<1, [FU_NPipe]>], [7, 1, 1]>,
235 // Double-precision FP Multiply
236 InstrItinData<IIC_fpMUL64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
237 InstrStage<11, [FU_NPipe], 0>,
238 InstrStage<11, [FU_NLSPipe]>], [11, 1, 1]>,
240 // Single-precision FP MAC
241 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
242 InstrStage<1, [FU_NPipe]>], [7, 2, 1, 1]>,
244 // Double-precision FP MAC
245 InstrItinData<IIC_fpMAC64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
246 InstrStage<19, [FU_NPipe], 0>,
247 InstrStage<19, [FU_NLSPipe]>], [19, 2, 1, 1]>,
249 // Single-precision FP DIV
250 InstrItinData<IIC_fpDIV32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
251 InstrStage<20, [FU_NPipe], 0>,
252 InstrStage<20, [FU_NLSPipe]>], [20, 1, 1]>,
254 // Double-precision FP DIV
255 InstrItinData<IIC_fpDIV64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
256 InstrStage<29, [FU_NPipe], 0>,
257 InstrStage<29, [FU_NLSPipe]>], [29, 1, 1]>,
259 // Single-precision FP SQRT
260 InstrItinData<IIC_fpSQRT32, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
261 InstrStage<19, [FU_NPipe], 0>,
262 InstrStage<19, [FU_NLSPipe]>], [19, 1]>,
264 // Double-precision FP SQRT
265 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
266 InstrStage<29, [FU_NPipe], 0>,
267 InstrStage<29, [FU_NLSPipe]>], [29, 1]>,
269 // Single-precision FP Load
270 // use FU_Issue to enforce the 1 load/store per cycle limit
271 InstrItinData<IIC_fpLoad32, [InstrStage<1, [FU_Issue], 0>,
272 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
273 InstrStage<1, [FU_LdSt0], 0>,
274 InstrStage<1, [FU_NLSPipe]>]>,
276 // Double-precision FP Load
277 // use FU_Issue to enforce the 1 load/store per cycle limit
278 InstrItinData<IIC_fpLoad64, [InstrStage<2, [FU_Issue], 0>,
279 InstrStage<1, [FU_Pipe0], 0>,
280 InstrStage<1, [FU_Pipe1]>,
281 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
282 InstrStage<1, [FU_LdSt0], 0>,
283 InstrStage<1, [FU_NLSPipe]>]>,
286 // use FU_Issue to enforce the 1 load/store per cycle limit
287 InstrItinData<IIC_fpLoadm, [InstrStage<3, [FU_Issue], 0>,
288 InstrStage<2, [FU_Pipe0], 0>,
289 InstrStage<2, [FU_Pipe1]>,
290 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
291 InstrStage<1, [FU_LdSt0], 0>,
292 InstrStage<1, [FU_NLSPipe]>]>,
294 // Single-precision FP Store
295 // use FU_Issue to enforce the 1 load/store per cycle limit
296 InstrItinData<IIC_fpStore32,[InstrStage<1, [FU_Issue], 0>,
297 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
298 InstrStage<1, [FU_LdSt0], 0>,
299 InstrStage<1, [FU_NLSPipe]>]>,
301 // Double-precision FP Store
302 // use FU_Issue to enforce the 1 load/store per cycle limit
303 InstrItinData<IIC_fpStore64,[InstrStage<2, [FU_Issue], 0>,
304 InstrStage<1, [FU_Pipe0], 0>,
305 InstrStage<1, [FU_Pipe1]>,
306 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
307 InstrStage<1, [FU_LdSt0], 0>,
308 InstrStage<1, [FU_NLSPipe]>]>,
311 // use FU_Issue to enforce the 1 load/store per cycle limit
312 InstrItinData<IIC_fpStorem, [InstrStage<3, [FU_Issue], 0>,
313 InstrStage<2, [FU_Pipe0], 0>,
314 InstrStage<2, [FU_Pipe1]>,
315 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
316 InstrStage<1, [FU_LdSt0], 0>,
317 InstrStage<1, [FU_NLSPipe]>]>,
320 // Issue through integer pipeline, and execute in NEON unit.
323 InstrItinData<IIC_VLD1, [InstrStage<1, [FU_Issue], 0>,
324 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
325 InstrStage<1, [FU_LdSt0], 0>,
326 InstrStage<1, [FU_NLSPipe]>]>,
329 InstrItinData<IIC_VLD2, [InstrStage<1, [FU_Issue], 0>,
330 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
331 InstrStage<1, [FU_LdSt0], 0>,
332 InstrStage<1, [FU_NLSPipe]>], [2, 2, 1]>,
335 InstrItinData<IIC_VLD3, [InstrStage<1, [FU_Issue], 0>,
336 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
337 InstrStage<1, [FU_LdSt0], 0>,
338 InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 1]>,
341 InstrItinData<IIC_VLD4, [InstrStage<1, [FU_Issue], 0>,
342 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
343 InstrStage<1, [FU_LdSt0], 0>,
344 InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 2, 1]>,
347 InstrItinData<IIC_VST, [InstrStage<1, [FU_Issue], 0>,
348 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
349 InstrStage<1, [FU_LdSt0], 0>,
350 InstrStage<1, [FU_NLSPipe]>]>,
352 // Double-register FP Unary
353 InstrItinData<IIC_VUNAD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
354 InstrStage<1, [FU_NPipe]>], [5, 2]>,
356 // Quad-register FP Unary
357 // Result written in N5, but that is relative to the last cycle of multicycle,
358 // so we use 6 for those cases
359 InstrItinData<IIC_VUNAQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
360 InstrStage<2, [FU_NPipe]>], [6, 2]>,
362 // Double-register FP Binary
363 InstrItinData<IIC_VBIND, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
364 InstrStage<1, [FU_NPipe]>], [5, 2, 2]>,
366 // Quad-register FP Binary
367 // Result written in N5, but that is relative to the last cycle of multicycle,
368 // so we use 6 for those cases
369 InstrItinData<IIC_VBINQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
370 InstrStage<2, [FU_NPipe]>], [6, 2, 2]>,
373 InstrItinData<IIC_VMOVImm, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
374 InstrStage<1, [FU_NPipe]>], [3]>,
376 // Double-register Permute Move
377 InstrItinData<IIC_VMOVD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
378 InstrStage<1, [FU_NLSPipe]>], [2, 1]>,
380 // Quad-register Permute Move
381 // Result written in N2, but that is relative to the last cycle of multicycle,
382 // so we use 3 for those cases
383 InstrItinData<IIC_VMOVQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
384 InstrStage<2, [FU_NLSPipe]>], [3, 1]>,
386 // Integer to Single-precision Move
387 InstrItinData<IIC_VMOVIS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
388 InstrStage<1, [FU_NLSPipe]>], [2, 1]>,
390 // Integer to Double-precision Move
391 InstrItinData<IIC_VMOVID , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
392 InstrStage<1, [FU_NLSPipe]>], [2, 1, 1]>,
394 // Single-precision to Integer Move
395 InstrItinData<IIC_VMOVSI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
396 InstrStage<1, [FU_NLSPipe]>], [20, 1]>,
398 // Double-precision to Integer Move
399 InstrItinData<IIC_VMOVDI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
400 InstrStage<1, [FU_NLSPipe]>], [20, 20, 1]>,
402 // Integer to Lane Move
403 InstrItinData<IIC_VMOVISL , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
404 InstrStage<2, [FU_NLSPipe]>], [3, 1, 1]>,
406 // Double-register Permute
407 InstrItinData<IIC_VPERMD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
408 InstrStage<1, [FU_NLSPipe]>], [2, 2, 1, 1]>,
410 // Quad-register Permute
411 // Result written in N2, but that is relative to the last cycle of multicycle,
412 // so we use 3 for those cases
413 InstrItinData<IIC_VPERMQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
414 InstrStage<2, [FU_NLSPipe]>], [3, 3, 1, 1]>,
416 // Quad-register Permute (3 cycle issue)
417 // Result written in N2, but that is relative to the last cycle of multicycle,
418 // so we use 4 for those cases
419 InstrItinData<IIC_VPERMQ3, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
420 InstrStage<1, [FU_NLSPipe]>,
421 InstrStage<1, [FU_NPipe], 0>,
422 InstrStage<2, [FU_NLSPipe]>], [4, 4, 1, 1]>,
424 // Double-register FP Multiple-Accumulate
425 InstrItinData<IIC_VMACD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
426 InstrStage<1, [FU_NPipe]>], [9, 2, 2, 3]>,
428 // Quad-register FP Multiple-Accumulate
429 // Result written in N9, but that is relative to the last cycle of multicycle,
430 // so we use 10 for those cases
431 InstrItinData<IIC_VMACQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
432 InstrStage<2, [FU_NPipe]>], [10, 2, 2, 3]>,
434 // Double-register Reciprical Step
435 InstrItinData<IIC_VRECSD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
436 InstrStage<1, [FU_NPipe]>], [9, 2, 2]>,
438 // Quad-register Reciprical Step
439 InstrItinData<IIC_VRECSQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
440 InstrStage<2, [FU_NPipe]>], [10, 2, 2]>,
442 // Double-register Integer Count
443 InstrItinData<IIC_VCNTiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
444 InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
446 // Quad-register Integer Count
447 // Result written in N3, but that is relative to the last cycle of multicycle,
448 // so we use 4 for those cases
449 InstrItinData<IIC_VCNTiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
450 InstrStage<2, [FU_NPipe]>], [4, 2, 2]>,
452 // Double-register Integer Unary
453 InstrItinData<IIC_VUNAiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
454 InstrStage<1, [FU_NPipe]>], [4, 2]>,
456 // Quad-register Integer Unary
457 InstrItinData<IIC_VUNAiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
458 InstrStage<1, [FU_NPipe]>], [4, 2]>,
460 // Double-register Integer Q-Unary
461 InstrItinData<IIC_VQUNAiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
462 InstrStage<1, [FU_NPipe]>], [4, 1]>,
464 // Quad-register Integer CountQ-Unary
465 InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
466 InstrStage<1, [FU_NPipe]>], [4, 1]>,
468 // Double-register Integer Binary
469 InstrItinData<IIC_VBINiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
470 InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
472 // Quad-register Integer Binary
473 InstrItinData<IIC_VBINiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
474 InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
476 // Double-register Integer Binary (4 cycle)
477 InstrItinData<IIC_VBINi4D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
478 InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
480 // Quad-register Integer Binary (4 cycle)
481 InstrItinData<IIC_VBINi4Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
482 InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
485 // Double-register Integer Subtract
486 InstrItinData<IIC_VSUBiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
487 InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
489 // Quad-register Integer Subtract
490 InstrItinData<IIC_VSUBiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
491 InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
493 // Double-register Integer Subtract
494 InstrItinData<IIC_VSUBi4D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
495 InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
497 // Quad-register Integer Subtract
498 InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
499 InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
501 // Double-register Integer Shift
502 InstrItinData<IIC_VSHLiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
503 InstrStage<1, [FU_NPipe]>], [3, 1, 1]>,
505 // Quad-register Integer Shift
506 InstrItinData<IIC_VSHLiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
507 InstrStage<2, [FU_NPipe]>], [4, 1, 1]>,
509 // Double-register Integer Shift (4 cycle)
510 InstrItinData<IIC_VSHLi4D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
511 InstrStage<1, [FU_NPipe]>], [4, 1, 1]>,
513 // Quad-register Integer Shift (4 cycle)
514 InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
515 InstrStage<2, [FU_NPipe]>], [5, 1, 1]>,
517 // Double-register Integer Pair Add Long
518 InstrItinData<IIC_VPALiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
519 InstrStage<1, [FU_NPipe]>], [6, 3, 2, 1]>,
521 // Quad-register Integer Pair Add Long
522 InstrItinData<IIC_VPALiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
523 InstrStage<2, [FU_NPipe]>], [7, 3, 2, 1]>,
525 // Double-register Integer Multiply (.8, .16)
526 InstrItinData<IIC_VMULi16D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
527 InstrStage<1, [FU_NPipe]>], [6, 2, 2]>,
529 // Double-register Integer Multiply (.32)
530 InstrItinData<IIC_VMULi32D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
531 InstrStage<2, [FU_NPipe]>], [7, 2, 1]>,
533 // Quad-register Integer Multiply (.8, .16)
534 InstrItinData<IIC_VMULi16Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
535 InstrStage<2, [FU_NPipe]>], [7, 2, 2]>,
537 // Quad-register Integer Multiply (.32)
538 InstrItinData<IIC_VMULi32Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
539 InstrStage<1, [FU_NPipe]>,
540 InstrStage<2, [FU_NLSPipe], 0>,
541 InstrStage<3, [FU_NPipe]>], [9, 2, 1]>,
543 // Double-register Integer Multiply-Accumulate (.8, .16)
544 InstrItinData<IIC_VMACi16D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
545 InstrStage<1, [FU_NPipe]>], [6, 2, 2, 3]>,
547 // Double-register Integer Multiply-Accumulate (.32)
548 InstrItinData<IIC_VMACi32D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
549 InstrStage<2, [FU_NPipe]>], [7, 2, 1, 3]>,
551 // Quad-register Integer Multiply-Accumulate (.8, .16)
552 InstrItinData<IIC_VMACi16Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
553 InstrStage<2, [FU_NPipe]>], [7, 2, 2, 3]>,
555 // Quad-register Integer Multiply-Accumulate (.32)
556 InstrItinData<IIC_VMACi32Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
557 InstrStage<1, [FU_NPipe]>,
558 InstrStage<2, [FU_NLSPipe], 0>,
559 InstrStage<3, [FU_NPipe]>], [9, 2, 1, 3]>,
561 // Double-register VEXT
562 InstrItinData<IIC_VEXTD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
563 InstrStage<1, [FU_NLSPipe]>], [2, 1, 1]>,
565 // Quad-register VEXT
566 InstrItinData<IIC_VEXTQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
567 InstrStage<2, [FU_NLSPipe]>], [3, 1, 1]>,
570 InstrItinData<IIC_VTB1, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
571 InstrStage<2, [FU_NLSPipe]>], [3, 2, 1]>,
572 InstrItinData<IIC_VTB2, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
573 InstrStage<2, [FU_NLSPipe]>], [3, 2, 2, 1]>,
574 InstrItinData<IIC_VTB3, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
575 InstrStage<1, [FU_NLSPipe]>,
576 InstrStage<1, [FU_NPipe], 0>,
577 InstrStage<2, [FU_NLSPipe]>], [4, 2, 2, 3, 1]>,
578 InstrItinData<IIC_VTB4, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
579 InstrStage<1, [FU_NLSPipe]>,
580 InstrStage<1, [FU_NPipe], 0>,
581 InstrStage<2, [FU_NLSPipe]>], [4, 2, 2, 3, 3, 1]>,
584 InstrItinData<IIC_VTBX1, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
585 InstrStage<2, [FU_NLSPipe]>], [3, 1, 2, 1]>,
586 InstrItinData<IIC_VTBX2, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
587 InstrStage<2, [FU_NLSPipe]>], [3, 1, 2, 2, 1]>,
588 InstrItinData<IIC_VTBX3, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
589 InstrStage<1, [FU_NLSPipe]>,
590 InstrStage<1, [FU_NPipe], 0>,
591 InstrStage<2, [FU_NLSPipe]>], [4, 1, 2, 2, 3, 1]>,
592 InstrItinData<IIC_VTBX4, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
593 InstrStage<1, [FU_NLSPipe]>,
594 InstrStage<1, [FU_NPipe], 0>,
595 InstrStage<2, [FU_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>
599 // Ad-hoc scheduling information derived from pretty vague "Cortex-A9 Technical
600 // Reference Manual".
602 // Dual issue pipeline represented by FU_Pipe0 | FU_Pipe1
604 def CortexA9Itineraries : ProcessorItineraries<[
605 // VFP and NEON shares the same register file. This means that every VFP
606 // instruction should wait for full completion of the consecutive NEON
607 // instruction and vice-versa. We model this behavior with two artificial FUs:
608 // DRegsVFP and DRegsVFP.
610 // Every VFP instruction:
611 // - Acquires DRegsVFP resource for 1 cycle
612 // - Reserves DRegsN resource for the whole duration (including time to
613 // register file writeback!).
614 // Every NEON instruction does the same but with FUs swapped.
616 // Since the reserved FU cannot be acquired this models precisly "cross-domain"
620 // Issue through integer pipeline, and execute in NEON unit.
622 // FP Special Register to Integer Register File Move
623 InstrItinData<IIC_fpSTAT , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
624 InstrStage2<2, [FU_DRegsN], 0, Reserved>,
625 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
626 InstrStage<1, [FU_NPipe]>]>,
628 // Single-precision FP Unary
629 InstrItinData<IIC_fpUNA32 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
630 // Extra 1 latency cycle since wbck is 2 cycles
631 InstrStage2<3, [FU_DRegsN], 0, Reserved>,
632 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
633 InstrStage<1, [FU_NPipe]>], [1, 1]>,
635 // Double-precision FP Unary
636 InstrItinData<IIC_fpUNA64 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
637 // Extra 1 latency cycle since wbck is 2 cycles
638 InstrStage2<3, [FU_DRegsN], 0, Reserved>,
639 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
640 InstrStage<1, [FU_NPipe]>], [1, 1]>,
643 // Single-precision FP Compare
644 InstrItinData<IIC_fpCMP32 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
645 // Extra 3 latency cycle since wbck is 4 cycles
646 InstrStage2<5, [FU_DRegsN], 0, Reserved>,
647 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
648 InstrStage<1, [FU_NPipe]>], [1, 1]>,
650 // Double-precision FP Compare
651 InstrItinData<IIC_fpCMP64 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
652 // Extra 3 latency cycle since wbck is 4 cycles
653 InstrStage2<5, [FU_DRegsN], 0, Reserved>,
654 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
655 InstrStage<1, [FU_NPipe]>], [1, 1]>,
657 // Single to Double FP Convert
658 InstrItinData<IIC_fpCVTSD , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
659 InstrStage2<5, [FU_DRegsN], 0, Reserved>,
660 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
661 InstrStage<1, [FU_NPipe]>], [4, 1]>,
663 // Double to Single FP Convert
664 InstrItinData<IIC_fpCVTDS , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
665 InstrStage2<5, [FU_DRegsN], 0, Reserved>,
666 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
667 InstrStage<1, [FU_NPipe]>], [4, 1]>,
670 // Single to Half FP Convert
671 InstrItinData<IIC_fpCVTSH , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
672 InstrStage2<5, [FU_DRegsN], 0, Reserved>,
673 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
674 InstrStage<1, [FU_NPipe]>], [4, 1]>,
676 // Half to Single FP Convert
677 InstrItinData<IIC_fpCVTHS , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
678 InstrStage2<3, [FU_DRegsN], 0, Reserved>,
679 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
680 InstrStage<1, [FU_NPipe]>], [2, 1]>,
683 // Single-Precision FP to Integer Convert
684 InstrItinData<IIC_fpCVTSI , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
685 InstrStage2<5, [FU_DRegsN], 0, Reserved>,
686 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
687 InstrStage<1, [FU_NPipe]>], [4, 1]>,
689 // Double-Precision FP to Integer Convert
690 InstrItinData<IIC_fpCVTDI , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
691 InstrStage2<5, [FU_DRegsN], 0, Reserved>,
692 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
693 InstrStage<1, [FU_NPipe]>], [4, 1]>,
695 // Integer to Single-Precision FP Convert
696 InstrItinData<IIC_fpCVTIS , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
697 InstrStage2<5, [FU_DRegsN], 0, Reserved>,
698 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
699 InstrStage<1, [FU_NPipe]>], [4, 1]>,
701 // Integer to Double-Precision FP Convert
702 InstrItinData<IIC_fpCVTID , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
703 InstrStage2<5, [FU_DRegsN], 0, Reserved>,
704 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
705 InstrStage<1, [FU_NPipe]>], [4, 1]>,
707 // Single-precision FP ALU
708 InstrItinData<IIC_fpALU32 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
709 InstrStage2<5, [FU_DRegsN], 0, Reserved>,
710 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
711 InstrStage<1, [FU_NPipe]>], [4, 1, 1]>,
713 // Double-precision FP ALU
714 InstrItinData<IIC_fpALU64 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
715 InstrStage2<5, [FU_DRegsN], 0, Reserved>,
716 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
717 InstrStage<1, [FU_NPipe]>], [4, 1, 1]>,
719 // Single-precision FP Multiply
720 InstrItinData<IIC_fpMUL32 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
721 InstrStage2<6, [FU_DRegsN], 0, Reserved>,
722 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
723 InstrStage<1, [FU_NPipe]>], [5, 1, 1]>,
725 // Double-precision FP Multiply
726 InstrItinData<IIC_fpMUL64 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
727 InstrStage2<7, [FU_DRegsN], 0, Reserved>,
728 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
729 InstrStage<2, [FU_NPipe]>], [6, 1, 1]>,
731 // Single-precision FP MAC
732 InstrItinData<IIC_fpMAC32 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
733 InstrStage2<9, [FU_DRegsN], 0, Reserved>,
734 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
735 InstrStage<1, [FU_NPipe]>], [8, 0, 1, 1]>,
737 // Double-precision FP MAC
738 InstrItinData<IIC_fpMAC64 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
739 InstrStage2<10, [FU_DRegsN], 0, Reserved>,
740 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
741 InstrStage<2, [FU_NPipe]>], [9, 0, 1, 1]>,
743 // Single-precision FP DIV
744 InstrItinData<IIC_fpDIV32 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
745 InstrStage2<16, [FU_DRegsN], 0, Reserved>,
746 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
747 InstrStage<10, [FU_NPipe]>], [15, 1, 1]>,
749 // Double-precision FP DIV
750 InstrItinData<IIC_fpDIV64 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
751 InstrStage2<26, [FU_DRegsN], 0, Reserved>,
752 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
753 InstrStage<20, [FU_NPipe]>], [25, 1, 1]>,
755 // Single-precision FP SQRT
756 InstrItinData<IIC_fpSQRT32, [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
757 InstrStage2<18, [FU_DRegsN], 0, Reserved>,
758 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
759 InstrStage<13, [FU_NPipe]>], [17, 1]>,
761 // Double-precision FP SQRT
762 InstrItinData<IIC_fpSQRT64, [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
763 InstrStage2<33, [FU_DRegsN], 0, Reserved>,
764 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
765 InstrStage<28, [FU_NPipe]>], [32, 1]>,
768 // Integer to Single-precision Move
769 InstrItinData<IIC_fpMOVIS, [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
770 // Extra 1 latency cycle since wbck is 2 cycles
771 InstrStage2<3, [FU_DRegsN], 0, Reserved>,
772 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
773 InstrStage<1, [FU_NPipe]>], [1, 1]>,
775 // Integer to Double-precision Move
776 InstrItinData<IIC_fpMOVID, [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
777 // Extra 1 latency cycle since wbck is 2 cycles
778 InstrStage2<3, [FU_DRegsN], 0, Reserved>,
779 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
780 InstrStage<1, [FU_NPipe]>], [1, 1, 1]>,
782 // Single-precision to Integer Move
783 InstrItinData<IIC_fpMOVSI, [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
784 InstrStage2<2, [FU_DRegsN], 0, Reserved>,
785 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
786 InstrStage<1, [FU_NPipe]>], [1, 1]>,
788 // Double-precision to Integer Move
789 InstrItinData<IIC_fpMOVDI, [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
790 InstrStage2<2, [FU_DRegsN], 0, Reserved>,
791 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
792 InstrStage<1, [FU_NPipe]>], [1, 1, 1]>,
794 // Issue through integer pipeline, and execute in NEON unit.
797 // Double-register Integer Binary
798 InstrItinData<IIC_VBINiD, [InstrStage2<1, [FU_DRegsN], 0, Required>,
799 // Extra 3 latency cycle since wbck is 6 cycles
800 InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
801 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
802 InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
804 // Quad-register Integer Binary
805 InstrItinData<IIC_VBINiQ, [InstrStage2<1, [FU_DRegsN], 0, Required>,
806 // Extra 3 latency cycle since wbck is 6 cycles
807 InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
808 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
809 InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
811 // Double-register Integer Subtract
812 InstrItinData<IIC_VSUBiD, [InstrStage2<1, [FU_DRegsN], 0, Required>,
813 // Extra 3 latency cycle since wbck is 6 cycles
814 InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
815 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
816 InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
818 // Quad-register Integer Subtract
819 InstrItinData<IIC_VSUBiQ, [InstrStage2<1, [FU_DRegsN], 0, Required>,
820 // Extra 3 latency cycle since wbck is 6 cycles
821 InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
822 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
823 InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
825 // Double-register Integer Shift
826 InstrItinData<IIC_VSHLiD, [InstrStage2<1, [FU_DRegsN], 0, Required>,
827 // Extra 3 latency cycle since wbck is 6 cycles
828 InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
829 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
830 InstrStage<1, [FU_NPipe]>], [3, 1, 1]>,
832 // Double-register Integer Binary (4 cycle)
833 InstrItinData<IIC_VBINi4D, [InstrStage2<1, [FU_DRegsN], 0, Required>,
834 // Extra 3 latency cycle since wbck is 6 cycles
835 InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
836 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
837 InstrStage<1, [FU_NPipe]>], [4, 2, 2]>,
839 // Quad-register Integer Binary (4 cycle)
840 InstrItinData<IIC_VBINi4Q, [InstrStage2<1, [FU_DRegsN], 0, Required>,
841 // Extra 3 latency cycle since wbck is 6 cycles
842 InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
843 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
844 InstrStage<1, [FU_NPipe]>], [4, 2, 2]>,
846 // Double-register Integer Subtract (4 cycle)
847 InstrItinData<IIC_VSUBiD, [InstrStage2<1, [FU_DRegsN], 0, Required>,
848 // Extra 3 latency cycle since wbck is 6 cycles
849 InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
850 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
851 InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
853 // Quad-register Integer Subtract (4 cycle)
854 InstrItinData<IIC_VSUBiQ, [InstrStage2<1, [FU_DRegsN], 0, Required>,
855 // Extra 3 latency cycle since wbck is 6 cycles
856 InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
857 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
858 InstrStage<1, [FU_NPipe]>], [4, 2, 1]>