lib/Target/ARM/ARMScheduleV7.td

   1 //===- ARMScheduleV7.td - ARM v7 Scheduling Definitions ----*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM v7 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //
  15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
  16 //
  17 // Dual issue pipeline represented by FU_Pipe0 | FU_Pipe1
  18 //
  19 def CortexA8Itineraries : ProcessorItineraries<[
  20
  21   // Two fully-pipelined integer ALU pipelines
  22   //
  23   // No operand cycles
  24   InstrItinData<IIC_iALUx    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
  25   //
  26   // Binary Instructions that produce a result
  27   InstrItinData<IIC_iALUi    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
  28   InstrItinData<IIC_iALUr    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 2]>,
  29   InstrItinData<IIC_iALUsi   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1]>,
  30   InstrItinData<IIC_iALUsr   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1, 1]>,
  31   //
  32   // Unary Instructions that produce a result
  33   InstrItinData<IIC_iUNAr    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
  34   InstrItinData<IIC_iUNAsi   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
  35   InstrItinData<IIC_iUNAsr   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
  36   //
  37   // Compare instructions
  38   InstrItinData<IIC_iCMPi    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
  39   InstrItinData<IIC_iCMPr    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
  40   InstrItinData<IIC_iCMPsi   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
  41   InstrItinData<IIC_iCMPsr   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
  42   //
  43   // Move instructions, unconditional
  44   InstrItinData<IIC_iMOVi    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1]>,
  45   InstrItinData<IIC_iMOVr    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
  46   InstrItinData<IIC_iMOVsi   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
  47   InstrItinData<IIC_iMOVsr   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1, 1]>,
  48   //
  49   // Move instructions, conditional
  50   InstrItinData<IIC_iCMOVi   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
  51   InstrItinData<IIC_iCMOVr   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
  52   InstrItinData<IIC_iCMOVsi  , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
  53   InstrItinData<IIC_iCMOVsr  , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
  54
  55   // Integer multiply pipeline
  56   // Result written in E5, but that is relative to the last cycle of multicycle,
  57   // so we use 6 for those cases
  58   //
  59   InstrItinData<IIC_iMUL16   , [InstrStage<1, [FU_Pipe0]>], [5, 1, 1]>,
  60   InstrItinData<IIC_iMAC16   , [InstrStage<1, [FU_Pipe1], 0>,
  61                                 InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
  62   InstrItinData<IIC_iMUL32   , [InstrStage<1, [FU_Pipe1], 0>,
  63                                 InstrStage<2, [FU_Pipe0]>], [6, 1, 1]>,
  64   InstrItinData<IIC_iMAC32   , [InstrStage<1, [FU_Pipe1], 0>,
  65                                 InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
  66   InstrItinData<IIC_iMUL64   , [InstrStage<2, [FU_Pipe1], 0>,
  67                                 InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
  68   InstrItinData<IIC_iMAC64   , [InstrStage<2, [FU_Pipe1], 0>,
  69                                 InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
  70
  71   // Integer load pipeline
  72   //
  73   // loads have an extra cycle of latency, but are fully pipelined
  74   // use FU_Issue to enforce the 1 load/store per cycle limit
  75   //
  76   // Immediate offset
  77   InstrItinData<IIC_iLoadi   , [InstrStage<1, [FU_Issue], 0>,
  78                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
  79                                 InstrStage<1, [FU_LdSt0]>], [3, 1]>,
  80   //
  81   // Register offset
  82   InstrItinData<IIC_iLoadr   , [InstrStage<1, [FU_Issue], 0>,
  83                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
  84                                 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
  85   //
  86   // Scaled register offset, issues over 2 cycles
  87   InstrItinData<IIC_iLoadsi  , [InstrStage<2, [FU_Issue], 0>,
  88                                 InstrStage<1, [FU_Pipe0], 0>,
  89                                 InstrStage<1, [FU_Pipe1]>,
  90                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
  91                                 InstrStage<1, [FU_LdSt0]>], [4, 1, 1]>,
  92   //
  93   // Immediate offset with update
  94   InstrItinData<IIC_iLoadiu  , [InstrStage<1, [FU_Issue], 0>,
  95                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
  96                                 InstrStage<1, [FU_LdSt0]>], [3, 2, 1]>,
  97   //
  98   // Register offset with update
  99   InstrItinData<IIC_iLoadru  , [InstrStage<1, [FU_Issue], 0>,
 100                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 101                                 InstrStage<1, [FU_LdSt0]>], [3, 2, 1, 1]>,
 102   //
 103   // Scaled register offset with update, issues over 2 cycles
 104   InstrItinData<IIC_iLoadsiu , [InstrStage<2, [FU_Issue], 0>,
 105                                 InstrStage<1, [FU_Pipe0], 0>,
 106                                 InstrStage<1, [FU_Pipe1]>,
 107                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 108                                 InstrStage<1, [FU_LdSt0]>], [4, 3, 1, 1]>,
 109   //
 110   // Load multiple
 111   InstrItinData<IIC_iLoadm   , [InstrStage<2, [FU_Issue], 0>,
 112                                 InstrStage<2, [FU_Pipe0], 0>,
 113                                 InstrStage<2, [FU_Pipe1]>,
 114                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 115                                 InstrStage<1, [FU_LdSt0]>]>,
 116
 117   // Integer store pipeline
 118   //
 119   // use FU_Issue to enforce the 1 load/store per cycle limit
 120   //
 121   // Immediate offset
 122   InstrItinData<IIC_iStorei  , [InstrStage<1, [FU_Issue], 0>,
 123                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 124                                 InstrStage<1, [FU_LdSt0]>], [3, 1]>,
 125   //
 126   // Register offset
 127   InstrItinData<IIC_iStorer  , [InstrStage<1, [FU_Issue], 0>,
 128                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 129                                 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
 130   //
 131   // Scaled register offset, issues over 2 cycles
 132   InstrItinData<IIC_iStoresi , [InstrStage<2, [FU_Issue], 0>,
 133                                 InstrStage<1, [FU_Pipe0], 0>,
 134                                 InstrStage<1, [FU_Pipe1]>,
 135                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 136                                 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
 137   //
 138   // Immediate offset with update
 139   InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Issue], 0>,
 140                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 141                                 InstrStage<1, [FU_LdSt0]>], [2, 3, 1]>,
 142   //
 143   // Register offset with update
 144   InstrItinData<IIC_iStoreru  , [InstrStage<1, [FU_Issue], 0>,
 145                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 146                                 InstrStage<1, [FU_LdSt0]>], [2, 3, 1, 1]>,
 147   //
 148   // Scaled register offset with update, issues over 2 cycles
 149   InstrItinData<IIC_iStoresiu, [InstrStage<2, [FU_Issue], 0>,
 150                                 InstrStage<1, [FU_Pipe0], 0>,
 151                                 InstrStage<1, [FU_Pipe1]>,
 152                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 153                                 InstrStage<1, [FU_LdSt0]>], [3, 3, 1, 1]>,
 154   //
 155   // Store multiple
 156   InstrItinData<IIC_iStorem  , [InstrStage<2, [FU_Issue], 0>,
 157                                 InstrStage<2, [FU_Pipe0], 0>,
 158                                 InstrStage<2, [FU_Pipe1]>,
 159                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 160                                 InstrStage<1, [FU_LdSt0]>]>,
 161
 162   // Branch
 163   //
 164   // no delay slots, so the latency of a branch is unimportant
 165   InstrItinData<IIC_Br      , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
 166
 167   // VFP
 168   // Issue through integer pipeline, and execute in NEON unit. We assume
 169   // RunFast mode so that NFP pipeline is used for single-precision when
 170   // possible.
 171   //
 172   // FP Special Register to Integer Register File Move
 173   InstrItinData<IIC_fpSTAT , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 174                               InstrStage<1, [FU_NLSPipe]>]>,
 175   //
 176   // Single-precision FP Unary
 177   InstrItinData<IIC_fpUNA32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 178                                InstrStage<1, [FU_NPipe]>], [7, 1]>,
 179   //
 180   // Double-precision FP Unary
 181   InstrItinData<IIC_fpUNA64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 182                                InstrStage<4, [FU_NPipe], 0>,
 183                                InstrStage<4, [FU_NLSPipe]>], [4, 1]>,
 184   //
 185   // Single-precision FP Compare
 186   InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 187                                InstrStage<1, [FU_NPipe]>], [1, 1]>,
 188   //
 189   // Double-precision FP Compare
 190   InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 191                                InstrStage<4, [FU_NPipe], 0>,
 192                                InstrStage<4, [FU_NLSPipe]>], [4, 1]>,
 193   //
 194   // Single to Double FP Convert
 195   InstrItinData<IIC_fpCVTSD , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 196                                InstrStage<7, [FU_NPipe], 0>,
 197                                InstrStage<7, [FU_NLSPipe]>], [7, 1]>,
 198   //
 199   // Double to Single FP Convert
 200   InstrItinData<IIC_fpCVTDS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 201                                InstrStage<5, [FU_NPipe], 0>,
 202                                InstrStage<5, [FU_NLSPipe]>], [5, 1]>,
 203   //
 204   // Single-Precision FP to Integer Convert
 205   InstrItinData<IIC_fpCVTSI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 206                                InstrStage<1, [FU_NPipe]>], [7, 1]>,
 207   //
 208   // Double-Precision FP to Integer Convert
 209   InstrItinData<IIC_fpCVTDI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 210                                InstrStage<8, [FU_NPipe], 0>,
 211                                InstrStage<8, [FU_NLSPipe]>], [8, 1]>,
 212   //
 213   // Integer to Single-Precision FP Convert
 214   InstrItinData<IIC_fpCVTIS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 215                                InstrStage<1, [FU_NPipe]>], [7, 1]>,
 216   //
 217   // Integer to Double-Precision FP Convert
 218   InstrItinData<IIC_fpCVTID , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 219                                InstrStage<8, [FU_NPipe], 0>,
 220                                InstrStage<8, [FU_NLSPipe]>], [8, 1]>,
 221   //
 222   // Single-precision FP ALU
 223   InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 224                                InstrStage<1, [FU_NPipe]>], [7, 1, 1]>,
 225   //
 226   // Double-precision FP ALU
 227   InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 228                                InstrStage<9, [FU_NPipe], 0>,
 229                                InstrStage<9, [FU_NLSPipe]>], [9, 1, 1]>,
 230   //
 231   // Single-precision FP Multiply
 232   InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 233                                InstrStage<1, [FU_NPipe]>], [7, 1, 1]>,
 234   //
 235   // Double-precision FP Multiply
 236   InstrItinData<IIC_fpMUL64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 237                                InstrStage<11, [FU_NPipe], 0>,
 238                                InstrStage<11, [FU_NLSPipe]>], [11, 1, 1]>,
 239   //
 240   // Single-precision FP MAC
 241   InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 242                                InstrStage<1, [FU_NPipe]>], [7, 2, 1, 1]>,
 243   //
 244   // Double-precision FP MAC
 245   InstrItinData<IIC_fpMAC64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 246                                InstrStage<19, [FU_NPipe], 0>,
 247                                InstrStage<19, [FU_NLSPipe]>], [19, 2, 1, 1]>,
 248   //
 249   // Single-precision FP DIV
 250   InstrItinData<IIC_fpDIV32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 251                                InstrStage<20, [FU_NPipe], 0>,
 252                                InstrStage<20, [FU_NLSPipe]>], [20, 1, 1]>,
 253   //
 254   // Double-precision FP DIV
 255   InstrItinData<IIC_fpDIV64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 256                                InstrStage<29, [FU_NPipe], 0>,
 257                                InstrStage<29, [FU_NLSPipe]>], [29, 1, 1]>,
 258   //
 259   // Single-precision FP SQRT
 260   InstrItinData<IIC_fpSQRT32, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 261                                InstrStage<19, [FU_NPipe], 0>,
 262                                InstrStage<19, [FU_NLSPipe]>], [19, 1]>,
 263   //
 264   // Double-precision FP SQRT
 265   InstrItinData<IIC_fpSQRT64, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 266                                InstrStage<29, [FU_NPipe], 0>,
 267                                InstrStage<29, [FU_NLSPipe]>], [29, 1]>,
 268   //
 269   // Single-precision FP Load
 270   // use FU_Issue to enforce the 1 load/store per cycle limit
 271   InstrItinData<IIC_fpLoad32, [InstrStage<1, [FU_Issue], 0>,
 272                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 273                                InstrStage<1, [FU_LdSt0], 0>,
 274                                InstrStage<1, [FU_NLSPipe]>]>,
 275   //
 276   // Double-precision FP Load
 277   // use FU_Issue to enforce the 1 load/store per cycle limit
 278   InstrItinData<IIC_fpLoad64, [InstrStage<2, [FU_Issue], 0>,
 279                                InstrStage<1, [FU_Pipe0], 0>,
 280                                InstrStage<1, [FU_Pipe1]>,
 281                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 282                                InstrStage<1, [FU_LdSt0], 0>,
 283                                InstrStage<1, [FU_NLSPipe]>]>,
 284   //
 285   // FP Load Multiple
 286   // use FU_Issue to enforce the 1 load/store per cycle limit
 287   InstrItinData<IIC_fpLoadm,  [InstrStage<3, [FU_Issue], 0>,
 288                                InstrStage<2, [FU_Pipe0], 0>,
 289                                InstrStage<2, [FU_Pipe1]>,
 290                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 291                                InstrStage<1, [FU_LdSt0], 0>,
 292                                InstrStage<1, [FU_NLSPipe]>]>,
 293   //
 294   // Single-precision FP Store
 295   // use FU_Issue to enforce the 1 load/store per cycle limit
 296   InstrItinData<IIC_fpStore32,[InstrStage<1, [FU_Issue], 0>,
 297                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 298                                InstrStage<1, [FU_LdSt0], 0>,
 299                                InstrStage<1, [FU_NLSPipe]>]>,
 300   //
 301   // Double-precision FP Store
 302   // use FU_Issue to enforce the 1 load/store per cycle limit
 303   InstrItinData<IIC_fpStore64,[InstrStage<2, [FU_Issue], 0>,
 304                                InstrStage<1, [FU_Pipe0], 0>,
 305                                InstrStage<1, [FU_Pipe1]>,
 306                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 307                                InstrStage<1, [FU_LdSt0], 0>,
 308                                InstrStage<1, [FU_NLSPipe]>]>,
 309   //
 310   // FP Store Multiple
 311   // use FU_Issue to enforce the 1 load/store per cycle limit
 312   InstrItinData<IIC_fpStorem, [InstrStage<3, [FU_Issue], 0>,
 313                                InstrStage<2, [FU_Pipe0], 0>,
 314                                InstrStage<2, [FU_Pipe1]>,
 315                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 316                                InstrStage<1, [FU_LdSt0], 0>,
 317                                InstrStage<1, [FU_NLSPipe]>]>,
 318
 319   // NEON
 320   // Issue through integer pipeline, and execute in NEON unit.
 321   //
 322   // VLD1
 323   InstrItinData<IIC_VLD1,     [InstrStage<1, [FU_Issue], 0>,
 324                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 325                                InstrStage<1, [FU_LdSt0], 0>,
 326                                InstrStage<1, [FU_NLSPipe]>]>,
 327   //
 328   // VLD2
 329   InstrItinData<IIC_VLD2,     [InstrStage<1, [FU_Issue], 0>,
 330                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 331                                InstrStage<1, [FU_LdSt0], 0>,
 332                                InstrStage<1, [FU_NLSPipe]>], [2, 2, 1]>,
 333   //
 334   // VLD3
 335   InstrItinData<IIC_VLD3,     [InstrStage<1, [FU_Issue], 0>,
 336                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 337                                InstrStage<1, [FU_LdSt0], 0>,
 338                                InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 1]>,
 339   //
 340   // VLD4
 341   InstrItinData<IIC_VLD4,     [InstrStage<1, [FU_Issue], 0>,
 342                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 343                                InstrStage<1, [FU_LdSt0], 0>,
 344                                InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 2, 1]>,
 345   //
 346   // VST
 347   InstrItinData<IIC_VST,      [InstrStage<1, [FU_Issue], 0>,
 348                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 349                                InstrStage<1, [FU_LdSt0], 0>,
 350                                InstrStage<1, [FU_NLSPipe]>]>,
 351   //
 352   // Double-register FP Unary
 353   InstrItinData<IIC_VUNAD,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 354                                InstrStage<1, [FU_NPipe]>], [5, 2]>,
 355   //
 356   // Quad-register FP Unary
 357   // Result written in N5, but that is relative to the last cycle of multicycle,
 358   // so we use 6 for those cases
 359   InstrItinData<IIC_VUNAQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 360                                InstrStage<2, [FU_NPipe]>], [6, 2]>,
 361   //
 362   // Double-register FP Binary
 363   InstrItinData<IIC_VBIND,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 364                                InstrStage<1, [FU_NPipe]>], [5, 2, 2]>,
 365   //
 366   // Quad-register FP Binary
 367   // Result written in N5, but that is relative to the last cycle of multicycle,
 368   // so we use 6 for those cases
 369   InstrItinData<IIC_VBINQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 370                                InstrStage<2, [FU_NPipe]>], [6, 2, 2]>,
 371   //
 372   // Move Immediate
 373   InstrItinData<IIC_VMOVImm,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 374                                InstrStage<1, [FU_NPipe]>], [3]>,
 375   //
 376   // Double-register Permute Move
 377   InstrItinData<IIC_VMOVD,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 378                                InstrStage<1, [FU_NLSPipe]>], [2, 1]>,
 379   //
 380   // Quad-register Permute Move
 381   // Result written in N2, but that is relative to the last cycle of multicycle,
 382   // so we use 3 for those cases
 383   InstrItinData<IIC_VMOVQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 384                                InstrStage<2, [FU_NLSPipe]>], [3, 1]>,
 385   //
 386   // Integer to Single-precision Move
 387   InstrItinData<IIC_VMOVIS ,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 388                                InstrStage<1, [FU_NLSPipe]>], [2, 1]>,
 389   //
 390   // Integer to Double-precision Move
 391   InstrItinData<IIC_VMOVID ,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 392                                InstrStage<1, [FU_NLSPipe]>], [2, 1, 1]>,
 393   //
 394   // Single-precision to Integer Move
 395   InstrItinData<IIC_VMOVSI ,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 396                                InstrStage<1, [FU_NLSPipe]>], [20, 1]>,
 397   //
 398   // Double-precision to Integer Move
 399   InstrItinData<IIC_VMOVDI ,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 400                                InstrStage<1, [FU_NLSPipe]>], [20, 20, 1]>,
 401   //
 402   // Integer to Lane Move
 403   InstrItinData<IIC_VMOVISL , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 404                                InstrStage<2, [FU_NLSPipe]>], [3, 1, 1]>,
 405   //
 406   // Double-register Permute
 407   InstrItinData<IIC_VPERMD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 408                                InstrStage<1, [FU_NLSPipe]>], [2, 2, 1, 1]>,
 409   //
 410   // Quad-register Permute
 411   // Result written in N2, but that is relative to the last cycle of multicycle,
 412   // so we use 3 for those cases
 413   InstrItinData<IIC_VPERMQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 414                                InstrStage<2, [FU_NLSPipe]>], [3, 3, 1, 1]>,
 415   //
 416   // Quad-register Permute (3 cycle issue)
 417   // Result written in N2, but that is relative to the last cycle of multicycle,
 418   // so we use 4 for those cases
 419   InstrItinData<IIC_VPERMQ3,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 420                                InstrStage<1, [FU_NLSPipe]>,
 421                                InstrStage<1, [FU_NPipe], 0>,
 422                                InstrStage<2, [FU_NLSPipe]>], [4, 4, 1, 1]>,
 423   //
 424   // Double-register FP Multiple-Accumulate
 425   InstrItinData<IIC_VMACD,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 426                                InstrStage<1, [FU_NPipe]>], [9, 2, 2, 3]>,
 427   //
 428   // Quad-register FP Multiple-Accumulate
 429   // Result written in N9, but that is relative to the last cycle of multicycle,
 430   // so we use 10 for those cases
 431   InstrItinData<IIC_VMACQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 432                                InstrStage<2, [FU_NPipe]>], [10, 2, 2, 3]>,
 433   //
 434   // Double-register Reciprical Step
 435   InstrItinData<IIC_VRECSD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 436                                InstrStage<1, [FU_NPipe]>], [9, 2, 2]>,
 437   //
 438   // Quad-register Reciprical Step
 439   InstrItinData<IIC_VRECSQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 440                                InstrStage<2, [FU_NPipe]>], [10, 2, 2]>,
 441   //
 442   // Double-register Integer Count
 443   InstrItinData<IIC_VCNTiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 444                                InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
 445   //
 446   // Quad-register Integer Count
 447   // Result written in N3, but that is relative to the last cycle of multicycle,
 448   // so we use 4 for those cases
 449   InstrItinData<IIC_VCNTiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 450                                InstrStage<2, [FU_NPipe]>], [4, 2, 2]>,
 451   //
 452   // Double-register Integer Unary
 453   InstrItinData<IIC_VUNAiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 454                                InstrStage<1, [FU_NPipe]>], [4, 2]>,
 455   //
 456   // Quad-register Integer Unary
 457   InstrItinData<IIC_VUNAiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 458                                InstrStage<1, [FU_NPipe]>], [4, 2]>,
 459   //
 460   // Double-register Integer Q-Unary
 461   InstrItinData<IIC_VQUNAiD,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 462                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 463   //
 464   // Quad-register Integer CountQ-Unary
 465   InstrItinData<IIC_VQUNAiQ,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 466                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 467   //
 468   // Double-register Integer Binary
 469   InstrItinData<IIC_VBINiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 470                                InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
 471   //
 472   // Quad-register Integer Binary
 473   InstrItinData<IIC_VBINiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 474                                InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
 475   //
 476   // Double-register Integer Binary (4 cycle)
 477   InstrItinData<IIC_VBINi4D,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 478                                InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
 479   //
 480   // Quad-register Integer Binary (4 cycle)
 481   InstrItinData<IIC_VBINi4Q,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 482                                InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
 483
 484   //
 485   // Double-register Integer Subtract
 486   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 487                                InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
 488   //
 489   // Quad-register Integer Subtract
 490   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 491                                InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
 492   //
 493   // Double-register Integer Subtract
 494   InstrItinData<IIC_VSUBi4D,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 495                                InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
 496   //
 497   // Quad-register Integer Subtract
 498   InstrItinData<IIC_VSUBi4Q,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 499                                InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
 500   //
 501   // Double-register Integer Shift
 502   InstrItinData<IIC_VSHLiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 503                                InstrStage<1, [FU_NPipe]>], [3, 1, 1]>,
 504   //
 505   // Quad-register Integer Shift
 506   InstrItinData<IIC_VSHLiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 507                                InstrStage<2, [FU_NPipe]>], [4, 1, 1]>,
 508   //
 509   // Double-register Integer Shift (4 cycle)
 510   InstrItinData<IIC_VSHLi4D,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 511                                InstrStage<1, [FU_NPipe]>], [4, 1, 1]>,
 512   //
 513   // Quad-register Integer Shift (4 cycle)
 514   InstrItinData<IIC_VSHLi4Q,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 515                                InstrStage<2, [FU_NPipe]>], [5, 1, 1]>,
 516   //
 517   // Double-register Integer Pair Add Long
 518   InstrItinData<IIC_VPALiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 519                                InstrStage<1, [FU_NPipe]>], [6, 3, 1]>,
 520   //
 521   // Quad-register Integer Pair Add Long
 522   InstrItinData<IIC_VPALiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 523                                InstrStage<2, [FU_NPipe]>], [7, 3, 1]>,
 524   //
 525   // Double-register Absolute Difference and Accumulate
 526   InstrItinData<IIC_VABAD,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 527                                InstrStage<1, [FU_NPipe]>], [6, 3, 2, 1]>,
 528   //
 529   // Quad-register Absolute Difference and Accumulate
 530   InstrItinData<IIC_VABAQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 531                                InstrStage<2, [FU_NPipe]>], [6, 3, 2, 1]>,
 532
 533   //
 534   // Double-register Integer Multiply (.8, .16)
 535   InstrItinData<IIC_VMULi16D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 536                                InstrStage<1, [FU_NPipe]>], [6, 2, 2]>,
 537   //
 538   // Double-register Integer Multiply (.32)
 539   InstrItinData<IIC_VMULi32D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 540                                InstrStage<2, [FU_NPipe]>], [7, 2, 1]>,
 541   //
 542   // Quad-register Integer Multiply (.8, .16)
 543   InstrItinData<IIC_VMULi16Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 544                                InstrStage<2, [FU_NPipe]>], [7, 2, 2]>,
 545   //
 546   // Quad-register Integer Multiply (.32)
 547   InstrItinData<IIC_VMULi32Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 548                                InstrStage<1, [FU_NPipe]>,
 549                                InstrStage<2, [FU_NLSPipe], 0>,
 550                                InstrStage<3, [FU_NPipe]>], [9, 2, 1]>,
 551   //
 552   // Double-register Integer Multiply-Accumulate (.8, .16)
 553   InstrItinData<IIC_VMACi16D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 554                                InstrStage<1, [FU_NPipe]>], [6, 3, 2, 2]>,
 555   //
 556   // Double-register Integer Multiply-Accumulate (.32)
 557   InstrItinData<IIC_VMACi32D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 558                                InstrStage<2, [FU_NPipe]>], [7, 3, 2, 1]>,
 559   //
 560   // Quad-register Integer Multiply-Accumulate (.8, .16)
 561   InstrItinData<IIC_VMACi16Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 562                                InstrStage<2, [FU_NPipe]>], [7, 3, 2, 2]>,
 563   //
 564   // Quad-register Integer Multiply-Accumulate (.32)
 565   InstrItinData<IIC_VMACi32Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 566                                InstrStage<1, [FU_NPipe]>,
 567                                InstrStage<2, [FU_NLSPipe], 0>,
 568                                InstrStage<3, [FU_NPipe]>], [9, 3, 2, 1]>,
 569   //
 570   // Double-register VEXT
 571   InstrItinData<IIC_VEXTD,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 572                                InstrStage<1, [FU_NLSPipe]>], [2, 1, 1]>,
 573   //
 574   // Quad-register VEXT
 575   InstrItinData<IIC_VEXTQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 576                                InstrStage<2, [FU_NLSPipe]>], [3, 1, 1]>,
 577   //
 578   // VTB
 579   InstrItinData<IIC_VTB1,     [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 580                                InstrStage<2, [FU_NLSPipe]>], [3, 2, 1]>,
 581   InstrItinData<IIC_VTB2,     [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 582                                InstrStage<2, [FU_NLSPipe]>], [3, 2, 2, 1]>,
 583   InstrItinData<IIC_VTB3,     [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 584                                InstrStage<1, [FU_NLSPipe]>,
 585                                InstrStage<1, [FU_NPipe], 0>,
 586                                InstrStage<2, [FU_NLSPipe]>], [4, 2, 2, 3, 1]>,
 587   InstrItinData<IIC_VTB4,     [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 588                                InstrStage<1, [FU_NLSPipe]>,
 589                                InstrStage<1, [FU_NPipe], 0>,
 590                                InstrStage<2, [FU_NLSPipe]>], [4, 2, 2, 3, 3, 1]>,
 591   //
 592   // VTBX
 593   InstrItinData<IIC_VTBX1,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 594                                InstrStage<2, [FU_NLSPipe]>], [3, 1, 2, 1]>,
 595   InstrItinData<IIC_VTBX2,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 596                                InstrStage<2, [FU_NLSPipe]>], [3, 1, 2, 2, 1]>,
 597   InstrItinData<IIC_VTBX3,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 598                                InstrStage<1, [FU_NLSPipe]>,
 599                                InstrStage<1, [FU_NPipe], 0>,
 600                                InstrStage<2, [FU_NLSPipe]>], [4, 1, 2, 2, 3, 1]>,
 601   InstrItinData<IIC_VTBX4,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 602                                InstrStage<1, [FU_NLSPipe]>,
 603                                InstrStage<1, [FU_NPipe], 0>,
 604                                InstrStage<2, [FU_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>
 605 ]>;
 606
 607 //
 608 // Ad-hoc scheduling information derived from pretty vague "Cortex-A9 Technical
 609 // Reference Manual".
 610 //
 611 // Dual issue pipeline represented by FU_Pipe0 | FU_Pipe1
 612 //
 613 def CortexA9Itineraries : ProcessorItineraries<[
 614   // VFP and NEON shares the same register file. This means that every VFP
 615   // instruction should wait for full completion of the consecutive NEON
 616   // instruction and vice-versa. We model this behavior with two artificial FUs:
 617   // DRegsVFP and DRegsVFP.
 618   //
 619   // Every VFP instruction:
 620   //  - Acquires DRegsVFP resource for 1 cycle
 621   //  - Reserves DRegsN resource for the whole duration (including time to
 622   //    register file writeback!).
 623   // Every NEON instruction does the same but with FUs swapped.
 624   //
 625   // Since the reserved FU cannot be acquired this models precisly "cross-domain"
 626   // stalls.
 627
 628   // VFP
 629   // Issue through integer pipeline, and execute in NEON unit.
 630
 631   // FP Special Register to Integer Register File Move
 632   InstrItinData<IIC_fpSTAT , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 633                               InstrStage2<2, [FU_DRegsN],   0, Reserved>,
 634                               InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 635                               InstrStage<1,  [FU_NPipe]>]>,
 636   //
 637   // Single-precision FP Unary
 638   InstrItinData<IIC_fpUNA32 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 639                                // Extra 1 latency cycle since wbck is 2 cycles
 640                                InstrStage2<3, [FU_DRegsN],   0, Reserved>,
 641                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 642                                InstrStage<1,  [FU_NPipe]>], [1, 1]>,
 643   //
 644   // Double-precision FP Unary
 645   InstrItinData<IIC_fpUNA64 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 646                                // Extra 1 latency cycle since wbck is 2 cycles
 647                                InstrStage2<3, [FU_DRegsN],   0, Reserved>,
 648                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 649                                InstrStage<1,  [FU_NPipe]>], [1, 1]>,
 650
 651   //
 652   // Single-precision FP Compare
 653   InstrItinData<IIC_fpCMP32 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 654                                // Extra 3 latency cycle since wbck is 4 cycles
 655                                InstrStage2<5, [FU_DRegsN],   0, Reserved>,
 656                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 657                                InstrStage<1,  [FU_NPipe]>], [1, 1]>,
 658   //
 659   // Double-precision FP Compare
 660   InstrItinData<IIC_fpCMP64 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 661                                // Extra 3 latency cycle since wbck is 4 cycles
 662                                InstrStage2<5, [FU_DRegsN],   0, Reserved>,
 663                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 664                                InstrStage<1,  [FU_NPipe]>], [1, 1]>,
 665   //
 666   // Single to Double FP Convert
 667   InstrItinData<IIC_fpCVTSD , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 668                                InstrStage2<5, [FU_DRegsN],   0, Reserved>,
 669                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 670                                InstrStage<1,  [FU_NPipe]>], [4, 1]>,
 671   //
 672   // Double to Single FP Convert
 673   InstrItinData<IIC_fpCVTDS , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 674                                InstrStage2<5, [FU_DRegsN],   0, Reserved>,
 675                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 676                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 677
 678   //
 679   // Single to Half FP Convert
 680   InstrItinData<IIC_fpCVTSH , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 681                                InstrStage2<5, [FU_DRegsN],   0, Reserved>,
 682                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 683                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 684   //
 685   // Half to Single FP Convert
 686   InstrItinData<IIC_fpCVTHS , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 687                                InstrStage2<3, [FU_DRegsN],   0, Reserved>,
 688                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 689                                InstrStage<1,  [FU_NPipe]>], [2, 1]>,
 690
 691   //
 692   // Single-Precision FP to Integer Convert
 693   InstrItinData<IIC_fpCVTSI , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 694                                InstrStage2<5, [FU_DRegsN],   0, Reserved>,
 695                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 696                                InstrStage<1,  [FU_NPipe]>], [4, 1]>,
 697   //
 698   // Double-Precision FP to Integer Convert
 699   InstrItinData<IIC_fpCVTDI , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 700                                InstrStage2<5, [FU_DRegsN],   0, Reserved>,
 701                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 702                                InstrStage<1,  [FU_NPipe]>], [4, 1]>,
 703   //
 704   // Integer to Single-Precision FP Convert
 705   InstrItinData<IIC_fpCVTIS , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 706                                InstrStage2<5, [FU_DRegsN],   0, Reserved>,
 707                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 708                                InstrStage<1,  [FU_NPipe]>], [4, 1]>,
 709   //
 710   // Integer to Double-Precision FP Convert
 711   InstrItinData<IIC_fpCVTID , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 712                                InstrStage2<5, [FU_DRegsN],   0, Reserved>,
 713                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 714                                InstrStage<1,  [FU_NPipe]>], [4, 1]>,
 715   //
 716   // Single-precision FP ALU
 717   InstrItinData<IIC_fpALU32 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 718                                InstrStage2<5, [FU_DRegsN],   0, Reserved>,
 719                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 720                                InstrStage<1,  [FU_NPipe]>], [4, 1, 1]>,
 721   //
 722   // Double-precision FP ALU
 723   InstrItinData<IIC_fpALU64 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 724                                InstrStage2<5, [FU_DRegsN],   0, Reserved>,
 725                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 726                                InstrStage<1,  [FU_NPipe]>], [4, 1, 1]>,
 727   //
 728   // Single-precision FP Multiply
 729   InstrItinData<IIC_fpMUL32 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 730                                InstrStage2<6, [FU_DRegsN],   0, Reserved>,
 731                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 732                                InstrStage<1,  [FU_NPipe]>], [5, 1, 1]>,
 733   //
 734   // Double-precision FP Multiply
 735   InstrItinData<IIC_fpMUL64 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 736                                InstrStage2<7, [FU_DRegsN],   0, Reserved>,
 737                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 738                                InstrStage<2,  [FU_NPipe]>], [6, 1, 1]>,
 739   //
 740   // Single-precision FP MAC
 741   InstrItinData<IIC_fpMAC32 , [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 742                                InstrStage2<9, [FU_DRegsN],   0, Reserved>,
 743                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 744                                InstrStage<1,  [FU_NPipe]>], [8, 0, 1, 1]>,
 745   //
 746   // Double-precision FP MAC
 747   InstrItinData<IIC_fpMAC64 , [InstrStage2<1,  [FU_DRegsVFP], 0, Required>,
 748                                InstrStage2<10, [FU_DRegsN],  0, Reserved>,
 749                                InstrStage<1,   [FU_Pipe0, FU_Pipe1]>,
 750                                InstrStage<2,   [FU_NPipe]>], [9, 0, 1, 1]>,
 751   //
 752   // Single-precision FP DIV
 753   InstrItinData<IIC_fpDIV32 , [InstrStage2<1,  [FU_DRegsVFP], 0, Required>,
 754                                InstrStage2<16, [FU_DRegsN],  0, Reserved>,
 755                                InstrStage<1,   [FU_Pipe0, FU_Pipe1]>,
 756                                InstrStage<10,  [FU_NPipe]>], [15, 1, 1]>,
 757   //
 758   // Double-precision FP DIV
 759   InstrItinData<IIC_fpDIV64 , [InstrStage2<1,  [FU_DRegsVFP], 0, Required>,
 760                                InstrStage2<26, [FU_DRegsN],  0, Reserved>,
 761                                InstrStage<1,   [FU_Pipe0, FU_Pipe1]>,
 762                                InstrStage<20,  [FU_NPipe]>], [25, 1, 1]>,
 763   //
 764   // Single-precision FP SQRT
 765   InstrItinData<IIC_fpSQRT32, [InstrStage2<1,  [FU_DRegsVFP], 0, Required>,
 766                                InstrStage2<18, [FU_DRegsN],   0, Reserved>,
 767                                InstrStage<1,   [FU_Pipe0, FU_Pipe1]>,
 768                                InstrStage<13,  [FU_NPipe]>], [17, 1]>,
 769   //
 770   // Double-precision FP SQRT
 771   InstrItinData<IIC_fpSQRT64, [InstrStage2<1,  [FU_DRegsVFP], 0, Required>,
 772                                InstrStage2<33, [FU_DRegsN],   0, Reserved>,
 773                                InstrStage<1,   [FU_Pipe0, FU_Pipe1]>,
 774                                InstrStage<28,  [FU_NPipe]>], [32, 1]>,
 775
 776   //
 777   // Integer to Single-precision Move
 778   InstrItinData<IIC_fpMOVIS,  [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 779                                // Extra 1 latency cycle since wbck is 2 cycles
 780                                InstrStage2<3, [FU_DRegsN],   0, Reserved>,
 781                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 782                                InstrStage<1,  [FU_NPipe]>], [1, 1]>,
 783   //
 784   // Integer to Double-precision Move
 785   InstrItinData<IIC_fpMOVID,  [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 786                                // Extra 1 latency cycle since wbck is 2 cycles
 787                                InstrStage2<3, [FU_DRegsN],   0, Reserved>,
 788                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 789                                InstrStage<1,  [FU_NPipe]>], [1, 1, 1]>,
 790   //
 791   // Single-precision to Integer Move
 792   InstrItinData<IIC_fpMOVSI,  [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 793                                InstrStage2<2, [FU_DRegsN],   0, Reserved>,
 794                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 795                                InstrStage<1,  [FU_NPipe]>], [1, 1]>,
 796   //
 797   // Double-precision to Integer Move
 798   InstrItinData<IIC_fpMOVDI,  [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
 799                                InstrStage2<2, [FU_DRegsN],   0, Reserved>,
 800                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 801                                InstrStage<1,  [FU_NPipe]>], [1, 1, 1]>,
 802   // NEON
 803   // Issue through integer pipeline, and execute in NEON unit.
 804
 805   //
 806   // Double-register Integer Unary
 807   InstrItinData<IIC_VUNAiD,   [InstrStage2<1, [FU_DRegsN],   0, Required>,
 808                                // Extra 3 latency cycle since wbck is 6 cycles
 809                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 810                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 811                                InstrStage<1, [FU_NPipe]>], [4, 2]>,
 812   //
 813   // Quad-register Integer Unary
 814   InstrItinData<IIC_VUNAiQ,   [InstrStage2<1, [FU_DRegsN],   0, Required>,
 815                                // Extra 3 latency cycle since wbck is 6 cycles
 816                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 817                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 818                                InstrStage<1, [FU_NPipe]>], [4, 2]>,
 819   //
 820   // Double-register Integer Q-Unary
 821   InstrItinData<IIC_VQUNAiD,  [InstrStage2<1, [FU_DRegsN],   0, Required>,
 822                                // Extra 3 latency cycle since wbck is 6 cycles
 823                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 824                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 825                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 826   //
 827   // Quad-register Integer CountQ-Unary
 828   InstrItinData<IIC_VQUNAiQ,  [InstrStage2<1, [FU_DRegsN],   0, Required>,
 829                                // Extra 3 latency cycle since wbck is 6 cycles
 830                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 831                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 832                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 833   //
 834   // Double-register Integer Binary
 835   InstrItinData<IIC_VBINiD,   [InstrStage2<1, [FU_DRegsN],   0, Required>,
 836                                // Extra 3 latency cycle since wbck is 6 cycles
 837                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 838                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 839                                InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
 840   //
 841   // Quad-register Integer Binary
 842   InstrItinData<IIC_VBINiQ,   [InstrStage2<1, [FU_DRegsN],   0, Required>,
 843                                // Extra 3 latency cycle since wbck is 6 cycles
 844                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 845                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 846                                InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
 847   //
 848   // Double-register Integer Subtract
 849   InstrItinData<IIC_VSUBiD,   [InstrStage2<1, [FU_DRegsN],   0, Required>,
 850                                // Extra 3 latency cycle since wbck is 6 cycles
 851                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 852                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 853                                InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
 854   //
 855   // Quad-register Integer Subtract
 856   InstrItinData<IIC_VSUBiQ,   [InstrStage2<1, [FU_DRegsN],   0, Required>,
 857                                // Extra 3 latency cycle since wbck is 6 cycles
 858                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 859                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 860                                InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
 861   //
 862   // Double-register Integer Shift
 863   InstrItinData<IIC_VSHLiD,   [InstrStage2<1, [FU_DRegsN],   0, Required>,
 864                                // Extra 3 latency cycle since wbck is 6 cycles
 865                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 866                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 867                                InstrStage<1, [FU_NPipe]>], [3, 1, 1]>,
 868   //
 869   // Double-register Integer Binary (4 cycle)
 870   InstrItinData<IIC_VBINi4D,  [InstrStage2<1, [FU_DRegsN],   0, Required>,
 871                                // Extra 3 latency cycle since wbck is 6 cycles
 872                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 873                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 874                                InstrStage<1, [FU_NPipe]>], [4, 2, 2]>,
 875   //
 876   // Quad-register Integer Binary (4 cycle)
 877   InstrItinData<IIC_VBINi4Q,  [InstrStage2<1, [FU_DRegsN],   0, Required>,
 878                                // Extra 3 latency cycle since wbck is 6 cycles
 879                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 880                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 881                                InstrStage<1, [FU_NPipe]>], [4, 2, 2]>,
 882   //
 883   // Double-register Integer Subtract (4 cycle)
 884   InstrItinData<IIC_VSUBiD,   [InstrStage2<1, [FU_DRegsN],   0, Required>,
 885                                // Extra 3 latency cycle since wbck is 6 cycles
 886                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 887                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 888                                InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
 889   //
 890   // Quad-register Integer Subtract (4 cycle)
 891   InstrItinData<IIC_VSUBiQ,   [InstrStage2<1, [FU_DRegsN],   0, Required>,
 892                                // Extra 3 latency cycle since wbck is 6 cycles
 893                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 894                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 895                                InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
 896
 897   //
 898   // Double-register Integer Count
 899   InstrItinData<IIC_VCNTiD,   [InstrStage2<1, [FU_DRegsN],   0, Required>,
 900                                // Extra 3 latency cycle since wbck is 6 cycles
 901                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 902                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 903                                InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
 904   //
 905   // Quad-register Integer Count
 906   // Result written in N3, but that is relative to the last cycle of multicycle,
 907   // so we use 4 for those cases
 908   InstrItinData<IIC_VCNTiQ,   [InstrStage2<1, [FU_DRegsN],   0, Required>,
 909                                // Extra 3 latency cycle since wbck is 7 cycles
 910                                InstrStage2<8, [FU_DRegsVFP], 0, Reserved>,
 911                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 912                                InstrStage<2, [FU_NPipe]>], [4, 2, 2]>,
 913   //
 914   // Double-register Absolute Difference and Accumulate
 915   InstrItinData<IIC_VABAD,    [InstrStage2<1, [FU_DRegsN],   0, Required>,
 916                                // Extra 3 latency cycle since wbck is 6 cycles
 917                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 918                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 919                                InstrStage<1, [FU_NPipe]>], [6, 3, 2, 1]>,
 920   //
 921   // Quad-register Absolute Difference and Accumulate
 922   InstrItinData<IIC_VABAQ,    [InstrStage2<1, [FU_DRegsN],   0, Required>,
 923                                // Extra 3 latency cycle since wbck is 6 cycles
 924                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 925                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 926                                InstrStage<2, [FU_NPipe]>], [6, 3, 2, 1]>,
 927   //
 928   // Double-register Integer Pair Add Long
 929   InstrItinData<IIC_VPALiD,   [InstrStage2<1, [FU_DRegsN],   0, Required>,
 930                                // Extra 3 latency cycle since wbck is 6 cycles
 931                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 932                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 933                                InstrStage<1, [FU_NPipe]>], [6, 3, 1]>,
 934   //
 935   // Quad-register Integer Pair Add Long
 936   InstrItinData<IIC_VPALiQ,   [InstrStage2<1, [FU_DRegsN],   0, Required>,
 937                                // Extra 3 latency cycle since wbck is 6 cycles
 938                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 939                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 940                                InstrStage<2, [FU_NPipe]>], [6, 3, 1]>,
 941
 942   //
 943   // Double-register Integer Multiply (.8, .16)
 944   InstrItinData<IIC_VMULi16D, [InstrStage2<1, [FU_DRegsN],   0, Required>,
 945                                // Extra 3 latency cycle since wbck is 6 cycles
 946                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 947                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 948                                InstrStage<1, [FU_NPipe]>], [6, 2, 2]>,
 949   //
 950   // Quad-register Integer Multiply (.8, .16)
 951   InstrItinData<IIC_VMULi16Q, [InstrStage2<1, [FU_DRegsN],   0, Required>,
 952                                // Extra 3 latency cycle since wbck is 7 cycles
 953                                InstrStage2<8, [FU_DRegsVFP], 0, Reserved>,
 954                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 955                                InstrStage<2, [FU_NPipe]>], [7, 2, 2]>,
 956
 957   //
 958   // Double-register Integer Multiply (.32)
 959   InstrItinData<IIC_VMULi32D, [InstrStage2<1, [FU_DRegsN],   0, Required>,
 960                                // Extra 3 latency cycle since wbck is 7 cycles
 961                                InstrStage2<8, [FU_DRegsVFP], 0, Reserved>,
 962                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 963                                InstrStage<2, [FU_NPipe]>], [7, 2, 1]>,
 964   //
 965   // Quad-register Integer Multiply (.32)
 966   InstrItinData<IIC_VMULi32Q, [InstrStage2<1, [FU_DRegsN],   0, Required>,
 967                                // Extra 3 latency cycle since wbck is 9 cycles
 968                                InstrStage2<10, [FU_DRegsVFP], 0, Reserved>,
 969                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 970                                InstrStage<4, [FU_NPipe]>], [9, 2, 1]>,
 971   //
 972   // Double-register Integer Multiply-Accumulate (.8, .16)
 973   InstrItinData<IIC_VMACi16D, [InstrStage2<1, [FU_DRegsN],   0, Required>,
 974                                // Extra 3 latency cycle since wbck is 6 cycles
 975                                InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
 976                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 977                                InstrStage<1, [FU_NPipe]>], [6, 3, 2, 2]>,
 978   //
 979   // Double-register Integer Multiply-Accumulate (.32)
 980   InstrItinData<IIC_VMACi32D, [InstrStage2<1, [FU_DRegsN],   0, Required>,
 981                                // Extra 3 latency cycle since wbck is 7 cycles
 982                                InstrStage2<8, [FU_DRegsVFP], 0, Reserved>,
 983                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 984                                InstrStage<2, [FU_NPipe]>], [7, 3, 2, 1]>,
 985   //
 986   // Quad-register Integer Multiply-Accumulate (.8, .16)
 987   InstrItinData<IIC_VMACi16Q, [InstrStage2<1, [FU_DRegsN],   0, Required>,
 988                                // Extra 3 latency cycle since wbck is 7 cycles
 989                                InstrStage2<8, [FU_DRegsVFP], 0, Reserved>,
 990                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 991                                InstrStage<2, [FU_NPipe]>], [7, 3, 2, 2]>,
 992   //
 993   // Quad-register Integer Multiply-Accumulate (.32)
 994   InstrItinData<IIC_VMACi32Q, [InstrStage2<1, [FU_DRegsN],   0, Required>,
 995                                // Extra 3 latency cycle since wbck is 9 cycles
 996                                InstrStage2<8, [FU_DRegsVFP], 0, Reserved>,
 997                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 998                                InstrStage<4, [FU_NPipe]>], [9, 3, 2, 1]>
 999 ]>;
1000
1001