1 //===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the ARM v6 processors.
12 //===----------------------------------------------------------------------===//
14 // Model based on ARM1176
17 def V6_Pipe : FuncUnit; // pipeline
19 // Scheduling information derived from "ARM1176JZF-S Technical Reference Manual"
21 def ARMV6Itineraries : ProcessorItineraries<
25 InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>,
27 // Binary Instructions that produce a result
28 InstrItinData<IIC_iALUi , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
29 InstrItinData<IIC_iALUr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,
30 InstrItinData<IIC_iALUsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,
31 InstrItinData<IIC_iALUsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>,
33 // Unary Instructions that produce a result
34 InstrItinData<IIC_iUNAr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
35 InstrItinData<IIC_iUNAsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
36 InstrItinData<IIC_iUNAsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,
38 // Compare instructions
39 InstrItinData<IIC_iCMPi , [InstrStage<1, [V6_Pipe]>], [2]>,
40 InstrItinData<IIC_iCMPr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
41 InstrItinData<IIC_iCMPsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
42 InstrItinData<IIC_iCMPsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,
44 // Move instructions, unconditional
45 InstrItinData<IIC_iMOVi , [InstrStage<1, [V6_Pipe]>], [2]>,
46 InstrItinData<IIC_iMOVr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
47 InstrItinData<IIC_iMOVsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
48 InstrItinData<IIC_iMOVsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,
50 // Move instructions, conditional
51 InstrItinData<IIC_iCMOVi , [InstrStage<1, [V6_Pipe]>], [3]>,
52 InstrItinData<IIC_iCMOVr , [InstrStage<1, [V6_Pipe]>], [3, 2]>,
53 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [V6_Pipe]>], [3, 1]>,
54 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>,
56 // Integer multiply pipeline
58 InstrItinData<IIC_iMUL16 , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>,
59 InstrItinData<IIC_iMAC16 , [InstrStage<1, [V6_Pipe]>], [4, 1, 1, 2]>,
60 InstrItinData<IIC_iMUL32 , [InstrStage<2, [V6_Pipe]>], [5, 1, 1]>,
61 InstrItinData<IIC_iMAC32 , [InstrStage<2, [V6_Pipe]>], [5, 1, 1, 2]>,
62 InstrItinData<IIC_iMUL64 , [InstrStage<3, [V6_Pipe]>], [6, 1, 1]>,
63 InstrItinData<IIC_iMAC64 , [InstrStage<3, [V6_Pipe]>], [6, 1, 1, 2]>,
65 // Integer load pipeline
68 InstrItinData<IIC_iLoadi , [InstrStage<1, [V6_Pipe]>], [4, 1]>,
71 InstrItinData<IIC_iLoadr , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>,
73 // Scaled register offset, issues over 2 cycles
74 InstrItinData<IIC_iLoadsi , [InstrStage<2, [V6_Pipe]>], [5, 2, 1]>,
76 // Immediate offset with update
77 InstrItinData<IIC_iLoadiu , [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>,
79 // Register offset with update
80 InstrItinData<IIC_iLoadru , [InstrStage<1, [V6_Pipe]>], [4, 2, 1, 1]>,
82 // Scaled register offset with update, issues over 2 cycles
83 InstrItinData<IIC_iLoadsiu , [InstrStage<2, [V6_Pipe]>], [5, 2, 2, 1]>,
87 InstrItinData<IIC_iLoadm , [InstrStage<3, [V6_Pipe]>]>,
90 // Load multiple plus branch
91 InstrItinData<IIC_iLoadmBr , [InstrStage<3, [V6_Pipe]>,
92 InstrStage<1, [V6_Pipe]>]>,
94 // Integer store pipeline
97 InstrItinData<IIC_iStorei , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
100 InstrItinData<IIC_iStorer , [InstrStage<1, [V6_Pipe]>], [2, 1, 1]>,
103 // Scaled register offset, issues over 2 cycles
104 InstrItinData<IIC_iStoresi , [InstrStage<2, [V6_Pipe]>], [2, 2, 1]>,
106 // Immediate offset with update
107 InstrItinData<IIC_iStoreiu , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,
109 // Register offset with update
110 InstrItinData<IIC_iStoreru , [InstrStage<1, [V6_Pipe]>], [2, 2, 1, 1]>,
112 // Scaled register offset with update, issues over 2 cycles
113 InstrItinData<IIC_iStoresiu, [InstrStage<2, [V6_Pipe]>], [2, 2, 2, 1]>,
116 InstrItinData<IIC_iStorem , [InstrStage<3, [V6_Pipe]>]>,
120 // no delay slots, so the latency of a branch is unimportant
121 InstrItinData<IIC_Br , [InstrStage<1, [V6_Pipe]>]>,
124 // Issue through integer pipeline, and execute in NEON unit. We assume
125 // RunFast mode so that NFP pipeline is used for single-precision when
128 // FP Special Register to Integer Register File Move
129 InstrItinData<IIC_fpSTAT , [InstrStage<1, [V6_Pipe]>], [3]>,
131 // Single-precision FP Unary
132 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [V6_Pipe]>], [5, 2]>,
134 // Double-precision FP Unary
135 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [V6_Pipe]>], [5, 2]>,
137 // Single-precision FP Compare
138 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
140 // Double-precision FP Compare
141 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
143 // Single to Double FP Convert
144 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [V6_Pipe]>], [5, 2]>,
146 // Double to Single FP Convert
147 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [V6_Pipe]>], [5, 2]>,
149 // Single-Precision FP to Integer Convert
150 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [V6_Pipe]>], [9, 2]>,
152 // Double-Precision FP to Integer Convert
153 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [V6_Pipe]>], [9, 2]>,
155 // Integer to Single-Precision FP Convert
156 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [V6_Pipe]>], [9, 2]>,
158 // Integer to Double-Precision FP Convert
159 InstrItinData<IIC_fpCVTID , [InstrStage<1, [V6_Pipe]>], [9, 2]>,
161 // Single-precision FP ALU
162 InstrItinData<IIC_fpALU32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>,
164 // Double-precision FP ALU
165 InstrItinData<IIC_fpALU64 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>,
167 // Single-precision FP Multiply
168 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>,
170 // Double-precision FP Multiply
171 InstrItinData<IIC_fpMUL64 , [InstrStage<2, [V6_Pipe]>], [9, 2, 2]>,
173 // Single-precision FP MAC
174 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2, 2]>,
176 // Double-precision FP MAC
177 InstrItinData<IIC_fpMAC64 , [InstrStage<2, [V6_Pipe]>], [9, 2, 2, 2]>,
179 // Single-precision FP DIV
180 InstrItinData<IIC_fpDIV32 , [InstrStage<15, [V6_Pipe]>], [20, 2, 2]>,
182 // Double-precision FP DIV
183 InstrItinData<IIC_fpDIV64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>,
185 // Single-precision FP SQRT
186 InstrItinData<IIC_fpSQRT32 , [InstrStage<15, [V6_Pipe]>], [20, 2, 2]>,
188 // Double-precision FP SQRT
189 InstrItinData<IIC_fpSQRT64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>,
191 // Single-precision FP Load
192 InstrItinData<IIC_fpLoad32 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>,
194 // Double-precision FP Load
195 InstrItinData<IIC_fpLoad64 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>,
198 InstrItinData<IIC_fpLoadm , [InstrStage<3, [V6_Pipe]>]>,
200 // Single-precision FP Store
201 InstrItinData<IIC_fpStore32 , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,
203 // Double-precision FP Store
204 // use FU_Issue to enforce the 1 load/store per cycle limit
205 InstrItinData<IIC_fpStore64 , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,
208 InstrItinData<IIC_fpStorem , [InstrStage<3, [V6_Pipe]>]>