lib/Target/ARM/ARMScheduleA9.td

   1 //=- ARMScheduleA9.td - ARM Cortex-A9 Scheduling Definitions -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM Cortex A9 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //
  15 // Ad-hoc scheduling information derived from pretty vague "Cortex-A9 Technical
  16 // Reference Manual".
  17 //
  18 // Functional units
  19 def A9_Pipe0   : FuncUnit; // pipeline 0
  20 def A9_Pipe1   : FuncUnit; // pipeline 1
  21 def A9_LSPipe  : FuncUnit; // LS pipe
  22 def A9_NPipe   : FuncUnit; // NEON ALU/MUL pipe
  23 def A9_DRegsVFP: FuncUnit; // FP register set, VFP side
  24 def A9_DRegsN  : FuncUnit; // FP register set, NEON side
  25
  26 // Dual issue pipeline represented by A9_Pipe0 | A9_Pipe1
  27 //
  28 def CortexA9Itineraries : ProcessorItineraries<
  29   [A9_NPipe, A9_DRegsN, A9_DRegsVFP, A9_LSPipe, A9_Pipe0, A9_Pipe1], [], [
  30   // Two fully-pipelined integer ALU pipelines
  31   // FIXME: There are no operand latencies for these instructions at all!
  32   //
  33   // Move instructions, unconditional
  34   InstrItinData<IIC_iMOVi   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1]>,
  35   InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>,
  36                                InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2]>,
  37   InstrItinData<IIC_iMOVr   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1, 1]>,
  38   InstrItinData<IIC_iMOVsi  , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1, 1]>,
  39   InstrItinData<IIC_iMOVsr  , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 2, 1]>,
  40   //
  41   // No operand cycles
  42   InstrItinData<IIC_iALUx    , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>]>,
  43   //
  44   // Binary Instructions that produce a result
  45   InstrItinData<IIC_iALUi , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 2]>,
  46   InstrItinData<IIC_iALUr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 2, 2]>,
  47   InstrItinData<IIC_iALUsi, [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 2, 1]>,
  48   InstrItinData<IIC_iALUsr,[InstrStage<3, [A9_Pipe0, A9_Pipe1]>], [2, 2, 1, 1]>,
  49   //
  50   // Bitwise Instructions that produce a result
  51   InstrItinData<IIC_iBITi , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 2]>,
  52   InstrItinData<IIC_iBITr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 2, 2]>,
  53   InstrItinData<IIC_iBITsi, [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 2, 1]>,
  54   InstrItinData<IIC_iBITsr,[InstrStage<3, [A9_Pipe0, A9_Pipe1]>], [2, 2, 1, 1]>,
  55   //
  56   // Unary Instructions that produce a result
  57   InstrItinData<IIC_iUNAr   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 2]>,
  58   InstrItinData<IIC_iUNAsi  , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,
  59   //
  60   // Zero and sign extension instructions
  61   InstrItinData<IIC_iEXTr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,
  62   InstrItinData<IIC_iEXTAr, [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [3, 1, 1]>,
  63   InstrItinData<IIC_iEXTAsr,[InstrStage<2, [A9_Pipe0, A9_Pipe1]>],[3, 1, 1, 1]>,
  64   //
  65   // Compare instructions
  66   InstrItinData<IIC_iCMPi   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2]>,
  67   InstrItinData<IIC_iCMPr   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 2]>,
  68   InstrItinData<IIC_iCMPsi  , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,
  69   InstrItinData<IIC_iCMPsr  , [InstrStage<3, [A9_Pipe0, A9_Pipe1]>], [2, 1, 1]>,
  70   //
  71   // Move instructions, conditional
  72   InstrItinData<IIC_iCMOVi  , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2]>,
  73   InstrItinData<IIC_iCMOVr  , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,
  74   InstrItinData<IIC_iCMOVsi , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,
  75   InstrItinData<IIC_iCMOVsr , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 1, 1]>,
  76
  77   // Integer multiply pipeline
  78   //
  79   InstrItinData<IIC_iMUL16   , [InstrStage<1, [A9_Pipe1], 0>,
  80                                 InstrStage<2, [A9_Pipe0]>], [4, 1, 1]>,
  81   InstrItinData<IIC_iMAC16   , [InstrStage<1, [A9_Pipe1], 0>,
  82                                 InstrStage<2, [A9_Pipe0]>], [4, 1, 1, 2]>,
  83   InstrItinData<IIC_iMUL32   , [InstrStage<1, [A9_Pipe1], 0>,
  84                                 InstrStage<2, [A9_Pipe0]>], [4, 1, 1]>,
  85   InstrItinData<IIC_iMAC32   , [InstrStage<1, [A9_Pipe1], 0>,
  86                                 InstrStage<2, [A9_Pipe0]>], [4, 1, 1, 2]>,
  87   InstrItinData<IIC_iMUL64   , [InstrStage<2, [A9_Pipe1], 0>,
  88                                 InstrStage<3, [A9_Pipe0]>], [4, 5, 1, 1]>,
  89   InstrItinData<IIC_iMAC64   , [InstrStage<2, [A9_Pipe1], 0>,
  90                                 InstrStage<3, [A9_Pipe0]>], [4, 5, 1, 1]>,
  91   // Integer load pipeline
  92   // FIXME: The timings are some rough approximations
  93   //
  94   // Immediate offset
  95   InstrItinData<IIC_iLoadi   , [InstrStage<1, [A9_Pipe1]>,
  96                                 InstrStage<1, [A9_LSPipe]>], [3, 1]>,
  97   //
  98   // Register offset
  99   InstrItinData<IIC_iLoadr   , [InstrStage<1, [A9_Pipe1]>,
 100                                 InstrStage<1, [A9_LSPipe]>], [3, 1, 1]>,
 101   //
 102   // Scaled register offset
 103   InstrItinData<IIC_iLoadsi  , [InstrStage<1, [A9_Pipe1]>,
 104                                 InstrStage<2, [A9_LSPipe]>], [4, 1, 1]>,
 105   //
 106   // Immediate offset with update
 107   InstrItinData<IIC_iLoadiu  , [InstrStage<1, [A9_Pipe1]>,
 108                                 InstrStage<2, [A9_LSPipe]>], [3, 2, 1]>,
 109   //
 110   // Register offset with update
 111   InstrItinData<IIC_iLoadru  , [InstrStage<1, [A9_Pipe1]>,
 112                                 InstrStage<2, [A9_LSPipe]>], [3, 2, 1, 1]>,
 113   //
 114   // Scaled register offset with update
 115   InstrItinData<IIC_iLoadsiu , [InstrStage<1, [A9_Pipe1]>,
 116                                 InstrStage<2, [A9_LSPipe]>], [4, 3, 1, 1]>,
 117   //
 118   // Load multiple
 119   InstrItinData<IIC_iLoadm   , [InstrStage<1, [A9_Pipe1]>,
 120                                 InstrStage<1, [A9_LSPipe]>]>,
 121
 122   //
 123   // Load multiple plus branch
 124   InstrItinData<IIC_iLoadmBr , [InstrStage<1, [A9_Pipe1]>,
 125                                 InstrStage<1, [A9_LSPipe]>,
 126                                 InstrStage<1, [A9_Pipe0, A9_Pipe1]>]>,
 127
 128   //
 129   // iLoadi + iALUr for t2LDRpci_pic.
 130   InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Pipe1]>,
 131                                 InstrStage<1, [A9_LSPipe]>,
 132                                 InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [4, 1]>,
 133
 134   // Integer store pipeline
 135   ///
 136   // Immediate offset
 137   InstrItinData<IIC_iStorei  , [InstrStage<1, [A9_Pipe1]>,
 138                                 InstrStage<1, [A9_LSPipe]>], [3, 1]>,
 139   //
 140   // Register offset
 141   InstrItinData<IIC_iStorer  , [InstrStage<1, [ A9_Pipe1]>,
 142                                 InstrStage<1, [A9_LSPipe]>], [3, 1, 1]>,
 143   //
 144   // Scaled register offset
 145   InstrItinData<IIC_iStoresi , [InstrStage<1, [A9_Pipe1]>,
 146                                 InstrStage<2, [A9_LSPipe]>], [3, 1, 1]>,
 147   //
 148   // Immediate offset with update
 149   InstrItinData<IIC_iStoreiu , [InstrStage<1, [A9_Pipe1]>,
 150                                 InstrStage<1, [A9_LSPipe]>], [2, 3, 1]>,
 151   //
 152   // Register offset with update
 153   InstrItinData<IIC_iStoreru , [InstrStage<1, [A9_Pipe1]>,
 154                                 InstrStage<1, [A9_LSPipe]>], [2, 3, 1, 1]>,
 155   //
 156   // Scaled register offset with update
 157   InstrItinData<IIC_iStoresiu, [InstrStage<1, [A9_Pipe1]>,
 158                                 InstrStage<2, [A9_LSPipe]>], [3, 3, 1, 1]>,
 159   //
 160   // Store multiple
 161   InstrItinData<IIC_iStorem  , [InstrStage<1, [A9_Pipe1]>,
 162                                 InstrStage<1, [A9_LSPipe]>]>,
 163   // Branch
 164   //
 165   // no delay slots, so the latency of a branch is unimportant
 166   InstrItinData<IIC_Br       , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>]>,
 167
 168   // VFP and NEON shares the same register file. This means that every VFP
 169   // instruction should wait for full completion of the consecutive NEON
 170   // instruction and vice-versa. We model this behavior with two artificial FUs:
 171   // DRegsVFP and DRegsVFP.
 172   //
 173   // Every VFP instruction:
 174   //  - Acquires DRegsVFP resource for 1 cycle
 175   //  - Reserves DRegsN resource for the whole duration (including time to
 176   //    register file writeback!).
 177   // Every NEON instruction does the same but with FUs swapped.
 178   //
 179   // Since the reserved FU cannot be acquired, this models precisely
 180   // "cross-domain" stalls.
 181
 182   // VFP
 183   // Issue through integer pipeline, and execute in NEON unit.
 184
 185   // FP Special Register to Integer Register File Move
 186   InstrItinData<IIC_fpSTAT , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 187                               InstrStage<2, [A9_DRegsN],   0, Reserved>,
 188                               InstrStage<1, [A9_Pipe1]>,
 189                               InstrStage<1, [A9_NPipe]>]>,
 190   //
 191   // Single-precision FP Unary
 192   InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 193                                // Extra latency cycles since wbck is 2 cycles
 194                                InstrStage<3, [A9_DRegsN],   0, Reserved>,
 195                                InstrStage<1, [A9_Pipe1]>,
 196                                InstrStage<1, [A9_NPipe]>], [1, 1]>,
 197   //
 198   // Double-precision FP Unary
 199   InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 200                                // Extra latency cycles since wbck is 2 cycles
 201                                InstrStage<3, [A9_DRegsN],   0, Reserved>,
 202                                InstrStage<1, [A9_Pipe1]>,
 203                                InstrStage<1, [A9_NPipe]>], [1, 1]>,
 204
 205   //
 206   // Single-precision FP Compare
 207   InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 208                                // Extra latency cycles since wbck is 4 cycles
 209                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 210                                InstrStage<1, [A9_Pipe1]>,
 211                                InstrStage<1, [A9_NPipe]>], [1, 1]>,
 212   //
 213   // Double-precision FP Compare
 214   InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 215                                // Extra latency cycles since wbck is 4 cycles
 216                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 217                                InstrStage<1, [A9_Pipe1]>,
 218                                InstrStage<1, [A9_NPipe]>], [1, 1]>,
 219   //
 220   // Single to Double FP Convert
 221   InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 222                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 223                                InstrStage<1, [A9_Pipe1]>,
 224                                InstrStage<1, [A9_NPipe]>], [4, 1]>,
 225   //
 226   // Double to Single FP Convert
 227   InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 228                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 229                                InstrStage<1, [A9_Pipe1]>,
 230                                InstrStage<1, [A9_NPipe]>], [4, 1]>,
 231
 232   //
 233   // Single to Half FP Convert
 234   InstrItinData<IIC_fpCVTSH , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 235                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 236                                InstrStage<1, [A9_Pipe1]>,
 237                                InstrStage<1, [A9_NPipe]>], [4, 1]>,
 238   //
 239   // Half to Single FP Convert
 240   InstrItinData<IIC_fpCVTHS , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 241                                InstrStage<3, [A9_DRegsN],   0, Reserved>,
 242                                InstrStage<1, [A9_Pipe1]>,
 243                                InstrStage<1, [A9_NPipe]>], [2, 1]>,
 244
 245   //
 246   // Single-Precision FP to Integer Convert
 247   InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 248                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 249                                InstrStage<1, [A9_Pipe1]>,
 250                                InstrStage<1, [A9_NPipe]>], [4, 1]>,
 251   //
 252   // Double-Precision FP to Integer Convert
 253   InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 254                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 255                                InstrStage<1, [A9_Pipe1]>,
 256                                InstrStage<1, [A9_NPipe]>], [4, 1]>,
 257   //
 258   // Integer to Single-Precision FP Convert
 259   InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 260                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 261                                InstrStage<1, [A9_Pipe1]>,
 262                                InstrStage<1, [A9_NPipe]>], [4, 1]>,
 263   //
 264   // Integer to Double-Precision FP Convert
 265   InstrItinData<IIC_fpCVTID , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 266                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 267                                InstrStage<1, [A9_Pipe1]>,
 268                                InstrStage<1, [A9_NPipe]>], [4, 1]>,
 269   //
 270   // Single-precision FP ALU
 271   InstrItinData<IIC_fpALU32 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 272                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 273                                InstrStage<1, [A9_Pipe1]>,
 274                                InstrStage<1, [A9_NPipe]>], [4, 1, 1]>,
 275   //
 276   // Double-precision FP ALU
 277   InstrItinData<IIC_fpALU64 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 278                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 279                                InstrStage<1, [A9_Pipe1]>,
 280                                InstrStage<1, [A9_NPipe]>], [4, 1, 1]>,
 281   //
 282   // Single-precision FP Multiply
 283   InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 284                                InstrStage<6, [A9_DRegsN],   0, Reserved>,
 285                                InstrStage<1, [A9_Pipe1]>,
 286                                InstrStage<1, [A9_NPipe]>], [5, 1, 1]>,
 287   //
 288   // Double-precision FP Multiply
 289   InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 290                                InstrStage<7, [A9_DRegsN],   0, Reserved>,
 291                                InstrStage<1, [A9_Pipe1]>,
 292                                InstrStage<2, [A9_NPipe]>], [6, 1, 1]>,
 293   //
 294   // Single-precision FP MAC
 295   InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 296                                InstrStage<9, [A9_DRegsN],   0, Reserved>,
 297                                InstrStage<1, [A9_Pipe1]>,
 298                                InstrStage<1, [A9_NPipe]>], [8, 0, 1, 1]>,
 299   //
 300   // Double-precision FP MAC
 301   InstrItinData<IIC_fpMAC64 , [InstrStage<1,  [A9_DRegsVFP], 0, Required>,
 302                                InstrStage<10, [A9_DRegsN],  0, Reserved>,
 303                                InstrStage<1,  [A9_Pipe1]>,
 304                                InstrStage<2,  [A9_NPipe]>], [9, 0, 1, 1]>,
 305   //
 306   // Single-precision FP DIV
 307   InstrItinData<IIC_fpDIV32 , [InstrStage<1,  [A9_DRegsVFP], 0, Required>,
 308                                InstrStage<16, [A9_DRegsN],  0, Reserved>,
 309                                InstrStage<1,  [A9_Pipe1]>,
 310                                InstrStage<10, [A9_NPipe]>], [15, 1, 1]>,
 311   //
 312   // Double-precision FP DIV
 313   InstrItinData<IIC_fpDIV64 , [InstrStage<1,  [A9_DRegsVFP], 0, Required>,
 314                                InstrStage<26, [A9_DRegsN],  0, Reserved>,
 315                                InstrStage<1,  [A9_Pipe1]>,
 316                                InstrStage<20, [A9_NPipe]>], [25, 1, 1]>,
 317   //
 318   // Single-precision FP SQRT
 319   InstrItinData<IIC_fpSQRT32, [InstrStage<1,  [A9_DRegsVFP], 0, Required>,
 320                                InstrStage<18, [A9_DRegsN],   0, Reserved>,
 321                                InstrStage<1,  [A9_Pipe1]>,
 322                                InstrStage<13, [A9_NPipe]>], [17, 1]>,
 323   //
 324   // Double-precision FP SQRT
 325   InstrItinData<IIC_fpSQRT64, [InstrStage<1,  [A9_DRegsVFP], 0, Required>,
 326                                InstrStage<33, [A9_DRegsN],   0, Reserved>,
 327                                InstrStage<1,  [A9_Pipe1]>,
 328                                InstrStage<28, [A9_NPipe]>], [32, 1]>,
 329
 330   //
 331   // Integer to Single-precision Move
 332   InstrItinData<IIC_fpMOVIS,  [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 333                                // Extra 1 latency cycle since wbck is 2 cycles
 334                                InstrStage<3, [A9_DRegsN],   0, Reserved>,
 335                                InstrStage<1, [A9_Pipe1]>,
 336                                InstrStage<1, [A9_NPipe]>], [1, 1]>,
 337   //
 338   // Integer to Double-precision Move
 339   InstrItinData<IIC_fpMOVID,  [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 340                                // Extra 1 latency cycle since wbck is 2 cycles
 341                                InstrStage<3, [A9_DRegsN],   0, Reserved>,
 342                                InstrStage<1, [A9_Pipe1]>,
 343                                InstrStage<1, [A9_NPipe]>], [1, 1, 1]>,
 344   //
 345   // Single-precision to Integer Move
 346   InstrItinData<IIC_fpMOVSI,  [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 347                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 348                                InstrStage<1, [A9_Pipe1]>,
 349                                InstrStage<1, [A9_NPipe]>], [1, 1]>,
 350   //
 351   // Double-precision to Integer Move
 352   InstrItinData<IIC_fpMOVDI,  [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 353                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 354                                InstrStage<1, [A9_Pipe1]>,
 355                                InstrStage<1, [A9_NPipe]>], [1, 1, 1]>,
 356   //
 357   // Single-precision FP Load
 358   InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 359                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 360                                InstrStage<1, [A9_Pipe1], 0>,
 361                                InstrStage<1, [A9_LSPipe]>,
 362                                InstrStage<1, [A9_NPipe]>]>,
 363   //
 364   // Double-precision FP Load
 365   InstrItinData<IIC_fpLoad64, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 366                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 367                                InstrStage<1, [A9_Pipe1], 0>,
 368                                InstrStage<1, [A9_LSPipe]>,
 369                                InstrStage<1, [A9_NPipe]>]>,
 370   //
 371   // FP Load Multiple
 372   InstrItinData<IIC_fpLoadm,  [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 373                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 374                                InstrStage<1, [A9_Pipe1], 0>,
 375                                InstrStage<1, [A9_LSPipe]>,
 376                                InstrStage<1, [A9_NPipe]>]>,
 377   //
 378   // Single-precision FP Store
 379   InstrItinData<IIC_fpStore32,[InstrStage<1, [A9_DRegsVFP], 0, Required>,
 380                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 381                                InstrStage<1, [A9_Pipe1], 0>,
 382                                InstrStage<1, [A9_LSPipe]>,
 383                                InstrStage<1, [A9_NPipe]>]>,
 384   //
 385   // Double-precision FP Store
 386   InstrItinData<IIC_fpStore64,[InstrStage<1, [A9_DRegsVFP], 0, Required>,
 387                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 388                                InstrStage<1, [A9_Pipe1], 0>,
 389                                InstrStage<1, [A9_LSPipe]>,
 390                                InstrStage<1, [A9_NPipe]>]>,
 391   //
 392   // FP Store Multiple
 393   InstrItinData<IIC_fpStorem, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
 394                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 395                                InstrStage<1, [A9_Pipe1], 0>,
 396                                InstrStage<1, [A9_LSPipe]>,
 397                                InstrStage<1, [A9_NPipe]>]>,
 398   // NEON
 399   // Issue through integer pipeline, and execute in NEON unit.
 400   // FIXME: Neon pipeline and LdSt unit are multiplexed.
 401   //        Add some syntactic sugar to model this!
 402   // VLD1
 403   // FIXME: We don't model this instruction properly
 404   InstrItinData<IIC_VLD1,     [InstrStage<1, [A9_DRegsN],   0, Required>,
 405                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 406                                InstrStage<1, [A9_Pipe1], 0>,
 407                                InstrStage<1, [A9_LSPipe]>,
 408                                InstrStage<1, [A9_NPipe]>]>,
 409   //
 410   // VLD2
 411   // FIXME: We don't model this instruction properly
 412   InstrItinData<IIC_VLD2,     [InstrStage<1, [A9_DRegsN],   0, Required>,
 413                                // Extra latency cycles since wbck is 6 cycles
 414                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 415                                InstrStage<1, [A9_Pipe1], 0>,
 416                                InstrStage<1, [A9_LSPipe]>,
 417                                InstrStage<1, [A9_NPipe]>], [2, 2, 1]>,
 418   //
 419   // VLD3
 420   // FIXME: We don't model this instruction properly
 421   InstrItinData<IIC_VLD3,     [InstrStage<1, [A9_DRegsN],   0, Required>,
 422                                // Extra latency cycles since wbck is 6 cycles
 423                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 424                                InstrStage<1, [A9_Pipe1], 0>,
 425                                InstrStage<1, [A9_LSPipe]>,
 426                                InstrStage<1, [A9_NPipe]>], [2, 2, 2, 1]>,
 427   //
 428   // VLD4
 429   // FIXME: We don't model this instruction properly
 430   InstrItinData<IIC_VLD4,     [InstrStage<1, [A9_DRegsN],   0, Required>,
 431                                // Extra latency cycles since wbck is 6 cycles
 432                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 433                                InstrStage<1, [A9_Pipe1], 0>,
 434                                InstrStage<1, [A9_LSPipe]>,
 435                                InstrStage<1, [A9_NPipe]>], [2, 2, 2, 2, 1]>,
 436   //
 437   // VST
 438   // FIXME: We don't model this instruction properly
 439   InstrItinData<IIC_VST,      [InstrStage<1, [A9_DRegsN],   0, Required>,
 440                                // Extra latency cycles since wbck is 6 cycles
 441                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 442                                InstrStage<1, [A9_Pipe1], 0>,
 443                                InstrStage<1, [A9_LSPipe]>,
 444                                InstrStage<1, [A9_NPipe]>]>,
 445   //
 446   // Double-register Integer Unary
 447   InstrItinData<IIC_VUNAiD,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 448                                // Extra latency cycles since wbck is 6 cycles
 449                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 450                                InstrStage<1, [A9_Pipe1]>,
 451                                InstrStage<1, [A9_NPipe]>], [4, 2]>,
 452   //
 453   // Quad-register Integer Unary
 454   InstrItinData<IIC_VUNAiQ,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 455                                // Extra latency cycles since wbck is 6 cycles
 456                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 457                                InstrStage<1, [A9_Pipe1]>,
 458                                InstrStage<1, [A9_NPipe]>], [4, 2]>,
 459   //
 460   // Double-register Integer Q-Unary
 461   InstrItinData<IIC_VQUNAiD,  [InstrStage<1, [A9_DRegsN],   0, Required>,
 462                                // Extra latency cycles since wbck is 6 cycles
 463                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 464                                InstrStage<1, [A9_Pipe1]>,
 465                                InstrStage<1, [A9_NPipe]>], [4, 1]>,
 466   //
 467   // Quad-register Integer CountQ-Unary
 468   InstrItinData<IIC_VQUNAiQ,  [InstrStage<1, [A9_DRegsN],   0, Required>,
 469                                // Extra latency cycles since wbck is 6 cycles
 470                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 471                                InstrStage<1, [A9_Pipe1]>,
 472                                InstrStage<1, [A9_NPipe]>], [4, 1]>,
 473   //
 474   // Double-register Integer Binary
 475   InstrItinData<IIC_VBINiD,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 476                                // Extra latency cycles since wbck is 6 cycles
 477                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 478                                InstrStage<1, [A9_Pipe1]>,
 479                                InstrStage<1, [A9_NPipe]>], [3, 2, 2]>,
 480   //
 481   // Quad-register Integer Binary
 482   InstrItinData<IIC_VBINiQ,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 483                                // Extra latency cycles since wbck is 6 cycles
 484                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 485                                InstrStage<1, [A9_Pipe1]>,
 486                                InstrStage<1, [A9_NPipe]>], [3, 2, 2]>,
 487   //
 488   // Double-register Integer Subtract
 489   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 490                                // Extra latency cycles since wbck is 6 cycles
 491                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 492                                InstrStage<1, [A9_Pipe1]>,
 493                                InstrStage<1, [A9_NPipe]>], [3, 2, 1]>,
 494   //
 495   // Quad-register Integer Subtract
 496   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 497                                // Extra latency cycles since wbck is 6 cycles
 498                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 499                                InstrStage<1, [A9_Pipe1]>,
 500                                InstrStage<1, [A9_NPipe]>], [3, 2, 1]>,
 501   //
 502   // Double-register Integer Shift
 503   InstrItinData<IIC_VSHLiD,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 504                                // Extra latency cycles since wbck is 6 cycles
 505                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 506                                InstrStage<1, [A9_Pipe1]>,
 507                                InstrStage<1, [A9_NPipe]>], [3, 1, 1]>,
 508   //
 509   // Quad-register Integer Shift
 510   InstrItinData<IIC_VSHLiQ,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 511                                // Extra latency cycles since wbck is 6 cycles
 512                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 513                                InstrStage<1, [A9_Pipe1]>,
 514                                InstrStage<1, [A9_NPipe]>], [3, 1, 1]>,
 515   //
 516   // Double-register Integer Shift (4 cycle)
 517   InstrItinData<IIC_VSHLi4D,  [InstrStage<1, [A9_DRegsN],   0, Required>,
 518                                // Extra latency cycles since wbck is 6 cycles
 519                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 520                                InstrStage<1, [A9_Pipe1]>,
 521                                InstrStage<1, [A9_NPipe]>], [4, 1, 1]>,
 522   //
 523   // Quad-register Integer Shift (4 cycle)
 524   InstrItinData<IIC_VSHLi4Q,  [InstrStage<1, [A9_DRegsN],   0, Required>,
 525                                // Extra latency cycles since wbck is 6 cycles
 526                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 527                                InstrStage<1, [A9_Pipe1]>,
 528                                InstrStage<1, [A9_NPipe]>], [4, 1, 1]>,
 529   //
 530   // Double-register Integer Binary (4 cycle)
 531   InstrItinData<IIC_VBINi4D,  [InstrStage<1, [A9_DRegsN],   0, Required>,
 532                                // Extra latency cycles since wbck is 6 cycles
 533                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 534                                InstrStage<1, [A9_Pipe1]>,
 535                                InstrStage<1, [A9_NPipe]>], [4, 2, 2]>,
 536   //
 537   // Quad-register Integer Binary (4 cycle)
 538   InstrItinData<IIC_VBINi4Q,  [InstrStage<1, [A9_DRegsN],   0, Required>,
 539                                // Extra latency cycles since wbck is 6 cycles
 540                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 541                                InstrStage<1, [A9_Pipe1]>,
 542                                InstrStage<1, [A9_NPipe]>], [4, 2, 2]>,
 543   //
 544   // Double-register Integer Subtract (4 cycle)
 545   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 546                                // Extra latency cycles since wbck is 6 cycles
 547                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 548                                InstrStage<1, [A9_Pipe1]>,
 549                                InstrStage<1, [A9_NPipe]>], [4, 2, 1]>,
 550   //
 551   // Quad-register Integer Subtract (4 cycle)
 552   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 553                                // Extra latency cycles since wbck is 6 cycles
 554                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 555                                InstrStage<1, [A9_Pipe1]>,
 556                                InstrStage<1, [A9_NPipe]>], [4, 2, 1]>,
 557
 558   //
 559   // Double-register Integer Count
 560   InstrItinData<IIC_VCNTiD,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 561                                // Extra latency cycles since wbck is 6 cycles
 562                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 563                                InstrStage<1, [A9_Pipe1]>,
 564                                InstrStage<1, [A9_NPipe]>], [3, 2, 2]>,
 565   //
 566   // Quad-register Integer Count
 567   // Result written in N3, but that is relative to the last cycle of multicycle,
 568   // so we use 4 for those cases
 569   InstrItinData<IIC_VCNTiQ,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 570                                // Extra latency cycles since wbck is 7 cycles
 571                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 572                                InstrStage<1, [A9_Pipe1]>,
 573                                InstrStage<2, [A9_NPipe]>], [4, 2, 2]>,
 574   //
 575   // Double-register Absolute Difference and Accumulate
 576   InstrItinData<IIC_VABAD,    [InstrStage<1, [A9_DRegsN],   0, Required>,
 577                                // Extra latency cycles since wbck is 6 cycles
 578                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 579                                InstrStage<1, [A9_Pipe1]>,
 580                                InstrStage<1, [A9_NPipe]>], [6, 3, 2, 1]>,
 581   //
 582   // Quad-register Absolute Difference and Accumulate
 583   InstrItinData<IIC_VABAQ,    [InstrStage<1, [A9_DRegsN],   0, Required>,
 584                                // Extra latency cycles since wbck is 6 cycles
 585                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 586                                InstrStage<1, [A9_Pipe1]>,
 587                                InstrStage<2, [A9_NPipe]>], [6, 3, 2, 1]>,
 588   //
 589   // Double-register Integer Pair Add Long
 590   InstrItinData<IIC_VPALiD,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 591                                // Extra latency cycles since wbck is 6 cycles
 592                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 593                                InstrStage<1, [A9_Pipe1]>,
 594                                InstrStage<1, [A9_NPipe]>], [6, 3, 1]>,
 595   //
 596   // Quad-register Integer Pair Add Long
 597   InstrItinData<IIC_VPALiQ,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 598                                // Extra latency cycles since wbck is 6 cycles
 599                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 600                                InstrStage<1, [A9_Pipe1]>,
 601                                InstrStage<2, [A9_NPipe]>], [6, 3, 1]>,
 602
 603   //
 604   // Double-register Integer Multiply (.8, .16)
 605   InstrItinData<IIC_VMULi16D, [InstrStage<1, [A9_DRegsN],   0, Required>,
 606                                // Extra latency cycles since wbck is 6 cycles
 607                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 608                                InstrStage<1, [A9_Pipe1]>,
 609                                InstrStage<1, [A9_NPipe]>], [6, 2, 2]>,
 610   //
 611   // Quad-register Integer Multiply (.8, .16)
 612   InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A9_DRegsN],   0, Required>,
 613                                // Extra latency cycles since wbck is 7 cycles
 614                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 615                                InstrStage<1, [A9_Pipe1]>,
 616                                InstrStage<2, [A9_NPipe]>], [7, 2, 2]>,
 617
 618   //
 619   // Double-register Integer Multiply (.32)
 620   InstrItinData<IIC_VMULi32D, [InstrStage<1, [A9_DRegsN],   0, Required>,
 621                                // Extra latency cycles since wbck is 7 cycles
 622                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 623                                InstrStage<1, [A9_Pipe1]>,
 624                                InstrStage<2, [A9_NPipe]>], [7, 2, 1]>,
 625   //
 626   // Quad-register Integer Multiply (.32)
 627   InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A9_DRegsN],   0, Required>,
 628                                // Extra latency cycles since wbck is 9 cycles
 629                                InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
 630                                InstrStage<1, [A9_Pipe1]>,
 631                                InstrStage<4, [A9_NPipe]>], [9, 2, 1]>,
 632   //
 633   // Double-register Integer Multiply-Accumulate (.8, .16)
 634   InstrItinData<IIC_VMACi16D, [InstrStage<1, [A9_DRegsN],   0, Required>,
 635                                // Extra latency cycles since wbck is 6 cycles
 636                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 637                                InstrStage<1, [A9_Pipe1]>,
 638                                InstrStage<1, [A9_NPipe]>], [6, 3, 2, 2]>,
 639   //
 640   // Double-register Integer Multiply-Accumulate (.32)
 641   InstrItinData<IIC_VMACi32D, [InstrStage<1, [A9_DRegsN],   0, Required>,
 642                                // Extra latency cycles since wbck is 7 cycles
 643                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 644                                InstrStage<1, [A9_Pipe1]>,
 645                                InstrStage<2, [A9_NPipe]>], [7, 3, 2, 1]>,
 646   //
 647   // Quad-register Integer Multiply-Accumulate (.8, .16)
 648   InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A9_DRegsN],   0, Required>,
 649                                // Extra latency cycles since wbck is 7 cycles
 650                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 651                                InstrStage<1, [A9_Pipe1]>,
 652                                InstrStage<2, [A9_NPipe]>], [7, 3, 2, 2]>,
 653   //
 654   // Quad-register Integer Multiply-Accumulate (.32)
 655   InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A9_DRegsN],   0, Required>,
 656                                // Extra latency cycles since wbck is 9 cycles
 657                                InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
 658                                InstrStage<1, [A9_Pipe1]>,
 659                                InstrStage<4, [A9_NPipe]>], [9, 3, 2, 1]>,
 660   //
 661   // Move Immediate
 662   InstrItinData<IIC_VMOVImm,  [InstrStage<1, [A9_DRegsN],   0, Required>,
 663                                // Extra latency cycles since wbck is 6 cycles
 664                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 665                                InstrStage<1, [A9_Pipe1]>,
 666                                InstrStage<1, [A9_NPipe]>], [3]>,
 667   //
 668   // Double-register Permute Move
 669   InstrItinData<IIC_VMOVD,    [InstrStage<1, [A9_DRegsN],   0, Required>,
 670   // FIXME: all latencies are arbitrary, no information is available
 671                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
 672                                InstrStage<1, [A9_Pipe1]>,
 673                                InstrStage<1, [A9_LSPipe]>], [2, 1]>,
 674   //
 675   // Quad-register Permute Move
 676   // Result written in N2, but that is relative to the last cycle of multicycle,
 677   // so we use 3 for those cases
 678   InstrItinData<IIC_VMOVQ,    [InstrStage<1, [A9_DRegsN],   0, Required>,
 679   // FIXME: all latencies are arbitrary, no information is available
 680                                InstrStage<4, [A9_DRegsVFP], 0, Reserved>,
 681                                InstrStage<1, [A9_Pipe1]>,
 682                                InstrStage<2, [A9_NPipe]>], [3, 1]>,
 683   //
 684   // Integer to Single-precision Move
 685   InstrItinData<IIC_VMOVIS ,  [InstrStage<1, [A9_DRegsN],   0, Required>,
 686   // FIXME: all latencies are arbitrary, no information is available
 687                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
 688                                InstrStage<1, [A9_Pipe1]>,
 689                                InstrStage<1, [A9_NPipe]>], [2, 1]>,
 690   //
 691   // Integer to Double-precision Move
 692   InstrItinData<IIC_VMOVID ,  [InstrStage<1, [A9_DRegsN],   0, Required>,
 693   // FIXME: all latencies are arbitrary, no information is available
 694                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
 695                                InstrStage<1, [A9_Pipe1]>,
 696                                InstrStage<1, [A9_NPipe]>], [2, 1, 1]>,
 697   //
 698   // Single-precision to Integer Move
 699   InstrItinData<IIC_VMOVSI ,  [InstrStage<1, [A9_DRegsN],   0, Required>,
 700   // FIXME: all latencies are arbitrary, no information is available
 701                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
 702                                InstrStage<1, [A9_Pipe1]>,
 703                                InstrStage<1, [A9_NPipe]>], [2, 1]>,
 704   //
 705   // Double-precision to Integer Move
 706   InstrItinData<IIC_VMOVDI ,  [InstrStage<1, [A9_DRegsN],   0, Required>,
 707   // FIXME: all latencies are arbitrary, no information is available
 708                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
 709                                InstrStage<1, [A9_Pipe1]>,
 710                                InstrStage<1, [A9_NPipe]>], [2, 2, 1]>,
 711   //
 712   // Integer to Lane Move
 713   InstrItinData<IIC_VMOVISL , [InstrStage<1, [A9_DRegsN],   0, Required>,
 714   // FIXME: all latencies are arbitrary, no information is available
 715                                InstrStage<4, [A9_DRegsVFP], 0, Reserved>,
 716                                InstrStage<1, [A9_Pipe1]>,
 717                                InstrStage<2, [A9_NPipe]>], [3, 1, 1]>,
 718
 719   //
 720   // Double-register FP Unary
 721   InstrItinData<IIC_VUNAD,    [InstrStage<1, [A9_DRegsN],   0, Required>,
 722                                // Extra latency cycles since wbck is 6 cycles
 723                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 724                                InstrStage<1, [A9_Pipe1]>,
 725                                InstrStage<1, [A9_NPipe]>], [5, 2]>,
 726   //
 727   // Quad-register FP Unary
 728   // Result written in N5, but that is relative to the last cycle of multicycle,
 729   // so we use 6 for those cases
 730   InstrItinData<IIC_VUNAQ,    [InstrStage<1, [A9_DRegsN],   0, Required>,
 731                                // Extra latency cycles since wbck is 7 cycles
 732                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 733                                InstrStage<1, [A9_Pipe1]>,
 734                                InstrStage<2, [A9_NPipe]>], [6, 2]>,
 735   //
 736   // Double-register FP Binary
 737   // FIXME: We're using this itin for many instructions and [2, 2] here is too
 738   // optimistic.
 739   InstrItinData<IIC_VBIND,    [InstrStage<1, [A9_DRegsN],   0, Required>,
 740                                // Extra latency cycles since wbck is 7 cycles
 741                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 742                                InstrStage<1, [A9_Pipe1]>,
 743                                InstrStage<1, [A9_NPipe]>], [5, 2, 2]>,
 744   //
 745   // Quad-register FP Binary
 746   // Result written in N5, but that is relative to the last cycle of multicycle,
 747   // so we use 6 for those cases
 748   // FIXME: We're using this itin for many instructions and [2, 2] here is too
 749   // optimistic.
 750   InstrItinData<IIC_VBINQ,    [InstrStage<1, [A9_DRegsN],   0, Required>,
 751                                // Extra latency cycles since wbck is 8 cycles
 752                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 753                                InstrStage<1, [A9_Pipe1]>,
 754                                InstrStage<2, [A9_NPipe]>], [6, 2, 2]>,
 755   //
 756   // Double-register FP Multiple-Accumulate
 757   InstrItinData<IIC_VMACD,    [InstrStage<1, [A9_DRegsN],   0, Required>,
 758                                // Extra latency cycles since wbck is 7 cycles
 759                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 760                                InstrStage<1, [A9_Pipe1]>,
 761                                InstrStage<2, [A9_NPipe]>], [6, 3, 2, 1]>,
 762   //
 763   // Quad-register FP Multiple-Accumulate
 764   // Result written in N9, but that is relative to the last cycle of multicycle,
 765   // so we use 10 for those cases
 766   InstrItinData<IIC_VMACQ,    [InstrStage<1, [A9_DRegsN],   0, Required>,
 767                                // Extra latency cycles since wbck is 9 cycles
 768                                InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
 769                                InstrStage<1, [A9_Pipe1]>,
 770                                InstrStage<4, [A9_NPipe]>], [8, 4, 2, 1]>,
 771   //
 772   // Double-register Reciprical Step
 773   InstrItinData<IIC_VRECSD,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 774                                // Extra latency cycles since wbck is 7 cycles
 775                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 776                                InstrStage<1, [A9_Pipe1]>,
 777                                InstrStage<2, [A9_NPipe]>], [6, 2, 2]>,
 778   //
 779   // Quad-register Reciprical Step
 780   InstrItinData<IIC_VRECSQ,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 781                                // Extra latency cycles since wbck is 9 cycles
 782                                InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
 783                                InstrStage<1, [A9_Pipe1]>,
 784                                InstrStage<4, [A9_NPipe]>], [8, 2, 2]>,
 785   //
 786   // Double-register Permute
 787   InstrItinData<IIC_VPERMD,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 788                                // Extra latency cycles since wbck is 6 cycles
 789                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 790                                InstrStage<1, [A9_Pipe1]>,
 791                                InstrStage<1, [A9_NPipe]>], [2, 2, 1, 1]>,
 792   //
 793   // Quad-register Permute
 794   // Result written in N2, but that is relative to the last cycle of multicycle,
 795   // so we use 3 for those cases
 796   InstrItinData<IIC_VPERMQ,   [InstrStage<1, [A9_DRegsN],   0, Required>,
 797                                // Extra latency cycles since wbck is 7 cycles
 798                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 799                                InstrStage<1, [A9_Pipe1]>,
 800                                InstrStage<2, [A9_NPipe]>], [3, 3, 1, 1]>,
 801   //
 802   // Quad-register Permute (3 cycle issue)
 803   // Result written in N2, but that is relative to the last cycle of multicycle,
 804   // so we use 4 for those cases
 805   InstrItinData<IIC_VPERMQ3,  [InstrStage<1, [A9_DRegsN],   0, Required>,
 806                                // Extra latency cycles since wbck is 8 cycles
 807                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
 808                                InstrStage<1, [A9_Pipe1]>,
 809                                InstrStage<3, [A9_LSPipe]>], [4, 4, 1, 1]>,
 810
 811   //
 812   // Double-register VEXT
 813   InstrItinData<IIC_VEXTD,    [InstrStage<1, [A9_DRegsN],   0, Required>,
 814                                // Extra latency cycles since wbck is 7 cycles
 815                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
 816                                InstrStage<1, [A9_Pipe1]>,
 817                                InstrStage<1, [A9_NPipe]>], [2, 1, 1]>,
 818   //
 819   // Quad-register VEXT
 820   InstrItinData<IIC_VEXTQ,    [InstrStage<1, [A9_DRegsN],   0, Required>,
 821                                // Extra latency cycles since wbck is 9 cycles
 822                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 823                                InstrStage<1, [A9_Pipe1]>,
 824                                InstrStage<2, [A9_NPipe]>], [3, 1, 1]>,
 825   //
 826   // VTB
 827   InstrItinData<IIC_VTB1,     [InstrStage<1, [A9_DRegsN],   0, Required>,
 828                                // Extra latency cycles since wbck is 7 cycles
 829                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 830                                InstrStage<1, [A9_Pipe1]>,
 831                                InstrStage<2, [A9_NPipe]>], [3, 2, 1]>,
 832   InstrItinData<IIC_VTB2,     [InstrStage<2, [A9_DRegsN],   0, Required>,
 833                                // Extra latency cycles since wbck is 7 cycles
 834                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 835                                InstrStage<1, [A9_Pipe1]>,
 836                                InstrStage<2, [A9_NPipe]>], [3, 2, 2, 1]>,
 837   InstrItinData<IIC_VTB3,     [InstrStage<2, [A9_DRegsN],   0, Required>,
 838                                // Extra latency cycles since wbck is 8 cycles
 839                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
 840                                InstrStage<1, [A9_Pipe1]>,
 841                                InstrStage<3, [A9_NPipe]>], [4, 2, 2, 3, 1]>,
 842   InstrItinData<IIC_VTB4,     [InstrStage<1, [A9_DRegsN],   0, Required>,
 843                                // Extra latency cycles since wbck is 8 cycles
 844                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
 845                                InstrStage<1, [A9_Pipe1]>,
 846                                InstrStage<3, [A9_NPipe]>], [4, 2, 2, 3, 3, 1]>,
 847   //
 848   // VTBX
 849   InstrItinData<IIC_VTBX1,    [InstrStage<1, [A9_DRegsN],   0, Required>,
 850                                // Extra latency cycles since wbck is 7 cycles
 851                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 852                                InstrStage<1, [A9_Pipe1]>,
 853                                InstrStage<2, [A9_NPipe]>], [3, 1, 2, 1]>,
 854   InstrItinData<IIC_VTBX2,    [InstrStage<1, [A9_DRegsN],   0, Required>,
 855                                // Extra latency cycles since wbck is 7 cycles
 856                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 857                                InstrStage<1, [A9_Pipe1]>,
 858                                InstrStage<2, [A9_NPipe]>], [3, 1, 2, 2, 1]>,
 859   InstrItinData<IIC_VTBX3,    [InstrStage<1, [A9_DRegsN],   0, Required>,
 860                                // Extra latency cycles since wbck is 8 cycles
 861                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
 862                                InstrStage<1, [A9_Pipe1]>,
 863                                InstrStage<3, [A9_NPipe]>], [4, 1, 2, 2, 3, 1]>,
 864   InstrItinData<IIC_VTBX4,    [InstrStage<1, [A9_DRegsN],   0, Required>,
 865                                // Extra latency cycles since wbck is 8 cycles
 866                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
 867                                InstrStage<1, [A9_Pipe1]>,
 868                               InstrStage<2, [A9_NPipe]>], [4, 1, 2, 2, 3, 3, 1]>
 869 ]>;