lib/Target/ARM/ARMScheduleA8.td

   1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //
  15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
  16 // Functional Units.
  17 def A8_Pipe0   : FuncUnit; // pipeline 0
  18 def A8_Pipe1   : FuncUnit; // pipeline 1
  19 def A8_LSPipe  : FuncUnit; // Load / store pipeline
  20 def A8_NPipe   : FuncUnit; // NEON ALU/MUL pipe
  21 def A8_NLSPipe : FuncUnit; // NEON LS pipe
  22 //
  23 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
  24 //
  25 def CortexA8Itineraries : MultiIssueItineraries<
  26   2,  // IssueWidth
  27   -1, // MinLatency - OperandCycles are interpreted as MinLatency.
  28   2,  // LoadLatency - overriden by OperandCycles.
  29   10, // HighLatency - currently unused.
  30   [A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe],
  31   [], [
  32   // Two fully-pipelined integer ALU pipelines
  33   //
  34   // No operand cycles
  35   InstrItinData<IIC_iALUx    , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
  36   //
  37   // Binary Instructions that produce a result
  38   InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  39   InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  40   InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  41   InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
  42   InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  43   //
  44   // Bitwise Instructions that produce a result
  45   InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  46   InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  47   InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  48   InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  49   //
  50   // Unary Instructions that produce a result
  51   InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  52   InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  53   //
  54   // Zero and sign extension instructions
  55   InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  56   InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  57   InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>,
  58   //
  59   // Compare instructions
  60   InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  61   InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  62   InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  63   InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  64   //
  65   // Test instructions
  66   InstrItinData<IIC_iTSTi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  67   InstrItinData<IIC_iTSTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  68   InstrItinData<IIC_iTSTsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  69   InstrItinData<IIC_iTSTsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  70   //
  71   // Move instructions, unconditional
  72   InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  73   InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  74   InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  75   InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  76   InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  77                              InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  78   InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  79                                   InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  80                                   InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [3]>,
  81   InstrItinData<IIC_iMOVix2ld,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  82                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  83                                InstrStage<1, [A8_LSPipe]>], [5]>,
  84   //
  85   // Move instructions, conditional
  86   InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  87   InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  88   InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  89   InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  90   InstrItinData<IIC_iCMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  91                               InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [3, 1]>,
  92   //
  93   // MVN instructions
  94   InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  95   InstrItinData<IIC_iMVNr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  96   InstrItinData<IIC_iMVNsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  97   InstrItinData<IIC_iMVNsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  98
  99   // Integer multiply pipeline
 100   // Result written in E5, but that is relative to the last cycle of multicycle,
 101   // so we use 6 for those cases
 102   //
 103   InstrItinData<IIC_iMUL16   , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>,
 104   InstrItinData<IIC_iMAC16   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
 105   InstrItinData<IIC_iMUL32   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>,
 106   InstrItinData<IIC_iMAC32   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
 107   InstrItinData<IIC_iMUL64   , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
 108   InstrItinData<IIC_iMAC64   , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
 109
 110   // Integer load pipeline
 111   //
 112   // Immediate offset
 113   InstrItinData<IIC_iLoad_i   , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 114                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 115   InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 116                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 117   InstrItinData<IIC_iLoad_d_i,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 118                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 119   //
 120   // Register offset
 121   InstrItinData<IIC_iLoad_r   , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 122                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 123   InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 124                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 125   InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 126                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 127   //
 128   // Scaled register offset, issues over 2 cycles
 129   // FIXME: lsl by 2 takes 1 cycle.
 130   InstrItinData<IIC_iLoad_si  , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 131                                  InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
 132   InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 133                                  InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
 134   //
 135   // Immediate offset with update
 136   InstrItinData<IIC_iLoad_iu  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 137                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
 138   InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 139                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
 140   //
 141   // Register offset with update
 142   InstrItinData<IIC_iLoad_ru  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 143                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 144   InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 145                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 146   InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 147                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 148   //
 149   // Scaled register offset with update, issues over 2 cycles
 150   InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 151                                  InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>,
 152   InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 153                                   InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>,
 154   //
 155   // Load multiple, def is the 5th operand. Pipeline 0 only.
 156   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 157   InstrItinData<IIC_iLoad_m  , [InstrStage<2, [A8_Pipe0], 0>,
 158                                 InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1, 3]>,
 159   //
 160   // Load multiple + update, defs are the 1st and 5th operands.
 161   InstrItinData<IIC_iLoad_mu , [InstrStage<3, [A8_Pipe0], 0>,
 162                                 InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 3]>,
 163   //
 164   // Load multiple plus branch
 165   InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [A8_Pipe0], 0>,
 166                                 InstrStage<3, [A8_LSPipe]>,
 167                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
 168                                [1, 2, 1, 1, 3]>,
 169   //
 170   // Pop, def is the 3rd operand.
 171   InstrItinData<IIC_iPop  ,    [InstrStage<3, [A8_Pipe0], 0>,
 172                                 InstrStage<3, [A8_LSPipe]>], [1, 1, 3]>,
 173   //
 174   // Push, def is the 3th operand.
 175   InstrItinData<IIC_iPop_Br,   [InstrStage<3, [A8_Pipe0], 0>,
 176                                 InstrStage<3, [A8_LSPipe]>,
 177                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
 178                                [1, 1, 3]>,
 179
 180   //
 181   // iLoadi + iALUr for t2LDRpci_pic.
 182   InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 183                                 InstrStage<1, [A8_LSPipe]>,
 184                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
 185
 186
 187   // Integer store pipeline
 188   //
 189   // Immediate offset
 190   InstrItinData<IIC_iStore_i  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 191                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 192   InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 193                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 194   InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 195                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 196   //
 197   // Register offset
 198   InstrItinData<IIC_iStore_r  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 199                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 200   InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 201                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 202   InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 203                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 204   //
 205   // Scaled register offset, issues over 2 cycles
 206   InstrItinData<IIC_iStore_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 207                                  InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
 208   InstrItinData<IIC_iStore_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 209                                   InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
 210   //
 211   // Immediate offset with update
 212   InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 213                                  InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
 214   InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 215                                  InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
 216   //
 217   // Register offset with update
 218   InstrItinData<IIC_iStore_ru  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 219                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 220   InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 221                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 222   InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 223                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 224   //
 225   // Scaled register offset with update, issues over 2 cycles
 226   InstrItinData<IIC_iStore_siu, [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 227                                  InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
 228   InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 229                                    InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
 230   //
 231   // Store multiple. Pipeline 0 only.
 232   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 233   InstrItinData<IIC_iStore_m , [InstrStage<2, [A8_Pipe0], 0>,
 234                                 InstrStage<2, [A8_LSPipe]>]>,
 235   //
 236   // Store multiple + update
 237   InstrItinData<IIC_iStore_mu, [InstrStage<2, [A8_Pipe0], 0>,
 238                                 InstrStage<2, [A8_LSPipe]>], [2]>,
 239
 240   //
 241   // Preload
 242   InstrItinData<IIC_Preload, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
 243
 244   // Branch
 245   //
 246   // no delay slots, so the latency of a branch is unimportant
 247   InstrItinData<IIC_Br      , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
 248
 249   // VFP
 250   // Issue through integer pipeline, and execute in NEON unit. We assume
 251   // RunFast mode so that NFP pipeline is used for single-precision when
 252   // possible.
 253   //
 254   // FP Special Register to Integer Register File Move
 255   InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 256                               InstrStage<1, [A8_NLSPipe]>], [20]>,
 257   //
 258   // Single-precision FP Unary
 259   InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 260                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 261   //
 262   // Double-precision FP Unary
 263   InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 264                                InstrStage<4, [A8_NPipe], 0>,
 265                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 266   //
 267   // Single-precision FP Compare
 268   InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 269                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 270   //
 271   // Double-precision FP Compare
 272   InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 273                                InstrStage<4, [A8_NPipe], 0>,
 274                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 275   //
 276   // Single to Double FP Convert
 277   InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 278                                InstrStage<7, [A8_NPipe], 0>,
 279                                InstrStage<7, [A8_NLSPipe]>], [7, 1]>,
 280   //
 281   // Double to Single FP Convert
 282   InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 283                                InstrStage<5, [A8_NPipe], 0>,
 284                                InstrStage<5, [A8_NLSPipe]>], [5, 1]>,
 285   //
 286   // Single-Precision FP to Integer Convert
 287   InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 288                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 289   //
 290   // Double-Precision FP to Integer Convert
 291   InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 292                                InstrStage<8, [A8_NPipe], 0>,
 293                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 294   //
 295   // Integer to Single-Precision FP Convert
 296   InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 297                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 298   //
 299   // Integer to Double-Precision FP Convert
 300   InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 301                                InstrStage<8, [A8_NPipe], 0>,
 302                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 303   //
 304   // Single-precision FP ALU
 305   InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 306                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 307   //
 308   // Double-precision FP ALU
 309   InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 310                                InstrStage<9, [A8_NPipe], 0>,
 311                                InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>,
 312   //
 313   // Single-precision FP Multiply
 314   InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 315                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 316   //
 317   // Double-precision FP Multiply
 318   InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 319                                InstrStage<11, [A8_NPipe], 0>,
 320                                InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>,
 321   //
 322   // Single-precision FP MAC
 323   InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 324                                InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
 325   //
 326   // Double-precision FP MAC
 327   InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 328                                InstrStage<19, [A8_NPipe], 0>,
 329                                InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
 330   //
 331   // Single-precision Fused FP MAC
 332   InstrItinData<IIC_fpFMAC32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 333                                InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
 334   //
 335   // Double-precision Fused FP MAC
 336   InstrItinData<IIC_fpFMAC64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 337                                InstrStage<19, [A8_NPipe], 0>,
 338                                InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
 339   //
 340   // Single-precision FP DIV
 341   InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 342                                InstrStage<20, [A8_NPipe], 0>,
 343                                InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>,
 344   //
 345   // Double-precision FP DIV
 346   InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 347                                InstrStage<29, [A8_NPipe], 0>,
 348                                InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>,
 349   //
 350   // Single-precision FP SQRT
 351   InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 352                                InstrStage<19, [A8_NPipe], 0>,
 353                                InstrStage<19, [A8_NLSPipe]>], [19, 1]>,
 354   //
 355   // Double-precision FP SQRT
 356   InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 357                                InstrStage<29, [A8_NPipe], 0>,
 358                                InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
 359
 360   //
 361   // Integer to Single-precision Move
 362   InstrItinData<IIC_fpMOVIS,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 363                                InstrStage<1, [A8_NPipe]>],
 364                               [2, 1]>,
 365   //
 366   // Integer to Double-precision Move
 367   InstrItinData<IIC_fpMOVID,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 368                                InstrStage<1, [A8_NPipe]>],
 369                               [2, 1, 1]>,
 370   //
 371   // Single-precision to Integer Move
 372   InstrItinData<IIC_fpMOVSI,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 373                                InstrStage<1, [A8_NPipe]>],
 374                               [20, 1]>,
 375   //
 376   // Double-precision to Integer Move
 377   InstrItinData<IIC_fpMOVDI,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 378                                InstrStage<1, [A8_NPipe]>],
 379                               [20, 20, 1]>,
 380
 381   //
 382   // Single-precision FP Load
 383   InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 384                                InstrStage<1, [A8_NLSPipe], 0>,
 385                                InstrStage<1, [A8_LSPipe]>],
 386                               [2, 1]>,
 387   //
 388   // Double-precision FP Load
 389   InstrItinData<IIC_fpLoad64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 390                                InstrStage<1, [A8_NLSPipe], 0>,
 391                                InstrStage<1, [A8_LSPipe]>],
 392                               [2, 1]>,
 393   //
 394   // FP Load Multiple
 395   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 396   InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 397                                InstrStage<1, [A8_NLSPipe], 0>,
 398                                InstrStage<1, [A8_LSPipe]>,
 399                                InstrStage<1, [A8_NLSPipe], 0>,
 400                                InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 2]>,
 401   //
 402   // FP Load Multiple + update
 403   InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 404                                InstrStage<1, [A8_NLSPipe], 0>,
 405                                InstrStage<1, [A8_LSPipe]>,
 406                                InstrStage<1, [A8_NLSPipe], 0>,
 407                                InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 2]>,
 408   //
 409   // Single-precision FP Store
 410   InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 411                                InstrStage<1, [A8_NLSPipe], 0>,
 412                                InstrStage<1, [A8_LSPipe]>],
 413                               [1, 1]>,
 414   //
 415   // Double-precision FP Store
 416   InstrItinData<IIC_fpStore64,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 417                                InstrStage<1, [A8_NLSPipe], 0>,
 418                                InstrStage<1, [A8_LSPipe]>],
 419                               [1, 1]>,
 420   //
 421   // FP Store Multiple
 422   InstrItinData<IIC_fpStore_m,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 423                                InstrStage<1, [A8_NLSPipe], 0>,
 424                                InstrStage<1, [A8_LSPipe]>,
 425                                InstrStage<1, [A8_NLSPipe], 0>,
 426                                InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 1]>,
 427   //
 428   // FP Store Multiple + update
 429   InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 430                                 InstrStage<1, [A8_NLSPipe], 0>,
 431                                 InstrStage<1, [A8_LSPipe]>,
 432                                 InstrStage<1, [A8_NLSPipe], 0>,
 433                                 InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 1]>,
 434
 435   // NEON
 436   // Issue through integer pipeline, and execute in NEON unit.
 437   //
 438   // VLD1
 439   InstrItinData<IIC_VLD1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 440                                InstrStage<2, [A8_NLSPipe], 0>,
 441                                InstrStage<2, [A8_LSPipe]>],
 442                               [2, 1]>,
 443   // VLD1x2
 444   InstrItinData<IIC_VLD1x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 445                                InstrStage<2, [A8_NLSPipe], 0>,
 446                                InstrStage<2, [A8_LSPipe]>],
 447                               [2, 2, 1]>,
 448   //
 449   // VLD1x3
 450   InstrItinData<IIC_VLD1x3,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 451                                InstrStage<3, [A8_NLSPipe], 0>,
 452                                InstrStage<3, [A8_LSPipe]>],
 453                               [2, 2, 3, 1]>,
 454   //
 455   // VLD1x4
 456   InstrItinData<IIC_VLD1x4,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 457                                InstrStage<3, [A8_NLSPipe], 0>,
 458                                InstrStage<3, [A8_LSPipe]>],
 459                               [2, 2, 3, 3, 1]>,
 460   //
 461   // VLD1u
 462   InstrItinData<IIC_VLD1u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 463                                InstrStage<2, [A8_NLSPipe], 0>,
 464                                InstrStage<2, [A8_LSPipe]>],
 465                               [2, 2, 1]>,
 466   //
 467   // VLD1x2u
 468   InstrItinData<IIC_VLD1x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 469                                InstrStage<2, [A8_NLSPipe], 0>,
 470                                InstrStage<2, [A8_LSPipe]>],
 471                               [2, 2, 2, 1]>,
 472   //
 473   // VLD1x3u
 474   InstrItinData<IIC_VLD1x3u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 475                                InstrStage<3, [A8_NLSPipe], 0>,
 476                                InstrStage<3, [A8_LSPipe]>],
 477                               [2, 2, 3, 2, 1]>,
 478   //
 479   // VLD1x4u
 480   InstrItinData<IIC_VLD1x4u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 481                                InstrStage<3, [A8_NLSPipe], 0>,
 482                                InstrStage<3, [A8_LSPipe]>],
 483                               [2, 2, 3, 3, 2, 1]>,
 484   //
 485   // VLD1ln
 486   InstrItinData<IIC_VLD1ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 487                                InstrStage<3, [A8_NLSPipe], 0>,
 488                                InstrStage<3, [A8_LSPipe]>],
 489                               [3, 1, 1, 1]>,
 490   //
 491   // VLD1lnu
 492   InstrItinData<IIC_VLD1lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 493                                InstrStage<3, [A8_NLSPipe], 0>,
 494                                InstrStage<3, [A8_LSPipe]>],
 495                               [3, 2, 1, 1, 1, 1]>,
 496   //
 497   // VLD1dup
 498   InstrItinData<IIC_VLD1dup,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 499                                InstrStage<2, [A8_NLSPipe], 0>,
 500                                InstrStage<2, [A8_LSPipe]>],
 501                               [2, 1]>,
 502   //
 503   // VLD1dupu
 504   InstrItinData<IIC_VLD1dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 505                                InstrStage<2, [A8_NLSPipe], 0>,
 506                                InstrStage<2, [A8_LSPipe]>],
 507                               [2, 2, 1, 1]>,
 508   //
 509   // VLD2
 510   InstrItinData<IIC_VLD2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 511                                InstrStage<2, [A8_NLSPipe], 0>,
 512                                InstrStage<2, [A8_LSPipe]>],
 513                               [2, 2, 1]>,
 514   //
 515   // VLD2x2
 516   InstrItinData<IIC_VLD2x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 517                                InstrStage<3, [A8_NLSPipe], 0>,
 518                                InstrStage<3, [A8_LSPipe]>],
 519                               [2, 2, 3, 3, 1]>,
 520   //
 521   // VLD2ln
 522   InstrItinData<IIC_VLD2ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 523                                InstrStage<3, [A8_NLSPipe], 0>,
 524                                InstrStage<3, [A8_LSPipe]>],
 525                               [3, 3, 1, 1, 1, 1]>,
 526   //
 527   // VLD2u
 528   InstrItinData<IIC_VLD2u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 529                                InstrStage<2, [A8_NLSPipe], 0>,
 530                                InstrStage<2, [A8_LSPipe]>],
 531                               [2, 2, 2, 1, 1, 1]>,
 532   //
 533   // VLD2x2u
 534   InstrItinData<IIC_VLD2x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 535                                InstrStage<3, [A8_NLSPipe], 0>,
 536                                InstrStage<3, [A8_LSPipe]>],
 537                               [2, 2, 3, 3, 2, 1]>,
 538   //
 539   // VLD2lnu
 540   InstrItinData<IIC_VLD2lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 541                                InstrStage<3, [A8_NLSPipe], 0>,
 542                                InstrStage<3, [A8_LSPipe]>],
 543                               [3, 3, 2, 1, 1, 1, 1, 1]>,
 544   //
 545   // VLD2dup
 546   InstrItinData<IIC_VLD2dup,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 547                                InstrStage<2, [A8_NLSPipe], 0>,
 548                                InstrStage<2, [A8_LSPipe]>],
 549                               [2, 2, 1]>,
 550   //
 551   // VLD2dupu
 552   InstrItinData<IIC_VLD2dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 553                                InstrStage<2, [A8_NLSPipe], 0>,
 554                                InstrStage<2, [A8_LSPipe]>],
 555                               [2, 2, 2, 1, 1]>,
 556   //
 557   // VLD3
 558   InstrItinData<IIC_VLD3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 559                                InstrStage<4, [A8_NLSPipe], 0>,
 560                                InstrStage<4, [A8_LSPipe]>],
 561                               [3, 3, 4, 1]>,
 562   //
 563   // VLD3ln
 564   InstrItinData<IIC_VLD3ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 565                                InstrStage<5, [A8_NLSPipe], 0>,
 566                                InstrStage<5, [A8_LSPipe]>],
 567                               [4, 4, 5, 1, 1, 1, 1, 2]>,
 568   //
 569   // VLD3u
 570   InstrItinData<IIC_VLD3u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 571                                InstrStage<4, [A8_NLSPipe], 0>,
 572                                InstrStage<4, [A8_LSPipe]>],
 573                               [3, 3, 4, 2, 1]>,
 574   //
 575   // VLD3lnu
 576   InstrItinData<IIC_VLD3lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 577                                InstrStage<5, [A8_NLSPipe], 0>,
 578                                InstrStage<5, [A8_LSPipe]>],
 579                               [4, 4, 5, 2, 1, 1, 1, 1, 1, 2]>,
 580   //
 581   // VLD3dup
 582   InstrItinData<IIC_VLD3dup,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 583                                InstrStage<3, [A8_NLSPipe], 0>,
 584                                InstrStage<3, [A8_LSPipe]>],
 585                               [2, 2, 3, 1]>,
 586   //
 587   // VLD3dupu
 588   InstrItinData<IIC_VLD3dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 589                                InstrStage<3, [A8_NLSPipe], 0>,
 590                                InstrStage<3, [A8_LSPipe]>],
 591                               [2, 2, 3, 2, 1, 1]>,
 592   //
 593   // VLD4
 594   InstrItinData<IIC_VLD4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 595                                InstrStage<4, [A8_NLSPipe], 0>,
 596                                InstrStage<4, [A8_LSPipe]>],
 597                               [3, 3, 4, 4, 1]>,
 598   //
 599   // VLD4ln
 600   InstrItinData<IIC_VLD4ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 601                                InstrStage<5, [A8_NLSPipe], 0>,
 602                                InstrStage<5, [A8_LSPipe]>],
 603                               [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>,
 604   //
 605   // VLD4u
 606   InstrItinData<IIC_VLD4u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 607                                InstrStage<4, [A8_NLSPipe], 0>,
 608                                InstrStage<4, [A8_LSPipe]>],
 609                               [3, 3, 4, 4, 2, 1]>,
 610   //
 611   // VLD4lnu
 612   InstrItinData<IIC_VLD4lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 613                                InstrStage<5, [A8_NLSPipe], 0>,
 614                                InstrStage<5, [A8_LSPipe]>],
 615                               [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>,
 616   //
 617   // VLD4dup
 618   InstrItinData<IIC_VLD4dup,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 619                                InstrStage<3, [A8_NLSPipe], 0>,
 620                                InstrStage<3, [A8_LSPipe]>],
 621                               [2, 2, 3, 3, 1]>,
 622   //
 623   // VLD4dupu
 624   InstrItinData<IIC_VLD4dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 625                                InstrStage<3, [A8_NLSPipe], 0>,
 626                                InstrStage<3, [A8_LSPipe]>],
 627                               [2, 2, 3, 3, 2, 1, 1]>,
 628   //
 629   // VST1
 630   InstrItinData<IIC_VST1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 631                                InstrStage<2, [A8_NLSPipe], 0>,
 632                                InstrStage<2, [A8_LSPipe]>],
 633                               [1, 1, 1]>,
 634   //
 635   // VST1x2
 636   InstrItinData<IIC_VST1x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 637                                InstrStage<2, [A8_NLSPipe], 0>,
 638                                InstrStage<2, [A8_LSPipe]>],
 639                               [1, 1, 1, 1]>,
 640   //
 641   // VST1x3
 642   InstrItinData<IIC_VST1x3,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 643                                InstrStage<3, [A8_NLSPipe], 0>,
 644                                InstrStage<3, [A8_LSPipe]>],
 645                               [1, 1, 1, 1, 2]>,
 646   //
 647   // VST1x4
 648   InstrItinData<IIC_VST1x4,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 649                                InstrStage<3, [A8_NLSPipe], 0>,
 650                                InstrStage<3, [A8_LSPipe]>],
 651                               [1, 1, 1, 1, 2, 2]>,
 652   //
 653   // VST1u
 654   InstrItinData<IIC_VST1u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 655                                InstrStage<2, [A8_NLSPipe], 0>,
 656                                InstrStage<2, [A8_LSPipe]>],
 657                               [2, 1, 1, 1, 1]>,
 658   //
 659   // VST1x2u
 660   InstrItinData<IIC_VST1x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 661                                InstrStage<2, [A8_NLSPipe], 0>,
 662                                InstrStage<2, [A8_LSPipe]>],
 663                               [2, 1, 1, 1, 1, 1]>,
 664   //
 665   // VST1x3u
 666   InstrItinData<IIC_VST1x3u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 667                                InstrStage<3, [A8_NLSPipe], 0>,
 668                                InstrStage<3, [A8_LSPipe]>],
 669                               [2, 1, 1, 1, 1, 1, 2]>,
 670   //
 671   // VST1x4u
 672   InstrItinData<IIC_VST1x4u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 673                                InstrStage<3, [A8_NLSPipe], 0>,
 674                                InstrStage<3, [A8_LSPipe]>],
 675                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 676   //
 677   // VST1ln
 678   InstrItinData<IIC_VST1ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 679                                InstrStage<2, [A8_NLSPipe], 0>,
 680                                InstrStage<2, [A8_LSPipe]>],
 681                               [1, 1, 1]>,
 682   //
 683   // VST1lnu
 684   InstrItinData<IIC_VST1lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 685                                InstrStage<2, [A8_NLSPipe], 0>,
 686                                InstrStage<2, [A8_LSPipe]>],
 687                               [2, 1, 1, 1, 1]>,
 688   //
 689   // VST2
 690   InstrItinData<IIC_VST2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 691                                InstrStage<2, [A8_NLSPipe], 0>,
 692                                InstrStage<2, [A8_LSPipe]>],
 693                               [1, 1, 1, 1]>,
 694   //
 695   // VST2x2
 696   InstrItinData<IIC_VST2x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 697                                InstrStage<4, [A8_NLSPipe], 0>,
 698                                InstrStage<4, [A8_LSPipe]>],
 699                               [1, 1, 1, 1, 2, 2]>,
 700   //
 701   // VST2u
 702   InstrItinData<IIC_VST2u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 703                                InstrStage<2, [A8_NLSPipe], 0>,
 704                                InstrStage<2, [A8_LSPipe]>],
 705                               [2, 1, 1, 1, 1, 1]>,
 706   //
 707   // VST2x2u
 708   InstrItinData<IIC_VST2x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 709                                InstrStage<4, [A8_NLSPipe], 0>,
 710                                InstrStage<4, [A8_LSPipe]>],
 711                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 712   //
 713   // VST2ln
 714   InstrItinData<IIC_VST2ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 715                                InstrStage<2, [A8_NLSPipe], 0>,
 716                                InstrStage<2, [A8_LSPipe]>],
 717                               [1, 1, 1, 1]>,
 718   //
 719   // VST2lnu
 720   InstrItinData<IIC_VST2lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 721                                InstrStage<2, [A8_NLSPipe], 0>,
 722                                InstrStage<2, [A8_LSPipe]>],
 723                               [2, 1, 1, 1, 1, 1]>,
 724   //
 725   // VST3
 726   InstrItinData<IIC_VST3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 727                                InstrStage<3, [A8_NLSPipe], 0>,
 728                                InstrStage<3, [A8_LSPipe]>],
 729                               [1, 1, 1, 1, 2]>,
 730   //
 731   // VST3u
 732   InstrItinData<IIC_VST3u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 733                                InstrStage<3, [A8_NLSPipe], 0>,
 734                                InstrStage<3, [A8_LSPipe]>],
 735                               [2, 1, 1, 1, 1, 1, 2]>,
 736   //
 737   // VST3ln
 738   InstrItinData<IIC_VST3ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 739                                InstrStage<3, [A8_NLSPipe], 0>,
 740                                InstrStage<3, [A8_LSPipe]>],
 741                               [1, 1, 1, 1, 2]>,
 742   //
 743   // VST3lnu
 744   InstrItinData<IIC_VST3lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 745                                InstrStage<3, [A8_NLSPipe], 0>,
 746                                InstrStage<3, [A8_LSPipe]>],
 747                               [2, 1, 1, 1, 1, 1, 2]>,
 748   //
 749   // VST4
 750   InstrItinData<IIC_VST4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 751                                InstrStage<4, [A8_NLSPipe], 0>,
 752                                InstrStage<4, [A8_LSPipe]>],
 753                               [1, 1, 1, 1, 2, 2]>,
 754   //
 755   // VST4u
 756   InstrItinData<IIC_VST4u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 757                                InstrStage<4, [A8_NLSPipe], 0>,
 758                                InstrStage<4, [A8_LSPipe]>],
 759                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 760   //
 761   // VST4ln
 762   InstrItinData<IIC_VST4ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 763                                InstrStage<4, [A8_NLSPipe], 0>,
 764                                InstrStage<4, [A8_LSPipe]>],
 765                               [1, 1, 1, 1, 2, 2]>,
 766   //
 767   // VST4lnu
 768   InstrItinData<IIC_VST4lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 769                                InstrStage<4, [A8_NLSPipe], 0>,
 770                                InstrStage<4, [A8_LSPipe]>],
 771                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 772   //
 773   // Double-register FP Unary
 774   InstrItinData<IIC_VUNAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 775                                InstrStage<1, [A8_NPipe]>], [5, 2]>,
 776   //
 777   // Quad-register FP Unary
 778   // Result written in N5, but that is relative to the last cycle of multicycle,
 779   // so we use 6 for those cases
 780   InstrItinData<IIC_VUNAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 781                                InstrStage<2, [A8_NPipe]>], [6, 2]>,
 782   //
 783   // Double-register FP Binary
 784   InstrItinData<IIC_VBIND,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 785                                InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
 786   //
 787   // VPADD, etc.
 788   InstrItinData<IIC_VPBIND,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 789                                InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
 790   //
 791   // Double-register FP VMUL
 792   InstrItinData<IIC_VFMULD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 793                                InstrStage<1, [A8_NPipe]>], [5, 2, 1]>,
 794
 795   //
 796   // Quad-register FP Binary
 797   // Result written in N5, but that is relative to the last cycle of multicycle,
 798   // so we use 6 for those cases
 799   InstrItinData<IIC_VBINQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 800                                InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
 801   //
 802   // Quad-register FP VMUL
 803   InstrItinData<IIC_VFMULQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 804                                InstrStage<1, [A8_NPipe]>], [6, 2, 1]>,
 805   //
 806   // Move
 807   InstrItinData<IIC_VMOV,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 808                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 809   //
 810   // Move Immediate
 811   InstrItinData<IIC_VMOVImm,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 812                                InstrStage<1, [A8_NPipe]>], [3]>,
 813   //
 814   // Double-register Permute Move
 815   InstrItinData<IIC_VMOVD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 816                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 817   //
 818   // Quad-register Permute Move
 819   // Result written in N2, but that is relative to the last cycle of multicycle,
 820   // so we use 3 for those cases
 821   InstrItinData<IIC_VMOVQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 822                                InstrStage<2, [A8_NLSPipe]>], [3, 1]>,
 823   //
 824   // Integer to Single-precision Move
 825   InstrItinData<IIC_VMOVIS ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 826                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 827   //
 828   // Integer to Double-precision Move
 829   InstrItinData<IIC_VMOVID ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 830                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 831   //
 832   // Single-precision to Integer Move
 833   InstrItinData<IIC_VMOVSI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 834                                InstrStage<1, [A8_NLSPipe]>], [20, 1]>,
 835   //
 836   // Double-precision to Integer Move
 837   InstrItinData<IIC_VMOVDI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 838                                InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>,
 839   //
 840   // Integer to Lane Move
 841   InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 842                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 843   //
 844   // Vector narrow move
 845   InstrItinData<IIC_VMOVN   , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 846                                InstrStage<1, [A8_NPipe]>], [2, 1]>,
 847   //
 848   // Double-register Permute
 849   InstrItinData<IIC_VPERMD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 850                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
 851   //
 852   // Quad-register Permute
 853   // Result written in N2, but that is relative to the last cycle of multicycle,
 854   // so we use 3 for those cases
 855   InstrItinData<IIC_VPERMQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 856                                InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>,
 857   //
 858   // Quad-register Permute (3 cycle issue)
 859   // Result written in N2, but that is relative to the last cycle of multicycle,
 860   // so we use 4 for those cases
 861   InstrItinData<IIC_VPERMQ3,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 862                                InstrStage<1, [A8_NLSPipe]>,
 863                                InstrStage<1, [A8_NPipe], 0>,
 864                                InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>,
 865   //
 866   // Double-register FP Multiple-Accumulate
 867   InstrItinData<IIC_VMACD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 868                                InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
 869   //
 870   // Quad-register FP Multiple-Accumulate
 871   // Result written in N9, but that is relative to the last cycle of multicycle,
 872   // so we use 10 for those cases
 873   InstrItinData<IIC_VMACQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 874                                InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
 875   //
 876   // Double-register Fused FP Multiple-Accumulate
 877   InstrItinData<IIC_VFMACD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 878                                InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
 879   //
 880   // Quad-register Fused FP Multiple-Accumulate
 881   // Result written in N9, but that is relative to the last cycle of multicycle,
 882   // so we use 10 for those cases
 883   InstrItinData<IIC_VFMACQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 884                                InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
 885   //
 886   // Double-register Reciprical Step
 887   InstrItinData<IIC_VRECSD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 888                                InstrStage<1, [A8_NPipe]>], [9, 2, 2]>,
 889   //
 890   // Quad-register Reciprical Step
 891   InstrItinData<IIC_VRECSQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 892                                InstrStage<2, [A8_NPipe]>], [10, 2, 2]>,
 893   //
 894   // Double-register Integer Count
 895   InstrItinData<IIC_VCNTiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 896                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 897   //
 898   // Quad-register Integer Count
 899   // Result written in N3, but that is relative to the last cycle of multicycle,
 900   // so we use 4 for those cases
 901   InstrItinData<IIC_VCNTiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 902                                InstrStage<2, [A8_NPipe]>], [4, 2, 2]>,
 903   //
 904   // Double-register Integer Unary
 905   InstrItinData<IIC_VUNAiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 906                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 907   //
 908   // Quad-register Integer Unary
 909   InstrItinData<IIC_VUNAiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 910                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 911   //
 912   // Double-register Integer Q-Unary
 913   InstrItinData<IIC_VQUNAiD,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 914                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 915   //
 916   // Quad-register Integer CountQ-Unary
 917   InstrItinData<IIC_VQUNAiQ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 918                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 919   //
 920   // Double-register Integer Binary
 921   InstrItinData<IIC_VBINiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 922                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 923   //
 924   // Quad-register Integer Binary
 925   InstrItinData<IIC_VBINiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 926                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 927   //
 928   // Double-register Integer Binary (4 cycle)
 929   InstrItinData<IIC_VBINi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 930                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 931   //
 932   // Quad-register Integer Binary (4 cycle)
 933   InstrItinData<IIC_VBINi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 934                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 935
 936   //
 937   // Double-register Integer Subtract
 938   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 939                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 940   //
 941   // Quad-register Integer Subtract
 942   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 943                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 944   //
 945   // Double-register Integer Subtract
 946   InstrItinData<IIC_VSUBi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 947                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 948   //
 949   // Quad-register Integer Subtract
 950   InstrItinData<IIC_VSUBi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 951                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 952   //
 953   // Double-register Integer Shift
 954   InstrItinData<IIC_VSHLiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 955                                InstrStage<1, [A8_NPipe]>], [3, 1, 1]>,
 956   //
 957   // Quad-register Integer Shift
 958   InstrItinData<IIC_VSHLiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 959                                InstrStage<2, [A8_NPipe]>], [4, 1, 1]>,
 960   //
 961   // Double-register Integer Shift (4 cycle)
 962   InstrItinData<IIC_VSHLi4D,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 963                                InstrStage<1, [A8_NPipe]>], [4, 1, 1]>,
 964   //
 965   // Quad-register Integer Shift (4 cycle)
 966   InstrItinData<IIC_VSHLi4Q,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 967                                InstrStage<2, [A8_NPipe]>], [5, 1, 1]>,
 968   //
 969   // Double-register Integer Pair Add Long
 970   InstrItinData<IIC_VPALiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 971                                InstrStage<1, [A8_NPipe]>], [6, 3, 1]>,
 972   //
 973   // Quad-register Integer Pair Add Long
 974   InstrItinData<IIC_VPALiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 975                                InstrStage<2, [A8_NPipe]>], [7, 3, 1]>,
 976   //
 977   // Double-register Absolute Difference and Accumulate
 978   InstrItinData<IIC_VABAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 979                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>,
 980   //
 981   // Quad-register Absolute Difference and Accumulate
 982   InstrItinData<IIC_VABAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 983                                InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>,
 984
 985   //
 986   // Double-register Integer Multiply (.8, .16)
 987   InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 988                                InstrStage<1, [A8_NPipe]>], [6, 2, 2]>,
 989   //
 990   // Double-register Integer Multiply (.32)
 991   InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 992                                InstrStage<2, [A8_NPipe]>], [7, 2, 1]>,
 993   //
 994   // Quad-register Integer Multiply (.8, .16)
 995   InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 996                                InstrStage<2, [A8_NPipe]>], [7, 2, 2]>,
 997   //
 998   // Quad-register Integer Multiply (.32)
 999   InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1000                                InstrStage<1, [A8_NPipe]>,
1001                                InstrStage<2, [A8_NLSPipe], 0>,
1002                                InstrStage<3, [A8_NPipe]>], [9, 2, 1]>,
1003   //
1004   // Double-register Integer Multiply-Accumulate (.8, .16)
1005   InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1006                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>,
1007   //
1008   // Double-register Integer Multiply-Accumulate (.32)
1009   InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1010                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>,
1011   //
1012   // Quad-register Integer Multiply-Accumulate (.8, .16)
1013   InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1014                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>,
1015   //
1016   // Quad-register Integer Multiply-Accumulate (.32)
1017   InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1018                                InstrStage<1, [A8_NPipe]>,
1019                                InstrStage<2, [A8_NLSPipe], 0>,
1020                                InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>,
1021   //
1022   // Double-register VEXT
1023   InstrItinData<IIC_VEXTD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1024                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
1025   //
1026   // Quad-register VEXT
1027   InstrItinData<IIC_VEXTQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1028                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
1029   //
1030   // VTB
1031   InstrItinData<IIC_VTB1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1032                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>,
1033   InstrItinData<IIC_VTB2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1034                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>,
1035   InstrItinData<IIC_VTB3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1036                                InstrStage<1, [A8_NLSPipe]>,
1037                                InstrStage<1, [A8_NPipe], 0>,
1038                                InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>,
1039   InstrItinData<IIC_VTB4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1040                                InstrStage<1, [A8_NLSPipe]>,
1041                                InstrStage<1, [A8_NPipe], 0>,
1042                                InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>,
1043   //
1044   // VTBX
1045   InstrItinData<IIC_VTBX1,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1046                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>,
1047   InstrItinData<IIC_VTBX2,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1048                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>,
1049   InstrItinData<IIC_VTBX3,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1050                                InstrStage<1, [A8_NLSPipe]>,
1051                                InstrStage<1, [A8_NPipe], 0>,
1052                                InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>,
1053   InstrItinData<IIC_VTBX4,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1054                                InstrStage<1, [A8_NLSPipe]>,
1055                                InstrStage<1, [A8_NPipe], 0>,
1056                             InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>
1057 ]>;