lib/Target/ARM/ARMScheduleA8.td

   1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //
  15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
  16 //
  17 // Dual issue pipeline represented by FU_Pipe0 | FU_Pipe1
  18 //
  19 def CortexA8Itineraries : ProcessorItineraries<[
  20
  21   // Two fully-pipelined integer ALU pipelines
  22   //
  23   // No operand cycles
  24   InstrItinData<IIC_iALUx    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
  25   //
  26   // Binary Instructions that produce a result
  27   InstrItinData<IIC_iALUi    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
  28   InstrItinData<IIC_iALUr    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 2]>,
  29   InstrItinData<IIC_iALUsi   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1]>,
  30   InstrItinData<IIC_iALUsr   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1, 1]>,
  31   //
  32   // Unary Instructions that produce a result
  33   InstrItinData<IIC_iUNAr    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
  34   InstrItinData<IIC_iUNAsi   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
  35   InstrItinData<IIC_iUNAsr   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
  36   //
  37   // Compare instructions
  38   InstrItinData<IIC_iCMPi    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
  39   InstrItinData<IIC_iCMPr    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
  40   InstrItinData<IIC_iCMPsi   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
  41   InstrItinData<IIC_iCMPsr   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
  42   //
  43   // Move instructions, unconditional
  44   InstrItinData<IIC_iMOVi    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1]>,
  45   InstrItinData<IIC_iMOVr    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
  46   InstrItinData<IIC_iMOVsi   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
  47   InstrItinData<IIC_iMOVsr   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1, 1]>,
  48   //
  49   // Move instructions, conditional
  50   InstrItinData<IIC_iCMOVi   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
  51   InstrItinData<IIC_iCMOVr   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
  52   InstrItinData<IIC_iCMOVsi  , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
  53   InstrItinData<IIC_iCMOVsr  , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
  54
  55   // Integer multiply pipeline
  56   // Result written in E5, but that is relative to the last cycle of multicycle,
  57   // so we use 6 for those cases
  58   //
  59   InstrItinData<IIC_iMUL16   , [InstrStage<1, [FU_Pipe0]>], [5, 1, 1]>,
  60   InstrItinData<IIC_iMAC16   , [InstrStage<1, [FU_Pipe1], 0>,
  61                                 InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
  62   InstrItinData<IIC_iMUL32   , [InstrStage<1, [FU_Pipe1], 0>,
  63                                 InstrStage<2, [FU_Pipe0]>], [6, 1, 1]>,
  64   InstrItinData<IIC_iMAC32   , [InstrStage<1, [FU_Pipe1], 0>,
  65                                 InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
  66   InstrItinData<IIC_iMUL64   , [InstrStage<2, [FU_Pipe1], 0>,
  67                                 InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
  68   InstrItinData<IIC_iMAC64   , [InstrStage<2, [FU_Pipe1], 0>,
  69                                 InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
  70
  71   // Integer load pipeline
  72   //
  73   // loads have an extra cycle of latency, but are fully pipelined
  74   // use FU_Issue to enforce the 1 load/store per cycle limit
  75   //
  76   // Immediate offset
  77   InstrItinData<IIC_iLoadi   , [InstrStage<1, [FU_Issue], 0>,
  78                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
  79                                 InstrStage<1, [FU_LdSt0]>], [3, 1]>,
  80   //
  81   // Register offset
  82   InstrItinData<IIC_iLoadr   , [InstrStage<1, [FU_Issue], 0>,
  83                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
  84                                 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
  85   //
  86   // Scaled register offset, issues over 2 cycles
  87   InstrItinData<IIC_iLoadsi  , [InstrStage<2, [FU_Issue], 0>,
  88                                 InstrStage<1, [FU_Pipe0], 0>,
  89                                 InstrStage<1, [FU_Pipe1]>,
  90                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
  91                                 InstrStage<1, [FU_LdSt0]>], [4, 1, 1]>,
  92   //
  93   // Immediate offset with update
  94   InstrItinData<IIC_iLoadiu  , [InstrStage<1, [FU_Issue], 0>,
  95                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
  96                                 InstrStage<1, [FU_LdSt0]>], [3, 2, 1]>,
  97   //
  98   // Register offset with update
  99   InstrItinData<IIC_iLoadru  , [InstrStage<1, [FU_Issue], 0>,
 100                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 101                                 InstrStage<1, [FU_LdSt0]>], [3, 2, 1, 1]>,
 102   //
 103   // Scaled register offset with update, issues over 2 cycles
 104   InstrItinData<IIC_iLoadsiu , [InstrStage<2, [FU_Issue], 0>,
 105                                 InstrStage<1, [FU_Pipe0], 0>,
 106                                 InstrStage<1, [FU_Pipe1]>,
 107                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 108                                 InstrStage<1, [FU_LdSt0]>], [4, 3, 1, 1]>,
 109   //
 110   // Load multiple
 111   InstrItinData<IIC_iLoadm   , [InstrStage<2, [FU_Issue], 0>,
 112                                 InstrStage<2, [FU_Pipe0], 0>,
 113                                 InstrStage<2, [FU_Pipe1]>,
 114                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 115                                 InstrStage<1, [FU_LdSt0]>]>,
 116
 117   // Integer store pipeline
 118   //
 119   // use FU_Issue to enforce the 1 load/store per cycle limit
 120   //
 121   // Immediate offset
 122   InstrItinData<IIC_iStorei  , [InstrStage<1, [FU_Issue], 0>,
 123                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 124                                 InstrStage<1, [FU_LdSt0]>], [3, 1]>,
 125   //
 126   // Register offset
 127   InstrItinData<IIC_iStorer  , [InstrStage<1, [FU_Issue], 0>,
 128                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 129                                 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
 130   //
 131   // Scaled register offset, issues over 2 cycles
 132   InstrItinData<IIC_iStoresi , [InstrStage<2, [FU_Issue], 0>,
 133                                 InstrStage<1, [FU_Pipe0], 0>,
 134                                 InstrStage<1, [FU_Pipe1]>,
 135                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 136                                 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
 137   //
 138   // Immediate offset with update
 139   InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Issue], 0>,
 140                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 141                                 InstrStage<1, [FU_LdSt0]>], [2, 3, 1]>,
 142   //
 143   // Register offset with update
 144   InstrItinData<IIC_iStoreru  , [InstrStage<1, [FU_Issue], 0>,
 145                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 146                                 InstrStage<1, [FU_LdSt0]>], [2, 3, 1, 1]>,
 147   //
 148   // Scaled register offset with update, issues over 2 cycles
 149   InstrItinData<IIC_iStoresiu, [InstrStage<2, [FU_Issue], 0>,
 150                                 InstrStage<1, [FU_Pipe0], 0>,
 151                                 InstrStage<1, [FU_Pipe1]>,
 152                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 153                                 InstrStage<1, [FU_LdSt0]>], [3, 3, 1, 1]>,
 154   //
 155   // Store multiple
 156   InstrItinData<IIC_iStorem  , [InstrStage<2, [FU_Issue], 0>,
 157                                 InstrStage<2, [FU_Pipe0], 0>,
 158                                 InstrStage<2, [FU_Pipe1]>,
 159                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 160                                 InstrStage<1, [FU_LdSt0]>]>,
 161
 162   // Branch
 163   //
 164   // no delay slots, so the latency of a branch is unimportant
 165   InstrItinData<IIC_Br      , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
 166
 167   // VFP
 168   // Issue through integer pipeline, and execute in NEON unit. We assume
 169   // RunFast mode so that NFP pipeline is used for single-precision when
 170   // possible.
 171   //
 172   // FP Special Register to Integer Register File Move
 173   InstrItinData<IIC_fpSTAT , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 174                               InstrStage<1, [FU_NLSPipe]>]>,
 175   //
 176   // Single-precision FP Unary
 177   InstrItinData<IIC_fpUNA32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 178                                InstrStage<1, [FU_NPipe]>], [7, 1]>,
 179   //
 180   // Double-precision FP Unary
 181   InstrItinData<IIC_fpUNA64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 182                                InstrStage<4, [FU_NPipe], 0>,
 183                                InstrStage<4, [FU_NLSPipe]>], [4, 1]>,
 184   //
 185   // Single-precision FP Compare
 186   InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 187                                InstrStage<1, [FU_NPipe]>], [1, 1]>,
 188   //
 189   // Double-precision FP Compare
 190   InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 191                                InstrStage<4, [FU_NPipe], 0>,
 192                                InstrStage<4, [FU_NLSPipe]>], [4, 1]>,
 193   //
 194   // Single to Double FP Convert
 195   InstrItinData<IIC_fpCVTSD , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 196                                InstrStage<7, [FU_NPipe], 0>,
 197                                InstrStage<7, [FU_NLSPipe]>], [7, 1]>,
 198   //
 199   // Double to Single FP Convert
 200   InstrItinData<IIC_fpCVTDS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 201                                InstrStage<5, [FU_NPipe], 0>,
 202                                InstrStage<5, [FU_NLSPipe]>], [5, 1]>,
 203   //
 204   // Single-Precision FP to Integer Convert
 205   InstrItinData<IIC_fpCVTSI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 206                                InstrStage<1, [FU_NPipe]>], [7, 1]>,
 207   //
 208   // Double-Precision FP to Integer Convert
 209   InstrItinData<IIC_fpCVTDI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 210                                InstrStage<8, [FU_NPipe], 0>,
 211                                InstrStage<8, [FU_NLSPipe]>], [8, 1]>,
 212   //
 213   // Integer to Single-Precision FP Convert
 214   InstrItinData<IIC_fpCVTIS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 215                                InstrStage<1, [FU_NPipe]>], [7, 1]>,
 216   //
 217   // Integer to Double-Precision FP Convert
 218   InstrItinData<IIC_fpCVTID , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 219                                InstrStage<8, [FU_NPipe], 0>,
 220                                InstrStage<8, [FU_NLSPipe]>], [8, 1]>,
 221   //
 222   // Single-precision FP ALU
 223   InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 224                                InstrStage<1, [FU_NPipe]>], [7, 1, 1]>,
 225   //
 226   // Double-precision FP ALU
 227   InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 228                                InstrStage<9, [FU_NPipe], 0>,
 229                                InstrStage<9, [FU_NLSPipe]>], [9, 1, 1]>,
 230   //
 231   // Single-precision FP Multiply
 232   InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 233                                InstrStage<1, [FU_NPipe]>], [7, 1, 1]>,
 234   //
 235   // Double-precision FP Multiply
 236   InstrItinData<IIC_fpMUL64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 237                                InstrStage<11, [FU_NPipe], 0>,
 238                                InstrStage<11, [FU_NLSPipe]>], [11, 1, 1]>,
 239   //
 240   // Single-precision FP MAC
 241   InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 242                                InstrStage<1, [FU_NPipe]>], [7, 2, 1, 1]>,
 243   //
 244   // Double-precision FP MAC
 245   InstrItinData<IIC_fpMAC64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 246                                InstrStage<19, [FU_NPipe], 0>,
 247                                InstrStage<19, [FU_NLSPipe]>], [19, 2, 1, 1]>,
 248   //
 249   // Single-precision FP DIV
 250   InstrItinData<IIC_fpDIV32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 251                                InstrStage<20, [FU_NPipe], 0>,
 252                                InstrStage<20, [FU_NLSPipe]>], [20, 1, 1]>,
 253   //
 254   // Double-precision FP DIV
 255   InstrItinData<IIC_fpDIV64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 256                                InstrStage<29, [FU_NPipe], 0>,
 257                                InstrStage<29, [FU_NLSPipe]>], [29, 1, 1]>,
 258   //
 259   // Single-precision FP SQRT
 260   InstrItinData<IIC_fpSQRT32, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 261                                InstrStage<19, [FU_NPipe], 0>,
 262                                InstrStage<19, [FU_NLSPipe]>], [19, 1]>,
 263   //
 264   // Double-precision FP SQRT
 265   InstrItinData<IIC_fpSQRT64, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 266                                InstrStage<29, [FU_NPipe], 0>,
 267                                InstrStage<29, [FU_NLSPipe]>], [29, 1]>,
 268   //
 269   // Single-precision FP Load
 270   // use FU_Issue to enforce the 1 load/store per cycle limit
 271   InstrItinData<IIC_fpLoad32, [InstrStage<1, [FU_Issue], 0>,
 272                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 273                                InstrStage<1, [FU_LdSt0], 0>,
 274                                InstrStage<1, [FU_NLSPipe]>]>,
 275   //
 276   // Double-precision FP Load
 277   // use FU_Issue to enforce the 1 load/store per cycle limit
 278   InstrItinData<IIC_fpLoad64, [InstrStage<2, [FU_Issue], 0>,
 279                                InstrStage<1, [FU_Pipe0], 0>,
 280                                InstrStage<1, [FU_Pipe1]>,
 281                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 282                                InstrStage<1, [FU_LdSt0], 0>,
 283                                InstrStage<1, [FU_NLSPipe]>]>,
 284   //
 285   // FP Load Multiple
 286   // use FU_Issue to enforce the 1 load/store per cycle limit
 287   InstrItinData<IIC_fpLoadm,  [InstrStage<3, [FU_Issue], 0>,
 288                                InstrStage<2, [FU_Pipe0], 0>,
 289                                InstrStage<2, [FU_Pipe1]>,
 290                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 291                                InstrStage<1, [FU_LdSt0], 0>,
 292                                InstrStage<1, [FU_NLSPipe]>]>,
 293   //
 294   // Single-precision FP Store
 295   // use FU_Issue to enforce the 1 load/store per cycle limit
 296   InstrItinData<IIC_fpStore32,[InstrStage<1, [FU_Issue], 0>,
 297                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 298                                InstrStage<1, [FU_LdSt0], 0>,
 299                                InstrStage<1, [FU_NLSPipe]>]>,
 300   //
 301   // Double-precision FP Store
 302   // use FU_Issue to enforce the 1 load/store per cycle limit
 303   InstrItinData<IIC_fpStore64,[InstrStage<2, [FU_Issue], 0>,
 304                                InstrStage<1, [FU_Pipe0], 0>,
 305                                InstrStage<1, [FU_Pipe1]>,
 306                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 307                                InstrStage<1, [FU_LdSt0], 0>,
 308                                InstrStage<1, [FU_NLSPipe]>]>,
 309   //
 310   // FP Store Multiple
 311   // use FU_Issue to enforce the 1 load/store per cycle limit
 312   InstrItinData<IIC_fpStorem, [InstrStage<3, [FU_Issue], 0>,
 313                                InstrStage<2, [FU_Pipe0], 0>,
 314                                InstrStage<2, [FU_Pipe1]>,
 315                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 316                                InstrStage<1, [FU_LdSt0], 0>,
 317                                InstrStage<1, [FU_NLSPipe]>]>,
 318
 319   // NEON
 320   // Issue through integer pipeline, and execute in NEON unit.
 321   //
 322   // VLD1
 323   // FIXME: We don't model this instruction properly
 324   InstrItinData<IIC_VLD1,     [InstrStage<1, [FU_Issue], 0>,
 325                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 326                                InstrStage<1, [FU_LdSt0], 0>,
 327                                InstrStage<1, [FU_NLSPipe]>]>,
 328   //
 329   // VLD2
 330   // FIXME: We don't model this instruction properly
 331   InstrItinData<IIC_VLD2,     [InstrStage<1, [FU_Issue], 0>,
 332                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 333                                InstrStage<1, [FU_LdSt0], 0>,
 334                                InstrStage<1, [FU_NLSPipe]>], [2, 2, 1]>,
 335   //
 336   // VLD3
 337   // FIXME: We don't model this instruction properly
 338   InstrItinData<IIC_VLD3,     [InstrStage<1, [FU_Issue], 0>,
 339                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 340                                InstrStage<1, [FU_LdSt0], 0>,
 341                                InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 1]>,
 342   //
 343   // VLD4
 344   // FIXME: We don't model this instruction properly
 345   InstrItinData<IIC_VLD4,     [InstrStage<1, [FU_Issue], 0>,
 346                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 347                                InstrStage<1, [FU_LdSt0], 0>,
 348                                InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 2, 1]>,
 349   //
 350   // VST
 351   // FIXME: We don't model this instruction properly
 352   InstrItinData<IIC_VST,      [InstrStage<1, [FU_Issue], 0>,
 353                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 354                                InstrStage<1, [FU_LdSt0], 0>,
 355                                InstrStage<1, [FU_NLSPipe]>]>,
 356   //
 357   // Double-register FP Unary
 358   InstrItinData<IIC_VUNAD,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 359                                InstrStage<1, [FU_NPipe]>], [5, 2]>,
 360   //
 361   // Quad-register FP Unary
 362   // Result written in N5, but that is relative to the last cycle of multicycle,
 363   // so we use 6 for those cases
 364   InstrItinData<IIC_VUNAQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 365                                InstrStage<2, [FU_NPipe]>], [6, 2]>,
 366   //
 367   // Double-register FP Binary
 368   InstrItinData<IIC_VBIND,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 369                                InstrStage<1, [FU_NPipe]>], [5, 2, 2]>,
 370   //
 371   // Quad-register FP Binary
 372   // Result written in N5, but that is relative to the last cycle of multicycle,
 373   // so we use 6 for those cases
 374   InstrItinData<IIC_VBINQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 375                                InstrStage<2, [FU_NPipe]>], [6, 2, 2]>,
 376   //
 377   // Move Immediate
 378   InstrItinData<IIC_VMOVImm,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 379                                InstrStage<1, [FU_NPipe]>], [3]>,
 380   //
 381   // Double-register Permute Move
 382   InstrItinData<IIC_VMOVD,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 383                                InstrStage<1, [FU_NLSPipe]>], [2, 1]>,
 384   //
 385   // Quad-register Permute Move
 386   // Result written in N2, but that is relative to the last cycle of multicycle,
 387   // so we use 3 for those cases
 388   InstrItinData<IIC_VMOVQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 389                                InstrStage<2, [FU_NLSPipe]>], [3, 1]>,
 390   //
 391   // Integer to Single-precision Move
 392   InstrItinData<IIC_VMOVIS ,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 393                                InstrStage<1, [FU_NLSPipe]>], [2, 1]>,
 394   //
 395   // Integer to Double-precision Move
 396   InstrItinData<IIC_VMOVID ,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 397                                InstrStage<1, [FU_NLSPipe]>], [2, 1, 1]>,
 398   //
 399   // Single-precision to Integer Move
 400   InstrItinData<IIC_VMOVSI ,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 401                                InstrStage<1, [FU_NLSPipe]>], [20, 1]>,
 402   //
 403   // Double-precision to Integer Move
 404   InstrItinData<IIC_VMOVDI ,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 405                                InstrStage<1, [FU_NLSPipe]>], [20, 20, 1]>,
 406   //
 407   // Integer to Lane Move
 408   InstrItinData<IIC_VMOVISL , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 409                                InstrStage<2, [FU_NLSPipe]>], [3, 1, 1]>,
 410   //
 411   // Double-register Permute
 412   InstrItinData<IIC_VPERMD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 413                                InstrStage<1, [FU_NLSPipe]>], [2, 2, 1, 1]>,
 414   //
 415   // Quad-register Permute
 416   // Result written in N2, but that is relative to the last cycle of multicycle,
 417   // so we use 3 for those cases
 418   InstrItinData<IIC_VPERMQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 419                                InstrStage<2, [FU_NLSPipe]>], [3, 3, 1, 1]>,
 420   //
 421   // Quad-register Permute (3 cycle issue)
 422   // Result written in N2, but that is relative to the last cycle of multicycle,
 423   // so we use 4 for those cases
 424   InstrItinData<IIC_VPERMQ3,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 425                                InstrStage<1, [FU_NLSPipe]>,
 426                                InstrStage<1, [FU_NPipe], 0>,
 427                                InstrStage<2, [FU_NLSPipe]>], [4, 4, 1, 1]>,
 428   //
 429   // Double-register FP Multiple-Accumulate
 430   InstrItinData<IIC_VMACD,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 431                                InstrStage<1, [FU_NPipe]>], [9, 3, 2, 2]>,
 432   //
 433   // Quad-register FP Multiple-Accumulate
 434   // Result written in N9, but that is relative to the last cycle of multicycle,
 435   // so we use 10 for those cases
 436   InstrItinData<IIC_VMACQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 437                                InstrStage<2, [FU_NPipe]>], [10, 3, 2, 2]>,
 438   //
 439   // Double-register Reciprical Step
 440   InstrItinData<IIC_VRECSD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 441                                InstrStage<1, [FU_NPipe]>], [9, 2, 2]>,
 442   //
 443   // Quad-register Reciprical Step
 444   InstrItinData<IIC_VRECSQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 445                                InstrStage<2, [FU_NPipe]>], [10, 2, 2]>,
 446   //
 447   // Double-register Integer Count
 448   InstrItinData<IIC_VCNTiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 449                                InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
 450   //
 451   // Quad-register Integer Count
 452   // Result written in N3, but that is relative to the last cycle of multicycle,
 453   // so we use 4 for those cases
 454   InstrItinData<IIC_VCNTiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 455                                InstrStage<2, [FU_NPipe]>], [4, 2, 2]>,
 456   //
 457   // Double-register Integer Unary
 458   InstrItinData<IIC_VUNAiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 459                                InstrStage<1, [FU_NPipe]>], [4, 2]>,
 460   //
 461   // Quad-register Integer Unary
 462   InstrItinData<IIC_VUNAiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 463                                InstrStage<1, [FU_NPipe]>], [4, 2]>,
 464   //
 465   // Double-register Integer Q-Unary
 466   InstrItinData<IIC_VQUNAiD,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 467                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 468   //
 469   // Quad-register Integer CountQ-Unary
 470   InstrItinData<IIC_VQUNAiQ,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 471                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 472   //
 473   // Double-register Integer Binary
 474   InstrItinData<IIC_VBINiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 475                                InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
 476   //
 477   // Quad-register Integer Binary
 478   InstrItinData<IIC_VBINiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 479                                InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
 480   //
 481   // Double-register Integer Binary (4 cycle)
 482   InstrItinData<IIC_VBINi4D,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 483                                InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
 484   //
 485   // Quad-register Integer Binary (4 cycle)
 486   InstrItinData<IIC_VBINi4Q,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 487                                InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
 488
 489   //
 490   // Double-register Integer Subtract
 491   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 492                                InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
 493   //
 494   // Quad-register Integer Subtract
 495   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 496                                InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
 497   //
 498   // Double-register Integer Subtract
 499   InstrItinData<IIC_VSUBi4D,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 500                                InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
 501   //
 502   // Quad-register Integer Subtract
 503   InstrItinData<IIC_VSUBi4Q,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 504                                InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
 505   //
 506   // Double-register Integer Shift
 507   InstrItinData<IIC_VSHLiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 508                                InstrStage<1, [FU_NPipe]>], [3, 1, 1]>,
 509   //
 510   // Quad-register Integer Shift
 511   InstrItinData<IIC_VSHLiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 512                                InstrStage<2, [FU_NPipe]>], [4, 1, 1]>,
 513   //
 514   // Double-register Integer Shift (4 cycle)
 515   InstrItinData<IIC_VSHLi4D,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 516                                InstrStage<1, [FU_NPipe]>], [4, 1, 1]>,
 517   //
 518   // Quad-register Integer Shift (4 cycle)
 519   InstrItinData<IIC_VSHLi4Q,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 520                                InstrStage<2, [FU_NPipe]>], [5, 1, 1]>,
 521   //
 522   // Double-register Integer Pair Add Long
 523   InstrItinData<IIC_VPALiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 524                                InstrStage<1, [FU_NPipe]>], [6, 3, 1]>,
 525   //
 526   // Quad-register Integer Pair Add Long
 527   InstrItinData<IIC_VPALiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 528                                InstrStage<2, [FU_NPipe]>], [7, 3, 1]>,
 529   //
 530   // Double-register Absolute Difference and Accumulate
 531   InstrItinData<IIC_VABAD,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 532                                InstrStage<1, [FU_NPipe]>], [6, 3, 2, 1]>,
 533   //
 534   // Quad-register Absolute Difference and Accumulate
 535   InstrItinData<IIC_VABAQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 536                                InstrStage<2, [FU_NPipe]>], [6, 3, 2, 1]>,
 537
 538   //
 539   // Double-register Integer Multiply (.8, .16)
 540   InstrItinData<IIC_VMULi16D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 541                                InstrStage<1, [FU_NPipe]>], [6, 2, 2]>,
 542   //
 543   // Double-register Integer Multiply (.32)
 544   InstrItinData<IIC_VMULi32D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 545                                InstrStage<2, [FU_NPipe]>], [7, 2, 1]>,
 546   //
 547   // Quad-register Integer Multiply (.8, .16)
 548   InstrItinData<IIC_VMULi16Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 549                                InstrStage<2, [FU_NPipe]>], [7, 2, 2]>,
 550   //
 551   // Quad-register Integer Multiply (.32)
 552   InstrItinData<IIC_VMULi32Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 553                                InstrStage<1, [FU_NPipe]>,
 554                                InstrStage<2, [FU_NLSPipe], 0>,
 555                                InstrStage<3, [FU_NPipe]>], [9, 2, 1]>,
 556   //
 557   // Double-register Integer Multiply-Accumulate (.8, .16)
 558   InstrItinData<IIC_VMACi16D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 559                                InstrStage<1, [FU_NPipe]>], [6, 3, 2, 2]>,
 560   //
 561   // Double-register Integer Multiply-Accumulate (.32)
 562   InstrItinData<IIC_VMACi32D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 563                                InstrStage<2, [FU_NPipe]>], [7, 3, 2, 1]>,
 564   //
 565   // Quad-register Integer Multiply-Accumulate (.8, .16)
 566   InstrItinData<IIC_VMACi16Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 567                                InstrStage<2, [FU_NPipe]>], [7, 3, 2, 2]>,
 568   //
 569   // Quad-register Integer Multiply-Accumulate (.32)
 570   InstrItinData<IIC_VMACi32Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 571                                InstrStage<1, [FU_NPipe]>,
 572                                InstrStage<2, [FU_NLSPipe], 0>,
 573                                InstrStage<3, [FU_NPipe]>], [9, 3, 2, 1]>,
 574   //
 575   // Double-register VEXT
 576   InstrItinData<IIC_VEXTD,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 577                                InstrStage<1, [FU_NLSPipe]>], [2, 1, 1]>,
 578   //
 579   // Quad-register VEXT
 580   InstrItinData<IIC_VEXTQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 581                                InstrStage<2, [FU_NLSPipe]>], [3, 1, 1]>,
 582   //
 583   // VTB
 584   InstrItinData<IIC_VTB1,     [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 585                                InstrStage<2, [FU_NLSPipe]>], [3, 2, 1]>,
 586   InstrItinData<IIC_VTB2,     [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 587                                InstrStage<2, [FU_NLSPipe]>], [3, 2, 2, 1]>,
 588   InstrItinData<IIC_VTB3,     [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 589                                InstrStage<1, [FU_NLSPipe]>,
 590                                InstrStage<1, [FU_NPipe], 0>,
 591                                InstrStage<2, [FU_NLSPipe]>], [4, 2, 2, 3, 1]>,
 592   InstrItinData<IIC_VTB4,     [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 593                                InstrStage<1, [FU_NLSPipe]>,
 594                                InstrStage<1, [FU_NPipe], 0>,
 595                                InstrStage<2, [FU_NLSPipe]>], [4, 2, 2, 3, 3, 1]>,
 596   //
 597   // VTBX
 598   InstrItinData<IIC_VTBX1,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 599                                InstrStage<2, [FU_NLSPipe]>], [3, 1, 2, 1]>,
 600   InstrItinData<IIC_VTBX2,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 601                                InstrStage<2, [FU_NLSPipe]>], [3, 1, 2, 2, 1]>,
 602   InstrItinData<IIC_VTBX3,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 603                                InstrStage<1, [FU_NLSPipe]>,
 604                                InstrStage<1, [FU_NPipe], 0>,
 605                                InstrStage<2, [FU_NLSPipe]>], [4, 1, 2, 2, 3, 1]>,
 606   InstrItinData<IIC_VTBX4,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 607                                InstrStage<1, [FU_NLSPipe]>,
 608                                InstrStage<1, [FU_NPipe], 0>,
 609                                InstrStage<2, [FU_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>
 610 ]>;