lib/Target/ARM/ARMScheduleA8.td

   1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //
  15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
  16 // Functional Units.
  17 def A8_Issue   : FuncUnit; // issue
  18 def A8_Pipe0   : FuncUnit; // pipeline 0
  19 def A8_Pipe1   : FuncUnit; // pipeline 1
  20 def A8_LdSt0   : FuncUnit; // pipeline 0 load/store
  21 def A8_LdSt1   : FuncUnit; // pipeline 1 load/store
  22 def A8_NPipe   : FuncUnit; // NEON ALU/MUL pipe
  23 def A8_NLSPipe : FuncUnit; // NEON LS pipe
  24 //
  25 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
  26 //
  27 def CortexA8Itineraries : ProcessorItineraries<
  28   [A8_Issue, A8_Pipe0, A8_Pipe1, A8_LdSt0, A8_LdSt1, A8_NPipe, A8_NLSPipe],
  29   [], [
  30   // Two fully-pipelined integer ALU pipelines
  31   //
  32   // No operand cycles
  33   InstrItinData<IIC_iALUx    , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
  34   //
  35   // Binary Instructions that produce a result
  36   InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  37   InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  38   InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  39   InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
  40   InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  41   //
  42   // Bitwise Instructions that produce a result
  43   InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  44   InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  45   InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  46   InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  47   //
  48   // Unary Instructions that produce a result
  49   InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  50   InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  51   //
  52   // Zero and sign extension instructions
  53   InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  54   InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  55   InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>,
  56   //
  57   // Compare instructions
  58   InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  59   InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  60   InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  61   InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  62   //
  63   // Test instructions
  64   InstrItinData<IIC_iTSTi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  65   InstrItinData<IIC_iTSTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  66   InstrItinData<IIC_iTSTsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  67   InstrItinData<IIC_iTSTsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  68   //
  69   // Move instructions, unconditional
  70   InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  71   InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  72   InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  73   InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  74   InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  75                              InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  76   //
  77   // Move instructions, conditional
  78   InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  79   InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  80   InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  81   InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  82   //
  83   // MVN instructions
  84   InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  85   InstrItinData<IIC_iMVNr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  86   InstrItinData<IIC_iMVNsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  87   InstrItinData<IIC_iMVNsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  88
  89   // Integer multiply pipeline
  90   // Result written in E5, but that is relative to the last cycle of multicycle,
  91   // so we use 6 for those cases
  92   //
  93   InstrItinData<IIC_iMUL16   , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>,
  94   InstrItinData<IIC_iMAC16   , [InstrStage<1, [A8_Pipe1], 0>,
  95                                 InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
  96   InstrItinData<IIC_iMUL32   , [InstrStage<1, [A8_Pipe1], 0>,
  97                                 InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>,
  98   InstrItinData<IIC_iMAC32   , [InstrStage<1, [A8_Pipe1], 0>,
  99                                 InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
 100   InstrItinData<IIC_iMUL64   , [InstrStage<2, [A8_Pipe1], 0>,
 101                                 InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
 102   InstrItinData<IIC_iMAC64   , [InstrStage<2, [A8_Pipe1], 0>,
 103                                 InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
 104
 105   // Integer load pipeline
 106   //
 107   // loads have an extra cycle of latency, but are fully pipelined
 108   // use A8_Issue to enforce the 1 load/store per cycle limit
 109   //
 110   // Immediate offset
 111   InstrItinData<IIC_iLoad_i   , [InstrStage<1, [A8_Issue], 0>,
 112                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 113                                  InstrStage<1, [A8_LdSt0]>], [3, 1]>,
 114   InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Issue], 0>,
 115                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 116                                  InstrStage<1, [A8_LdSt0]>], [3, 1]>,
 117   InstrItinData<IIC_iLoad_d_i,  [InstrStage<1, [A8_Issue], 0>,
 118                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 119                                  InstrStage<1, [A8_LdSt0]>], [3, 1]>,
 120   //
 121   // Register offset
 122   InstrItinData<IIC_iLoad_r   , [InstrStage<1, [A8_Issue], 0>,
 123                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 124                                  InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
 125   InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Issue], 0>,
 126                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 127                                  InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
 128   InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Issue], 0>,
 129                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 130                                  InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
 131   //
 132   // Scaled register offset, issues over 2 cycles
 133   InstrItinData<IIC_iLoad_si  , [InstrStage<2, [A8_Issue], 0>,
 134                                  InstrStage<1, [A8_Pipe0], 0>,
 135                                  InstrStage<1, [A8_Pipe1]>,
 136                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 137                                  InstrStage<1, [A8_LdSt0]>], [4, 1, 1]>,
 138   InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Issue], 0>,
 139                                  InstrStage<1, [A8_Pipe0], 0>,
 140                                  InstrStage<1, [A8_Pipe1]>,
 141                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 142                                  InstrStage<1, [A8_LdSt0]>], [4, 1, 1]>,
 143   //
 144   // Immediate offset with update
 145   InstrItinData<IIC_iLoad_iu  , [InstrStage<1, [A8_Issue], 0>,
 146                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 147                                  InstrStage<1, [A8_LdSt0]>], [3, 2, 1]>,
 148   InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Issue], 0>,
 149                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 150                                  InstrStage<1, [A8_LdSt0]>], [3, 2, 1]>,
 151   //
 152   // Register offset with update
 153   InstrItinData<IIC_iLoad_ru  , [InstrStage<1, [A8_Issue], 0>,
 154                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 155                                  InstrStage<1, [A8_LdSt0]>], [3, 2, 1, 1]>,
 156   InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Issue], 0>,
 157                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 158                                  InstrStage<1, [A8_LdSt0]>], [3, 2, 1, 1]>,
 159   InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Issue], 0>,
 160                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 161                                  InstrStage<1, [A8_LdSt0]>], [3, 2, 1, 1]>,
 162   //
 163   // Scaled register offset with update, issues over 2 cycles
 164   InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Issue], 0>,
 165                                  InstrStage<1, [A8_Pipe0], 0>,
 166                                  InstrStage<1, [A8_Pipe1]>,
 167                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 168                                  InstrStage<1, [A8_LdSt0]>], [4, 3, 1, 1]>,
 169   InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Issue], 0>,
 170                                  InstrStage<1, [A8_Pipe0], 0>,
 171                                  InstrStage<1, [A8_Pipe1]>,
 172                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 173                                  InstrStage<1, [A8_LdSt0]>], [4, 3, 1, 1]>,
 174   //
 175   // Load multiple, def is the 5th operand.
 176   InstrItinData<IIC_iLoad_m  , [InstrStage<2, [A8_Issue], 0>,
 177                                 InstrStage<2, [A8_Pipe0], 0>,
 178                                 InstrStage<2, [A8_Pipe1]>,
 179                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 180                                 InstrStage<1, [A8_LdSt0]>], [1, 1, 1, 1, 3]>,
 181   //
 182   // Load multiple + update, defs are the 1st and 5th operands.
 183   InstrItinData<IIC_iLoad_mu , [InstrStage<2, [A8_Issue], 0>,
 184                                 InstrStage<2, [A8_Pipe0], 0>,
 185                                 InstrStage<2, [A8_Pipe1]>,
 186                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 187                                 InstrStage<1, [A8_LdSt0]>], [2, 1, 1, 1, 3]>,
 188   //
 189   // Load multiple plus branch
 190   InstrItinData<IIC_iLoad_mBr, [InstrStage<2, [A8_Issue], 0>,
 191                                 InstrStage<2, [A8_Pipe0], 0>,
 192                                 InstrStage<2, [A8_Pipe1]>,
 193                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 194                                 InstrStage<1, [A8_LdSt0]>,
 195                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
 196                                [1, 2, 1, 1, 3]>,
 197   //
 198   // Pop, def is the 3rd operand.
 199   InstrItinData<IIC_iPop  ,    [InstrStage<2, [A8_Issue], 0>,
 200                                 InstrStage<2, [A8_Pipe0], 0>,
 201                                 InstrStage<2, [A8_Pipe1]>,
 202                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 203                                 InstrStage<1, [A8_LdSt0]>], [1, 1, 3]>,
 204   //
 205   // Push, def is the 3th operand.
 206   InstrItinData<IIC_iPop_Br,   [InstrStage<2, [A8_Issue], 0>,
 207                                 InstrStage<2, [A8_Pipe0], 0>,
 208                                 InstrStage<2, [A8_Pipe1]>,
 209                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 210                                 InstrStage<1, [A8_LdSt0]>,
 211                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
 212                                [1, 1, 3]>,
 213
 214   //
 215   // iLoadi + iALUr for t2LDRpci_pic.
 216   InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Issue], 0>,
 217                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 218                                 InstrStage<1, [A8_LdSt0]>,
 219                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
 220
 221
 222   // Integer store pipeline
 223   //
 224   // use A8_Issue to enforce the 1 load/store per cycle limit
 225   //
 226   // Immediate offset
 227   InstrItinData<IIC_iStore_i  , [InstrStage<1, [A8_Issue], 0>,
 228                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 229                                  InstrStage<1, [A8_LdSt0]>], [3, 1]>,
 230   InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Issue], 0>,
 231                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 232                                  InstrStage<1, [A8_LdSt0]>], [3, 1]>,
 233   InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Issue], 0>,
 234                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 235                                  InstrStage<1, [A8_LdSt0]>], [3, 1]>,
 236   //
 237   // Register offset
 238   InstrItinData<IIC_iStore_r  , [InstrStage<1, [A8_Issue], 0>,
 239                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 240                                  InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
 241   InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Issue], 0>,
 242                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 243                                  InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
 244   InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Issue], 0>,
 245                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 246                                  InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
 247   //
 248   // Scaled register offset, issues over 2 cycles
 249   InstrItinData<IIC_iStore_si , [InstrStage<2, [A8_Issue], 0>,
 250                                  InstrStage<1, [A8_Pipe0], 0>,
 251                                  InstrStage<1, [A8_Pipe1]>,
 252                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 253                                  InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
 254   InstrItinData<IIC_iStore_bh_si,[InstrStage<2, [A8_Issue], 0>,
 255                                  InstrStage<1, [A8_Pipe0], 0>,
 256                                  InstrStage<1, [A8_Pipe1]>,
 257                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 258                                  InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
 259   //
 260   // Immediate offset with update
 261   InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Issue], 0>,
 262                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 263                                  InstrStage<1, [A8_LdSt0]>], [2, 3, 1]>,
 264   InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Issue], 0>,
 265                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 266                                  InstrStage<1, [A8_LdSt0]>], [2, 3, 1]>,
 267   //
 268   // Register offset with update
 269   InstrItinData<IIC_iStore_ru  , [InstrStage<1, [A8_Issue], 0>,
 270                                   InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 271                                   InstrStage<1, [A8_LdSt0]>], [2, 3, 1, 1]>,
 272   InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Issue], 0>,
 273                                   InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 274                                   InstrStage<1, [A8_LdSt0]>], [2, 3, 1, 1]>,
 275   InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Issue], 0>,
 276                                   InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 277                                   InstrStage<1, [A8_LdSt0]>], [2, 3, 1, 1]>,
 278   //
 279   // Scaled register offset with update, issues over 2 cycles
 280   InstrItinData<IIC_iStore_siu, [InstrStage<2, [A8_Issue], 0>,
 281                                  InstrStage<1, [A8_Pipe0], 0>,
 282                                  InstrStage<1, [A8_Pipe1]>,
 283                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 284                                  InstrStage<1, [A8_LdSt0]>], [3, 3, 1, 1]>,
 285   InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [A8_Issue], 0>,
 286                                  InstrStage<1, [A8_Pipe0], 0>,
 287                                  InstrStage<1, [A8_Pipe1]>,
 288                                  InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 289                                  InstrStage<1, [A8_LdSt0]>], [3, 3, 1, 1]>,
 290   //
 291   // Store multiple
 292   InstrItinData<IIC_iStore_m , [InstrStage<2, [A8_Issue], 0>,
 293                                 InstrStage<2, [A8_Pipe0], 0>,
 294                                 InstrStage<2, [A8_Pipe1]>,
 295                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 296                                 InstrStage<1, [A8_LdSt0]>]>,
 297   //
 298   // Store multiple + update
 299   InstrItinData<IIC_iStore_mu, [InstrStage<2, [A8_Issue], 0>,
 300                                 InstrStage<2, [A8_Pipe0], 0>,
 301                                 InstrStage<2, [A8_Pipe1]>,
 302                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 303                                 InstrStage<1, [A8_LdSt0]>], [2]>,
 304
 305   // Branch
 306   //
 307   // no delay slots, so the latency of a branch is unimportant
 308   InstrItinData<IIC_Br      , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
 309
 310   // VFP
 311   // Issue through integer pipeline, and execute in NEON unit. We assume
 312   // RunFast mode so that NFP pipeline is used for single-precision when
 313   // possible.
 314   //
 315   // FP Special Register to Integer Register File Move
 316   InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 317                               InstrStage<1, [A8_NLSPipe]>]>,
 318   //
 319   // Single-precision FP Unary
 320   InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 321                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 322   //
 323   // Double-precision FP Unary
 324   InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 325                                InstrStage<4, [A8_NPipe], 0>,
 326                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 327   //
 328   // Single-precision FP Compare
 329   InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 330                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 331   //
 332   // Double-precision FP Compare
 333   InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 334                                InstrStage<4, [A8_NPipe], 0>,
 335                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 336   //
 337   // Single to Double FP Convert
 338   InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 339                                InstrStage<7, [A8_NPipe], 0>,
 340                                InstrStage<7, [A8_NLSPipe]>], [7, 1]>,
 341   //
 342   // Double to Single FP Convert
 343   InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 344                                InstrStage<5, [A8_NPipe], 0>,
 345                                InstrStage<5, [A8_NLSPipe]>], [5, 1]>,
 346   //
 347   // Single-Precision FP to Integer Convert
 348   InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 349                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 350   //
 351   // Double-Precision FP to Integer Convert
 352   InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 353                                InstrStage<8, [A8_NPipe], 0>,
 354                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 355   //
 356   // Integer to Single-Precision FP Convert
 357   InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 358                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 359   //
 360   // Integer to Double-Precision FP Convert
 361   InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 362                                InstrStage<8, [A8_NPipe], 0>,
 363                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 364   //
 365   // Single-precision FP ALU
 366   InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 367                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 368   //
 369   // Double-precision FP ALU
 370   InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 371                                InstrStage<9, [A8_NPipe], 0>,
 372                                InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>,
 373   //
 374   // Single-precision FP Multiply
 375   InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 376                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 377   //
 378   // Double-precision FP Multiply
 379   InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 380                                InstrStage<11, [A8_NPipe], 0>,
 381                                InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>,
 382   //
 383   // Single-precision FP MAC
 384   InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 385                                InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
 386   //
 387   // Double-precision FP MAC
 388   InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 389                                InstrStage<19, [A8_NPipe], 0>,
 390                                InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
 391   //
 392   // Single-precision FP DIV
 393   InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 394                                InstrStage<20, [A8_NPipe], 0>,
 395                                InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>,
 396   //
 397   // Double-precision FP DIV
 398   InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 399                                InstrStage<29, [A8_NPipe], 0>,
 400                                InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>,
 401   //
 402   // Single-precision FP SQRT
 403   InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 404                                InstrStage<19, [A8_NPipe], 0>,
 405                                InstrStage<19, [A8_NLSPipe]>], [19, 1]>,
 406   //
 407   // Double-precision FP SQRT
 408   InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 409                                InstrStage<29, [A8_NPipe], 0>,
 410                                InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
 411   //
 412   // Single-precision FP Load
 413   // use A8_Issue to enforce the 1 load/store per cycle limit
 414   InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Issue], 0>,
 415                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 416                                InstrStage<1, [A8_LdSt0], 0>,
 417                                InstrStage<2, [A8_NLSPipe]>],
 418                               [2, 1]>,
 419   //
 420   // Double-precision FP Load
 421   // use A8_Issue to enforce the 1 load/store per cycle limit
 422   InstrItinData<IIC_fpLoad64, [InstrStage<2, [A8_Issue], 0>,
 423                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 424                                InstrStage<1, [A8_LdSt0], 0>,
 425                                InstrStage<2, [A8_NLSPipe]>],
 426                               [2, 1]>,
 427   //
 428   // FP Load Multiple
 429   // use A8_Issue to enforce the 1 load/store per cycle limit
 430   InstrItinData<IIC_fpLoad_m, [InstrStage<3, [A8_Issue], 0>,
 431                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 432                                InstrStage<1, [A8_LdSt0], 0>,
 433                                InstrStage<1, [A8_NLSPipe]>], [1, 1, 1, 2]>,
 434   //
 435   // FP Load Multiple + update
 436   InstrItinData<IIC_fpLoad_mu,[InstrStage<3, [A8_Issue], 0>,
 437                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 438                                InstrStage<1, [A8_LdSt0], 0>,
 439                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1, 1, 2]>,
 440   //
 441   // Single-precision FP Store
 442   // use A8_Issue to enforce the 1 load/store per cycle limit
 443   InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Issue], 0>,
 444                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 445                                InstrStage<1, [A8_LdSt0], 0>,
 446                                InstrStage<2, [A8_NLSPipe]>],
 447                               [1, 1]>,
 448   //
 449   // Double-precision FP Store
 450   // use A8_Issue to enforce the 1 load/store per cycle limit
 451   InstrItinData<IIC_fpStore64,[InstrStage<2, [A8_Issue], 0>,
 452                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 453                                InstrStage<1, [A8_LdSt0], 0>,
 454                                InstrStage<2, [A8_NLSPipe]>],
 455                               [1, 1]>,
 456   //
 457   // FP Store Multiple
 458   // use A8_Issue to enforce the 1 load/store per cycle limit
 459   InstrItinData<IIC_fpStore_m,[InstrStage<3, [A8_Issue], 0>,
 460                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 461                                InstrStage<1, [A8_LdSt0], 0>,
 462                                InstrStage<1, [A8_NLSPipe]>], [1, 1, 1, 1]>,
 463   //
 464   // FP Store Multiple + update
 465   InstrItinData<IIC_fpStore_mu,[InstrStage<3, [A8_Issue], 0>,
 466                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 467                                 InstrStage<1, [A8_LdSt0], 0>,
 468                                 InstrStage<1, [A8_NLSPipe]>], [2, 1, 1, 1, 1]>,
 469
 470   // NEON
 471   // Issue through integer pipeline, and execute in NEON unit.
 472   //
 473   // VLD1
 474   // FIXME: We don't model this instruction properly
 475   InstrItinData<IIC_VLD1,     [InstrStage<1, [A8_Issue], 0>,
 476                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 477                                InstrStage<1, [A8_LdSt0], 0>,
 478                                InstrStage<1, [A8_NLSPipe]>]>,
 479   //
 480   // VLD2
 481   // FIXME: We don't model this instruction properly
 482   InstrItinData<IIC_VLD2,     [InstrStage<1, [A8_Issue], 0>,
 483                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 484                                InstrStage<1, [A8_LdSt0], 0>,
 485                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 1]>,
 486   //
 487   // VLD3
 488   // FIXME: We don't model this instruction properly
 489   InstrItinData<IIC_VLD3,     [InstrStage<1, [A8_Issue], 0>,
 490                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 491                                InstrStage<1, [A8_LdSt0], 0>,
 492                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 2, 1]>,
 493   //
 494   // VLD4
 495   // FIXME: We don't model this instruction properly
 496   InstrItinData<IIC_VLD4,     [InstrStage<1, [A8_Issue], 0>,
 497                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 498                                InstrStage<1, [A8_LdSt0], 0>,
 499                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 2, 2, 1]>,
 500   //
 501   // VST
 502   // FIXME: We don't model this instruction properly
 503   InstrItinData<IIC_VST,      [InstrStage<1, [A8_Issue], 0>,
 504                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 505                                InstrStage<1, [A8_LdSt0], 0>,
 506                                InstrStage<1, [A8_NLSPipe]>]>,
 507   //
 508   // Double-register FP Unary
 509   InstrItinData<IIC_VUNAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 510                                InstrStage<1, [A8_NPipe]>], [5, 2]>,
 511   //
 512   // Quad-register FP Unary
 513   // Result written in N5, but that is relative to the last cycle of multicycle,
 514   // so we use 6 for those cases
 515   InstrItinData<IIC_VUNAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 516                                InstrStage<2, [A8_NPipe]>], [6, 2]>,
 517   //
 518   // Double-register FP Binary
 519   InstrItinData<IIC_VBIND,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 520                                InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
 521   //
 522   // Quad-register FP Binary
 523   // Result written in N5, but that is relative to the last cycle of multicycle,
 524   // so we use 6 for those cases
 525   InstrItinData<IIC_VBINQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 526                                InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
 527   //
 528   // Move
 529   InstrItinData<IIC_VMOV,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 530                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 531   //
 532   // Move Immediate
 533   InstrItinData<IIC_VMOVImm,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 534                                InstrStage<1, [A8_NPipe]>], [3]>,
 535   //
 536   // Double-register Permute Move
 537   InstrItinData<IIC_VMOVD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 538                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 539   //
 540   // Quad-register Permute Move
 541   // Result written in N2, but that is relative to the last cycle of multicycle,
 542   // so we use 3 for those cases
 543   InstrItinData<IIC_VMOVQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 544                                InstrStage<2, [A8_NLSPipe]>], [3, 1]>,
 545   //
 546   // Integer to Single-precision Move
 547   InstrItinData<IIC_VMOVIS ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 548                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 549   //
 550   // Integer to Double-precision Move
 551   InstrItinData<IIC_VMOVID ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 552                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 553   //
 554   // Single-precision to Integer Move
 555   InstrItinData<IIC_VMOVSI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 556                                InstrStage<1, [A8_NLSPipe]>], [20, 1]>,
 557   //
 558   // Double-precision to Integer Move
 559   InstrItinData<IIC_VMOVDI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 560                                InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>,
 561   //
 562   // Integer to Lane Move
 563   InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 564                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 565   //
 566   // Vector narrow move
 567   InstrItinData<IIC_VMOVN   , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 568                                InstrStage<1, [A8_NPipe]>], [2, 1]>,
 569   //
 570   // Double-register Permute
 571   InstrItinData<IIC_VPERMD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 572                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
 573   //
 574   // Quad-register Permute
 575   // Result written in N2, but that is relative to the last cycle of multicycle,
 576   // so we use 3 for those cases
 577   InstrItinData<IIC_VPERMQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 578                                InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>,
 579   //
 580   // Quad-register Permute (3 cycle issue)
 581   // Result written in N2, but that is relative to the last cycle of multicycle,
 582   // so we use 4 for those cases
 583   InstrItinData<IIC_VPERMQ3,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 584                                InstrStage<1, [A8_NLSPipe]>,
 585                                InstrStage<1, [A8_NPipe], 0>,
 586                                InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>,
 587   //
 588   // Double-register FP Multiple-Accumulate
 589   InstrItinData<IIC_VMACD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 590                                InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
 591   //
 592   // Quad-register FP Multiple-Accumulate
 593   // Result written in N9, but that is relative to the last cycle of multicycle,
 594   // so we use 10 for those cases
 595   InstrItinData<IIC_VMACQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 596                                InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
 597   //
 598   // Double-register Reciprical Step
 599   InstrItinData<IIC_VRECSD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 600                                InstrStage<1, [A8_NPipe]>], [9, 2, 2]>,
 601   //
 602   // Quad-register Reciprical Step
 603   InstrItinData<IIC_VRECSQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 604                                InstrStage<2, [A8_NPipe]>], [10, 2, 2]>,
 605   //
 606   // Double-register Integer Count
 607   InstrItinData<IIC_VCNTiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 608                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 609   //
 610   // Quad-register Integer Count
 611   // Result written in N3, but that is relative to the last cycle of multicycle,
 612   // so we use 4 for those cases
 613   InstrItinData<IIC_VCNTiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 614                                InstrStage<2, [A8_NPipe]>], [4, 2, 2]>,
 615   //
 616   // Double-register Integer Unary
 617   InstrItinData<IIC_VUNAiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 618                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 619   //
 620   // Quad-register Integer Unary
 621   InstrItinData<IIC_VUNAiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 622                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 623   //
 624   // Double-register Integer Q-Unary
 625   InstrItinData<IIC_VQUNAiD,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 626                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 627   //
 628   // Quad-register Integer CountQ-Unary
 629   InstrItinData<IIC_VQUNAiQ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 630                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 631   //
 632   // Double-register Integer Binary
 633   InstrItinData<IIC_VBINiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 634                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 635   //
 636   // Quad-register Integer Binary
 637   InstrItinData<IIC_VBINiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 638                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 639   //
 640   // Double-register Integer Binary (4 cycle)
 641   InstrItinData<IIC_VBINi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 642                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 643   //
 644   // Quad-register Integer Binary (4 cycle)
 645   InstrItinData<IIC_VBINi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 646                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 647
 648   //
 649   // Double-register Integer Subtract
 650   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 651                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 652   //
 653   // Quad-register Integer Subtract
 654   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 655                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 656   //
 657   // Double-register Integer Subtract
 658   InstrItinData<IIC_VSUBi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 659                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 660   //
 661   // Quad-register Integer Subtract
 662   InstrItinData<IIC_VSUBi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 663                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 664   //
 665   // Double-register Integer Shift
 666   InstrItinData<IIC_VSHLiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 667                                InstrStage<1, [A8_NPipe]>], [3, 1, 1]>,
 668   //
 669   // Quad-register Integer Shift
 670   InstrItinData<IIC_VSHLiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 671                                InstrStage<2, [A8_NPipe]>], [4, 1, 1]>,
 672   //
 673   // Double-register Integer Shift (4 cycle)
 674   InstrItinData<IIC_VSHLi4D,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 675                                InstrStage<1, [A8_NPipe]>], [4, 1, 1]>,
 676   //
 677   // Quad-register Integer Shift (4 cycle)
 678   InstrItinData<IIC_VSHLi4Q,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 679                                InstrStage<2, [A8_NPipe]>], [5, 1, 1]>,
 680   //
 681   // Double-register Integer Pair Add Long
 682   InstrItinData<IIC_VPALiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 683                                InstrStage<1, [A8_NPipe]>], [6, 3, 1]>,
 684   //
 685   // Quad-register Integer Pair Add Long
 686   InstrItinData<IIC_VPALiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 687                                InstrStage<2, [A8_NPipe]>], [7, 3, 1]>,
 688   //
 689   // Double-register Absolute Difference and Accumulate
 690   InstrItinData<IIC_VABAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 691                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>,
 692   //
 693   // Quad-register Absolute Difference and Accumulate
 694   InstrItinData<IIC_VABAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 695                                InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>,
 696
 697   //
 698   // Double-register Integer Multiply (.8, .16)
 699   InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 700                                InstrStage<1, [A8_NPipe]>], [6, 2, 2]>,
 701   //
 702   // Double-register Integer Multiply (.32)
 703   InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 704                                InstrStage<2, [A8_NPipe]>], [7, 2, 1]>,
 705   //
 706   // Quad-register Integer Multiply (.8, .16)
 707   InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 708                                InstrStage<2, [A8_NPipe]>], [7, 2, 2]>,
 709   //
 710   // Quad-register Integer Multiply (.32)
 711   InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 712                                InstrStage<1, [A8_NPipe]>,
 713                                InstrStage<2, [A8_NLSPipe], 0>,
 714                                InstrStage<3, [A8_NPipe]>], [9, 2, 1]>,
 715   //
 716   // Double-register Integer Multiply-Accumulate (.8, .16)
 717   InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 718                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>,
 719   //
 720   // Double-register Integer Multiply-Accumulate (.32)
 721   InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 722                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>,
 723   //
 724   // Quad-register Integer Multiply-Accumulate (.8, .16)
 725   InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 726                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>,
 727   //
 728   // Quad-register Integer Multiply-Accumulate (.32)
 729   InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 730                                InstrStage<1, [A8_NPipe]>,
 731                                InstrStage<2, [A8_NLSPipe], 0>,
 732                                InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>,
 733   //
 734   // Double-register VEXT
 735   InstrItinData<IIC_VEXTD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 736                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 737   //
 738   // Quad-register VEXT
 739   InstrItinData<IIC_VEXTQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 740                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 741   //
 742   // VTB
 743   InstrItinData<IIC_VTB1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 744                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>,
 745   InstrItinData<IIC_VTB2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 746                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>,
 747   InstrItinData<IIC_VTB3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 748                                InstrStage<1, [A8_NLSPipe]>,
 749                                InstrStage<1, [A8_NPipe], 0>,
 750                                InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>,
 751   InstrItinData<IIC_VTB4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 752                                InstrStage<1, [A8_NLSPipe]>,
 753                                InstrStage<1, [A8_NPipe], 0>,
 754                                InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>,
 755   //
 756   // VTBX
 757   InstrItinData<IIC_VTBX1,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 758                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>,
 759   InstrItinData<IIC_VTBX2,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 760                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>,
 761   InstrItinData<IIC_VTBX3,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 762                                InstrStage<1, [A8_NLSPipe]>,
 763                                InstrStage<1, [A8_NPipe], 0>,
 764                                InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>,
 765   InstrItinData<IIC_VTBX4,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 766                                InstrStage<1, [A8_NLSPipe]>,
 767                                InstrStage<1, [A8_NPipe], 0>,
 768                             InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>
 769 ]>;