lib/Target/ARM/ARMScheduleA8.td

   1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //
  15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
  16 // Functional Units.
  17 def A8_Pipe0   : FuncUnit; // pipeline 0
  18 def A8_Pipe1   : FuncUnit; // pipeline 1
  19 def A8_LSPipe  : FuncUnit; // Load / store pipeline
  20 def A8_NPipe   : FuncUnit; // NEON ALU/MUL pipe
  21 def A8_NLSPipe : FuncUnit; // NEON LS pipe
  22 //
  23 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
  24 //
  25 def CortexA8Itineraries : ProcessorItineraries<
  26   [A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe],
  27   [], [
  28   // Two fully-pipelined integer ALU pipelines
  29   //
  30   // No operand cycles
  31   InstrItinData<IIC_iALUx    , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
  32   //
  33   // Binary Instructions that produce a result
  34   InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  35   InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  36   InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  37   InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
  38   InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  39   //
  40   // Bitwise Instructions that produce a result
  41   InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  42   InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  43   InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  44   InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  45   //
  46   // Unary Instructions that produce a result
  47   InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  48   InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  49   //
  50   // Zero and sign extension instructions
  51   InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  52   InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  53   InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>,
  54   //
  55   // Compare instructions
  56   InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  57   InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  58   InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  59   InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  60   //
  61   // Test instructions
  62   InstrItinData<IIC_iTSTi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  63   InstrItinData<IIC_iTSTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  64   InstrItinData<IIC_iTSTsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  65   InstrItinData<IIC_iTSTsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  66   //
  67   // Move instructions, unconditional
  68   InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  69   InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  70   InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  71   InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  72   InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  73                              InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  74   //
  75   // Move instructions, conditional
  76   InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  77   InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  78   InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  79   InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  80   //
  81   // MVN instructions
  82   InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  83   InstrItinData<IIC_iMVNr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  84   InstrItinData<IIC_iMVNsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  85   InstrItinData<IIC_iMVNsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  86
  87   // Integer multiply pipeline
  88   // Result written in E5, but that is relative to the last cycle of multicycle,
  89   // so we use 6 for those cases
  90   //
  91   InstrItinData<IIC_iMUL16   , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>,
  92   InstrItinData<IIC_iMAC16   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
  93   InstrItinData<IIC_iMUL32   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>,
  94   InstrItinData<IIC_iMAC32   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
  95   InstrItinData<IIC_iMUL64   , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
  96   InstrItinData<IIC_iMAC64   , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
  97
  98   // Integer load pipeline
  99   //
 100   // Immediate offset
 101   InstrItinData<IIC_iLoad_i   , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 102                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 103   InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 104                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 105   InstrItinData<IIC_iLoad_d_i,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 106                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 107   //
 108   // Register offset
 109   InstrItinData<IIC_iLoad_r   , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 110                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 111   InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 112                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 113   InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 114                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 115   //
 116   // Scaled register offset, issues over 2 cycles
 117   // FIXME: lsl by 2 takes 1 cycle.
 118   InstrItinData<IIC_iLoad_si  , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 119                                  InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
 120   InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 121                                  InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
 122   //
 123   // Immediate offset with update
 124   InstrItinData<IIC_iLoad_iu  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 125                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
 126   InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 127                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
 128   //
 129   // Register offset with update
 130   InstrItinData<IIC_iLoad_ru  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 131                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 132   InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 133                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 134   InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 135                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 136   //
 137   // Scaled register offset with update, issues over 2 cycles
 138   InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 139                                  InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>,
 140   InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 141                                   InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>,
 142   //
 143   // Load multiple, def is the 5th operand. Pipeline 0 only.
 144   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 145   InstrItinData<IIC_iLoad_m  , [InstrStage<2, [A8_Pipe0], 0>,
 146                                 InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1, 3]>,
 147   //
 148   // Load multiple + update, defs are the 1st and 5th operands.
 149   InstrItinData<IIC_iLoad_mu , [InstrStage<3, [A8_Pipe0], 0>,
 150                                 InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 3]>,
 151   //
 152   // Load multiple plus branch
 153   InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [A8_Pipe0], 0>,
 154                                 InstrStage<3, [A8_LSPipe]>,
 155                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
 156                                [1, 2, 1, 1, 3]>,
 157   //
 158   // Pop, def is the 3rd operand.
 159   InstrItinData<IIC_iPop  ,    [InstrStage<3, [A8_Pipe0], 0>,
 160                                 InstrStage<3, [A8_LSPipe]>], [1, 1, 3]>,
 161   //
 162   // Push, def is the 3th operand.
 163   InstrItinData<IIC_iPop_Br,   [InstrStage<3, [A8_Pipe0], 0>,
 164                                 InstrStage<3, [A8_LSPipe]>,
 165                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
 166                                [1, 1, 3]>,
 167
 168   //
 169   // iLoadi + iALUr for t2LDRpci_pic.
 170   InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 171                                 InstrStage<1, [A8_LSPipe]>,
 172                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
 173
 174
 175   // Integer store pipeline
 176   //
 177   // Immediate offset
 178   InstrItinData<IIC_iStore_i  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 179                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 180   InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 181                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 182   InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 183                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 184   //
 185   // Register offset
 186   InstrItinData<IIC_iStore_r  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 187                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 188   InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 189                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 190   InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 191                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 192   //
 193   // Scaled register offset, issues over 2 cycles
 194   InstrItinData<IIC_iStore_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 195                                  InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
 196   InstrItinData<IIC_iStore_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 197                                   InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
 198   //
 199   // Immediate offset with update
 200   InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 201                                  InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
 202   InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 203                                  InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
 204   //
 205   // Register offset with update
 206   InstrItinData<IIC_iStore_ru  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 207                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 208   InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 209                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 210   InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 211                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 212   //
 213   // Scaled register offset with update, issues over 2 cycles
 214   InstrItinData<IIC_iStore_siu, [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 215                                  InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
 216   InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 217                                    InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
 218   //
 219   // Store multiple. Pipeline 0 only.
 220   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 221   InstrItinData<IIC_iStore_m , [InstrStage<2, [A8_Pipe0], 0>,
 222                                 InstrStage<2, [A8_LSPipe]>]>,
 223   //
 224   // Store multiple + update
 225   InstrItinData<IIC_iStore_mu, [InstrStage<2, [A8_Pipe0], 0>,
 226                                 InstrStage<2, [A8_LSPipe]>], [2]>,
 227
 228   // Branch
 229   //
 230   // no delay slots, so the latency of a branch is unimportant
 231   InstrItinData<IIC_Br      , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
 232
 233   // VFP
 234   // Issue through integer pipeline, and execute in NEON unit. We assume
 235   // RunFast mode so that NFP pipeline is used for single-precision when
 236   // possible.
 237   //
 238   // FP Special Register to Integer Register File Move
 239   InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 240                               InstrStage<1, [A8_NLSPipe]>], [20]>,
 241   //
 242   // Single-precision FP Unary
 243   InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 244                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 245   //
 246   // Double-precision FP Unary
 247   InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 248                                InstrStage<4, [A8_NPipe], 0>,
 249                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 250   //
 251   // Single-precision FP Compare
 252   InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 253                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 254   //
 255   // Double-precision FP Compare
 256   InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 257                                InstrStage<4, [A8_NPipe], 0>,
 258                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 259   //
 260   // Single to Double FP Convert
 261   InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 262                                InstrStage<7, [A8_NPipe], 0>,
 263                                InstrStage<7, [A8_NLSPipe]>], [7, 1]>,
 264   //
 265   // Double to Single FP Convert
 266   InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 267                                InstrStage<5, [A8_NPipe], 0>,
 268                                InstrStage<5, [A8_NLSPipe]>], [5, 1]>,
 269   //
 270   // Single-Precision FP to Integer Convert
 271   InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 272                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 273   //
 274   // Double-Precision FP to Integer Convert
 275   InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 276                                InstrStage<8, [A8_NPipe], 0>,
 277                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 278   //
 279   // Integer to Single-Precision FP Convert
 280   InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 281                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 282   //
 283   // Integer to Double-Precision FP Convert
 284   InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 285                                InstrStage<8, [A8_NPipe], 0>,
 286                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 287   //
 288   // Single-precision FP ALU
 289   InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 290                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 291   //
 292   // Double-precision FP ALU
 293   InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 294                                InstrStage<9, [A8_NPipe], 0>,
 295                                InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>,
 296   //
 297   // Single-precision FP Multiply
 298   InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 299                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 300   //
 301   // Double-precision FP Multiply
 302   InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 303                                InstrStage<11, [A8_NPipe], 0>,
 304                                InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>,
 305   //
 306   // Single-precision FP MAC
 307   InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 308                                InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
 309   //
 310   // Double-precision FP MAC
 311   InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 312                                InstrStage<19, [A8_NPipe], 0>,
 313                                InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
 314   //
 315   // Single-precision FP DIV
 316   InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 317                                InstrStage<20, [A8_NPipe], 0>,
 318                                InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>,
 319   //
 320   // Double-precision FP DIV
 321   InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 322                                InstrStage<29, [A8_NPipe], 0>,
 323                                InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>,
 324   //
 325   // Single-precision FP SQRT
 326   InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 327                                InstrStage<19, [A8_NPipe], 0>,
 328                                InstrStage<19, [A8_NLSPipe]>], [19, 1]>,
 329   //
 330   // Double-precision FP SQRT
 331   InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 332                                InstrStage<29, [A8_NPipe], 0>,
 333                                InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
 334
 335   //
 336   // Integer to Single-precision Move
 337   InstrItinData<IIC_fpMOVIS,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 338                                InstrStage<1, [A8_NPipe]>],
 339                               [2, 1]>,
 340   //
 341   // Integer to Double-precision Move
 342   InstrItinData<IIC_fpMOVID,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 343                                InstrStage<1, [A8_NPipe]>],
 344                               [2, 1, 1]>,
 345   //
 346   // Single-precision to Integer Move
 347   InstrItinData<IIC_fpMOVSI,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 348                                InstrStage<1, [A8_NPipe]>],
 349                               [20, 1]>,
 350   //
 351   // Double-precision to Integer Move
 352   InstrItinData<IIC_fpMOVDI,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 353                                InstrStage<1, [A8_NPipe]>],
 354                               [20, 20, 1]>,
 355
 356   //
 357   // Single-precision FP Load
 358   InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 359                                InstrStage<1, [A8_NLSPipe], 0>,
 360                                InstrStage<1, [A8_LSPipe]>],
 361                               [2, 1]>,
 362   //
 363   // Double-precision FP Load
 364   InstrItinData<IIC_fpLoad64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 365                                InstrStage<1, [A8_NLSPipe], 0>,
 366                                InstrStage<1, [A8_LSPipe]>],
 367                               [2, 1]>,
 368   //
 369   // FP Load Multiple
 370   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 371   InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 372                                InstrStage<1, [A8_NLSPipe], 0>,
 373                                InstrStage<1, [A8_LSPipe]>,
 374                                InstrStage<1, [A8_NLSPipe], 0>,
 375                                InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 2]>,
 376   //
 377   // FP Load Multiple + update
 378   InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 379                                InstrStage<1, [A8_NLSPipe], 0>,
 380                                InstrStage<1, [A8_LSPipe]>,
 381                                InstrStage<1, [A8_NLSPipe], 0>,
 382                                InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 2]>,
 383   //
 384   // Single-precision FP Store
 385   InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 386                                InstrStage<1, [A8_NLSPipe], 0>,
 387                                InstrStage<1, [A8_LSPipe]>],
 388                               [1, 1]>,
 389   //
 390   // Double-precision FP Store
 391   InstrItinData<IIC_fpStore64,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 392                                InstrStage<1, [A8_NLSPipe], 0>,
 393                                InstrStage<1, [A8_LSPipe]>],
 394                               [1, 1]>,
 395   //
 396   // FP Store Multiple
 397   InstrItinData<IIC_fpStore_m,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 398                                InstrStage<1, [A8_NLSPipe], 0>,
 399                                InstrStage<1, [A8_LSPipe]>,
 400                                InstrStage<1, [A8_NLSPipe], 0>,
 401                                InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 1]>,
 402   //
 403   // FP Store Multiple + update
 404   InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 405                                 InstrStage<1, [A8_NLSPipe], 0>,
 406                                 InstrStage<1, [A8_LSPipe]>,
 407                                 InstrStage<1, [A8_NLSPipe], 0>,
 408                                 InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 1]>,
 409
 410   // NEON
 411   // Issue through integer pipeline, and execute in NEON unit.
 412   //
 413   // VLD1
 414   InstrItinData<IIC_VLD1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 415                                InstrStage<2, [A8_NLSPipe], 0>,
 416                                InstrStage<2, [A8_LSPipe]>],
 417                               [2, 1]>,
 418   // VLD1x2
 419   InstrItinData<IIC_VLD1x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 420                                InstrStage<2, [A8_NLSPipe], 0>,
 421                                InstrStage<2, [A8_LSPipe]>],
 422                               [2, 2, 1]>,
 423   //
 424   // VLD1x3
 425   InstrItinData<IIC_VLD1x3,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 426                                InstrStage<3, [A8_NLSPipe], 0>,
 427                                InstrStage<3, [A8_LSPipe]>],
 428                               [2, 2, 3, 1]>,
 429   //
 430   // VLD1x4
 431   InstrItinData<IIC_VLD1x4,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 432                                InstrStage<3, [A8_NLSPipe], 0>,
 433                                InstrStage<3, [A8_LSPipe]>],
 434                               [2, 2, 3, 3, 1]>,
 435   //
 436   // VLD1u
 437   InstrItinData<IIC_VLD1u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 438                                InstrStage<2, [A8_NLSPipe], 0>,
 439                                InstrStage<2, [A8_LSPipe]>],
 440                               [2, 2, 1]>,
 441   //
 442   // VLD1x2u
 443   InstrItinData<IIC_VLD1x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 444                                InstrStage<2, [A8_NLSPipe], 0>,
 445                                InstrStage<2, [A8_LSPipe]>],
 446                               [2, 2, 2, 1]>,
 447   //
 448   // VLD1x3u
 449   InstrItinData<IIC_VLD1x3u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 450                                InstrStage<3, [A8_NLSPipe], 0>,
 451                                InstrStage<3, [A8_LSPipe]>],
 452                               [2, 2, 3, 2, 1]>,
 453   //
 454   // VLD1x4u
 455   InstrItinData<IIC_VLD1x4u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 456                                InstrStage<3, [A8_NLSPipe], 0>,
 457                                InstrStage<3, [A8_LSPipe]>],
 458                               [2, 2, 3, 3, 2, 1]>,
 459   //
 460   // VLD1ln
 461   InstrItinData<IIC_VLD1ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 462                                InstrStage<3, [A8_NLSPipe], 1>,
 463                                InstrStage<3, [A8_LSPipe]>],
 464                               [3, 1, 1, 1]>,
 465   //
 466   // VLD1lnu
 467   InstrItinData<IIC_VLD1lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 468                                InstrStage<3, [A8_NLSPipe], 1>,
 469                                InstrStage<3, [A8_LSPipe]>],
 470                               [3, 2, 1, 1, 1, 1]>,
 471   //
 472   // VLD2
 473   InstrItinData<IIC_VLD2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 474                                InstrStage<2, [A8_NLSPipe], 0>,
 475                                InstrStage<2, [A8_LSPipe]>],
 476                               [2, 2, 1]>,
 477   //
 478   // VLD2x2
 479   InstrItinData<IIC_VLD2x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 480                                InstrStage<3, [A8_NLSPipe], 0>,
 481                                InstrStage<3, [A8_LSPipe]>],
 482                               [2, 2, 3, 3, 1]>,
 483   //
 484   // VLD2ln
 485   InstrItinData<IIC_VLD2ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 486                                InstrStage<3, [A8_NLSPipe], 0>,
 487                                InstrStage<3, [A8_LSPipe]>],
 488                               [3, 3, 1, 1, 1, 1]>,
 489   //
 490   // VLD2u
 491   InstrItinData<IIC_VLD2u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 492                                InstrStage<2, [A8_NLSPipe], 0>,
 493                                InstrStage<2, [A8_LSPipe]>],
 494                               [2, 2, 2, 1, 1, 1]>,
 495   //
 496   // VLD2x2u
 497   InstrItinData<IIC_VLD2x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 498                                InstrStage<3, [A8_NLSPipe], 0>,
 499                                InstrStage<3, [A8_LSPipe]>],
 500                               [2, 2, 3, 3, 2, 1]>,
 501   //
 502   // VLD2lnu
 503   InstrItinData<IIC_VLD2lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 504                                InstrStage<3, [A8_NLSPipe], 0>,
 505                                InstrStage<3, [A8_LSPipe]>],
 506                               [3, 3, 2, 1, 1, 1, 1, 1]>,
 507   //
 508   // VLD3
 509   InstrItinData<IIC_VLD3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 510                                InstrStage<4, [A8_NLSPipe], 0>,
 511                                InstrStage<4, [A8_LSPipe]>],
 512                               [3, 3, 4, 1]>,
 513   //
 514   // VLD3ln
 515   InstrItinData<IIC_VLD3ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 516                                InstrStage<5, [A8_NLSPipe], 0>,
 517                                InstrStage<5, [A8_LSPipe]>],
 518                               [4, 4, 5, 1, 1, 1, 1, 2]>,
 519   //
 520   // VLD3u
 521   InstrItinData<IIC_VLD3u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 522                                InstrStage<4, [A8_NLSPipe], 0>,
 523                                InstrStage<4, [A8_LSPipe]>],
 524                               [3, 3, 4, 2, 1]>,
 525   //
 526   // VLD3lnu
 527   InstrItinData<IIC_VLD3lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 528                                InstrStage<5, [A8_NLSPipe], 0>,
 529                                InstrStage<5, [A8_LSPipe]>],
 530                               [4, 4, 5, 2, 1, 1, 1, 1, 1, 2]>,
 531   //
 532   // VLD4
 533   InstrItinData<IIC_VLD4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 534                                InstrStage<4, [A8_NLSPipe], 0>,
 535                                InstrStage<4, [A8_LSPipe]>],
 536                               [3, 3, 4, 4, 1]>,
 537   //
 538   // VLD4ln
 539   InstrItinData<IIC_VLD4ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 540                                InstrStage<5, [A8_NLSPipe], 0>,
 541                                InstrStage<5, [A8_LSPipe]>],
 542                               [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>,
 543   //
 544   // VLD4u
 545   InstrItinData<IIC_VLD4u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 546                                InstrStage<4, [A8_NLSPipe], 0>,
 547                                InstrStage<4, [A8_LSPipe]>],
 548                               [3, 3, 4, 4, 2, 1]>,
 549   //
 550   // VLD4lnu
 551   InstrItinData<IIC_VLD4lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 552                                InstrStage<5, [A8_NLSPipe], 0>,
 553                                InstrStage<5, [A8_LSPipe]>],
 554                               [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>,
 555   //
 556   // VST1
 557   InstrItinData<IIC_VST1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 558                                InstrStage<2, [A8_NLSPipe], 0>,
 559                                InstrStage<2, [A8_LSPipe]>],
 560                               [1, 1, 1]>,
 561   //
 562   // VST1x2
 563   InstrItinData<IIC_VST1x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 564                                InstrStage<2, [A8_NLSPipe], 0>,
 565                                InstrStage<2, [A8_LSPipe]>],
 566                               [1, 1, 1, 1]>,
 567   //
 568   // VST1x3
 569   InstrItinData<IIC_VST1x3,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 570                                InstrStage<3, [A8_NLSPipe], 0>,
 571                                InstrStage<3, [A8_LSPipe]>],
 572                               [1, 1, 1, 1, 2]>,
 573   //
 574   // VST1x4
 575   InstrItinData<IIC_VST1x4,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 576                                InstrStage<3, [A8_NLSPipe], 0>,
 577                                InstrStage<3, [A8_LSPipe]>],
 578                               [1, 1, 1, 1, 2, 2]>,
 579   //
 580   // VST1u
 581   InstrItinData<IIC_VST1u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 582                                InstrStage<2, [A8_NLSPipe], 0>,
 583                                InstrStage<2, [A8_LSPipe]>],
 584                               [2, 1, 1, 1, 1]>,
 585   //
 586   // VST1x2u
 587   InstrItinData<IIC_VST1x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 588                                InstrStage<2, [A8_NLSPipe], 0>,
 589                                InstrStage<2, [A8_LSPipe]>],
 590                               [2, 1, 1, 1, 1, 1]>,
 591   //
 592   // VST1x3u
 593   InstrItinData<IIC_VST1x3u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 594                                InstrStage<3, [A8_NLSPipe], 0>,
 595                                InstrStage<3, [A8_LSPipe]>],
 596                               [2, 1, 1, 1, 1, 1, 2]>,
 597   //
 598   // VST1x4u
 599   InstrItinData<IIC_VST1x4u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 600                                InstrStage<3, [A8_NLSPipe], 0>,
 601                                InstrStage<3, [A8_LSPipe]>],
 602                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 603   //
 604   // VST1ln
 605   InstrItinData<IIC_VST1ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 606                                InstrStage<2, [A8_NLSPipe], 1>,
 607                                InstrStage<2, [A8_LSPipe]>],
 608                               [1, 1, 1]>,
 609   //
 610   // VST1lnu
 611   InstrItinData<IIC_VST1lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 612                                InstrStage<2, [A8_NLSPipe], 1>,
 613                                InstrStage<2, [A8_LSPipe]>],
 614                               [2, 1, 1, 1, 1]>,
 615   //
 616   // VST2
 617   InstrItinData<IIC_VST2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 618                                InstrStage<2, [A8_NLSPipe], 0>,
 619                                InstrStage<2, [A8_LSPipe]>],
 620                               [1, 1, 1, 1]>,
 621   //
 622   // VST2x2
 623   InstrItinData<IIC_VST2x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 624                                InstrStage<4, [A8_NLSPipe], 0>,
 625                                InstrStage<4, [A8_LSPipe]>],
 626                               [1, 1, 1, 1, 2, 2]>,
 627   //
 628   // VST2u
 629   InstrItinData<IIC_VST2u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 630                                InstrStage<2, [A8_NLSPipe], 0>,
 631                                InstrStage<2, [A8_LSPipe]>],
 632                               [2, 1, 1, 1, 1, 1]>,
 633   //
 634   // VST2x2u
 635   InstrItinData<IIC_VST2x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 636                                InstrStage<4, [A8_NLSPipe], 0>,
 637                                InstrStage<4, [A8_LSPipe]>],
 638                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 639   //
 640   // VST2ln
 641   InstrItinData<IIC_VST2ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 642                                InstrStage<2, [A8_NLSPipe], 0>,
 643                                InstrStage<2, [A8_LSPipe]>],
 644                               [1, 1, 1, 1]>,
 645   //
 646   // VST2lnu
 647   InstrItinData<IIC_VST2lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 648                                InstrStage<2, [A8_NLSPipe], 0>,
 649                                InstrStage<2, [A8_LSPipe]>],
 650                               [2, 1, 1, 1, 1, 1]>,
 651   //
 652   // VST3
 653   InstrItinData<IIC_VST3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 654                                InstrStage<3, [A8_NLSPipe], 0>,
 655                                InstrStage<3, [A8_LSPipe]>],
 656                               [1, 1, 1, 1, 2]>,
 657   //
 658   // VST3u
 659   InstrItinData<IIC_VST3u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 660                                InstrStage<3, [A8_NLSPipe], 0>,
 661                                InstrStage<3, [A8_LSPipe]>],
 662                               [2, 1, 1, 1, 1, 1, 2]>,
 663   //
 664   // VST3ln
 665   InstrItinData<IIC_VST3ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 666                                InstrStage<3, [A8_NLSPipe], 0>,
 667                                InstrStage<3, [A8_LSPipe]>],
 668                               [1, 1, 1, 1, 2]>,
 669   //
 670   // VST3lnu
 671   InstrItinData<IIC_VST3lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 672                                InstrStage<3, [A8_NLSPipe], 0>,
 673                                InstrStage<3, [A8_LSPipe]>],
 674                               [2, 1, 1, 1, 1, 1, 2]>,
 675   //
 676   // VST4
 677   InstrItinData<IIC_VST4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 678                                InstrStage<4, [A8_NLSPipe], 0>,
 679                                InstrStage<4, [A8_LSPipe]>],
 680                               [1, 1, 1, 1, 2, 2]>,
 681   //
 682   // VST4u
 683   InstrItinData<IIC_VST4u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 684                                InstrStage<4, [A8_NLSPipe], 0>,
 685                                InstrStage<4, [A8_LSPipe]>],
 686                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 687   //
 688   // VST4ln
 689   InstrItinData<IIC_VST4ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 690                                InstrStage<4, [A8_NLSPipe], 0>,
 691                                InstrStage<4, [A8_LSPipe]>],
 692                               [1, 1, 1, 1, 2, 2]>,
 693   //
 694   // VST4lnu
 695   InstrItinData<IIC_VST4lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 696                                InstrStage<4, [A8_NLSPipe], 0>,
 697                                InstrStage<4, [A8_LSPipe]>],
 698                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 699   //
 700   // Double-register FP Unary
 701   InstrItinData<IIC_VUNAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 702                                InstrStage<1, [A8_NPipe]>], [5, 2]>,
 703   //
 704   // Quad-register FP Unary
 705   // Result written in N5, but that is relative to the last cycle of multicycle,
 706   // so we use 6 for those cases
 707   InstrItinData<IIC_VUNAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 708                                InstrStage<2, [A8_NPipe]>], [6, 2]>,
 709   //
 710   // Double-register FP Binary
 711   InstrItinData<IIC_VBIND,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 712                                InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
 713   //
 714   // VPADD, etc.
 715   InstrItinData<IIC_VPBIND,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 716                                InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
 717   //
 718   // Double-register FP VMUL
 719   InstrItinData<IIC_VFMULD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 720                                InstrStage<1, [A8_NPipe]>], [5, 2, 1]>,
 721
 722   //
 723   // Quad-register FP Binary
 724   // Result written in N5, but that is relative to the last cycle of multicycle,
 725   // so we use 6 for those cases
 726   InstrItinData<IIC_VBINQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 727                                InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
 728   //
 729   // Quad-register FP VMUL
 730   InstrItinData<IIC_VFMULQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 731                                InstrStage<1, [A8_NPipe]>], [6, 2, 1]>,
 732   //
 733   // Move
 734   InstrItinData<IIC_VMOV,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 735                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 736   //
 737   // Move Immediate
 738   InstrItinData<IIC_VMOVImm,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 739                                InstrStage<1, [A8_NPipe]>], [3]>,
 740   //
 741   // Double-register Permute Move
 742   InstrItinData<IIC_VMOVD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 743                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 744   //
 745   // Quad-register Permute Move
 746   // Result written in N2, but that is relative to the last cycle of multicycle,
 747   // so we use 3 for those cases
 748   InstrItinData<IIC_VMOVQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 749                                InstrStage<2, [A8_NLSPipe]>], [3, 1]>,
 750   //
 751   // Integer to Single-precision Move
 752   InstrItinData<IIC_VMOVIS ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 753                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 754   //
 755   // Integer to Double-precision Move
 756   InstrItinData<IIC_VMOVID ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 757                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 758   //
 759   // Single-precision to Integer Move
 760   InstrItinData<IIC_VMOVSI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 761                                InstrStage<1, [A8_NLSPipe]>], [20, 1]>,
 762   //
 763   // Double-precision to Integer Move
 764   InstrItinData<IIC_VMOVDI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 765                                InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>,
 766   //
 767   // Integer to Lane Move
 768   InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 769                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 770   //
 771   // Vector narrow move
 772   InstrItinData<IIC_VMOVN   , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 773                                InstrStage<1, [A8_NPipe]>], [2, 1]>,
 774   //
 775   // Double-register Permute
 776   InstrItinData<IIC_VPERMD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 777                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
 778   //
 779   // Quad-register Permute
 780   // Result written in N2, but that is relative to the last cycle of multicycle,
 781   // so we use 3 for those cases
 782   InstrItinData<IIC_VPERMQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 783                                InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>,
 784   //
 785   // Quad-register Permute (3 cycle issue)
 786   // Result written in N2, but that is relative to the last cycle of multicycle,
 787   // so we use 4 for those cases
 788   InstrItinData<IIC_VPERMQ3,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 789                                InstrStage<1, [A8_NLSPipe]>,
 790                                InstrStage<1, [A8_NPipe], 0>,
 791                                InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>,
 792   //
 793   // Double-register FP Multiple-Accumulate
 794   InstrItinData<IIC_VMACD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 795                                InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
 796   //
 797   // Quad-register FP Multiple-Accumulate
 798   // Result written in N9, but that is relative to the last cycle of multicycle,
 799   // so we use 10 for those cases
 800   InstrItinData<IIC_VMACQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 801                                InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
 802   //
 803   // Double-register Reciprical Step
 804   InstrItinData<IIC_VRECSD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 805                                InstrStage<1, [A8_NPipe]>], [9, 2, 2]>,
 806   //
 807   // Quad-register Reciprical Step
 808   InstrItinData<IIC_VRECSQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 809                                InstrStage<2, [A8_NPipe]>], [10, 2, 2]>,
 810   //
 811   // Double-register Integer Count
 812   InstrItinData<IIC_VCNTiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 813                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 814   //
 815   // Quad-register Integer Count
 816   // Result written in N3, but that is relative to the last cycle of multicycle,
 817   // so we use 4 for those cases
 818   InstrItinData<IIC_VCNTiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 819                                InstrStage<2, [A8_NPipe]>], [4, 2, 2]>,
 820   //
 821   // Double-register Integer Unary
 822   InstrItinData<IIC_VUNAiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 823                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 824   //
 825   // Quad-register Integer Unary
 826   InstrItinData<IIC_VUNAiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 827                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 828   //
 829   // Double-register Integer Q-Unary
 830   InstrItinData<IIC_VQUNAiD,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 831                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 832   //
 833   // Quad-register Integer CountQ-Unary
 834   InstrItinData<IIC_VQUNAiQ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 835                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 836   //
 837   // Double-register Integer Binary
 838   InstrItinData<IIC_VBINiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 839                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 840   //
 841   // Quad-register Integer Binary
 842   InstrItinData<IIC_VBINiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 843                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 844   //
 845   // Double-register Integer Binary (4 cycle)
 846   InstrItinData<IIC_VBINi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 847                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 848   //
 849   // Quad-register Integer Binary (4 cycle)
 850   InstrItinData<IIC_VBINi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 851                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 852
 853   //
 854   // Double-register Integer Subtract
 855   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 856                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 857   //
 858   // Quad-register Integer Subtract
 859   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 860                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 861   //
 862   // Double-register Integer Subtract
 863   InstrItinData<IIC_VSUBi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 864                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 865   //
 866   // Quad-register Integer Subtract
 867   InstrItinData<IIC_VSUBi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 868                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 869   //
 870   // Double-register Integer Shift
 871   InstrItinData<IIC_VSHLiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 872                                InstrStage<1, [A8_NPipe]>], [3, 1, 1]>,
 873   //
 874   // Quad-register Integer Shift
 875   InstrItinData<IIC_VSHLiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 876                                InstrStage<2, [A8_NPipe]>], [4, 1, 1]>,
 877   //
 878   // Double-register Integer Shift (4 cycle)
 879   InstrItinData<IIC_VSHLi4D,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 880                                InstrStage<1, [A8_NPipe]>], [4, 1, 1]>,
 881   //
 882   // Quad-register Integer Shift (4 cycle)
 883   InstrItinData<IIC_VSHLi4Q,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 884                                InstrStage<2, [A8_NPipe]>], [5, 1, 1]>,
 885   //
 886   // Double-register Integer Pair Add Long
 887   InstrItinData<IIC_VPALiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 888                                InstrStage<1, [A8_NPipe]>], [6, 3, 1]>,
 889   //
 890   // Quad-register Integer Pair Add Long
 891   InstrItinData<IIC_VPALiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 892                                InstrStage<2, [A8_NPipe]>], [7, 3, 1]>,
 893   //
 894   // Double-register Absolute Difference and Accumulate
 895   InstrItinData<IIC_VABAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 896                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>,
 897   //
 898   // Quad-register Absolute Difference and Accumulate
 899   InstrItinData<IIC_VABAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 900                                InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>,
 901
 902   //
 903   // Double-register Integer Multiply (.8, .16)
 904   InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 905                                InstrStage<1, [A8_NPipe]>], [6, 2, 2]>,
 906   //
 907   // Double-register Integer Multiply (.32)
 908   InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 909                                InstrStage<2, [A8_NPipe]>], [7, 2, 1]>,
 910   //
 911   // Quad-register Integer Multiply (.8, .16)
 912   InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 913                                InstrStage<2, [A8_NPipe]>], [7, 2, 2]>,
 914   //
 915   // Quad-register Integer Multiply (.32)
 916   InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 917                                InstrStage<1, [A8_NPipe]>,
 918                                InstrStage<2, [A8_NLSPipe], 0>,
 919                                InstrStage<3, [A8_NPipe]>], [9, 2, 1]>,
 920   //
 921   // Double-register Integer Multiply-Accumulate (.8, .16)
 922   InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 923                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>,
 924   //
 925   // Double-register Integer Multiply-Accumulate (.32)
 926   InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 927                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>,
 928   //
 929   // Quad-register Integer Multiply-Accumulate (.8, .16)
 930   InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 931                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>,
 932   //
 933   // Quad-register Integer Multiply-Accumulate (.32)
 934   InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 935                                InstrStage<1, [A8_NPipe]>,
 936                                InstrStage<2, [A8_NLSPipe], 0>,
 937                                InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>,
 938   //
 939   // Double-register VEXT
 940   InstrItinData<IIC_VEXTD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 941                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 942   //
 943   // Quad-register VEXT
 944   InstrItinData<IIC_VEXTQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 945                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 946   //
 947   // VTB
 948   InstrItinData<IIC_VTB1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 949                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>,
 950   InstrItinData<IIC_VTB2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 951                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>,
 952   InstrItinData<IIC_VTB3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 953                                InstrStage<1, [A8_NLSPipe]>,
 954                                InstrStage<1, [A8_NPipe], 0>,
 955                                InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>,
 956   InstrItinData<IIC_VTB4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 957                                InstrStage<1, [A8_NLSPipe]>,
 958                                InstrStage<1, [A8_NPipe], 0>,
 959                                InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>,
 960   //
 961   // VTBX
 962   InstrItinData<IIC_VTBX1,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 963                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>,
 964   InstrItinData<IIC_VTBX2,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 965                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>,
 966   InstrItinData<IIC_VTBX3,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 967                                InstrStage<1, [A8_NLSPipe]>,
 968                                InstrStage<1, [A8_NPipe], 0>,
 969                                InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>,
 970   InstrItinData<IIC_VTBX4,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 971                                InstrStage<1, [A8_NLSPipe]>,
 972                                InstrStage<1, [A8_NPipe], 0>,
 973                             InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>
 974 ]>;