lib/Target/ARM/ARMScheduleA8.td

   1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //
  15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
  16 // Functional Units.
  17 def A8_Pipe0   : FuncUnit; // pipeline 0
  18 def A8_Pipe1   : FuncUnit; // pipeline 1
  19 def A8_LSPipe  : FuncUnit; // Load / store pipeline
  20 def A8_NPipe   : FuncUnit; // NEON ALU/MUL pipe
  21 def A8_NLSPipe : FuncUnit; // NEON LS pipe
  22 //
  23 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
  24 //
  25 def CortexA8Itineraries : ProcessorItineraries<
  26   [A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe],
  27   [], [
  28   // Two fully-pipelined integer ALU pipelines
  29   //
  30   // No operand cycles
  31   InstrItinData<IIC_iALUx    , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
  32   //
  33   // Binary Instructions that produce a result
  34   InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  35   InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  36   InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  37   InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
  38   InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  39   //
  40   // Bitwise Instructions that produce a result
  41   InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  42   InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  43   InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  44   InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  45   //
  46   // Unary Instructions that produce a result
  47   InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  48   InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  49   //
  50   // Zero and sign extension instructions
  51   InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  52   InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  53   InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>,
  54   //
  55   // Compare instructions
  56   InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  57   InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  58   InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  59   InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  60   //
  61   // Test instructions
  62   InstrItinData<IIC_iTSTi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  63   InstrItinData<IIC_iTSTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  64   InstrItinData<IIC_iTSTsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  65   InstrItinData<IIC_iTSTsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  66   //
  67   // Move instructions, unconditional
  68   InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  69   InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  70   InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  71   InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  72   InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  73                              InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  74   //
  75   // Move instructions, conditional
  76   InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  77   InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  78   InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  79   InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  80   //
  81   // MVN instructions
  82   InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  83   InstrItinData<IIC_iMVNr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  84   InstrItinData<IIC_iMVNsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  85   InstrItinData<IIC_iMVNsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  86
  87   // Integer multiply pipeline
  88   // Result written in E5, but that is relative to the last cycle of multicycle,
  89   // so we use 6 for those cases
  90   //
  91   InstrItinData<IIC_iMUL16   , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>,
  92   InstrItinData<IIC_iMAC16   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
  93   InstrItinData<IIC_iMUL32   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>,
  94   InstrItinData<IIC_iMAC32   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
  95   InstrItinData<IIC_iMUL64   , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
  96   InstrItinData<IIC_iMAC64   , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
  97
  98   // Integer load pipeline
  99   //
 100   // Immediate offset
 101   InstrItinData<IIC_iLoad_i   , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 102                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 103   InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 104                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 105   InstrItinData<IIC_iLoad_d_i,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 106                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 107   //
 108   // Register offset
 109   InstrItinData<IIC_iLoad_r   , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 110                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 111   InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 112                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 113   InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 114                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 115   //
 116   // Scaled register offset, issues over 2 cycles
 117   // FIXME: lsl by 2 takes 1 cycle.
 118   InstrItinData<IIC_iLoad_si  , [InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
 119                                  InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
 120   InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
 121                                  InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
 122   //
 123   // Immediate offset with update
 124   InstrItinData<IIC_iLoad_iu  , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 125                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
 126   InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 127                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
 128   //
 129   // Register offset with update
 130   InstrItinData<IIC_iLoad_ru  , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 131                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 132   InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 133                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 134   InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 135                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 136   //
 137   // Scaled register offset with update, issues over 2 cycles
 138   InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
 139                                  InstrStage<1, [A8_LSPipe]>], [4, 3, 1, 1]>,
 140   InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
 141                                   InstrStage<1, [A8_LSPipe]>], [4, 3, 1, 1]>,
 142   //
 143   // Load multiple, def is the 5th operand. Pipeline 0 only.
 144   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 145   InstrItinData<IIC_iLoad_m  , [InstrStage<1, [A8_Pipe0]>,
 146                                 InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1, 3]>,
 147   //
 148   // Load multiple + update, defs are the 1st and 5th operands.
 149   InstrItinData<IIC_iLoad_mu , [InstrStage<1, [A8_Pipe0]>,
 150                                 InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 3]>,
 151   //
 152   // Load multiple plus branch
 153   InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [A8_Pipe0]>,
 154                                 InstrStage<3, [A8_LSPipe]>,
 155                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
 156                                [1, 2, 1, 1, 3]>,
 157   //
 158   // Pop, def is the 3rd operand.
 159   InstrItinData<IIC_iPop  ,    [InstrStage<1, [A8_Pipe0]>,
 160                                 InstrStage<3, [A8_LSPipe]>], [1, 1, 3]>,
 161   //
 162   // Push, def is the 3th operand.
 163   InstrItinData<IIC_iPop_Br,   [InstrStage<1, [A8_Pipe0]>,
 164                                 InstrStage<3, [A8_LSPipe]>,
 165                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
 166                                [1, 1, 3]>,
 167
 168   //
 169   // iLoadi + iALUr for t2LDRpci_pic.
 170   InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 171                                 InstrStage<1, [A8_LSPipe]>,
 172                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
 173
 174
 175   // Integer store pipeline
 176   //
 177   // Immediate offset
 178   InstrItinData<IIC_iStore_i  , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 179                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 180   InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 181                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 182   InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 183                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 184   //
 185   // Register offset
 186   InstrItinData<IIC_iStore_r  , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 187                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 188   InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 189                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 190   InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 191                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 192   //
 193   // Scaled register offset, issues over 2 cycles
 194   InstrItinData<IIC_iStore_si , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 195                                  InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
 196   InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 197                                   InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
 198   //
 199   // Immediate offset with update
 200   InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 201                                  InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
 202   InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 203                                  InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
 204   //
 205   // Register offset with update
 206   InstrItinData<IIC_iStore_ru  , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 207                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 208   InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 209                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 210   InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 211                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 212   //
 213   // Scaled register offset with update, issues over 2 cycles
 214   InstrItinData<IIC_iStore_siu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 215                                  InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
 216   InstrItinData<IIC_iStore_bh_siu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 217                                    InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
 218   //
 219   // Store multiple. Pipeline 0 only.
 220   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 221   InstrItinData<IIC_iStore_m , [InstrStage<1, [A8_Pipe0]>,
 222                                 InstrStage<2, [A8_LSPipe]>]>,
 223   //
 224   // Store multiple + update
 225   InstrItinData<IIC_iStore_mu, [InstrStage<1, [A8_Pipe0]>,
 226                                 InstrStage<2, [A8_LSPipe]>], [2]>,
 227
 228   // Branch
 229   //
 230   // no delay slots, so the latency of a branch is unimportant
 231   InstrItinData<IIC_Br      , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
 232
 233   // VFP
 234   // Issue through integer pipeline, and execute in NEON unit. We assume
 235   // RunFast mode so that NFP pipeline is used for single-precision when
 236   // possible.
 237   //
 238   // FP Special Register to Integer Register File Move
 239   InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 240                               InstrStage<1, [A8_NLSPipe]>]>,
 241   //
 242   // Single-precision FP Unary
 243   InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 244                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 245   //
 246   // Double-precision FP Unary
 247   InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 248                                InstrStage<4, [A8_NPipe], 0>,
 249                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 250   //
 251   // Single-precision FP Compare
 252   InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 253                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 254   //
 255   // Double-precision FP Compare
 256   InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 257                                InstrStage<4, [A8_NPipe], 0>,
 258                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 259   //
 260   // Single to Double FP Convert
 261   InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 262                                InstrStage<7, [A8_NPipe], 0>,
 263                                InstrStage<7, [A8_NLSPipe]>], [7, 1]>,
 264   //
 265   // Double to Single FP Convert
 266   InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 267                                InstrStage<5, [A8_NPipe], 0>,
 268                                InstrStage<5, [A8_NLSPipe]>], [5, 1]>,
 269   //
 270   // Single-Precision FP to Integer Convert
 271   InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 272                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 273   //
 274   // Double-Precision FP to Integer Convert
 275   InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 276                                InstrStage<8, [A8_NPipe], 0>,
 277                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 278   //
 279   // Integer to Single-Precision FP Convert
 280   InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 281                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 282   //
 283   // Integer to Double-Precision FP Convert
 284   InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 285                                InstrStage<8, [A8_NPipe], 0>,
 286                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 287   //
 288   // Single-precision FP ALU
 289   InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 290                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 291   //
 292   // Double-precision FP ALU
 293   InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 294                                InstrStage<9, [A8_NPipe], 0>,
 295                                InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>,
 296   //
 297   // Single-precision FP Multiply
 298   InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 299                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 300   //
 301   // Double-precision FP Multiply
 302   InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 303                                InstrStage<11, [A8_NPipe], 0>,
 304                                InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>,
 305   //
 306   // Single-precision FP MAC
 307   InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 308                                InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
 309   //
 310   // Double-precision FP MAC
 311   InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 312                                InstrStage<19, [A8_NPipe], 0>,
 313                                InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
 314   //
 315   // Single-precision FP DIV
 316   InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 317                                InstrStage<20, [A8_NPipe], 0>,
 318                                InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>,
 319   //
 320   // Double-precision FP DIV
 321   InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 322                                InstrStage<29, [A8_NPipe], 0>,
 323                                InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>,
 324   //
 325   // Single-precision FP SQRT
 326   InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 327                                InstrStage<19, [A8_NPipe], 0>,
 328                                InstrStage<19, [A8_NLSPipe]>], [19, 1]>,
 329   //
 330   // Double-precision FP SQRT
 331   InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 332                                InstrStage<29, [A8_NPipe], 0>,
 333                                InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
 334   //
 335   // Single-precision FP Load
 336   InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 337                                InstrStage<1, [A8_NLSPipe]>,
 338                                InstrStage<1, [A8_LSPipe]>],
 339                               [2, 1]>,
 340   //
 341   // Double-precision FP Load
 342   InstrItinData<IIC_fpLoad64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 343                                InstrStage<1, [A8_NLSPipe]>,
 344                                InstrStage<1, [A8_LSPipe]>],
 345                               [2, 1]>,
 346   //
 347   // FP Load Multiple
 348   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 349   InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 350                                InstrStage<1, [A8_NLSPipe]>,
 351                                InstrStage<1, [A8_LSPipe]>,
 352                                InstrStage<1, [A8_NLSPipe]>,
 353                                InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 2]>,
 354   //
 355   // FP Load Multiple + update
 356   InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 357                                InstrStage<1, [A8_NLSPipe]>,
 358                                InstrStage<1, [A8_LSPipe]>,
 359                                InstrStage<1, [A8_NLSPipe]>,
 360                                InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 2]>,
 361   //
 362   // Single-precision FP Store
 363   InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 364                                InstrStage<1, [A8_NLSPipe]>,
 365                                InstrStage<1, [A8_LSPipe]>],
 366                               [1, 1]>,
 367   //
 368   // Double-precision FP Store
 369   InstrItinData<IIC_fpStore64,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 370                                InstrStage<1, [A8_NLSPipe]>,
 371                                InstrStage<1, [A8_LSPipe]>],
 372                               [1, 1]>,
 373   //
 374   // FP Store Multiple
 375   InstrItinData<IIC_fpStore_m,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 376                                InstrStage<1, [A8_NLSPipe]>,
 377                                InstrStage<1, [A8_LSPipe]>,
 378                                InstrStage<1, [A8_NLSPipe]>,
 379                                InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 1]>,
 380   //
 381   // FP Store Multiple + update
 382   InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 383                                 InstrStage<1, [A8_NLSPipe]>,
 384                                 InstrStage<1, [A8_LSPipe]>,
 385                                 InstrStage<1, [A8_NLSPipe]>,
 386                                 InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 1]>,
 387
 388   // NEON
 389   // Issue through integer pipeline, and execute in NEON unit.
 390   //
 391   // VLD1
 392   InstrItinData<IIC_VLD1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 393                                InstrStage<1, [A8_NLSPipe]>,
 394                                InstrStage<1, [A8_LSPipe]>]>,
 395   // VLD1x2
 396   InstrItinData<IIC_VLD1x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 397                                InstrStage<2, [A8_NLSPipe], 1>,
 398                                InstrStage<2, [A8_LSPipe]>],
 399                               [2, 2, 1]>,
 400   //
 401   // VLD1x3
 402   InstrItinData<IIC_VLD1x3,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 403                                InstrStage<3, [A8_NLSPipe], 1>,
 404                                InstrStage<3, [A8_LSPipe]>],
 405                               [2, 2, 3, 1]>,
 406   //
 407   // VLD1x4
 408   InstrItinData<IIC_VLD1x4,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 409                                InstrStage<3, [A8_NLSPipe], 1>,
 410                                InstrStage<3, [A8_LSPipe]>],
 411                               [2, 2, 3, 3, 1]>,
 412   //
 413   // VLD1u
 414   InstrItinData<IIC_VLD1u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 415                                InstrStage<1, [A8_NLSPipe], 1>,
 416                                InstrStage<1, [A8_LSPipe]>],
 417                               [2, 2, 1]>,
 418   //
 419   // VLD1x2u
 420   InstrItinData<IIC_VLD1x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 421                                InstrStage<2, [A8_NLSPipe], 1>,
 422                                InstrStage<2, [A8_LSPipe]>],
 423                               [2, 2, 2, 1]>,
 424   //
 425   // VLD1x3u
 426   InstrItinData<IIC_VLD1x3u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 427                                InstrStage<3, [A8_NLSPipe], 1>,
 428                                InstrStage<3, [A8_LSPipe]>],
 429                               [2, 2, 3, 2, 1]>,
 430   //
 431   // VLD1x4u
 432   InstrItinData<IIC_VLD1x4u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 433                                InstrStage<3, [A8_NLSPipe], 1>,
 434                                InstrStage<3, [A8_LSPipe]>],
 435                               [2, 2, 3, 3, 2, 1]>,
 436   //
 437   // VLD2
 438   InstrItinData<IIC_VLD2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 439                                InstrStage<1, [A8_NLSPipe], 1>,
 440                                InstrStage<1, [A8_LSPipe]>],
 441                               [2, 2, 1]>,
 442   //
 443   // VLD2x2
 444   InstrItinData<IIC_VLD2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 445                                InstrStage<3, [A8_NLSPipe], 1>,
 446                                InstrStage<3, [A8_LSPipe]>],
 447                               [2, 2, 3, 3, 1]>,
 448   //
 449   // VLD2ln
 450   InstrItinData<IIC_VLD2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 451                                InstrStage<3, [A8_NLSPipe], 1>,
 452                                InstrStage<3, [A8_LSPipe]>],
 453                               [3, 3, 1, 1, 1, 1]>,
 454   //
 455   // VLD2u
 456   InstrItinData<IIC_VLD2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 457                                InstrStage<1, [A8_NLSPipe], 1>,
 458                                InstrStage<1, [A8_LSPipe]>],
 459                               [2, 2, 2, 1, 1, 1]>,
 460   //
 461   // VLD2x2u
 462   InstrItinData<IIC_VLD2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 463                                InstrStage<3, [A8_NLSPipe], 1>,
 464                                InstrStage<3, [A8_LSPipe]>],
 465                               [2, 2, 3, 3, 2, 1]>,
 466   //
 467   // VLD2lnu
 468   InstrItinData<IIC_VLD2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 469                                InstrStage<3, [A8_NLSPipe], 1>,
 470                                InstrStage<3, [A8_LSPipe]>],
 471                               [3, 3, 2, 1, 1, 1, 1, 1]>,
 472   //
 473   // VLD3
 474   InstrItinData<IIC_VLD3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 475                                InstrStage<1, [A8_NLSPipe]>,
 476                                InstrStage<1, [A8_LSPipe]>], [2, 2, 2, 1]>,
 477   //
 478   // VLD4
 479   InstrItinData<IIC_VLD4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 480                                InstrStage<1, [A8_NLSPipe]>,
 481                                InstrStage<1, [A8_LSPipe]>], [2, 2, 2, 2, 1]>,
 482   //
 483   // VST
 484   // FIXME: We don't model this instruction properly
 485   InstrItinData<IIC_VST,      [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 486                                InstrStage<1, [A8_NLSPipe]>,
 487                                InstrStage<1, [A8_LSPipe]>]>,
 488   //
 489   // Double-register FP Unary
 490   InstrItinData<IIC_VUNAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 491                                InstrStage<1, [A8_NPipe]>], [5, 2]>,
 492   //
 493   // Quad-register FP Unary
 494   // Result written in N5, but that is relative to the last cycle of multicycle,
 495   // so we use 6 for those cases
 496   InstrItinData<IIC_VUNAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 497                                InstrStage<2, [A8_NPipe]>], [6, 2]>,
 498   //
 499   // Double-register FP Binary
 500   InstrItinData<IIC_VBIND,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 501                                InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
 502   //
 503   // Quad-register FP Binary
 504   // Result written in N5, but that is relative to the last cycle of multicycle,
 505   // so we use 6 for those cases
 506   InstrItinData<IIC_VBINQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 507                                InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
 508   //
 509   // Move
 510   InstrItinData<IIC_VMOV,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 511                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 512   //
 513   // Move Immediate
 514   InstrItinData<IIC_VMOVImm,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 515                                InstrStage<1, [A8_NPipe]>], [3]>,
 516   //
 517   // Double-register Permute Move
 518   InstrItinData<IIC_VMOVD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 519                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 520   //
 521   // Quad-register Permute Move
 522   // Result written in N2, but that is relative to the last cycle of multicycle,
 523   // so we use 3 for those cases
 524   InstrItinData<IIC_VMOVQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 525                                InstrStage<2, [A8_NLSPipe]>], [3, 1]>,
 526   //
 527   // Integer to Single-precision Move
 528   InstrItinData<IIC_VMOVIS ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 529                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 530   //
 531   // Integer to Double-precision Move
 532   InstrItinData<IIC_VMOVID ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 533                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 534   //
 535   // Single-precision to Integer Move
 536   InstrItinData<IIC_VMOVSI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 537                                InstrStage<1, [A8_NLSPipe]>], [20, 1]>,
 538   //
 539   // Double-precision to Integer Move
 540   InstrItinData<IIC_VMOVDI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 541                                InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>,
 542   //
 543   // Integer to Lane Move
 544   InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 545                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 546   //
 547   // Vector narrow move
 548   InstrItinData<IIC_VMOVN   , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 549                                InstrStage<1, [A8_NPipe]>], [2, 1]>,
 550   //
 551   // Double-register Permute
 552   InstrItinData<IIC_VPERMD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 553                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
 554   //
 555   // Quad-register Permute
 556   // Result written in N2, but that is relative to the last cycle of multicycle,
 557   // so we use 3 for those cases
 558   InstrItinData<IIC_VPERMQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 559                                InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>,
 560   //
 561   // Quad-register Permute (3 cycle issue)
 562   // Result written in N2, but that is relative to the last cycle of multicycle,
 563   // so we use 4 for those cases
 564   InstrItinData<IIC_VPERMQ3,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 565                                InstrStage<1, [A8_NLSPipe]>,
 566                                InstrStage<1, [A8_NPipe], 0>,
 567                                InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>,
 568   //
 569   // Double-register FP Multiple-Accumulate
 570   InstrItinData<IIC_VMACD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 571                                InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
 572   //
 573   // Quad-register FP Multiple-Accumulate
 574   // Result written in N9, but that is relative to the last cycle of multicycle,
 575   // so we use 10 for those cases
 576   InstrItinData<IIC_VMACQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 577                                InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
 578   //
 579   // Double-register Reciprical Step
 580   InstrItinData<IIC_VRECSD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 581                                InstrStage<1, [A8_NPipe]>], [9, 2, 2]>,
 582   //
 583   // Quad-register Reciprical Step
 584   InstrItinData<IIC_VRECSQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 585                                InstrStage<2, [A8_NPipe]>], [10, 2, 2]>,
 586   //
 587   // Double-register Integer Count
 588   InstrItinData<IIC_VCNTiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 589                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 590   //
 591   // Quad-register Integer Count
 592   // Result written in N3, but that is relative to the last cycle of multicycle,
 593   // so we use 4 for those cases
 594   InstrItinData<IIC_VCNTiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 595                                InstrStage<2, [A8_NPipe]>], [4, 2, 2]>,
 596   //
 597   // Double-register Integer Unary
 598   InstrItinData<IIC_VUNAiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 599                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 600   //
 601   // Quad-register Integer Unary
 602   InstrItinData<IIC_VUNAiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 603                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 604   //
 605   // Double-register Integer Q-Unary
 606   InstrItinData<IIC_VQUNAiD,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 607                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 608   //
 609   // Quad-register Integer CountQ-Unary
 610   InstrItinData<IIC_VQUNAiQ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 611                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 612   //
 613   // Double-register Integer Binary
 614   InstrItinData<IIC_VBINiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 615                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 616   //
 617   // Quad-register Integer Binary
 618   InstrItinData<IIC_VBINiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 619                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 620   //
 621   // Double-register Integer Binary (4 cycle)
 622   InstrItinData<IIC_VBINi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 623                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 624   //
 625   // Quad-register Integer Binary (4 cycle)
 626   InstrItinData<IIC_VBINi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 627                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 628
 629   //
 630   // Double-register Integer Subtract
 631   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 632                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 633   //
 634   // Quad-register Integer Subtract
 635   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 636                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 637   //
 638   // Double-register Integer Subtract
 639   InstrItinData<IIC_VSUBi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 640                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 641   //
 642   // Quad-register Integer Subtract
 643   InstrItinData<IIC_VSUBi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 644                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 645   //
 646   // Double-register Integer Shift
 647   InstrItinData<IIC_VSHLiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 648                                InstrStage<1, [A8_NPipe]>], [3, 1, 1]>,
 649   //
 650   // Quad-register Integer Shift
 651   InstrItinData<IIC_VSHLiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 652                                InstrStage<2, [A8_NPipe]>], [4, 1, 1]>,
 653   //
 654   // Double-register Integer Shift (4 cycle)
 655   InstrItinData<IIC_VSHLi4D,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 656                                InstrStage<1, [A8_NPipe]>], [4, 1, 1]>,
 657   //
 658   // Quad-register Integer Shift (4 cycle)
 659   InstrItinData<IIC_VSHLi4Q,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 660                                InstrStage<2, [A8_NPipe]>], [5, 1, 1]>,
 661   //
 662   // Double-register Integer Pair Add Long
 663   InstrItinData<IIC_VPALiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 664                                InstrStage<1, [A8_NPipe]>], [6, 3, 1]>,
 665   //
 666   // Quad-register Integer Pair Add Long
 667   InstrItinData<IIC_VPALiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 668                                InstrStage<2, [A8_NPipe]>], [7, 3, 1]>,
 669   //
 670   // Double-register Absolute Difference and Accumulate
 671   InstrItinData<IIC_VABAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 672                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>,
 673   //
 674   // Quad-register Absolute Difference and Accumulate
 675   InstrItinData<IIC_VABAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 676                                InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>,
 677
 678   //
 679   // Double-register Integer Multiply (.8, .16)
 680   InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 681                                InstrStage<1, [A8_NPipe]>], [6, 2, 2]>,
 682   //
 683   // Double-register Integer Multiply (.32)
 684   InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 685                                InstrStage<2, [A8_NPipe]>], [7, 2, 1]>,
 686   //
 687   // Quad-register Integer Multiply (.8, .16)
 688   InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 689                                InstrStage<2, [A8_NPipe]>], [7, 2, 2]>,
 690   //
 691   // Quad-register Integer Multiply (.32)
 692   InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 693                                InstrStage<1, [A8_NPipe]>,
 694                                InstrStage<2, [A8_NLSPipe], 0>,
 695                                InstrStage<3, [A8_NPipe]>], [9, 2, 1]>,
 696   //
 697   // Double-register Integer Multiply-Accumulate (.8, .16)
 698   InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 699                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>,
 700   //
 701   // Double-register Integer Multiply-Accumulate (.32)
 702   InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 703                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>,
 704   //
 705   // Quad-register Integer Multiply-Accumulate (.8, .16)
 706   InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 707                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>,
 708   //
 709   // Quad-register Integer Multiply-Accumulate (.32)
 710   InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 711                                InstrStage<1, [A8_NPipe]>,
 712                                InstrStage<2, [A8_NLSPipe], 0>,
 713                                InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>,
 714   //
 715   // Double-register VEXT
 716   InstrItinData<IIC_VEXTD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 717                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 718   //
 719   // Quad-register VEXT
 720   InstrItinData<IIC_VEXTQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 721                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 722   //
 723   // VTB
 724   InstrItinData<IIC_VTB1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 725                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>,
 726   InstrItinData<IIC_VTB2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 727                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>,
 728   InstrItinData<IIC_VTB3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 729                                InstrStage<1, [A8_NLSPipe]>,
 730                                InstrStage<1, [A8_NPipe], 0>,
 731                                InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>,
 732   InstrItinData<IIC_VTB4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 733                                InstrStage<1, [A8_NLSPipe]>,
 734                                InstrStage<1, [A8_NPipe], 0>,
 735                                InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>,
 736   //
 737   // VTBX
 738   InstrItinData<IIC_VTBX1,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 739                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>,
 740   InstrItinData<IIC_VTBX2,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 741                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>,
 742   InstrItinData<IIC_VTBX3,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 743                                InstrStage<1, [A8_NLSPipe]>,
 744                                InstrStage<1, [A8_NPipe], 0>,
 745                                InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>,
 746   InstrItinData<IIC_VTBX4,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 747                                InstrStage<1, [A8_NLSPipe]>,
 748                                InstrStage<1, [A8_NPipe], 0>,
 749                             InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>
 750 ]>;