1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
12 //===----------------------------------------------------------------------===//
15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
17 def A8_Pipe0 : FuncUnit; // pipeline 0
18 def A8_Pipe1 : FuncUnit; // pipeline 1
19 def A8_LSPipe : FuncUnit; // Load / store pipeline
20 def A8_NPipe : FuncUnit; // NEON ALU/MUL pipe
21 def A8_NLSPipe : FuncUnit; // NEON LS pipe
23 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
25 def CortexA8Itineraries : ProcessorItineraries<
26 [A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe],
28 // Two fully-pipelined integer ALU pipelines
31 InstrItinData<IIC_iALUx , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
33 // Binary Instructions that produce a result
34 InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
35 InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
36 InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
37 InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
38 InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
40 // Bitwise Instructions that produce a result
41 InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
42 InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
43 InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
44 InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
46 // Unary Instructions that produce a result
47 InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
48 InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
50 // Zero and sign extension instructions
51 InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
52 InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
53 InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>,
55 // Compare instructions
56 InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
57 InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
58 InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
59 InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
62 InstrItinData<IIC_iTSTi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
63 InstrItinData<IIC_iTSTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
64 InstrItinData<IIC_iTSTsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
65 InstrItinData<IIC_iTSTsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
67 // Move instructions, unconditional
68 InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
69 InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
70 InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
71 InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
72 InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
73 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
75 // Move instructions, conditional
76 InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
77 InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
78 InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
79 InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
82 InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
83 InstrItinData<IIC_iMVNr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
84 InstrItinData<IIC_iMVNsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
85 InstrItinData<IIC_iMVNsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
87 // Integer multiply pipeline
88 // Result written in E5, but that is relative to the last cycle of multicycle,
89 // so we use 6 for those cases
91 InstrItinData<IIC_iMUL16 , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>,
92 InstrItinData<IIC_iMAC16 , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
93 InstrItinData<IIC_iMUL32 , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>,
94 InstrItinData<IIC_iMAC32 , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
95 InstrItinData<IIC_iMUL64 , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
96 InstrItinData<IIC_iMAC64 , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
98 // Integer load pipeline
101 InstrItinData<IIC_iLoad_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
102 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
103 InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
104 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
105 InstrItinData<IIC_iLoad_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
106 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
109 InstrItinData<IIC_iLoad_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
110 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
111 InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
112 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
113 InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
114 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
116 // Scaled register offset, issues over 2 cycles
117 // FIXME: lsl by 2 takes 1 cycle.
118 InstrItinData<IIC_iLoad_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
119 InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
120 InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
121 InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
123 // Immediate offset with update
124 InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
125 InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
126 InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
127 InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
129 // Register offset with update
130 InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
131 InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
132 InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
133 InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
134 InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
135 InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
137 // Scaled register offset with update, issues over 2 cycles
138 InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
139 InstrStage<1, [A8_LSPipe]>], [4, 3, 1, 1]>,
140 InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
141 InstrStage<1, [A8_LSPipe]>], [4, 3, 1, 1]>,
143 // Load multiple, def is the 5th operand. Pipeline 0 only.
144 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
145 InstrItinData<IIC_iLoad_m , [InstrStage<1, [A8_Pipe0]>,
146 InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1, 3]>,
148 // Load multiple + update, defs are the 1st and 5th operands.
149 InstrItinData<IIC_iLoad_mu , [InstrStage<1, [A8_Pipe0]>,
150 InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 3]>,
152 // Load multiple plus branch
153 InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [A8_Pipe0]>,
154 InstrStage<3, [A8_LSPipe]>,
155 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
158 // Pop, def is the 3rd operand.
159 InstrItinData<IIC_iPop , [InstrStage<1, [A8_Pipe0]>,
160 InstrStage<3, [A8_LSPipe]>], [1, 1, 3]>,
162 // Push, def is the 3th operand.
163 InstrItinData<IIC_iPop_Br, [InstrStage<1, [A8_Pipe0]>,
164 InstrStage<3, [A8_LSPipe]>,
165 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
169 // iLoadi + iALUr for t2LDRpci_pic.
170 InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
171 InstrStage<1, [A8_LSPipe]>,
172 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
175 // Integer store pipeline
178 InstrItinData<IIC_iStore_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
179 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
180 InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
181 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
182 InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
183 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
186 InstrItinData<IIC_iStore_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
187 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
188 InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
189 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
190 InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
191 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
193 // Scaled register offset, issues over 2 cycles
194 InstrItinData<IIC_iStore_si , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
195 InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
196 InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
197 InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
199 // Immediate offset with update
200 InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
201 InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
202 InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
203 InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
205 // Register offset with update
206 InstrItinData<IIC_iStore_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
207 InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
208 InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
209 InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
210 InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
211 InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
213 // Scaled register offset with update, issues over 2 cycles
214 InstrItinData<IIC_iStore_siu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
215 InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
216 InstrItinData<IIC_iStore_bh_siu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
217 InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
219 // Store multiple. Pipeline 0 only.
220 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
221 InstrItinData<IIC_iStore_m , [InstrStage<1, [A8_Pipe0]>,
222 InstrStage<2, [A8_LSPipe]>]>,
224 // Store multiple + update
225 InstrItinData<IIC_iStore_mu, [InstrStage<1, [A8_Pipe0]>,
226 InstrStage<2, [A8_LSPipe]>], [2]>,
230 // no delay slots, so the latency of a branch is unimportant
231 InstrItinData<IIC_Br , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
234 // Issue through integer pipeline, and execute in NEON unit. We assume
235 // RunFast mode so that NFP pipeline is used for single-precision when
238 // FP Special Register to Integer Register File Move
239 InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
240 InstrStage<1, [A8_NLSPipe]>]>,
242 // Single-precision FP Unary
243 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
244 InstrStage<1, [A8_NPipe]>], [7, 1]>,
246 // Double-precision FP Unary
247 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
248 InstrStage<4, [A8_NPipe], 0>,
249 InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
251 // Single-precision FP Compare
252 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
253 InstrStage<1, [A8_NPipe]>], [1, 1]>,
255 // Double-precision FP Compare
256 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
257 InstrStage<4, [A8_NPipe], 0>,
258 InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
260 // Single to Double FP Convert
261 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
262 InstrStage<7, [A8_NPipe], 0>,
263 InstrStage<7, [A8_NLSPipe]>], [7, 1]>,
265 // Double to Single FP Convert
266 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
267 InstrStage<5, [A8_NPipe], 0>,
268 InstrStage<5, [A8_NLSPipe]>], [5, 1]>,
270 // Single-Precision FP to Integer Convert
271 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
272 InstrStage<1, [A8_NPipe]>], [7, 1]>,
274 // Double-Precision FP to Integer Convert
275 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
276 InstrStage<8, [A8_NPipe], 0>,
277 InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
279 // Integer to Single-Precision FP Convert
280 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
281 InstrStage<1, [A8_NPipe]>], [7, 1]>,
283 // Integer to Double-Precision FP Convert
284 InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
285 InstrStage<8, [A8_NPipe], 0>,
286 InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
288 // Single-precision FP ALU
289 InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
290 InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
292 // Double-precision FP ALU
293 InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
294 InstrStage<9, [A8_NPipe], 0>,
295 InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>,
297 // Single-precision FP Multiply
298 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
299 InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
301 // Double-precision FP Multiply
302 InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
303 InstrStage<11, [A8_NPipe], 0>,
304 InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>,
306 // Single-precision FP MAC
307 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
308 InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
310 // Double-precision FP MAC
311 InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
312 InstrStage<19, [A8_NPipe], 0>,
313 InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
315 // Single-precision FP DIV
316 InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
317 InstrStage<20, [A8_NPipe], 0>,
318 InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>,
320 // Double-precision FP DIV
321 InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
322 InstrStage<29, [A8_NPipe], 0>,
323 InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>,
325 // Single-precision FP SQRT
326 InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
327 InstrStage<19, [A8_NPipe], 0>,
328 InstrStage<19, [A8_NLSPipe]>], [19, 1]>,
330 // Double-precision FP SQRT
331 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
332 InstrStage<29, [A8_NPipe], 0>,
333 InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
335 // Single-precision FP Load
336 InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
337 InstrStage<1, [A8_NLSPipe]>,
338 InstrStage<1, [A8_LSPipe]>],
341 // Double-precision FP Load
342 InstrItinData<IIC_fpLoad64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
343 InstrStage<1, [A8_NLSPipe]>,
344 InstrStage<1, [A8_LSPipe]>],
348 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
349 InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
350 InstrStage<1, [A8_NLSPipe]>,
351 InstrStage<1, [A8_LSPipe]>,
352 InstrStage<1, [A8_NLSPipe]>,
353 InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 2]>,
355 // FP Load Multiple + update
356 InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
357 InstrStage<1, [A8_NLSPipe]>,
358 InstrStage<1, [A8_LSPipe]>,
359 InstrStage<1, [A8_NLSPipe]>,
360 InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 2]>,
362 // Single-precision FP Store
363 InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
364 InstrStage<1, [A8_NLSPipe]>,
365 InstrStage<1, [A8_LSPipe]>],
368 // Double-precision FP Store
369 InstrItinData<IIC_fpStore64,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
370 InstrStage<1, [A8_NLSPipe]>,
371 InstrStage<1, [A8_LSPipe]>],
375 InstrItinData<IIC_fpStore_m,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
376 InstrStage<1, [A8_NLSPipe]>,
377 InstrStage<1, [A8_LSPipe]>,
378 InstrStage<1, [A8_NLSPipe]>,
379 InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 1]>,
381 // FP Store Multiple + update
382 InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
383 InstrStage<1, [A8_NLSPipe]>,
384 InstrStage<1, [A8_LSPipe]>,
385 InstrStage<1, [A8_NLSPipe]>,
386 InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 1]>,
389 // Issue through integer pipeline, and execute in NEON unit.
392 InstrItinData<IIC_VLD1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
393 InstrStage<1, [A8_NLSPipe], 1>,
394 InstrStage<1, [A8_LSPipe]>]>,
396 InstrItinData<IIC_VLD1x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
397 InstrStage<2, [A8_NLSPipe], 1>,
398 InstrStage<2, [A8_LSPipe]>],
402 InstrItinData<IIC_VLD1x3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
403 InstrStage<3, [A8_NLSPipe], 1>,
404 InstrStage<3, [A8_LSPipe]>],
408 InstrItinData<IIC_VLD1x4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
409 InstrStage<3, [A8_NLSPipe], 1>,
410 InstrStage<3, [A8_LSPipe]>],
414 InstrItinData<IIC_VLD1u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
415 InstrStage<1, [A8_NLSPipe], 1>,
416 InstrStage<1, [A8_LSPipe]>],
420 InstrItinData<IIC_VLD1x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
421 InstrStage<2, [A8_NLSPipe], 1>,
422 InstrStage<2, [A8_LSPipe]>],
426 InstrItinData<IIC_VLD1x3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
427 InstrStage<3, [A8_NLSPipe], 1>,
428 InstrStage<3, [A8_LSPipe]>],
432 InstrItinData<IIC_VLD1x4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
433 InstrStage<3, [A8_NLSPipe], 1>,
434 InstrStage<3, [A8_LSPipe]>],
438 InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
439 InstrStage<1, [A8_NLSPipe], 1>,
440 InstrStage<1, [A8_LSPipe]>],
444 InstrItinData<IIC_VLD2x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
445 InstrStage<3, [A8_NLSPipe], 1>,
446 InstrStage<3, [A8_LSPipe]>],
450 InstrItinData<IIC_VLD2ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
451 InstrStage<3, [A8_NLSPipe], 1>,
452 InstrStage<3, [A8_LSPipe]>],
456 InstrItinData<IIC_VLD2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
457 InstrStage<1, [A8_NLSPipe], 1>,
458 InstrStage<1, [A8_LSPipe]>],
462 InstrItinData<IIC_VLD2x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
463 InstrStage<3, [A8_NLSPipe], 1>,
464 InstrStage<3, [A8_LSPipe]>],
468 InstrItinData<IIC_VLD2lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
469 InstrStage<3, [A8_NLSPipe], 1>,
470 InstrStage<3, [A8_LSPipe]>],
471 [3, 3, 2, 1, 1, 1, 1, 1]>,
474 InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
475 InstrStage<4, [A8_NLSPipe], 1>,
476 InstrStage<4, [A8_LSPipe]>],
480 InstrItinData<IIC_VLD3ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
481 InstrStage<5, [A8_NLSPipe], 1>,
482 InstrStage<5, [A8_LSPipe]>],
483 [4, 4, 5, 1, 1, 1, 1, 2]>,
486 InstrItinData<IIC_VLD3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
487 InstrStage<4, [A8_NLSPipe], 1>,
488 InstrStage<4, [A8_LSPipe]>],
492 InstrItinData<IIC_VLD3lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
493 InstrStage<5, [A8_NLSPipe], 1>,
494 InstrStage<5, [A8_LSPipe]>],
495 [4, 4, 5, 2, 1, 1, 1, 1, 1, 2]>,
498 InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
499 InstrStage<4, [A8_NLSPipe], 1>,
500 InstrStage<4, [A8_LSPipe]>],
504 InstrItinData<IIC_VLD4ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
505 InstrStage<5, [A8_NLSPipe], 1>,
506 InstrStage<5, [A8_LSPipe]>],
507 [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>,
510 InstrItinData<IIC_VLD4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
511 InstrStage<4, [A8_NLSPipe], 1>,
512 InstrStage<4, [A8_LSPipe]>],
516 InstrItinData<IIC_VLD4lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
517 InstrStage<5, [A8_NLSPipe], 1>,
518 InstrStage<5, [A8_LSPipe]>],
519 [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>,
522 // FIXME: We don't model this instruction properly
523 InstrItinData<IIC_VST, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
524 InstrStage<1, [A8_NLSPipe]>,
525 InstrStage<1, [A8_LSPipe]>]>,
527 // Double-register FP Unary
528 InstrItinData<IIC_VUNAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
529 InstrStage<1, [A8_NPipe]>], [5, 2]>,
531 // Quad-register FP Unary
532 // Result written in N5, but that is relative to the last cycle of multicycle,
533 // so we use 6 for those cases
534 InstrItinData<IIC_VUNAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
535 InstrStage<2, [A8_NPipe]>], [6, 2]>,
537 // Double-register FP Binary
538 InstrItinData<IIC_VBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
539 InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
541 // Quad-register FP Binary
542 // Result written in N5, but that is relative to the last cycle of multicycle,
543 // so we use 6 for those cases
544 InstrItinData<IIC_VBINQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
545 InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
548 InstrItinData<IIC_VMOV, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
549 InstrStage<1, [A8_NPipe]>], [1, 1]>,
552 InstrItinData<IIC_VMOVImm, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
553 InstrStage<1, [A8_NPipe]>], [3]>,
555 // Double-register Permute Move
556 InstrItinData<IIC_VMOVD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
557 InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
559 // Quad-register Permute Move
560 // Result written in N2, but that is relative to the last cycle of multicycle,
561 // so we use 3 for those cases
562 InstrItinData<IIC_VMOVQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
563 InstrStage<2, [A8_NLSPipe]>], [3, 1]>,
565 // Integer to Single-precision Move
566 InstrItinData<IIC_VMOVIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
567 InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
569 // Integer to Double-precision Move
570 InstrItinData<IIC_VMOVID , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
571 InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
573 // Single-precision to Integer Move
574 InstrItinData<IIC_VMOVSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
575 InstrStage<1, [A8_NLSPipe]>], [20, 1]>,
577 // Double-precision to Integer Move
578 InstrItinData<IIC_VMOVDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
579 InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>,
581 // Integer to Lane Move
582 InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
583 InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
585 // Vector narrow move
586 InstrItinData<IIC_VMOVN , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
587 InstrStage<1, [A8_NPipe]>], [2, 1]>,
589 // Double-register Permute
590 InstrItinData<IIC_VPERMD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
591 InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
593 // Quad-register Permute
594 // Result written in N2, but that is relative to the last cycle of multicycle,
595 // so we use 3 for those cases
596 InstrItinData<IIC_VPERMQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
597 InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>,
599 // Quad-register Permute (3 cycle issue)
600 // Result written in N2, but that is relative to the last cycle of multicycle,
601 // so we use 4 for those cases
602 InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
603 InstrStage<1, [A8_NLSPipe]>,
604 InstrStage<1, [A8_NPipe], 0>,
605 InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>,
607 // Double-register FP Multiple-Accumulate
608 InstrItinData<IIC_VMACD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
609 InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
611 // Quad-register FP Multiple-Accumulate
612 // Result written in N9, but that is relative to the last cycle of multicycle,
613 // so we use 10 for those cases
614 InstrItinData<IIC_VMACQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
615 InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
617 // Double-register Reciprical Step
618 InstrItinData<IIC_VRECSD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
619 InstrStage<1, [A8_NPipe]>], [9, 2, 2]>,
621 // Quad-register Reciprical Step
622 InstrItinData<IIC_VRECSQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
623 InstrStage<2, [A8_NPipe]>], [10, 2, 2]>,
625 // Double-register Integer Count
626 InstrItinData<IIC_VCNTiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
627 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
629 // Quad-register Integer Count
630 // Result written in N3, but that is relative to the last cycle of multicycle,
631 // so we use 4 for those cases
632 InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
633 InstrStage<2, [A8_NPipe]>], [4, 2, 2]>,
635 // Double-register Integer Unary
636 InstrItinData<IIC_VUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
637 InstrStage<1, [A8_NPipe]>], [4, 2]>,
639 // Quad-register Integer Unary
640 InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
641 InstrStage<1, [A8_NPipe]>], [4, 2]>,
643 // Double-register Integer Q-Unary
644 InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
645 InstrStage<1, [A8_NPipe]>], [4, 1]>,
647 // Quad-register Integer CountQ-Unary
648 InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
649 InstrStage<1, [A8_NPipe]>], [4, 1]>,
651 // Double-register Integer Binary
652 InstrItinData<IIC_VBINiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
653 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
655 // Quad-register Integer Binary
656 InstrItinData<IIC_VBINiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
657 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
659 // Double-register Integer Binary (4 cycle)
660 InstrItinData<IIC_VBINi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
661 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
663 // Quad-register Integer Binary (4 cycle)
664 InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
665 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
668 // Double-register Integer Subtract
669 InstrItinData<IIC_VSUBiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
670 InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
672 // Quad-register Integer Subtract
673 InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
674 InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
676 // Double-register Integer Subtract
677 InstrItinData<IIC_VSUBi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
678 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
680 // Quad-register Integer Subtract
681 InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
682 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
684 // Double-register Integer Shift
685 InstrItinData<IIC_VSHLiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
686 InstrStage<1, [A8_NPipe]>], [3, 1, 1]>,
688 // Quad-register Integer Shift
689 InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
690 InstrStage<2, [A8_NPipe]>], [4, 1, 1]>,
692 // Double-register Integer Shift (4 cycle)
693 InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
694 InstrStage<1, [A8_NPipe]>], [4, 1, 1]>,
696 // Quad-register Integer Shift (4 cycle)
697 InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
698 InstrStage<2, [A8_NPipe]>], [5, 1, 1]>,
700 // Double-register Integer Pair Add Long
701 InstrItinData<IIC_VPALiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
702 InstrStage<1, [A8_NPipe]>], [6, 3, 1]>,
704 // Quad-register Integer Pair Add Long
705 InstrItinData<IIC_VPALiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
706 InstrStage<2, [A8_NPipe]>], [7, 3, 1]>,
708 // Double-register Absolute Difference and Accumulate
709 InstrItinData<IIC_VABAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
710 InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>,
712 // Quad-register Absolute Difference and Accumulate
713 InstrItinData<IIC_VABAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
714 InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>,
717 // Double-register Integer Multiply (.8, .16)
718 InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
719 InstrStage<1, [A8_NPipe]>], [6, 2, 2]>,
721 // Double-register Integer Multiply (.32)
722 InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
723 InstrStage<2, [A8_NPipe]>], [7, 2, 1]>,
725 // Quad-register Integer Multiply (.8, .16)
726 InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
727 InstrStage<2, [A8_NPipe]>], [7, 2, 2]>,
729 // Quad-register Integer Multiply (.32)
730 InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
731 InstrStage<1, [A8_NPipe]>,
732 InstrStage<2, [A8_NLSPipe], 0>,
733 InstrStage<3, [A8_NPipe]>], [9, 2, 1]>,
735 // Double-register Integer Multiply-Accumulate (.8, .16)
736 InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
737 InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>,
739 // Double-register Integer Multiply-Accumulate (.32)
740 InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
741 InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>,
743 // Quad-register Integer Multiply-Accumulate (.8, .16)
744 InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
745 InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>,
747 // Quad-register Integer Multiply-Accumulate (.32)
748 InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
749 InstrStage<1, [A8_NPipe]>,
750 InstrStage<2, [A8_NLSPipe], 0>,
751 InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>,
753 // Double-register VEXT
754 InstrItinData<IIC_VEXTD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
755 InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
757 // Quad-register VEXT
758 InstrItinData<IIC_VEXTQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
759 InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
762 InstrItinData<IIC_VTB1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
763 InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>,
764 InstrItinData<IIC_VTB2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
765 InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>,
766 InstrItinData<IIC_VTB3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
767 InstrStage<1, [A8_NLSPipe]>,
768 InstrStage<1, [A8_NPipe], 0>,
769 InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>,
770 InstrItinData<IIC_VTB4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
771 InstrStage<1, [A8_NLSPipe]>,
772 InstrStage<1, [A8_NPipe], 0>,
773 InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>,
776 InstrItinData<IIC_VTBX1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
777 InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>,
778 InstrItinData<IIC_VTBX2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
779 InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>,
780 InstrItinData<IIC_VTBX3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
781 InstrStage<1, [A8_NLSPipe]>,
782 InstrStage<1, [A8_NPipe], 0>,
783 InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>,
784 InstrItinData<IIC_VTBX4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
785 InstrStage<1, [A8_NLSPipe]>,
786 InstrStage<1, [A8_NPipe], 0>,
787 InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>