1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
12 //===----------------------------------------------------------------------===//
15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
17 def A8_Issue : FuncUnit; // issue
18 def A8_Pipe0 : FuncUnit; // pipeline 0
19 def A8_Pipe1 : FuncUnit; // pipeline 1
20 def A8_LdSt0 : FuncUnit; // pipeline 0 load/store
21 def A8_LdSt1 : FuncUnit; // pipeline 1 load/store
22 def A8_NPipe : FuncUnit; // NEON ALU/MUL pipe
23 def A8_NLSPipe : FuncUnit; // NEON LS pipe
25 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
27 def CortexA8Itineraries : ProcessorItineraries<
28 [A8_Issue, A8_Pipe0, A8_Pipe1, A8_LdSt0, A8_LdSt1, A8_NPipe, A8_NLSPipe],
30 // Two fully-pipelined integer ALU pipelines
33 InstrItinData<IIC_iALUx , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
35 // Binary Instructions that produce a result
36 InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
37 InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
38 InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
39 InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
40 InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
42 // Bitwise Instructions that produce a result
43 InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
44 InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
45 InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
46 InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
48 // Unary Instructions that produce a result
49 InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
50 InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
52 // Zero and sign extension instructions
53 InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
54 InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
55 InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>,
57 // Compare instructions
58 InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
59 InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
60 InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
61 InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
64 InstrItinData<IIC_iTSTi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
65 InstrItinData<IIC_iTSTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
66 InstrItinData<IIC_iTSTsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
67 InstrItinData<IIC_iTSTsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
69 // Move instructions, unconditional
70 InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
71 InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
72 InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
73 InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
74 InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
75 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
77 // Move instructions, conditional
78 InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
79 InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
80 InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
81 InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
84 InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
85 InstrItinData<IIC_iMVNr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
86 InstrItinData<IIC_iMVNsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
87 InstrItinData<IIC_iMVNsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
89 // Integer multiply pipeline
90 // Result written in E5, but that is relative to the last cycle of multicycle,
91 // so we use 6 for those cases
93 InstrItinData<IIC_iMUL16 , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>,
94 InstrItinData<IIC_iMAC16 , [InstrStage<1, [A8_Pipe1], 0>,
95 InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
96 InstrItinData<IIC_iMUL32 , [InstrStage<1, [A8_Pipe1], 0>,
97 InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>,
98 InstrItinData<IIC_iMAC32 , [InstrStage<1, [A8_Pipe1], 0>,
99 InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
100 InstrItinData<IIC_iMUL64 , [InstrStage<2, [A8_Pipe1], 0>,
101 InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
102 InstrItinData<IIC_iMAC64 , [InstrStage<2, [A8_Pipe1], 0>,
103 InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
105 // Integer load pipeline
107 // loads have an extra cycle of latency, but are fully pipelined
108 // use A8_Issue to enforce the 1 load/store per cycle limit
111 InstrItinData<IIC_iLoad_i , [InstrStage<1, [A8_Issue], 0>,
112 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
113 InstrStage<1, [A8_LdSt0]>], [3, 1]>,
114 InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Issue], 0>,
115 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
116 InstrStage<1, [A8_LdSt0]>], [3, 1]>,
117 InstrItinData<IIC_iLoad_d_i, [InstrStage<1, [A8_Issue], 0>,
118 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
119 InstrStage<1, [A8_LdSt0]>], [3, 1]>,
122 InstrItinData<IIC_iLoad_r , [InstrStage<1, [A8_Issue], 0>,
123 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
124 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
125 InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Issue], 0>,
126 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
127 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
128 InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Issue], 0>,
129 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
130 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
132 // Scaled register offset, issues over 2 cycles
133 InstrItinData<IIC_iLoad_si , [InstrStage<2, [A8_Issue], 0>,
134 InstrStage<1, [A8_Pipe0], 0>,
135 InstrStage<1, [A8_Pipe1]>,
136 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
137 InstrStage<1, [A8_LdSt0]>], [4, 1, 1]>,
138 InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Issue], 0>,
139 InstrStage<1, [A8_Pipe0], 0>,
140 InstrStage<1, [A8_Pipe1]>,
141 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
142 InstrStage<1, [A8_LdSt0]>], [4, 1, 1]>,
144 // Immediate offset with update
145 InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A8_Issue], 0>,
146 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
147 InstrStage<1, [A8_LdSt0]>], [3, 2, 1]>,
148 InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Issue], 0>,
149 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
150 InstrStage<1, [A8_LdSt0]>], [3, 2, 1]>,
152 // Register offset with update
153 InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A8_Issue], 0>,
154 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
155 InstrStage<1, [A8_LdSt0]>], [3, 2, 1, 1]>,
156 InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Issue], 0>,
157 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
158 InstrStage<1, [A8_LdSt0]>], [3, 2, 1, 1]>,
159 InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Issue], 0>,
160 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
161 InstrStage<1, [A8_LdSt0]>], [3, 2, 1, 1]>,
163 // Scaled register offset with update, issues over 2 cycles
164 InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Issue], 0>,
165 InstrStage<1, [A8_Pipe0], 0>,
166 InstrStage<1, [A8_Pipe1]>,
167 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
168 InstrStage<1, [A8_LdSt0]>], [4, 3, 1, 1]>,
169 InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Issue], 0>,
170 InstrStage<1, [A8_Pipe0], 0>,
171 InstrStage<1, [A8_Pipe1]>,
172 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
173 InstrStage<1, [A8_LdSt0]>], [4, 3, 1, 1]>,
176 InstrItinData<IIC_iLoadm , [InstrStage<2, [A8_Issue], 0>,
177 InstrStage<2, [A8_Pipe0], 0>,
178 InstrStage<2, [A8_Pipe1]>,
179 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
180 InstrStage<1, [A8_LdSt0]>]>,
183 // Load multiple plus branch
184 InstrItinData<IIC_iLoadmBr , [InstrStage<2, [A8_Issue], 0>,
185 InstrStage<2, [A8_Pipe0], 0>,
186 InstrStage<2, [A8_Pipe1]>,
187 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
188 InstrStage<1, [A8_LdSt0]>,
189 InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
192 // iLoadi + iALUr for t2LDRpci_pic.
193 InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Issue], 0>,
194 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
195 InstrStage<1, [A8_LdSt0]>,
196 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
199 // Integer store pipeline
201 // use A8_Issue to enforce the 1 load/store per cycle limit
204 InstrItinData<IIC_iStore_i , [InstrStage<1, [A8_Issue], 0>,
205 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
206 InstrStage<1, [A8_LdSt0]>], [3, 1]>,
207 InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Issue], 0>,
208 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
209 InstrStage<1, [A8_LdSt0]>], [3, 1]>,
210 InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Issue], 0>,
211 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
212 InstrStage<1, [A8_LdSt0]>], [3, 1]>,
215 InstrItinData<IIC_iStore_r , [InstrStage<1, [A8_Issue], 0>,
216 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
217 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
218 InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Issue], 0>,
219 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
220 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
221 InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Issue], 0>,
222 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
223 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
225 // Scaled register offset, issues over 2 cycles
226 InstrItinData<IIC_iStore_si , [InstrStage<2, [A8_Issue], 0>,
227 InstrStage<1, [A8_Pipe0], 0>,
228 InstrStage<1, [A8_Pipe1]>,
229 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
230 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
231 InstrItinData<IIC_iStore_bh_si,[InstrStage<2, [A8_Issue], 0>,
232 InstrStage<1, [A8_Pipe0], 0>,
233 InstrStage<1, [A8_Pipe1]>,
234 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
235 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
237 // Immediate offset with update
238 InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Issue], 0>,
239 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
240 InstrStage<1, [A8_LdSt0]>], [2, 3, 1]>,
241 InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Issue], 0>,
242 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
243 InstrStage<1, [A8_LdSt0]>], [2, 3, 1]>,
245 // Register offset with update
246 InstrItinData<IIC_iStore_ru , [InstrStage<1, [A8_Issue], 0>,
247 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
248 InstrStage<1, [A8_LdSt0]>], [2, 3, 1, 1]>,
249 InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Issue], 0>,
250 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
251 InstrStage<1, [A8_LdSt0]>], [2, 3, 1, 1]>,
252 InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Issue], 0>,
253 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
254 InstrStage<1, [A8_LdSt0]>], [2, 3, 1, 1]>,
256 // Scaled register offset with update, issues over 2 cycles
257 InstrItinData<IIC_iStore_siu, [InstrStage<2, [A8_Issue], 0>,
258 InstrStage<1, [A8_Pipe0], 0>,
259 InstrStage<1, [A8_Pipe1]>,
260 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
261 InstrStage<1, [A8_LdSt0]>], [3, 3, 1, 1]>,
262 InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [A8_Issue], 0>,
263 InstrStage<1, [A8_Pipe0], 0>,
264 InstrStage<1, [A8_Pipe1]>,
265 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
266 InstrStage<1, [A8_LdSt0]>], [3, 3, 1, 1]>,
269 InstrItinData<IIC_iStorem , [InstrStage<2, [A8_Issue], 0>,
270 InstrStage<2, [A8_Pipe0], 0>,
271 InstrStage<2, [A8_Pipe1]>,
272 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
273 InstrStage<1, [A8_LdSt0]>]>,
277 // no delay slots, so the latency of a branch is unimportant
278 InstrItinData<IIC_Br , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
281 // Issue through integer pipeline, and execute in NEON unit. We assume
282 // RunFast mode so that NFP pipeline is used for single-precision when
285 // FP Special Register to Integer Register File Move
286 InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
287 InstrStage<1, [A8_NLSPipe]>]>,
289 // Single-precision FP Unary
290 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
291 InstrStage<1, [A8_NPipe]>], [7, 1]>,
293 // Double-precision FP Unary
294 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
295 InstrStage<4, [A8_NPipe], 0>,
296 InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
298 // Single-precision FP Compare
299 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
300 InstrStage<1, [A8_NPipe]>], [1, 1]>,
302 // Double-precision FP Compare
303 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
304 InstrStage<4, [A8_NPipe], 0>,
305 InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
307 // Single to Double FP Convert
308 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
309 InstrStage<7, [A8_NPipe], 0>,
310 InstrStage<7, [A8_NLSPipe]>], [7, 1]>,
312 // Double to Single FP Convert
313 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
314 InstrStage<5, [A8_NPipe], 0>,
315 InstrStage<5, [A8_NLSPipe]>], [5, 1]>,
317 // Single-Precision FP to Integer Convert
318 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
319 InstrStage<1, [A8_NPipe]>], [7, 1]>,
321 // Double-Precision FP to Integer Convert
322 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
323 InstrStage<8, [A8_NPipe], 0>,
324 InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
326 // Integer to Single-Precision FP Convert
327 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
328 InstrStage<1, [A8_NPipe]>], [7, 1]>,
330 // Integer to Double-Precision FP Convert
331 InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
332 InstrStage<8, [A8_NPipe], 0>,
333 InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
335 // Single-precision FP ALU
336 InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
337 InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
339 // Double-precision FP ALU
340 InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
341 InstrStage<9, [A8_NPipe], 0>,
342 InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>,
344 // Single-precision FP Multiply
345 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
346 InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
348 // Double-precision FP Multiply
349 InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
350 InstrStage<11, [A8_NPipe], 0>,
351 InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>,
353 // Single-precision FP MAC
354 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
355 InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
357 // Double-precision FP MAC
358 InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
359 InstrStage<19, [A8_NPipe], 0>,
360 InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
362 // Single-precision FP DIV
363 InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
364 InstrStage<20, [A8_NPipe], 0>,
365 InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>,
367 // Double-precision FP DIV
368 InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
369 InstrStage<29, [A8_NPipe], 0>,
370 InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>,
372 // Single-precision FP SQRT
373 InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
374 InstrStage<19, [A8_NPipe], 0>,
375 InstrStage<19, [A8_NLSPipe]>], [19, 1]>,
377 // Double-precision FP SQRT
378 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
379 InstrStage<29, [A8_NPipe], 0>,
380 InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
382 // Single-precision FP Load
383 // use A8_Issue to enforce the 1 load/store per cycle limit
384 InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Issue], 0>,
385 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
386 InstrStage<1, [A8_LdSt0], 0>,
387 InstrStage<1, [A8_NLSPipe]>]>,
389 // Double-precision FP Load
390 // use A8_Issue to enforce the 1 load/store per cycle limit
391 InstrItinData<IIC_fpLoad64, [InstrStage<2, [A8_Issue], 0>,
392 InstrStage<1, [A8_Pipe0], 0>,
393 InstrStage<1, [A8_Pipe1]>,
394 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
395 InstrStage<1, [A8_LdSt0], 0>,
396 InstrStage<1, [A8_NLSPipe]>]>,
399 // use A8_Issue to enforce the 1 load/store per cycle limit
400 InstrItinData<IIC_fpLoadm, [InstrStage<3, [A8_Issue], 0>,
401 InstrStage<2, [A8_Pipe0], 0>,
402 InstrStage<2, [A8_Pipe1]>,
403 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
404 InstrStage<1, [A8_LdSt0], 0>,
405 InstrStage<1, [A8_NLSPipe]>]>,
407 // Single-precision FP Store
408 // use A8_Issue to enforce the 1 load/store per cycle limit
409 InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Issue], 0>,
410 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
411 InstrStage<1, [A8_LdSt0], 0>,
412 InstrStage<1, [A8_NLSPipe]>]>,
414 // Double-precision FP Store
415 // use A8_Issue to enforce the 1 load/store per cycle limit
416 InstrItinData<IIC_fpStore64,[InstrStage<2, [A8_Issue], 0>,
417 InstrStage<1, [A8_Pipe0], 0>,
418 InstrStage<1, [A8_Pipe1]>,
419 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
420 InstrStage<1, [A8_LdSt0], 0>,
421 InstrStage<1, [A8_NLSPipe]>]>,
424 // use A8_Issue to enforce the 1 load/store per cycle limit
425 InstrItinData<IIC_fpStorem, [InstrStage<3, [A8_Issue], 0>,
426 InstrStage<2, [A8_Pipe0], 0>,
427 InstrStage<2, [A8_Pipe1]>,
428 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
429 InstrStage<1, [A8_LdSt0], 0>,
430 InstrStage<1, [A8_NLSPipe]>]>,
433 // Issue through integer pipeline, and execute in NEON unit.
436 // FIXME: We don't model this instruction properly
437 InstrItinData<IIC_VLD1, [InstrStage<1, [A8_Issue], 0>,
438 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
439 InstrStage<1, [A8_LdSt0], 0>,
440 InstrStage<1, [A8_NLSPipe]>]>,
443 // FIXME: We don't model this instruction properly
444 InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Issue], 0>,
445 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
446 InstrStage<1, [A8_LdSt0], 0>,
447 InstrStage<1, [A8_NLSPipe]>], [2, 2, 1]>,
450 // FIXME: We don't model this instruction properly
451 InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Issue], 0>,
452 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
453 InstrStage<1, [A8_LdSt0], 0>,
454 InstrStage<1, [A8_NLSPipe]>], [2, 2, 2, 1]>,
457 // FIXME: We don't model this instruction properly
458 InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Issue], 0>,
459 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
460 InstrStage<1, [A8_LdSt0], 0>,
461 InstrStage<1, [A8_NLSPipe]>], [2, 2, 2, 2, 1]>,
464 // FIXME: We don't model this instruction properly
465 InstrItinData<IIC_VST, [InstrStage<1, [A8_Issue], 0>,
466 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
467 InstrStage<1, [A8_LdSt0], 0>,
468 InstrStage<1, [A8_NLSPipe]>]>,
470 // Double-register FP Unary
471 InstrItinData<IIC_VUNAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
472 InstrStage<1, [A8_NPipe]>], [5, 2]>,
474 // Quad-register FP Unary
475 // Result written in N5, but that is relative to the last cycle of multicycle,
476 // so we use 6 for those cases
477 InstrItinData<IIC_VUNAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
478 InstrStage<2, [A8_NPipe]>], [6, 2]>,
480 // Double-register FP Binary
481 InstrItinData<IIC_VBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
482 InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
484 // Quad-register FP Binary
485 // Result written in N5, but that is relative to the last cycle of multicycle,
486 // so we use 6 for those cases
487 InstrItinData<IIC_VBINQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
488 InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
491 InstrItinData<IIC_VMOVImm, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
492 InstrStage<1, [A8_NPipe]>], [3]>,
494 // Double-register Permute Move
495 InstrItinData<IIC_VMOVD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
496 InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
498 // Quad-register Permute Move
499 // Result written in N2, but that is relative to the last cycle of multicycle,
500 // so we use 3 for those cases
501 InstrItinData<IIC_VMOVQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
502 InstrStage<2, [A8_NLSPipe]>], [3, 1]>,
504 // Integer to Single-precision Move
505 InstrItinData<IIC_VMOVIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
506 InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
508 // Integer to Double-precision Move
509 InstrItinData<IIC_VMOVID , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
510 InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
512 // Single-precision to Integer Move
513 InstrItinData<IIC_VMOVSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
514 InstrStage<1, [A8_NLSPipe]>], [20, 1]>,
516 // Double-precision to Integer Move
517 InstrItinData<IIC_VMOVDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
518 InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>,
520 // Integer to Lane Move
521 InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
522 InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
524 // Double-register Permute
525 InstrItinData<IIC_VPERMD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
526 InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
528 // Quad-register Permute
529 // Result written in N2, but that is relative to the last cycle of multicycle,
530 // so we use 3 for those cases
531 InstrItinData<IIC_VPERMQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
532 InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>,
534 // Quad-register Permute (3 cycle issue)
535 // Result written in N2, but that is relative to the last cycle of multicycle,
536 // so we use 4 for those cases
537 InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
538 InstrStage<1, [A8_NLSPipe]>,
539 InstrStage<1, [A8_NPipe], 0>,
540 InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>,
542 // Double-register FP Multiple-Accumulate
543 InstrItinData<IIC_VMACD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
544 InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
546 // Quad-register FP Multiple-Accumulate
547 // Result written in N9, but that is relative to the last cycle of multicycle,
548 // so we use 10 for those cases
549 InstrItinData<IIC_VMACQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
550 InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
552 // Double-register Reciprical Step
553 InstrItinData<IIC_VRECSD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
554 InstrStage<1, [A8_NPipe]>], [9, 2, 2]>,
556 // Quad-register Reciprical Step
557 InstrItinData<IIC_VRECSQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
558 InstrStage<2, [A8_NPipe]>], [10, 2, 2]>,
560 // Double-register Integer Count
561 InstrItinData<IIC_VCNTiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
562 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
564 // Quad-register Integer Count
565 // Result written in N3, but that is relative to the last cycle of multicycle,
566 // so we use 4 for those cases
567 InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
568 InstrStage<2, [A8_NPipe]>], [4, 2, 2]>,
570 // Double-register Integer Unary
571 InstrItinData<IIC_VUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
572 InstrStage<1, [A8_NPipe]>], [4, 2]>,
574 // Quad-register Integer Unary
575 InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
576 InstrStage<1, [A8_NPipe]>], [4, 2]>,
578 // Double-register Integer Q-Unary
579 InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
580 InstrStage<1, [A8_NPipe]>], [4, 1]>,
582 // Quad-register Integer CountQ-Unary
583 InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
584 InstrStage<1, [A8_NPipe]>], [4, 1]>,
586 // Double-register Integer Binary
587 InstrItinData<IIC_VBINiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
588 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
590 // Quad-register Integer Binary
591 InstrItinData<IIC_VBINiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
592 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
594 // Double-register Integer Binary (4 cycle)
595 InstrItinData<IIC_VBINi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
596 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
598 // Quad-register Integer Binary (4 cycle)
599 InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
600 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
603 // Double-register Integer Subtract
604 InstrItinData<IIC_VSUBiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
605 InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
607 // Quad-register Integer Subtract
608 InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
609 InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
611 // Double-register Integer Subtract
612 InstrItinData<IIC_VSUBi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
613 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
615 // Quad-register Integer Subtract
616 InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
617 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
619 // Double-register Integer Shift
620 InstrItinData<IIC_VSHLiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
621 InstrStage<1, [A8_NPipe]>], [3, 1, 1]>,
623 // Quad-register Integer Shift
624 InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
625 InstrStage<2, [A8_NPipe]>], [4, 1, 1]>,
627 // Double-register Integer Shift (4 cycle)
628 InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
629 InstrStage<1, [A8_NPipe]>], [4, 1, 1]>,
631 // Quad-register Integer Shift (4 cycle)
632 InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
633 InstrStage<2, [A8_NPipe]>], [5, 1, 1]>,
635 // Double-register Integer Pair Add Long
636 InstrItinData<IIC_VPALiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
637 InstrStage<1, [A8_NPipe]>], [6, 3, 1]>,
639 // Quad-register Integer Pair Add Long
640 InstrItinData<IIC_VPALiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
641 InstrStage<2, [A8_NPipe]>], [7, 3, 1]>,
643 // Double-register Absolute Difference and Accumulate
644 InstrItinData<IIC_VABAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
645 InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>,
647 // Quad-register Absolute Difference and Accumulate
648 InstrItinData<IIC_VABAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
649 InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>,
652 // Double-register Integer Multiply (.8, .16)
653 InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
654 InstrStage<1, [A8_NPipe]>], [6, 2, 2]>,
656 // Double-register Integer Multiply (.32)
657 InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
658 InstrStage<2, [A8_NPipe]>], [7, 2, 1]>,
660 // Quad-register Integer Multiply (.8, .16)
661 InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
662 InstrStage<2, [A8_NPipe]>], [7, 2, 2]>,
664 // Quad-register Integer Multiply (.32)
665 InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
666 InstrStage<1, [A8_NPipe]>,
667 InstrStage<2, [A8_NLSPipe], 0>,
668 InstrStage<3, [A8_NPipe]>], [9, 2, 1]>,
670 // Double-register Integer Multiply-Accumulate (.8, .16)
671 InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
672 InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>,
674 // Double-register Integer Multiply-Accumulate (.32)
675 InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
676 InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>,
678 // Quad-register Integer Multiply-Accumulate (.8, .16)
679 InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
680 InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>,
682 // Quad-register Integer Multiply-Accumulate (.32)
683 InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
684 InstrStage<1, [A8_NPipe]>,
685 InstrStage<2, [A8_NLSPipe], 0>,
686 InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>,
688 // Double-register VEXT
689 InstrItinData<IIC_VEXTD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
690 InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
692 // Quad-register VEXT
693 InstrItinData<IIC_VEXTQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
694 InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
697 InstrItinData<IIC_VTB1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
698 InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>,
699 InstrItinData<IIC_VTB2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
700 InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>,
701 InstrItinData<IIC_VTB3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
702 InstrStage<1, [A8_NLSPipe]>,
703 InstrStage<1, [A8_NPipe], 0>,
704 InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>,
705 InstrItinData<IIC_VTB4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
706 InstrStage<1, [A8_NLSPipe]>,
707 InstrStage<1, [A8_NPipe], 0>,
708 InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>,
711 InstrItinData<IIC_VTBX1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
712 InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>,
713 InstrItinData<IIC_VTBX2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
714 InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>,
715 InstrItinData<IIC_VTBX3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
716 InstrStage<1, [A8_NLSPipe]>,
717 InstrStage<1, [A8_NPipe], 0>,
718 InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>,
719 InstrItinData<IIC_VTBX4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
720 InstrStage<1, [A8_NLSPipe]>,
721 InstrStage<1, [A8_NPipe], 0>,
722 InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>