1 //===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Functional units across ARM processors
13 def FU_Issue : FuncUnit; // issue
14 def FU_Pipe0 : FuncUnit; // pipeline 0
15 def FU_Pipe1 : FuncUnit; // pipeline 1
16 def FU_LdSt0 : FuncUnit; // pipeline 0 load/store
17 def FU_LdSt1 : FuncUnit; // pipeline 1 load/store
19 //===----------------------------------------------------------------------===//
20 // Instruction Itinerary classes used for ARM
22 def IIC_iALU : InstrItinClass;
23 def IIC_iMPYh : InstrItinClass;
24 def IIC_iMPYw : InstrItinClass;
25 def IIC_iMPYl : InstrItinClass;
26 def IIC_iLoad : InstrItinClass;
27 def IIC_iStore : InstrItinClass;
28 def IIC_fpALU : InstrItinClass;
29 def IIC_fpMPY : InstrItinClass;
30 def IIC_fpLoad : InstrItinClass;
31 def IIC_fpStore : InstrItinClass;
32 def IIC_Br : InstrItinClass;
34 //===----------------------------------------------------------------------===//
35 // Processor instruction itineraries.
37 def GenericItineraries : ProcessorItineraries<[
38 InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0]>]>,
39 InstrItinData<IIC_iMPYh , [InstrStage<1, [FU_Pipe0]>]>,
40 InstrItinData<IIC_iMPYw , [InstrStage<1, [FU_Pipe0]>]>,
41 InstrItinData<IIC_iMPYl , [InstrStage<1, [FU_Pipe0]>]>,
42 InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
43 InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0]>]>,
44 InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
45 InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>,
46 InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>,
47 InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
48 InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>
52 include "ARMScheduleV6.td"
53 include "ARMScheduleV7.td"