1 //===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMREGISTERINFO_H
15 #define ARMREGISTERINFO_H
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "ARMGenRegisterInfo.h.inc"
22 class TargetInstrInfo;
25 struct ARMRegisterInfo : public ARMGenRegisterInfo {
26 const TargetInstrInfo &TII;
27 const ARMSubtarget &STI;
29 /// FramePtr - ARM physical register used as frame ptr.
33 ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
35 /// emitLoadConstPool - Emits a load from constpool to materialize the
36 /// specified immediate.
37 void emitLoadConstPool(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator &MBBI,
39 unsigned DestReg, int Val,
40 unsigned Pred, unsigned PredReg,
41 const TargetInstrInfo *TII, bool isThumb) const;
43 /// getRegisterNumbering - Given the enum value for some register, e.g.
44 /// ARM::LR, return the number that it corresponds to (e.g. 14).
45 static unsigned getRegisterNumbering(unsigned RegEnum);
47 /// Same as previous getRegisterNumbering except it returns true in isSPVFP
48 /// if the register is a single precision VFP register.
49 static unsigned getRegisterNumbering(unsigned RegEnum, bool &isSPVFP);
51 /// getPointerRegClass - Return the register class to use to hold pointers.
52 /// This is used for addressing modes.
53 const TargetRegisterClass *getPointerRegClass() const;
55 /// Code Generation virtual methods...
56 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
58 const TargetRegisterClass* const*
59 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
61 BitVector getReservedRegs(const MachineFunction &MF) const;
63 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
65 bool requiresRegisterScavenging(const MachineFunction &MF) const;
67 bool hasFP(const MachineFunction &MF) const;
69 bool hasReservedCallFrame(MachineFunction &MF) const;
71 void eliminateCallFramePseudoInstr(MachineFunction &MF,
72 MachineBasicBlock &MBB,
73 MachineBasicBlock::iterator I) const;
75 void eliminateFrameIndex(MachineBasicBlock::iterator II,
76 int SPAdj, RegScavenger *RS = NULL) const;
78 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
79 RegScavenger *RS = NULL) const;
81 void emitPrologue(MachineFunction &MF) const;
82 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
84 // Debug information queries.
85 unsigned getRARegister() const;
86 unsigned getFrameRegister(MachineFunction &MF) const;
88 // Exception handling queries.
89 unsigned getEHExceptionRegister() const;
90 unsigned getEHHandlerRegister() const;
92 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
94 bool isLowRegister(unsigned Reg) const;
97 } // end namespace llvm