1 //===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMREGISTERINFO_H
15 #define ARMREGISTERINFO_H
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "ARMBaseRegisterInfo.h"
23 class TargetInstrInfo;
26 struct ARMRegisterInfo : public ARMBaseRegisterInfo {
28 ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
30 /// emitLoadConstPool - Emits a load from constpool to materialize the
31 /// specified immediate.
32 void emitLoadConstPool(MachineBasicBlock &MBB,
33 MachineBasicBlock::iterator &MBBI,
34 const TargetInstrInfo *TII, DebugLoc dl,
35 unsigned DestReg, int Val,
36 ARMCC::CondCodes Pred = ARMCC::AL,
37 unsigned PredReg = 0) const;
39 /// Code Generation virtual methods...
40 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
42 bool requiresRegisterScavenging(const MachineFunction &MF) const;
44 bool hasReservedCallFrame(MachineFunction &MF) const;
46 void eliminateCallFramePseudoInstr(MachineFunction &MF,
47 MachineBasicBlock &MBB,
48 MachineBasicBlock::iterator I) const;
50 void eliminateFrameIndex(MachineBasicBlock::iterator II,
51 int SPAdj, RegScavenger *RS = NULL) const;
53 void emitPrologue(MachineFunction &MF) const;
54 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
57 } // end namespace llvm