1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the ARM implementation of the MRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineLocation.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/Support/CommandLine.h"
39 static cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging",
41 cl::desc("Enable register scavenging on Thumb"));
43 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
46 case R0: case S0: case D0: return 0;
47 case R1: case S1: case D1: return 1;
48 case R2: case S2: case D2: return 2;
49 case R3: case S3: case D3: return 3;
50 case R4: case S4: case D4: return 4;
51 case R5: case S5: case D5: return 5;
52 case R6: case S6: case D6: return 6;
53 case R7: case S7: case D7: return 7;
54 case R8: case S8: case D8: return 8;
55 case R9: case S9: case D9: return 9;
56 case R10: case S10: case D10: return 10;
57 case R11: case S11: case D11: return 11;
58 case R12: case S12: case D12: return 12;
59 case SP: case S13: case D13: return 13;
60 case LR: case S14: case D14: return 14;
61 case PC: case S15: case D15: return 15;
79 assert(0 && "Unknown ARM register!");
84 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
85 const ARMSubtarget &sti)
86 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
88 FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
91 bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MI,
93 const std::vector<CalleeSavedInfo> &CSI) const {
94 MachineFunction &MF = *MBB.getParent();
95 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
96 if (!AFI->isThumbFunction() || CSI.empty())
99 MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH));
100 for (unsigned i = CSI.size(); i != 0; --i) {
101 unsigned Reg = CSI[i-1].getReg();
102 // Add the callee-saved register as live-in. It's killed at the spill.
104 MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
109 bool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator MI,
111 const std::vector<CalleeSavedInfo> &CSI) const {
112 MachineFunction &MF = *MBB.getParent();
113 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
114 if (!AFI->isThumbFunction() || CSI.empty())
117 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
118 MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP));
119 MBB.insert(MI, PopMI);
120 for (unsigned i = CSI.size(); i != 0; --i) {
121 unsigned Reg = CSI[i-1].getReg();
122 if (Reg == ARM::LR) {
123 // Special epilogue for vararg functions. See emitEpilogue
127 PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET));
130 PopMI->addRegOperand(Reg, true);
135 void ARMRegisterInfo::
136 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
137 unsigned SrcReg, int FI,
138 const TargetRegisterClass *RC) const {
139 if (RC == ARM::GPRRegisterClass) {
140 MachineFunction &MF = *MBB.getParent();
141 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
142 if (AFI->isThumbFunction())
143 BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true)
144 .addFrameIndex(FI).addImm(0);
146 BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true)
147 .addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL)
149 } else if (RC == ARM::DPRRegisterClass) {
150 BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true)
151 .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0);
153 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
154 BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true)
155 .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0);
159 void ARMRegisterInfo::
160 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
161 unsigned DestReg, int FI,
162 const TargetRegisterClass *RC) const {
163 if (RC == ARM::GPRRegisterClass) {
164 MachineFunction &MF = *MBB.getParent();
165 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
166 if (AFI->isThumbFunction())
167 BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg)
168 .addFrameIndex(FI).addImm(0);
170 BuildMI(MBB, I, TII.get(ARM::LDR), DestReg)
171 .addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL)
173 } else if (RC == ARM::DPRRegisterClass) {
174 BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg)
175 .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0);
177 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
178 BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg)
179 .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0);
183 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
184 MachineBasicBlock::iterator I,
185 unsigned DestReg, unsigned SrcReg,
186 const TargetRegisterClass *RC) const {
187 if (RC == ARM::GPRRegisterClass) {
188 MachineFunction &MF = *MBB.getParent();
189 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
190 if (AFI->isThumbFunction())
191 BuildMI(MBB, I, TII.get(ARM::tMOVr), DestReg).addReg(SrcReg);
193 BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg).addReg(SrcReg)
194 .addImm((int64_t)ARMCC::AL).addReg(0).addReg(0);
195 } else if (RC == ARM::SPRRegisterClass)
196 BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg)
197 .addImm((int64_t)ARMCC::AL).addReg(0);
198 else if (RC == ARM::DPRRegisterClass)
199 BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg)
200 .addImm((int64_t)ARMCC::AL).addReg(0);
205 /// emitLoadConstPool - Emits a load from constpool to materialize the
206 /// specified immediate.
207 static void emitLoadConstPool(MachineBasicBlock &MBB,
208 MachineBasicBlock::iterator &MBBI,
209 unsigned DestReg, int Val,
210 ARMCC::CondCodes Pred, unsigned PredReg,
211 const TargetInstrInfo &TII, bool isThumb) {
212 MachineFunction &MF = *MBB.getParent();
213 MachineConstantPool *ConstantPool = MF.getConstantPool();
214 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
215 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
217 BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx);
219 BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
220 .addReg(0).addImm(0).addImm((unsigned)Pred).addReg(PredReg);
223 void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
224 MachineBasicBlock::iterator I,
226 const MachineInstr *Orig) const {
227 if (Orig->getOpcode() == ARM::MOVi2pieces) {
228 emitLoadConstPool(MBB, I, DestReg,
229 Orig->getOperand(1).getImmedValue(),
230 (ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(),
231 Orig->getOperand(3).getReg(),
236 MachineInstr *MI = Orig->clone();
237 MI->getOperand(0).setReg(DestReg);
241 /// isLowRegister - Returns true if the register is low register r0-r7.
243 static bool isLowRegister(unsigned Reg) {
246 case R0: case R1: case R2: case R3:
247 case R4: case R5: case R6: case R7:
254 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
255 unsigned OpNum, int FI) const {
256 unsigned Opc = MI->getOpcode();
257 MachineInstr *NewMI = NULL;
261 if (MI->getOperand(4).getReg() == ARM::CPSR)
262 // If it is updating CPSR, then it cannot be foled.
264 unsigned Pred = MI->getOperand(2).getImmedValue();
265 unsigned PredReg = MI->getOperand(3).getReg();
266 if (OpNum == 0) { // move -> store
267 unsigned SrcReg = MI->getOperand(1).getReg();
268 NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
269 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
270 } else { // move -> load
271 unsigned DstReg = MI->getOperand(0).getReg();
272 NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
273 .addImm(0).addImm(Pred).addReg(PredReg);
278 if (OpNum == 0) { // move -> store
279 unsigned SrcReg = MI->getOperand(1).getReg();
280 if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg))
281 // tSpill cannot take a high register operand.
283 NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI)
285 } else { // move -> load
286 unsigned DstReg = MI->getOperand(0).getReg();
287 if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg))
288 // tRestore cannot target a high register operand.
290 NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI)
296 unsigned Pred = MI->getOperand(2).getImmedValue();
297 unsigned PredReg = MI->getOperand(3).getReg();
298 if (OpNum == 0) { // move -> store
299 unsigned SrcReg = MI->getOperand(1).getReg();
300 NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
301 .addImm(0).addImm(Pred).addReg(PredReg);
302 } else { // move -> load
303 unsigned DstReg = MI->getOperand(0).getReg();
304 NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI)
305 .addImm(0).addImm(Pred).addReg(PredReg);
310 unsigned Pred = MI->getOperand(2).getImmedValue();
311 unsigned PredReg = MI->getOperand(3).getReg();
312 if (OpNum == 0) { // move -> store
313 unsigned SrcReg = MI->getOperand(1).getReg();
314 NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
315 .addImm(0).addImm(Pred).addReg(PredReg);
316 } else { // move -> load
317 unsigned DstReg = MI->getOperand(0).getReg();
318 NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI)
319 .addImm(0).addImm(Pred).addReg(PredReg);
326 NewMI->copyKillDeadInfo(MI);
331 ARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
332 static const unsigned CalleeSavedRegs[] = {
333 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
334 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
336 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
337 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
341 static const unsigned DarwinCalleeSavedRegs[] = {
342 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
343 ARM::R11, ARM::R10, ARM::R9, ARM::R8,
345 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
346 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
349 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
352 const TargetRegisterClass* const *
353 ARMRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
354 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
355 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
356 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
357 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
359 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
360 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
363 return CalleeSavedRegClasses;
366 BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
367 // FIXME: avoid re-calculating this everytime.
368 BitVector Reserved(getNumRegs());
369 Reserved.set(ARM::SP);
370 Reserved.set(ARM::PC);
371 if (STI.isTargetDarwin() || hasFP(MF))
372 Reserved.set(FramePtr);
373 // Some targets reserve R9.
374 if (STI.isR9Reserved())
375 Reserved.set(ARM::R9);
380 ARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
388 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
392 return STI.isR9Reserved();
399 ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
400 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
401 return ThumbRegScavenging || !AFI->isThumbFunction();
404 /// hasFP - Return true if the specified function should have a dedicated frame
405 /// pointer register. This is true if the function has variable sized allocas
406 /// or if frame pointer elimination is disabled.
408 bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
409 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
412 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
413 // not required, we reserve argument space for call sites in the function
414 // immediately on entry to the current function. This eliminates the need for
415 // add/sub sp brackets around call sites. Returns true if the call frame is
416 // included as part of the stack frame.
417 bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
418 const MachineFrameInfo *FFI = MF.getFrameInfo();
419 unsigned CFSize = FFI->getMaxCallFrameSize();
420 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
421 // It's not always a good idea to include the call frame as part of the
422 // stack frame. ARM (especially Thumb) has small immediate offset to
423 // address the stack frame. So a large call frame can cause poor codegen
424 // and may even makes it impossible to scavenge a register.
425 if (AFI->isThumbFunction()) {
426 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
429 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
432 return !MF.getFrameInfo()->hasVarSizedObjects();
435 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
436 /// a destreg = basereg + immediate in ARM code.
438 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
439 MachineBasicBlock::iterator &MBBI,
440 unsigned DestReg, unsigned BaseReg, int NumBytes,
441 ARMCC::CondCodes Pred, unsigned PredReg,
442 const TargetInstrInfo &TII) {
443 bool isSub = NumBytes < 0;
444 if (isSub) NumBytes = -NumBytes;
447 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
448 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
449 assert(ThisVal && "Didn't extract field correctly");
451 // We will handle these bits from offset, clear them.
452 NumBytes &= ~ThisVal;
454 // Get the properly encoded SOImmVal field.
455 int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
456 assert(SOImmVal != -1 && "Bit extraction didn't work?");
458 // Build the new ADD / SUB.
459 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
460 .addReg(BaseReg, false, false, true).addImm(SOImmVal)
461 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
466 /// calcNumMI - Returns the number of instructions required to materialize
467 /// the specific add / sub r, c instruction.
468 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
469 unsigned NumBits, unsigned Scale) {
471 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
473 if (Opc == ARM::tADDrSPi) {
474 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
478 Scale = 1; // Followed by a number of tADDi8.
479 Chunk = ((1 << NumBits) - 1) * Scale;
482 NumMIs += Bytes / Chunk;
483 if ((Bytes % Chunk) != 0)
490 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
491 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
492 /// in a register using mov / mvn sequences or load the immediate from a
495 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
496 MachineBasicBlock::iterator &MBBI,
497 unsigned DestReg, unsigned BaseReg,
498 int NumBytes, bool CanChangeCC,
499 const TargetInstrInfo &TII) {
500 bool isHigh = !isLowRegister(DestReg) ||
501 (BaseReg != 0 && !isLowRegister(BaseReg));
503 // Subtract doesn't have high register version. Load the negative value
504 // if either base or dest register is a high register. Also, if do not
505 // issue sub as part of the sequence if condition register is to be
507 if (NumBytes < 0 && !isHigh && CanChangeCC) {
509 NumBytes = -NumBytes;
511 unsigned LdReg = DestReg;
512 if (DestReg == ARM::SP) {
513 assert(BaseReg == ARM::SP && "Unexpected!");
515 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12)
516 .addReg(ARM::R3, false, false, true);
519 if (NumBytes <= 255 && NumBytes >= 0)
520 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
521 else if (NumBytes < 0 && NumBytes >= -255) {
522 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
523 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
524 .addReg(LdReg, false, false, true);
526 emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, TII, true);
529 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
530 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
531 if (DestReg == ARM::SP || isSub)
532 MIB.addReg(BaseReg).addReg(LdReg, false, false, true);
534 MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
535 if (DestReg == ARM::SP)
536 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3)
537 .addReg(ARM::R12, false, false, true);
540 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
541 /// a destreg = basereg + immediate in Thumb code.
543 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
544 MachineBasicBlock::iterator &MBBI,
545 unsigned DestReg, unsigned BaseReg,
546 int NumBytes, const TargetInstrInfo &TII) {
547 bool isSub = NumBytes < 0;
548 unsigned Bytes = (unsigned)NumBytes;
549 if (isSub) Bytes = -NumBytes;
550 bool isMul4 = (Bytes & 3) == 0;
551 bool isTwoAddr = false;
552 bool DstNotEqBase = false;
553 unsigned NumBits = 1;
558 if (DestReg == BaseReg && BaseReg == ARM::SP) {
559 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
562 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
564 } else if (!isSub && BaseReg == ARM::SP) {
567 // r1 = add sp, 100 * 4
571 ExtraOpc = ARM::tADDi3;
580 if (DestReg != BaseReg)
583 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
587 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
588 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
589 if (NumMIs > Threshold) {
590 // This will expand into too many instructions. Load the immediate from a
592 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII);
597 if (isLowRegister(DestReg) && isLowRegister(BaseReg)) {
598 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
599 unsigned Chunk = (1 << 3) - 1;
600 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
602 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
603 .addReg(BaseReg, false, false, true).addImm(ThisVal);
605 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg)
606 .addReg(BaseReg, false, false, true);
611 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
613 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
616 // Build the new tADD / tSUB.
618 BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal);
620 bool isKill = BaseReg != ARM::SP;
621 BuildMI(MBB, MBBI, TII.get(Opc), DestReg)
622 .addReg(BaseReg, false, false, isKill).addImm(ThisVal);
625 if (Opc == ARM::tADDrSPi) {
631 Chunk = ((1 << NumBits) - 1) * Scale;
632 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
639 BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg)
640 .addReg(DestReg, false, false, true)
641 .addImm(((unsigned)NumBytes) & 3);
645 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
646 int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg,
647 bool isThumb, const TargetInstrInfo &TII) {
649 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
651 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
655 void ARMRegisterInfo::
656 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
657 MachineBasicBlock::iterator I) const {
658 if (!hasReservedCallFrame(MF)) {
659 // If we have alloca, convert as follows:
660 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
661 // ADJCALLSTACKUP -> add, sp, sp, amount
662 MachineInstr *Old = I;
663 unsigned Amount = Old->getOperand(0).getImmedValue();
665 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
666 // We need to keep the stack aligned properly. To do this, we round the
667 // amount of space needed for the outgoing arguments up to the next
668 // alignment boundary.
669 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
670 Amount = (Amount+Align-1)/Align*Align;
672 // Replace the pseudo instruction with a new instruction...
673 unsigned Opc = Old->getOpcode();
674 bool isThumb = AFI->isThumbFunction();
675 ARMCC::CondCodes Pred = isThumb
676 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue();
677 unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
678 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
679 emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII);
681 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
682 emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII);
689 /// emitThumbConstant - Emit a series of instructions to materialize a
691 static void emitThumbConstant(MachineBasicBlock &MBB,
692 MachineBasicBlock::iterator &MBBI,
693 unsigned DestReg, int Imm,
694 const TargetInstrInfo &TII) {
695 bool isSub = Imm < 0;
696 if (isSub) Imm = -Imm;
698 int Chunk = (1 << 8) - 1;
699 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
701 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
703 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII);
705 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg)
706 .addReg(DestReg, false, false, true);
709 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
710 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
711 /// register first and then a spilled callee-saved register if that fails.
713 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
714 ARMFunctionInfo *AFI) {
715 unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
717 // Try a already spilled CS register.
718 Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
723 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
724 int SPAdj, RegScavenger *RS) const{
726 MachineInstr &MI = *II;
727 MachineBasicBlock &MBB = *MI.getParent();
728 MachineFunction &MF = *MBB.getParent();
729 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
730 bool isThumb = AFI->isThumbFunction();
732 while (!MI.getOperand(i).isFrameIndex()) {
734 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
737 unsigned FrameReg = ARM::SP;
738 int FrameIndex = MI.getOperand(i).getFrameIndex();
739 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
740 MF.getFrameInfo()->getStackSize() + SPAdj;
742 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
743 Offset -= AFI->getGPRCalleeSavedArea1Offset();
744 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
745 Offset -= AFI->getGPRCalleeSavedArea2Offset();
746 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
747 Offset -= AFI->getDPRCalleeSavedAreaOffset();
748 else if (hasFP(MF)) {
749 assert(SPAdj == 0 && "Unexpected");
750 // There is alloca()'s in this function, must reference off the frame
752 FrameReg = getFrameRegister(MF);
753 Offset -= AFI->getFramePtrSpillOffset();
756 unsigned Opcode = MI.getOpcode();
757 const TargetInstrDescriptor &Desc = TII.get(Opcode);
758 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
761 if (Opcode == ARM::ADDri) {
762 Offset += MI.getOperand(i+1).getImm();
764 // Turn it into a move.
765 MI.setInstrDescriptor(TII.get(ARM::MOVr));
766 MI.getOperand(i).ChangeToRegister(FrameReg, false);
767 MI.RemoveOperand(i+1);
769 } else if (Offset < 0) {
772 MI.setInstrDescriptor(TII.get(ARM::SUBri));
775 // Common case: small offset, fits into instruction.
776 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
777 if (ImmedOffset != -1) {
778 // Replace the FrameIndex with sp / fp
779 MI.getOperand(i).ChangeToRegister(FrameReg, false);
780 MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
784 // Otherwise, we fallback to common code below to form the imm offset with
785 // a sequence of ADDri instructions. First though, pull as much of the imm
786 // into this ADDri as possible.
787 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
788 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
790 // We will handle these bits from offset, clear them.
791 Offset &= ~ThisImmVal;
793 // Get the properly encoded SOImmVal field.
794 int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
795 assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
796 MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
797 } else if (Opcode == ARM::tADDrSPi) {
798 Offset += MI.getOperand(i+1).getImm();
800 // Can't use tADDrSPi if it's based off the frame pointer.
801 unsigned NumBits = 0;
803 if (FrameReg != ARM::SP) {
804 Opcode = ARM::tADDi3;
805 MI.setInstrDescriptor(TII.get(ARM::tADDi3));
810 assert((Offset & 3) == 0 &&
811 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
815 // Turn it into a move.
816 MI.setInstrDescriptor(TII.get(ARM::tMOVr));
817 MI.getOperand(i).ChangeToRegister(FrameReg, false);
818 MI.RemoveOperand(i+1);
822 // Common case: small offset, fits into instruction.
823 unsigned Mask = (1 << NumBits) - 1;
824 if (((Offset / Scale) & ~Mask) == 0) {
825 // Replace the FrameIndex with sp / fp
826 MI.getOperand(i).ChangeToRegister(FrameReg, false);
827 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
831 unsigned DestReg = MI.getOperand(0).getReg();
832 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
833 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
834 // MI would expand into a large number of instructions. Don't try to
835 // simplify the immediate.
837 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII);
843 // Translate r0 = add sp, imm to
844 // r0 = add sp, 255*4
845 // r0 = add r0, (imm - 255*4)
846 MI.getOperand(i).ChangeToRegister(FrameReg, false);
847 MI.getOperand(i+1).ChangeToImmediate(Mask);
848 Offset = (Offset - Mask * Scale);
849 MachineBasicBlock::iterator NII = next(II);
850 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII);
852 // Translate r0 = add sp, -imm to
853 // r0 = -imm (this is then translated into a series of instructons)
855 emitThumbConstant(MBB, II, DestReg, Offset, TII);
856 MI.setInstrDescriptor(TII.get(ARM::tADDhirr));
857 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
858 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
864 unsigned NumBits = 0;
867 case ARMII::AddrMode2: {
869 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
870 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
875 case ARMII::AddrMode3: {
877 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
878 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
883 case ARMII::AddrMode5: {
885 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
886 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
892 case ARMII::AddrModeTs: {
894 InstrOffs = MI.getOperand(ImmIdx).getImm();
895 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
900 assert(0 && "Unsupported addressing mode!");
905 Offset += InstrOffs * Scale;
906 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
907 if (Offset < 0 && !isThumb) {
912 // Common case: small offset, fits into instruction.
913 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
914 int ImmedOffset = Offset / Scale;
915 unsigned Mask = (1 << NumBits) - 1;
916 if ((unsigned)Offset <= Mask * Scale) {
917 // Replace the FrameIndex with sp
918 MI.getOperand(i).ChangeToRegister(FrameReg, false);
920 ImmedOffset |= 1 << NumBits;
921 ImmOp.ChangeToImmediate(ImmedOffset);
925 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
926 if (AddrMode == ARMII::AddrModeTs) {
927 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
928 // a different base register.
930 Mask = (1 << NumBits) - 1;
932 // If this is a thumb spill / restore, we will be using a constpool load to
933 // materialize the offset.
934 if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore)
935 ImmOp.ChangeToImmediate(0);
937 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
938 ImmedOffset = ImmedOffset & Mask;
940 ImmedOffset |= 1 << NumBits;
941 ImmOp.ChangeToImmediate(ImmedOffset);
942 Offset &= ~(Mask*Scale);
946 // If we get here, the immediate doesn't fit into the instruction. We folded
947 // as much as possible above, handle the rest, providing a register that is
949 assert(Offset && "This code isn't needed if offset already handled!");
952 if (TII.isLoad(Opcode)) {
953 // Use the destination register to materialize sp + offset.
954 unsigned TmpReg = MI.getOperand(0).getReg();
956 if (Opcode == ARM::tRestore) {
957 if (FrameReg == ARM::SP)
958 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
960 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true);
964 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
965 MI.setInstrDescriptor(TII.get(ARM::tLDR));
966 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
968 MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
970 MI.addRegOperand(0, false); // tLDR has an extra register operand.
971 } else if (TII.isStore(Opcode)) {
972 // FIXME! This is horrific!!! We need register scavenging.
973 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
974 // also a ABI register so it's possible that is is the register that is
975 // being storing here. If that's the case, we do the following:
977 // Use r2 to materialize sp + offset
980 unsigned ValReg = MI.getOperand(0).getReg();
981 unsigned TmpReg = ARM::R3;
983 if (ValReg == ARM::R3) {
984 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
985 .addReg(ARM::R2, false, false, true);
988 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
989 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
990 .addReg(ARM::R3, false, false, true);
991 if (Opcode == ARM::tSpill) {
992 if (FrameReg == ARM::SP)
993 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
995 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true);
999 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
1000 MI.setInstrDescriptor(TII.get(ARM::tSTR));
1001 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
1003 MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
1005 MI.addRegOperand(0, false); // tSTR has an extra register operand.
1007 MachineBasicBlock::iterator NII = next(II);
1008 if (ValReg == ARM::R3)
1009 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2)
1010 .addReg(ARM::R12, false, false, true);
1011 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
1012 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3)
1013 .addReg(ARM::R12, false, false, true);
1015 assert(false && "Unexpected opcode!");
1017 // Insert a set of r12 with the full address: r12 = sp + offset
1018 // If the offset we have is too large to fit into the instruction, we need
1019 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
1021 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
1022 if (ScratchReg == 0)
1023 // No register is "free". Scavenge a register.
1024 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
1025 int PIdx = MI.findFirstPredOperandIdx();
1026 ARMCC::CondCodes Pred = (PIdx == -1)
1027 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImmedValue();
1028 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1029 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
1030 isSub ? -Offset : Offset, Pred, PredReg, TII);
1031 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1035 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
1036 const MachineFrameInfo *FFI = MF.getFrameInfo();
1038 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
1039 int FixedOff = -FFI->getObjectOffset(i);
1040 if (FixedOff > Offset) Offset = FixedOff;
1042 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
1043 Offset += FFI->getObjectSize(i);
1044 unsigned Align = FFI->getObjectAlignment(i);
1045 // Adjust to alignment boundary
1046 Offset = (Offset+Align-1)/Align*Align;
1048 return (unsigned)Offset;
1052 ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1053 RegScavenger *RS) const {
1054 // This tells PEI to spill the FP as if it is any other callee-save register
1055 // to take advantage the eliminateFrameIndex machinery. This also ensures it
1056 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1057 // to combine multiple loads / stores.
1058 bool CanEliminateFrame = true;
1059 bool CS1Spilled = false;
1060 bool LRSpilled = false;
1061 unsigned NumGPRSpills = 0;
1062 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1063 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1064 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1066 // Don't spill FP if the frame can be eliminated. This is determined
1067 // by scanning the callee-save registers to see if any is used.
1068 const unsigned *CSRegs = getCalleeSavedRegs();
1069 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
1070 for (unsigned i = 0; CSRegs[i]; ++i) {
1071 unsigned Reg = CSRegs[i];
1072 bool Spilled = false;
1073 if (MF.isPhysRegUsed(Reg)) {
1074 AFI->setCSRegisterIsSpilled(Reg);
1076 CanEliminateFrame = false;
1078 // Check alias registers too.
1079 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
1080 if (MF.isPhysRegUsed(*Aliases)) {
1082 CanEliminateFrame = false;
1087 if (CSRegClasses[i] == &ARM::GPRRegClass) {
1091 if (!STI.isTargetDarwin()) {
1098 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1113 if (!STI.isTargetDarwin()) {
1114 UnspilledCS1GPRs.push_back(Reg);
1124 UnspilledCS1GPRs.push_back(Reg);
1127 UnspilledCS2GPRs.push_back(Reg);
1134 bool ForceLRSpill = false;
1135 if (!LRSpilled && AFI->isThumbFunction()) {
1136 unsigned FnSize = ARM::GetFunctionSize(MF);
1137 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1138 // use of BL to implement far jump. If it turns out that it's not needed
1139 // then the branch fix up path will undo it.
1140 if (FnSize >= (1 << 11)) {
1141 CanEliminateFrame = false;
1142 ForceLRSpill = true;
1146 bool ExtraCSSpill = false;
1147 if (!CanEliminateFrame || hasFP(MF)) {
1148 AFI->setHasStackFrame(true);
1150 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1151 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1152 if (!LRSpilled && CS1Spilled) {
1153 MF.setPhysRegUsed(ARM::LR);
1154 AFI->setCSRegisterIsSpilled(ARM::LR);
1156 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
1157 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
1158 ForceLRSpill = false;
1159 ExtraCSSpill = true;
1162 // Darwin ABI requires FP to point to the stack slot that contains the
1164 if (STI.isTargetDarwin() || hasFP(MF)) {
1165 MF.setPhysRegUsed(FramePtr);
1169 // If stack and double are 8-byte aligned and we are spilling an odd number
1170 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
1171 // the integer and double callee save areas.
1172 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1173 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
1174 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1175 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1176 unsigned Reg = UnspilledCS1GPRs[i];
1177 // Don't spiil high register if the function is thumb
1178 if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) {
1179 MF.setPhysRegUsed(Reg);
1180 AFI->setCSRegisterIsSpilled(Reg);
1181 if (!isReservedReg(MF, Reg))
1182 ExtraCSSpill = true;
1186 } else if (!UnspilledCS2GPRs.empty() &&
1187 !AFI->isThumbFunction()) {
1188 unsigned Reg = UnspilledCS2GPRs.front();
1189 MF.setPhysRegUsed(Reg);
1190 AFI->setCSRegisterIsSpilled(Reg);
1191 if (!isReservedReg(MF, Reg))
1192 ExtraCSSpill = true;
1196 // Estimate if we might need to scavenge a register at some point in order
1197 // to materialize a stack offset. If so, either spill one additiona
1198 // callee-saved register or reserve a special spill slot to facilitate
1199 // register scavenging.
1200 if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) {
1201 MachineFrameInfo *MFI = MF.getFrameInfo();
1202 unsigned Size = estimateStackSize(MF, MFI);
1203 unsigned Limit = (1 << 12) - 1;
1204 for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
1205 for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
1206 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1207 if (I->getOperand(i).isFrameIndex()) {
1208 unsigned Opcode = I->getOpcode();
1209 const TargetInstrDescriptor &Desc = TII.get(Opcode);
1210 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1211 if (AddrMode == ARMII::AddrMode3) {
1212 Limit = (1 << 8) - 1;
1213 goto DoneEstimating;
1214 } else if (AddrMode == ARMII::AddrMode5) {
1215 unsigned ThisLimit = ((1 << 8) - 1) * 4;
1216 if (ThisLimit < Limit)
1222 if (Size >= Limit) {
1223 // If any non-reserved CS register isn't spilled, just spill one or two
1224 // extra. That should take care of it!
1225 unsigned NumExtras = TargetAlign / 4;
1226 SmallVector<unsigned, 2> Extras;
1227 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1228 unsigned Reg = UnspilledCS1GPRs.back();
1229 UnspilledCS1GPRs.pop_back();
1230 if (!isReservedReg(MF, Reg)) {
1231 Extras.push_back(Reg);
1235 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1236 unsigned Reg = UnspilledCS2GPRs.back();
1237 UnspilledCS2GPRs.pop_back();
1238 if (!isReservedReg(MF, Reg)) {
1239 Extras.push_back(Reg);
1243 if (Extras.size() && NumExtras == 0) {
1244 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1245 MF.setPhysRegUsed(Extras[i]);
1246 AFI->setCSRegisterIsSpilled(Extras[i]);
1249 // Reserve a slot closest to SP or frame pointer.
1250 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1251 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1252 RC->getAlignment()));
1259 MF.setPhysRegUsed(ARM::LR);
1260 AFI->setCSRegisterIsSpilled(ARM::LR);
1261 AFI->setLRIsSpilledForFarJump(true);
1265 /// Move iterator pass the next bunch of callee save load / store ops for
1266 /// the particular spill area (1: integer area 1, 2: integer area 2,
1267 /// 3: fp area, 0: don't care).
1268 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1269 MachineBasicBlock::iterator &MBBI,
1270 int Opc, unsigned Area,
1271 const ARMSubtarget &STI) {
1272 while (MBBI != MBB.end() &&
1273 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) {
1276 unsigned Category = 0;
1277 switch (MBBI->getOperand(0).getReg()) {
1278 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1282 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1283 Category = STI.isTargetDarwin() ? 2 : 1;
1285 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1286 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1293 if (Done || Category != Area)
1301 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
1302 MachineBasicBlock &MBB = MF.front();
1303 MachineBasicBlock::iterator MBBI = MBB.begin();
1304 MachineFrameInfo *MFI = MF.getFrameInfo();
1305 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1306 bool isThumb = AFI->isThumbFunction();
1307 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1308 unsigned NumBytes = MFI->getStackSize();
1309 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1312 // Check if R3 is live in. It might have to be used as a scratch register.
1313 for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end();
1315 if ((*I).first == ARM::R3) {
1316 AFI->setR3IsLiveIn(true);
1321 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
1322 NumBytes = (NumBytes + 3) & ~3;
1323 MFI->setStackSize(NumBytes);
1326 // Determine the sizes of each callee-save spill areas and record which frame
1327 // belongs to which callee-save spill areas.
1328 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1329 int FramePtrSpillFI = 0;
1332 emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII);
1334 if (!AFI->hasStackFrame()) {
1336 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII);
1340 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1341 unsigned Reg = CSI[i].getReg();
1342 int FI = CSI[i].getFrameIdx();
1349 if (Reg == FramePtr)
1350 FramePtrSpillFI = FI;
1351 AFI->addGPRCalleeSavedArea1Frame(FI);
1358 if (Reg == FramePtr)
1359 FramePtrSpillFI = FI;
1360 if (STI.isTargetDarwin()) {
1361 AFI->addGPRCalleeSavedArea2Frame(FI);
1364 AFI->addGPRCalleeSavedArea1Frame(FI);
1369 AFI->addDPRCalleeSavedAreaFrame(FI);
1375 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1376 emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII);
1377 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
1378 } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
1381 // Darwin ABI requires FP to point to the stack slot that contains the
1383 if (STI.isTargetDarwin() || hasFP(MF)) {
1384 MachineInstrBuilder MIB =
1385 BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr)
1386 .addFrameIndex(FramePtrSpillFI).addImm(0);
1387 if (!isThumb) MIB.addImm(ARMCC::AL).addReg(0).addReg(0);
1391 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1392 emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII);
1394 // Build the new SUBri to adjust SP for FP callee-save spill area.
1395 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
1396 emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII);
1399 // Determine starting offsets of spill areas.
1400 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1401 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1402 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1403 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1404 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1405 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1406 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1408 NumBytes = DPRCSOffset;
1410 // Insert it after all the callee-save spills.
1412 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
1413 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII);
1416 if(STI.isTargetELF() && hasFP(MF)) {
1417 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1418 AFI->getFramePtrSpillOffset());
1421 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1422 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1423 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1426 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1427 for (unsigned i = 0; CSRegs[i]; ++i)
1428 if (Reg == CSRegs[i])
1433 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
1434 return ((MI->getOpcode() == ARM::FLDD ||
1435 MI->getOpcode() == ARM::LDR ||
1436 MI->getOpcode() == ARM::tRestore) &&
1437 MI->getOperand(1).isFrameIndex() &&
1438 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1441 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
1442 MachineBasicBlock &MBB) const {
1443 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1444 assert((MBBI->getOpcode() == ARM::BX_RET ||
1445 MBBI->getOpcode() == ARM::tBX_RET ||
1446 MBBI->getOpcode() == ARM::tPOP_RET) &&
1447 "Can only insert epilog into returning blocks");
1449 MachineFrameInfo *MFI = MF.getFrameInfo();
1450 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1451 bool isThumb = AFI->isThumbFunction();
1452 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1453 int NumBytes = (int)MFI->getStackSize();
1454 if (!AFI->hasStackFrame()) {
1456 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
1458 // Unwind MBBI to point to first LDR / FLDD.
1459 const unsigned *CSRegs = getCalleeSavedRegs();
1460 if (MBBI != MBB.begin()) {
1463 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
1464 if (!isCSRestore(MBBI, CSRegs))
1468 // Move SP to start of FP callee save spill area.
1469 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1470 AFI->getGPRCalleeSavedArea2Size() +
1471 AFI->getDPRCalleeSavedAreaSize());
1474 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1475 // Reset SP based on frame pointer only if the stack frame extends beyond
1476 // frame pointer stack slot or target is ELF and the function has FP.
1478 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII);
1480 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr);
1482 if (MBBI->getOpcode() == ARM::tBX_RET &&
1483 &MBB.front() != MBBI &&
1484 prior(MBBI)->getOpcode() == ARM::tPOP) {
1485 MachineBasicBlock::iterator PMBBI = prior(MBBI);
1486 emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
1488 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
1491 // Darwin ABI requires FP to point to the stack slot that contains the
1493 if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
1494 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1495 // Reset SP based on frame pointer only if the stack frame extends beyond
1496 // frame pointer stack slot or target is ELF and the function has FP.
1497 if (AFI->getGPRCalleeSavedArea2Size() ||
1498 AFI->getDPRCalleeSavedAreaSize() ||
1499 AFI->getDPRCalleeSavedAreaOffset()||
1502 BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
1504 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1506 BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
1507 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1508 } else if (NumBytes) {
1509 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII);
1512 // Move SP to start of integer callee save spill area 2.
1513 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
1514 emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0,
1517 // Move SP to start of integer callee save spill area 1.
1518 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
1519 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0,
1522 // Move SP to SP upon entry to the function.
1523 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1524 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0,
1529 if (VARegSaveSize) {
1531 // Epilogue for vararg functions: pop LR to R3 and branch off it.
1532 // FIXME: Verify this is still ok when R3 is no longer being reserved.
1533 BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3);
1535 emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII);
1538 BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
1544 unsigned ARMRegisterInfo::getRARegister() const {
1548 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1549 if (STI.isTargetDarwin() || hasFP(MF))
1550 return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11;
1555 unsigned ARMRegisterInfo::getEHExceptionRegister() const {
1556 assert(0 && "What is the exception register");
1560 unsigned ARMRegisterInfo::getEHHandlerRegister() const {
1561 assert(0 && "What is the exception handler register");
1565 #include "ARMGenRegisterInfo.inc"