1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMRegisterInfo.h"
19 #include "ARMSubtarget.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/Support/CommandLine.h"
39 static cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging",
41 cl::desc("Enable register scavenging on Thumb"));
43 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
46 case R0: case S0: case D0: return 0;
47 case R1: case S1: case D1: return 1;
48 case R2: case S2: case D2: return 2;
49 case R3: case S3: case D3: return 3;
50 case R4: case S4: case D4: return 4;
51 case R5: case S5: case D5: return 5;
52 case R6: case S6: case D6: return 6;
53 case R7: case S7: case D7: return 7;
54 case R8: case S8: case D8: return 8;
55 case R9: case S9: case D9: return 9;
56 case R10: case S10: case D10: return 10;
57 case R11: case S11: case D11: return 11;
58 case R12: case S12: case D12: return 12;
59 case SP: case S13: case D13: return 13;
60 case LR: case S14: case D14: return 14;
61 case PC: case S15: case D15: return 15;
79 assert(0 && "Unknown ARM register!");
84 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum,
91 assert(0 && "Unknown ARM register!");
93 case R0: case D0: return 0;
94 case R1: case D1: return 1;
95 case R2: case D2: return 2;
96 case R3: case D3: return 3;
97 case R4: case D4: return 4;
98 case R5: case D5: return 5;
99 case R6: case D6: return 6;
100 case R7: case D7: return 7;
101 case R8: case D8: return 8;
102 case R9: case D9: return 9;
103 case R10: case D10: return 10;
104 case R11: case D11: return 11;
105 case R12: case D12: return 12;
106 case SP: case D13: return 13;
107 case LR: case D14: return 14;
108 case PC: case D15: return 15;
110 case S0: case S1: case S2: case S3:
111 case S4: case S5: case S6: case S7:
112 case S8: case S9: case S10: case S11:
113 case S12: case S13: case S14: case S15:
114 case S16: case S17: case S18: case S19:
115 case S20: case S21: case S22: case S23:
116 case S24: case S25: case S26: case S27:
117 case S28: case S29: case S30: case S31: {
120 default: return 0; // Avoid compile time warning.
158 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
159 const ARMSubtarget &sti)
160 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
162 FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
166 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
167 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
171 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
172 return MIB.addReg(0);
175 /// emitLoadConstPool - Emits a load from constpool to materialize the
176 /// specified immediate.
177 void ARMRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
178 MachineBasicBlock::iterator &MBBI,
179 unsigned DestReg, int Val,
180 unsigned Pred, unsigned PredReg,
181 const TargetInstrInfo *TII,
182 bool isThumb) const {
183 MachineFunction &MF = *MBB.getParent();
184 MachineConstantPool *ConstantPool = MF.getConstantPool();
185 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
186 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
188 BuildMI(MBB, MBBI, TII->get(ARM::tLDRcp),DestReg).addConstantPoolIndex(Idx);
190 BuildMI(MBB, MBBI, TII->get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
191 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
194 const TargetRegisterClass *ARMRegisterInfo::getPointerRegClass() const {
195 return &ARM::GPRRegClass;
198 /// isLowRegister - Returns true if the register is low register r0-r7.
200 bool ARMRegisterInfo::isLowRegister(unsigned Reg) const {
203 case R0: case R1: case R2: case R3:
204 case R4: case R5: case R6: case R7:
212 ARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
213 static const unsigned CalleeSavedRegs[] = {
214 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
215 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
217 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
218 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
222 static const unsigned DarwinCalleeSavedRegs[] = {
223 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
224 ARM::R11, ARM::R10, ARM::R9, ARM::R8,
226 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
227 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
230 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
233 const TargetRegisterClass* const *
234 ARMRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
235 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
236 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
237 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
238 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
240 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
241 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
244 return CalleeSavedRegClasses;
247 BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
248 // FIXME: avoid re-calculating this everytime.
249 BitVector Reserved(getNumRegs());
250 Reserved.set(ARM::SP);
251 Reserved.set(ARM::PC);
252 if (STI.isTargetDarwin() || hasFP(MF))
253 Reserved.set(FramePtr);
254 // Some targets reserve R9.
255 if (STI.isR9Reserved())
256 Reserved.set(ARM::R9);
261 ARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
269 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
273 return STI.isR9Reserved();
280 ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
281 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
282 return ThumbRegScavenging || !AFI->isThumbFunction();
285 /// hasFP - Return true if the specified function should have a dedicated frame
286 /// pointer register. This is true if the function has variable sized allocas
287 /// or if frame pointer elimination is disabled.
289 bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
290 const MachineFrameInfo *MFI = MF.getFrameInfo();
291 return NoFramePointerElim || MFI->hasVarSizedObjects();
294 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
295 // not required, we reserve argument space for call sites in the function
296 // immediately on entry to the current function. This eliminates the need for
297 // add/sub sp brackets around call sites. Returns true if the call frame is
298 // included as part of the stack frame.
299 bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
300 const MachineFrameInfo *FFI = MF.getFrameInfo();
301 unsigned CFSize = FFI->getMaxCallFrameSize();
302 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
303 // It's not always a good idea to include the call frame as part of the
304 // stack frame. ARM (especially Thumb) has small immediate offset to
305 // address the stack frame. So a large call frame can cause poor codegen
306 // and may even makes it impossible to scavenge a register.
307 if (AFI->isThumbFunction()) {
308 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
311 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
314 return !MF.getFrameInfo()->hasVarSizedObjects();
317 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
318 /// a destreg = basereg + immediate in ARM code.
320 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
321 MachineBasicBlock::iterator &MBBI,
322 unsigned DestReg, unsigned BaseReg, int NumBytes,
323 ARMCC::CondCodes Pred, unsigned PredReg,
324 const TargetInstrInfo &TII) {
325 bool isSub = NumBytes < 0;
326 if (isSub) NumBytes = -NumBytes;
329 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
330 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
331 assert(ThisVal && "Didn't extract field correctly");
333 // We will handle these bits from offset, clear them.
334 NumBytes &= ~ThisVal;
336 // Get the properly encoded SOImmVal field.
337 int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
338 assert(SOImmVal != -1 && "Bit extraction didn't work?");
340 // Build the new ADD / SUB.
341 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
342 .addReg(BaseReg, false, false, true).addImm(SOImmVal)
343 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
348 /// calcNumMI - Returns the number of instructions required to materialize
349 /// the specific add / sub r, c instruction.
350 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
351 unsigned NumBits, unsigned Scale) {
353 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
355 if (Opc == ARM::tADDrSPi) {
356 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
360 Scale = 1; // Followed by a number of tADDi8.
361 Chunk = ((1 << NumBits) - 1) * Scale;
364 NumMIs += Bytes / Chunk;
365 if ((Bytes % Chunk) != 0)
372 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
373 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
374 /// in a register using mov / mvn sequences or load the immediate from a
377 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
378 MachineBasicBlock::iterator &MBBI,
379 unsigned DestReg, unsigned BaseReg,
380 int NumBytes, bool CanChangeCC,
381 const TargetInstrInfo &TII,
382 const ARMRegisterInfo& MRI) {
383 bool isHigh = !MRI.isLowRegister(DestReg) ||
384 (BaseReg != 0 && !MRI.isLowRegister(BaseReg));
386 // Subtract doesn't have high register version. Load the negative value
387 // if either base or dest register is a high register. Also, if do not
388 // issue sub as part of the sequence if condition register is to be
390 if (NumBytes < 0 && !isHigh && CanChangeCC) {
392 NumBytes = -NumBytes;
394 unsigned LdReg = DestReg;
395 if (DestReg == ARM::SP) {
396 assert(BaseReg == ARM::SP && "Unexpected!");
398 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12)
399 .addReg(ARM::R3, false, false, true);
402 if (NumBytes <= 255 && NumBytes >= 0)
403 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
404 else if (NumBytes < 0 && NumBytes >= -255) {
405 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
406 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
407 .addReg(LdReg, false, false, true);
409 MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0,&TII,true);
412 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
413 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
414 if (DestReg == ARM::SP || isSub)
415 MIB.addReg(BaseReg).addReg(LdReg, false, false, true);
417 MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
418 if (DestReg == ARM::SP)
419 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3)
420 .addReg(ARM::R12, false, false, true);
423 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
424 /// a destreg = basereg + immediate in Thumb code.
426 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
427 MachineBasicBlock::iterator &MBBI,
428 unsigned DestReg, unsigned BaseReg,
429 int NumBytes, const TargetInstrInfo &TII,
430 const ARMRegisterInfo& MRI) {
431 bool isSub = NumBytes < 0;
432 unsigned Bytes = (unsigned)NumBytes;
433 if (isSub) Bytes = -NumBytes;
434 bool isMul4 = (Bytes & 3) == 0;
435 bool isTwoAddr = false;
436 bool DstNotEqBase = false;
437 unsigned NumBits = 1;
442 if (DestReg == BaseReg && BaseReg == ARM::SP) {
443 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
446 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
448 } else if (!isSub && BaseReg == ARM::SP) {
451 // r1 = add sp, 100 * 4
455 ExtraOpc = ARM::tADDi3;
464 if (DestReg != BaseReg)
467 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
471 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
472 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
473 if (NumMIs > Threshold) {
474 // This will expand into too many instructions. Load the immediate from a
476 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII, MRI);
481 if (MRI.isLowRegister(DestReg) && MRI.isLowRegister(BaseReg)) {
482 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
483 unsigned Chunk = (1 << 3) - 1;
484 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
486 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
487 .addReg(BaseReg, false, false, true).addImm(ThisVal);
489 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg)
490 .addReg(BaseReg, false, false, true);
495 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
497 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
500 // Build the new tADD / tSUB.
502 BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal);
504 bool isKill = BaseReg != ARM::SP;
505 BuildMI(MBB, MBBI, TII.get(Opc), DestReg)
506 .addReg(BaseReg, false, false, isKill).addImm(ThisVal);
509 if (Opc == ARM::tADDrSPi) {
515 Chunk = ((1 << NumBits) - 1) * Scale;
516 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
523 BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg)
524 .addReg(DestReg, false, false, true)
525 .addImm(((unsigned)NumBytes) & 3);
529 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
530 int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg,
531 bool isThumb, const TargetInstrInfo &TII,
532 const ARMRegisterInfo& MRI) {
534 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII, MRI);
536 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
540 void ARMRegisterInfo::
541 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
542 MachineBasicBlock::iterator I) const {
543 if (!hasReservedCallFrame(MF)) {
544 // If we have alloca, convert as follows:
545 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
546 // ADJCALLSTACKUP -> add, sp, sp, amount
547 MachineInstr *Old = I;
548 unsigned Amount = Old->getOperand(0).getImm();
550 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
551 // We need to keep the stack aligned properly. To do this, we round the
552 // amount of space needed for the outgoing arguments up to the next
553 // alignment boundary.
554 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
555 Amount = (Amount+Align-1)/Align*Align;
557 // Replace the pseudo instruction with a new instruction...
558 unsigned Opc = Old->getOpcode();
559 bool isThumb = AFI->isThumbFunction();
560 ARMCC::CondCodes Pred = isThumb
561 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImm();
562 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
563 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
564 unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
565 emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII, *this);
567 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
568 unsigned PredReg = isThumb ? 0 : Old->getOperand(3).getReg();
569 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
570 emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII, *this);
577 /// emitThumbConstant - Emit a series of instructions to materialize a
579 static void emitThumbConstant(MachineBasicBlock &MBB,
580 MachineBasicBlock::iterator &MBBI,
581 unsigned DestReg, int Imm,
582 const TargetInstrInfo &TII,
583 const ARMRegisterInfo& MRI) {
584 bool isSub = Imm < 0;
585 if (isSub) Imm = -Imm;
587 int Chunk = (1 << 8) - 1;
588 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
590 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
592 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI);
594 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg)
595 .addReg(DestReg, false, false, true);
598 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
599 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
600 /// register first and then a spilled callee-saved register if that fails.
602 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
603 ARMFunctionInfo *AFI) {
604 unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
606 // Try a already spilled CS register.
607 Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
612 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
613 int SPAdj, RegScavenger *RS) const{
615 MachineInstr &MI = *II;
616 MachineBasicBlock &MBB = *MI.getParent();
617 MachineFunction &MF = *MBB.getParent();
618 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
619 bool isThumb = AFI->isThumbFunction();
621 while (!MI.getOperand(i).isFI()) {
623 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
626 unsigned FrameReg = ARM::SP;
627 int FrameIndex = MI.getOperand(i).getIndex();
628 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
629 MF.getFrameInfo()->getStackSize() + SPAdj;
631 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
632 Offset -= AFI->getGPRCalleeSavedArea1Offset();
633 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
634 Offset -= AFI->getGPRCalleeSavedArea2Offset();
635 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
636 Offset -= AFI->getDPRCalleeSavedAreaOffset();
637 else if (hasFP(MF)) {
638 assert(SPAdj == 0 && "Unexpected");
639 // There is alloca()'s in this function, must reference off the frame
641 FrameReg = getFrameRegister(MF);
642 Offset -= AFI->getFramePtrSpillOffset();
645 unsigned Opcode = MI.getOpcode();
646 const TargetInstrDesc &Desc = MI.getDesc();
647 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
650 if (Opcode == ARM::ADDri) {
651 Offset += MI.getOperand(i+1).getImm();
653 // Turn it into a move.
654 MI.setDesc(TII.get(ARM::MOVr));
655 MI.getOperand(i).ChangeToRegister(FrameReg, false);
656 MI.RemoveOperand(i+1);
658 } else if (Offset < 0) {
661 MI.setDesc(TII.get(ARM::SUBri));
664 // Common case: small offset, fits into instruction.
665 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
666 if (ImmedOffset != -1) {
667 // Replace the FrameIndex with sp / fp
668 MI.getOperand(i).ChangeToRegister(FrameReg, false);
669 MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
673 // Otherwise, we fallback to common code below to form the imm offset with
674 // a sequence of ADDri instructions. First though, pull as much of the imm
675 // into this ADDri as possible.
676 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
677 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
679 // We will handle these bits from offset, clear them.
680 Offset &= ~ThisImmVal;
682 // Get the properly encoded SOImmVal field.
683 int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
684 assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
685 MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
686 } else if (Opcode == ARM::tADDrSPi) {
687 Offset += MI.getOperand(i+1).getImm();
689 // Can't use tADDrSPi if it's based off the frame pointer.
690 unsigned NumBits = 0;
692 if (FrameReg != ARM::SP) {
693 Opcode = ARM::tADDi3;
694 MI.setDesc(TII.get(ARM::tADDi3));
699 assert((Offset & 3) == 0 &&
700 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
704 // Turn it into a move.
705 MI.setDesc(TII.get(ARM::tMOVr));
706 MI.getOperand(i).ChangeToRegister(FrameReg, false);
707 MI.RemoveOperand(i+1);
711 // Common case: small offset, fits into instruction.
712 unsigned Mask = (1 << NumBits) - 1;
713 if (((Offset / Scale) & ~Mask) == 0) {
714 // Replace the FrameIndex with sp / fp
715 MI.getOperand(i).ChangeToRegister(FrameReg, false);
716 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
720 unsigned DestReg = MI.getOperand(0).getReg();
721 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
722 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
723 // MI would expand into a large number of instructions. Don't try to
724 // simplify the immediate.
726 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII, *this);
732 // Translate r0 = add sp, imm to
733 // r0 = add sp, 255*4
734 // r0 = add r0, (imm - 255*4)
735 MI.getOperand(i).ChangeToRegister(FrameReg, false);
736 MI.getOperand(i+1).ChangeToImmediate(Mask);
737 Offset = (Offset - Mask * Scale);
738 MachineBasicBlock::iterator NII = next(II);
739 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII, *this);
741 // Translate r0 = add sp, -imm to
742 // r0 = -imm (this is then translated into a series of instructons)
744 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this);
745 MI.setDesc(TII.get(ARM::tADDhirr));
746 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
747 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
753 unsigned NumBits = 0;
756 case ARMII::AddrMode2: {
758 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
759 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
764 case ARMII::AddrMode3: {
766 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
767 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
772 case ARMII::AddrMode5: {
774 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
775 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
781 case ARMII::AddrModeTs: {
783 InstrOffs = MI.getOperand(ImmIdx).getImm();
784 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
789 assert(0 && "Unsupported addressing mode!");
794 Offset += InstrOffs * Scale;
795 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
796 if (Offset < 0 && !isThumb) {
801 // Common case: small offset, fits into instruction.
802 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
803 int ImmedOffset = Offset / Scale;
804 unsigned Mask = (1 << NumBits) - 1;
805 if ((unsigned)Offset <= Mask * Scale) {
806 // Replace the FrameIndex with sp
807 MI.getOperand(i).ChangeToRegister(FrameReg, false);
809 ImmedOffset |= 1 << NumBits;
810 ImmOp.ChangeToImmediate(ImmedOffset);
814 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
815 if (AddrMode == ARMII::AddrModeTs) {
816 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
817 // a different base register.
819 Mask = (1 << NumBits) - 1;
821 // If this is a thumb spill / restore, we will be using a constpool load to
822 // materialize the offset.
823 if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore)
824 ImmOp.ChangeToImmediate(0);
826 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
827 ImmedOffset = ImmedOffset & Mask;
829 ImmedOffset |= 1 << NumBits;
830 ImmOp.ChangeToImmediate(ImmedOffset);
831 Offset &= ~(Mask*Scale);
835 // If we get here, the immediate doesn't fit into the instruction. We folded
836 // as much as possible above, handle the rest, providing a register that is
838 assert(Offset && "This code isn't needed if offset already handled!");
841 if (Desc.mayLoad()) {
842 // Use the destination register to materialize sp + offset.
843 unsigned TmpReg = MI.getOperand(0).getReg();
845 if (Opcode == ARM::tRestore) {
846 if (FrameReg == ARM::SP)
847 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
848 Offset, false, TII, *this);
850 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, true);
854 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, *this);
855 MI.setDesc(TII.get(ARM::tLDR));
856 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
858 // Use [reg, reg] addrmode.
859 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
860 else // tLDR has an extra register operand.
861 MI.addOperand(MachineOperand::CreateReg(0, false));
862 } else if (Desc.mayStore()) {
863 // FIXME! This is horrific!!! We need register scavenging.
864 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
865 // also a ABI register so it's possible that is is the register that is
866 // being storing here. If that's the case, we do the following:
868 // Use r2 to materialize sp + offset
871 unsigned ValReg = MI.getOperand(0).getReg();
872 unsigned TmpReg = ARM::R3;
874 if (ValReg == ARM::R3) {
875 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
876 .addReg(ARM::R2, false, false, true);
879 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
880 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
881 .addReg(ARM::R3, false, false, true);
882 if (Opcode == ARM::tSpill) {
883 if (FrameReg == ARM::SP)
884 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
885 Offset, false, TII, *this);
887 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, true);
891 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, *this);
892 MI.setDesc(TII.get(ARM::tSTR));
893 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
894 if (UseRR) // Use [reg, reg] addrmode.
895 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
896 else // tSTR has an extra register operand.
897 MI.addOperand(MachineOperand::CreateReg(0, false));
899 MachineBasicBlock::iterator NII = next(II);
900 if (ValReg == ARM::R3)
901 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2)
902 .addReg(ARM::R12, false, false, true);
903 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
904 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3)
905 .addReg(ARM::R12, false, false, true);
907 assert(false && "Unexpected opcode!");
909 // Insert a set of r12 with the full address: r12 = sp + offset
910 // If the offset we have is too large to fit into the instruction, we need
911 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
913 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
915 // No register is "free". Scavenge a register.
916 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
917 int PIdx = MI.findFirstPredOperandIdx();
918 ARMCC::CondCodes Pred = (PIdx == -1)
919 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
920 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
921 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
922 isSub ? -Offset : Offset, Pred, PredReg, TII);
923 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
927 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
928 const MachineFrameInfo *FFI = MF.getFrameInfo();
930 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
931 int FixedOff = -FFI->getObjectOffset(i);
932 if (FixedOff > Offset) Offset = FixedOff;
934 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
935 if (FFI->isDeadObjectIndex(i))
937 Offset += FFI->getObjectSize(i);
938 unsigned Align = FFI->getObjectAlignment(i);
939 // Adjust to alignment boundary
940 Offset = (Offset+Align-1)/Align*Align;
942 return (unsigned)Offset;
946 ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
947 RegScavenger *RS) const {
948 // This tells PEI to spill the FP as if it is any other callee-save register
949 // to take advantage the eliminateFrameIndex machinery. This also ensures it
950 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
951 // to combine multiple loads / stores.
952 bool CanEliminateFrame = true;
953 bool CS1Spilled = false;
954 bool LRSpilled = false;
955 unsigned NumGPRSpills = 0;
956 SmallVector<unsigned, 4> UnspilledCS1GPRs;
957 SmallVector<unsigned, 4> UnspilledCS2GPRs;
958 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
960 // Don't spill FP if the frame can be eliminated. This is determined
961 // by scanning the callee-save registers to see if any is used.
962 const unsigned *CSRegs = getCalleeSavedRegs();
963 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
964 for (unsigned i = 0; CSRegs[i]; ++i) {
965 unsigned Reg = CSRegs[i];
966 bool Spilled = false;
967 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
968 AFI->setCSRegisterIsSpilled(Reg);
970 CanEliminateFrame = false;
972 // Check alias registers too.
973 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
974 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
976 CanEliminateFrame = false;
981 if (CSRegClasses[i] == &ARM::GPRRegClass) {
985 if (!STI.isTargetDarwin()) {
992 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1007 if (!STI.isTargetDarwin()) {
1008 UnspilledCS1GPRs.push_back(Reg);
1018 UnspilledCS1GPRs.push_back(Reg);
1021 UnspilledCS2GPRs.push_back(Reg);
1028 bool ForceLRSpill = false;
1029 if (!LRSpilled && AFI->isThumbFunction()) {
1030 unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
1031 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1032 // use of BL to implement far jump. If it turns out that it's not needed
1033 // then the branch fix up path will undo it.
1034 if (FnSize >= (1 << 11)) {
1035 CanEliminateFrame = false;
1036 ForceLRSpill = true;
1040 bool ExtraCSSpill = false;
1041 if (!CanEliminateFrame || hasFP(MF)) {
1042 AFI->setHasStackFrame(true);
1044 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1045 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1046 if (!LRSpilled && CS1Spilled) {
1047 MF.getRegInfo().setPhysRegUsed(ARM::LR);
1048 AFI->setCSRegisterIsSpilled(ARM::LR);
1050 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
1051 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
1052 ForceLRSpill = false;
1053 ExtraCSSpill = true;
1056 // Darwin ABI requires FP to point to the stack slot that contains the
1058 if (STI.isTargetDarwin() || hasFP(MF)) {
1059 MF.getRegInfo().setPhysRegUsed(FramePtr);
1063 // If stack and double are 8-byte aligned and we are spilling an odd number
1064 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
1065 // the integer and double callee save areas.
1066 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1067 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
1068 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1069 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1070 unsigned Reg = UnspilledCS1GPRs[i];
1071 // Don't spiil high register if the function is thumb
1072 if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) {
1073 MF.getRegInfo().setPhysRegUsed(Reg);
1074 AFI->setCSRegisterIsSpilled(Reg);
1075 if (!isReservedReg(MF, Reg))
1076 ExtraCSSpill = true;
1080 } else if (!UnspilledCS2GPRs.empty() &&
1081 !AFI->isThumbFunction()) {
1082 unsigned Reg = UnspilledCS2GPRs.front();
1083 MF.getRegInfo().setPhysRegUsed(Reg);
1084 AFI->setCSRegisterIsSpilled(Reg);
1085 if (!isReservedReg(MF, Reg))
1086 ExtraCSSpill = true;
1090 // Estimate if we might need to scavenge a register at some point in order
1091 // to materialize a stack offset. If so, either spill one additiona
1092 // callee-saved register or reserve a special spill slot to facilitate
1093 // register scavenging.
1094 if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) {
1095 MachineFrameInfo *MFI = MF.getFrameInfo();
1096 unsigned Size = estimateStackSize(MF, MFI);
1097 unsigned Limit = (1 << 12) - 1;
1098 for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
1099 for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
1100 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1101 if (I->getOperand(i).isFI()) {
1102 unsigned Opcode = I->getOpcode();
1103 const TargetInstrDesc &Desc = TII.get(Opcode);
1104 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1105 if (AddrMode == ARMII::AddrMode3) {
1106 Limit = (1 << 8) - 1;
1107 goto DoneEstimating;
1108 } else if (AddrMode == ARMII::AddrMode5) {
1109 unsigned ThisLimit = ((1 << 8) - 1) * 4;
1110 if (ThisLimit < Limit)
1116 if (Size >= Limit) {
1117 // If any non-reserved CS register isn't spilled, just spill one or two
1118 // extra. That should take care of it!
1119 unsigned NumExtras = TargetAlign / 4;
1120 SmallVector<unsigned, 2> Extras;
1121 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1122 unsigned Reg = UnspilledCS1GPRs.back();
1123 UnspilledCS1GPRs.pop_back();
1124 if (!isReservedReg(MF, Reg)) {
1125 Extras.push_back(Reg);
1129 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1130 unsigned Reg = UnspilledCS2GPRs.back();
1131 UnspilledCS2GPRs.pop_back();
1132 if (!isReservedReg(MF, Reg)) {
1133 Extras.push_back(Reg);
1137 if (Extras.size() && NumExtras == 0) {
1138 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1139 MF.getRegInfo().setPhysRegUsed(Extras[i]);
1140 AFI->setCSRegisterIsSpilled(Extras[i]);
1143 // Reserve a slot closest to SP or frame pointer.
1144 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1145 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1146 RC->getAlignment()));
1153 MF.getRegInfo().setPhysRegUsed(ARM::LR);
1154 AFI->setCSRegisterIsSpilled(ARM::LR);
1155 AFI->setLRIsSpilledForFarJump(true);
1159 /// Move iterator pass the next bunch of callee save load / store ops for
1160 /// the particular spill area (1: integer area 1, 2: integer area 2,
1161 /// 3: fp area, 0: don't care).
1162 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1163 MachineBasicBlock::iterator &MBBI,
1164 int Opc, unsigned Area,
1165 const ARMSubtarget &STI) {
1166 while (MBBI != MBB.end() &&
1167 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
1170 unsigned Category = 0;
1171 switch (MBBI->getOperand(0).getReg()) {
1172 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1176 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1177 Category = STI.isTargetDarwin() ? 2 : 1;
1179 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1180 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1187 if (Done || Category != Area)
1195 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
1196 MachineBasicBlock &MBB = MF.front();
1197 MachineBasicBlock::iterator MBBI = MBB.begin();
1198 MachineFrameInfo *MFI = MF.getFrameInfo();
1199 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1200 bool isThumb = AFI->isThumbFunction();
1201 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1202 unsigned NumBytes = MFI->getStackSize();
1203 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1206 // Check if R3 is live in. It might have to be used as a scratch register.
1207 for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
1208 E = MF.getRegInfo().livein_end(); I != E; ++I) {
1209 if (I->first == ARM::R3) {
1210 AFI->setR3IsLiveIn(true);
1215 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
1216 NumBytes = (NumBytes + 3) & ~3;
1217 MFI->setStackSize(NumBytes);
1220 // Determine the sizes of each callee-save spill areas and record which frame
1221 // belongs to which callee-save spill areas.
1222 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1223 int FramePtrSpillFI = 0;
1226 emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII, *this);
1228 if (!AFI->hasStackFrame()) {
1230 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
1234 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1235 unsigned Reg = CSI[i].getReg();
1236 int FI = CSI[i].getFrameIdx();
1243 if (Reg == FramePtr)
1244 FramePtrSpillFI = FI;
1245 AFI->addGPRCalleeSavedArea1Frame(FI);
1252 if (Reg == FramePtr)
1253 FramePtrSpillFI = FI;
1254 if (STI.isTargetDarwin()) {
1255 AFI->addGPRCalleeSavedArea2Frame(FI);
1258 AFI->addGPRCalleeSavedArea1Frame(FI);
1263 AFI->addDPRCalleeSavedAreaFrame(FI);
1269 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1270 emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII, *this);
1271 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
1272 } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
1275 // Darwin ABI requires FP to point to the stack slot that contains the
1277 if (STI.isTargetDarwin() || hasFP(MF)) {
1278 MachineInstrBuilder MIB =
1279 BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr)
1280 .addFrameIndex(FramePtrSpillFI).addImm(0);
1281 if (!isThumb) AddDefaultCC(AddDefaultPred(MIB));
1285 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1286 emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII, *this);
1288 // Build the new SUBri to adjust SP for FP callee-save spill area.
1289 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
1290 emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII, *this);
1293 // Determine starting offsets of spill areas.
1294 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1295 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1296 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1297 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1298 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1299 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1300 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1302 NumBytes = DPRCSOffset;
1304 // Insert it after all the callee-save spills.
1306 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
1307 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
1310 if(STI.isTargetELF() && hasFP(MF)) {
1311 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1312 AFI->getFramePtrSpillOffset());
1315 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1316 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1317 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1320 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1321 for (unsigned i = 0; CSRegs[i]; ++i)
1322 if (Reg == CSRegs[i])
1327 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
1328 return ((MI->getOpcode() == ARM::FLDD ||
1329 MI->getOpcode() == ARM::LDR ||
1330 MI->getOpcode() == ARM::tRestore) &&
1331 MI->getOperand(1).isFI() &&
1332 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1335 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
1336 MachineBasicBlock &MBB) const {
1337 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1338 assert((MBBI->getOpcode() == ARM::BX_RET ||
1339 MBBI->getOpcode() == ARM::tBX_RET ||
1340 MBBI->getOpcode() == ARM::tPOP_RET) &&
1341 "Can only insert epilog into returning blocks");
1343 MachineFrameInfo *MFI = MF.getFrameInfo();
1344 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1345 bool isThumb = AFI->isThumbFunction();
1346 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1347 int NumBytes = (int)MFI->getStackSize();
1348 if (!AFI->hasStackFrame()) {
1350 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
1352 // Unwind MBBI to point to first LDR / FLDD.
1353 const unsigned *CSRegs = getCalleeSavedRegs();
1354 if (MBBI != MBB.begin()) {
1357 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
1358 if (!isCSRestore(MBBI, CSRegs))
1362 // Move SP to start of FP callee save spill area.
1363 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1364 AFI->getGPRCalleeSavedArea2Size() +
1365 AFI->getDPRCalleeSavedAreaSize());
1368 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1369 // Reset SP based on frame pointer only if the stack frame extends beyond
1370 // frame pointer stack slot or target is ELF and the function has FP.
1372 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
1375 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr);
1377 if (MBBI->getOpcode() == ARM::tBX_RET &&
1378 &MBB.front() != MBBI &&
1379 prior(MBBI)->getOpcode() == ARM::tPOP) {
1380 MachineBasicBlock::iterator PMBBI = prior(MBBI);
1381 emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
1383 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
1386 // Darwin ABI requires FP to point to the stack slot that contains the
1388 if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
1389 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1390 // Reset SP based on frame pointer only if the stack frame extends beyond
1391 // frame pointer stack slot or target is ELF and the function has FP.
1392 if (AFI->getGPRCalleeSavedArea2Size() ||
1393 AFI->getDPRCalleeSavedAreaSize() ||
1394 AFI->getDPRCalleeSavedAreaOffset()||
1397 BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
1399 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1401 BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
1402 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1404 } else if (NumBytes) {
1405 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this);
1408 // Move SP to start of integer callee save spill area 2.
1409 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
1410 emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0,
1413 // Move SP to start of integer callee save spill area 1.
1414 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
1415 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0,
1418 // Move SP to SP upon entry to the function.
1419 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1420 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0,
1425 if (VARegSaveSize) {
1427 // Epilogue for vararg functions: pop LR to R3 and branch off it.
1428 // FIXME: Verify this is still ok when R3 is no longer being reserved.
1429 BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3);
1431 emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII, *this);
1434 BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
1440 unsigned ARMRegisterInfo::getRARegister() const {
1444 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1445 if (STI.isTargetDarwin() || hasFP(MF))
1446 return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11;
1451 unsigned ARMRegisterInfo::getEHExceptionRegister() const {
1452 assert(0 && "What is the exception register");
1456 unsigned ARMRegisterInfo::getEHHandlerRegister() const {
1457 assert(0 && "What is the exception handler register");
1461 int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1462 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1465 #include "ARMGenRegisterInfo.inc"