1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/raw_ostream.h"
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
30 class ARMMCCodeEmitter : public MCCodeEmitter {
31 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33 const TargetMachine &TM;
34 const TargetInstrInfo &TII;
38 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
42 ~ARMMCCodeEmitter() {}
44 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
46 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
47 const static MCFixupKindInfo Infos[] = {
48 // name off bits flags
49 { "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
50 { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
51 { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
52 { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
53 { "fixup_arm_movt_hi16", 0, 16, 0 },
54 { "fixup_arm_movw_lo16", 0, 16, 0 },
57 if (Kind < FirstTargetFixupKind)
58 return MCCodeEmitter::getFixupKindInfo(Kind);
60 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
62 return Infos[Kind - FirstTargetFixupKind];
64 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
66 // getBinaryCodeForInstr - TableGen'erated function for getting the
67 // binary encoding for an instruction.
68 unsigned getBinaryCodeForInstr(const MCInst &MI,
69 SmallVectorImpl<MCFixup> &Fixups) const;
71 /// getMachineOpValue - Return binary encoding of operand. If the machine
72 /// operand requires relocation, record the relocation and return zero.
73 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
74 SmallVectorImpl<MCFixup> &Fixups) const;
76 /// getMovtImmOpValue - Return the encoding for the movw/movt pair
77 uint32_t getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
78 SmallVectorImpl<MCFixup> &Fixups) const;
80 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
81 unsigned &Reg, unsigned &Imm,
82 SmallVectorImpl<MCFixup> &Fixups) const;
84 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
86 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
87 SmallVectorImpl<MCFixup> &Fixups) const;
89 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
91 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
92 SmallVectorImpl<MCFixup> &Fixups) const;
94 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
96 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
97 SmallVectorImpl<MCFixup> &Fixups) const;
99 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
101 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
102 SmallVectorImpl<MCFixup> &Fixups) const;
105 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
106 /// operand as needed by load/store instructions.
107 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
108 SmallVectorImpl<MCFixup> &Fixups) const;
110 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
111 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
112 SmallVectorImpl<MCFixup> &Fixups) const {
113 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
115 default: assert(0 && "Unknown addressing sub-mode!");
116 case ARM_AM::da: return 0;
117 case ARM_AM::ia: return 1;
118 case ARM_AM::db: return 2;
119 case ARM_AM::ib: return 3;
122 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
124 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
126 default: llvm_unreachable("Unknown shift opc!");
127 case ARM_AM::no_shift:
128 case ARM_AM::lsl: return 0;
129 case ARM_AM::lsr: return 1;
130 case ARM_AM::asr: return 2;
132 case ARM_AM::rrx: return 3;
137 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
138 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
139 SmallVectorImpl<MCFixup> &Fixups) const;
141 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
142 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
143 SmallVectorImpl<MCFixup> &Fixups) const;
145 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
146 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
147 SmallVectorImpl<MCFixup> &Fixups) const;
149 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
150 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
151 SmallVectorImpl<MCFixup> &Fixups) const;
153 /// getAddrModeS4OpValue - Return encoding for t_addrmode_s4 operands.
154 uint32_t getAddrModeS4OpValue(const MCInst &MI, unsigned OpIdx,
155 SmallVectorImpl<MCFixup> &Fixups) const;
157 /// getAddrModeS2OpValue - Return encoding for t_addrmode_s2 operands.
158 uint32_t getAddrModeS2OpValue(const MCInst &MI, unsigned OpIdx,
159 SmallVectorImpl<MCFixup> &Fixups) const;
161 /// getAddrModeS1OpValue - Return encoding for t_addrmode_s1 operands.
162 uint32_t getAddrModeS1OpValue(const MCInst &MI, unsigned OpIdx,
163 SmallVectorImpl<MCFixup> &Fixups) const;
165 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
166 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
167 SmallVectorImpl<MCFixup> &Fixups) const;
169 /// getCCOutOpValue - Return encoding of the 's' bit.
170 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
171 SmallVectorImpl<MCFixup> &Fixups) const {
172 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
174 return MI.getOperand(Op).getReg() == ARM::CPSR;
177 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
178 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
179 SmallVectorImpl<MCFixup> &Fixups) const {
180 unsigned SoImm = MI.getOperand(Op).getImm();
181 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
182 assert(SoImmVal != -1 && "Not a valid so_imm value!");
184 // Encode rotate_imm.
185 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
186 << ARMII::SoRotImmShift;
189 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
193 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
194 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
195 SmallVectorImpl<MCFixup> &Fixups) const {
196 unsigned SoImm = MI.getOperand(Op).getImm();
197 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
198 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
202 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
203 SmallVectorImpl<MCFixup> &Fixups) const;
204 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
205 SmallVectorImpl<MCFixup> &Fixups) const;
206 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
207 SmallVectorImpl<MCFixup> &Fixups) const;
208 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
209 SmallVectorImpl<MCFixup> &Fixups) const;
211 /// getSORegOpValue - Return an encoded so_reg shifted register value.
212 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
213 SmallVectorImpl<MCFixup> &Fixups) const;
214 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
215 SmallVectorImpl<MCFixup> &Fixups) const;
217 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
218 SmallVectorImpl<MCFixup> &Fixups) const {
219 switch (MI.getOperand(Op).getImm()) {
220 default: assert (0 && "Not a valid rot_imm value!");
228 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
229 SmallVectorImpl<MCFixup> &Fixups) const {
230 return MI.getOperand(Op).getImm() - 1;
233 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
234 SmallVectorImpl<MCFixup> &Fixups) const {
235 return 64 - MI.getOperand(Op).getImm();
238 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
239 SmallVectorImpl<MCFixup> &Fixups) const;
241 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
242 SmallVectorImpl<MCFixup> &Fixups) const;
243 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
244 SmallVectorImpl<MCFixup> &Fixups) const;
245 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
246 SmallVectorImpl<MCFixup> &Fixups) const;
247 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
248 SmallVectorImpl<MCFixup> &Fixups) const;
250 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
251 unsigned EncodedValue) const;
252 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
253 unsigned EncodedValue) const;
254 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
255 unsigned EncodedValue) const;
257 unsigned VFPThumb2PostEncoder(const MCInst &MI,
258 unsigned EncodedValue) const;
260 void EmitByte(unsigned char C, raw_ostream &OS) const {
264 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
265 // Output the constant in little endian byte order.
266 for (unsigned i = 0; i != Size; ++i) {
267 EmitByte(Val & 255, OS);
272 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
273 SmallVectorImpl<MCFixup> &Fixups) const;
276 } // end anonymous namespace
278 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
280 return new ARMMCCodeEmitter(TM, Ctx);
283 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
284 /// instructions, and rewrite them to their Thumb2 form if we are currently in
286 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
287 unsigned EncodedValue) const {
288 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
289 if (Subtarget.isThumb2()) {
290 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
291 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
293 unsigned Bit24 = EncodedValue & 0x01000000;
294 unsigned Bit28 = Bit24 << 4;
295 EncodedValue &= 0xEFFFFFFF;
296 EncodedValue |= Bit28;
297 EncodedValue |= 0x0F000000;
303 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
304 /// instructions, and rewrite them to their Thumb2 form if we are currently in
306 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
307 unsigned EncodedValue) const {
308 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
309 if (Subtarget.isThumb2()) {
310 EncodedValue &= 0xF0FFFFFF;
311 EncodedValue |= 0x09000000;
317 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
318 /// instructions, and rewrite them to their Thumb2 form if we are currently in
320 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
321 unsigned EncodedValue) const {
322 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
323 if (Subtarget.isThumb2()) {
324 EncodedValue &= 0x00FFFFFF;
325 EncodedValue |= 0xEE000000;
331 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
332 /// them to their Thumb2 form if we are currently in Thumb2 mode.
333 unsigned ARMMCCodeEmitter::
334 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
335 if (TM.getSubtarget<ARMSubtarget>().isThumb2()) {
336 EncodedValue &= 0x0FFFFFFF;
337 EncodedValue |= 0xE0000000;
342 /// getMachineOpValue - Return binary encoding of operand. If the machine
343 /// operand requires relocation, record the relocation and return zero.
344 unsigned ARMMCCodeEmitter::
345 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
346 SmallVectorImpl<MCFixup> &Fixups) const {
348 unsigned Reg = MO.getReg();
349 unsigned RegNo = getARMRegisterNumbering(Reg);
351 // Q registers are encoded as 2x their register number.
355 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
356 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
357 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
358 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
361 } else if (MO.isImm()) {
362 return static_cast<unsigned>(MO.getImm());
363 } else if (MO.isFPImm()) {
364 return static_cast<unsigned>(APFloat(MO.getFPImm())
365 .bitcastToAPInt().getHiBits(32).getLimitedValue());
368 llvm_unreachable("Unable to encode MCOperand!");
372 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
373 bool ARMMCCodeEmitter::
374 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
375 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
376 const MCOperand &MO = MI.getOperand(OpIdx);
377 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
379 Reg = getARMRegisterNumbering(MO.getReg());
381 int32_t SImm = MO1.getImm();
384 // Special value for #-0
385 if (SImm == INT32_MIN)
388 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
398 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
400 uint32_t ARMMCCodeEmitter::
401 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
402 SmallVectorImpl<MCFixup> &Fixups) const {
403 const MCOperand &MO = MI.getOperand(OpIdx);
405 // If the destination is an immediate, we have nothing to do.
406 if (MO.isImm()) return MO.getImm();
407 assert (MO.isExpr() && "Unexpected branch target type!");
408 const MCExpr *Expr = MO.getExpr();
409 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_branch);
410 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
412 // All of the information is in the fixup.
416 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
417 /// ADR label target.
418 uint32_t ARMMCCodeEmitter::
419 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
420 SmallVectorImpl<MCFixup> &Fixups) const {
421 const MCOperand &MO = MI.getOperand(OpIdx);
422 assert (MO.isExpr() && "Unexpected adr target type!");
423 const MCExpr *Expr = MO.getExpr();
424 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_adr_pcrel_12);
425 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
426 // All of the information is in the fixup.
430 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
431 uint32_t ARMMCCodeEmitter::
432 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
433 SmallVectorImpl<MCFixup> &Fixups) const {
435 // {12} = (U)nsigned (add == '1', sub == '0')
439 // If The first operand isn't a register, we have a label reference.
440 const MCOperand &MO = MI.getOperand(OpIdx);
442 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
444 isAdd = false ; // 'U' bit is set as part of the fixup.
446 assert(MO.isExpr() && "Unexpected machine operand type!");
447 const MCExpr *Expr = MO.getExpr();
448 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
449 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
451 ++MCNumCPRelocations;
453 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
455 uint32_t Binary = Imm12 & 0xfff;
456 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
459 Binary |= (Reg << 13);
463 /// getT2AddrModeImm8s4OpValue - Return encoding info for
464 /// 'reg +/- imm8<<2' operand.
465 uint32_t ARMMCCodeEmitter::
466 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
467 SmallVectorImpl<MCFixup> &Fixups) const {
469 // {12} = (U)nsigned (add == '1', sub == '0')
473 // If The first operand isn't a register, we have a label reference.
474 const MCOperand &MO = MI.getOperand(OpIdx);
476 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
478 isAdd = false ; // 'U' bit is set as part of the fixup.
480 assert(MO.isExpr() && "Unexpected machine operand type!");
481 const MCExpr *Expr = MO.getExpr();
482 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
483 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
485 ++MCNumCPRelocations;
487 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
489 uint32_t Binary = (Imm8 >> 2) & 0xff;
490 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
493 Binary |= (Reg << 9);
497 uint32_t ARMMCCodeEmitter::
498 getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
499 SmallVectorImpl<MCFixup> &Fixups) const {
500 // {20-16} = imm{15-12}
501 // {11-0} = imm{11-0}
502 const MCOperand &MO = MI.getOperand(OpIdx);
504 return static_cast<unsigned>(MO.getImm());
505 } else if (const MCSymbolRefExpr *Expr =
506 dyn_cast<MCSymbolRefExpr>(MO.getExpr())) {
508 switch (Expr->getKind()) {
509 default: assert(0 && "Unsupported ARMFixup");
510 case MCSymbolRefExpr::VK_ARM_HI16:
511 Kind = MCFixupKind(ARM::fixup_arm_movt_hi16);
513 case MCSymbolRefExpr::VK_ARM_LO16:
514 Kind = MCFixupKind(ARM::fixup_arm_movw_lo16);
517 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
520 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
524 uint32_t ARMMCCodeEmitter::
525 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
526 SmallVectorImpl<MCFixup> &Fixups) const {
527 const MCOperand &MO = MI.getOperand(OpIdx);
528 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
529 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
530 unsigned Rn = getARMRegisterNumbering(MO.getReg());
531 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
532 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
533 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
534 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
535 unsigned SBits = getShiftOp(ShOp);
544 uint32_t Binary = Rm;
546 Binary |= SBits << 5;
547 Binary |= ShImm << 7;
553 uint32_t ARMMCCodeEmitter::
554 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
555 SmallVectorImpl<MCFixup> &Fixups) const {
557 // {13} 1 == imm12, 0 == Rm
560 const MCOperand &MO = MI.getOperand(OpIdx);
561 unsigned Rn = getARMRegisterNumbering(MO.getReg());
562 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
567 uint32_t ARMMCCodeEmitter::
568 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
569 SmallVectorImpl<MCFixup> &Fixups) const {
570 // {13} 1 == imm12, 0 == Rm
573 const MCOperand &MO = MI.getOperand(OpIdx);
574 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
575 unsigned Imm = MO1.getImm();
576 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
577 bool isReg = MO.getReg() != 0;
578 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
579 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
581 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
582 Binary <<= 7; // Shift amount is bits [11:7]
583 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
584 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
586 return Binary | (isAdd << 12) | (isReg << 13);
589 uint32_t ARMMCCodeEmitter::
590 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
591 SmallVectorImpl<MCFixup> &Fixups) const {
592 // {9} 1 == imm8, 0 == Rm
596 const MCOperand &MO = MI.getOperand(OpIdx);
597 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
598 unsigned Imm = MO1.getImm();
599 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
600 bool isImm = MO.getReg() == 0;
601 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
602 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
604 Imm8 = getARMRegisterNumbering(MO.getReg());
605 return Imm8 | (isAdd << 8) | (isImm << 9);
608 uint32_t ARMMCCodeEmitter::
609 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
610 SmallVectorImpl<MCFixup> &Fixups) const {
611 // {13} 1 == imm8, 0 == Rm
616 const MCOperand &MO = MI.getOperand(OpIdx);
617 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
618 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
619 unsigned Rn = getARMRegisterNumbering(MO.getReg());
620 unsigned Imm = MO2.getImm();
621 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
622 bool isImm = MO1.getReg() == 0;
623 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
624 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
626 Imm8 = getARMRegisterNumbering(MO1.getReg());
627 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
630 /// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
631 static unsigned getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
640 const MCOperand &MO = MI.getOperand(OpIdx);
641 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
642 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
643 unsigned Rn = getARMRegisterNumbering(MO.getReg());
644 unsigned Imm5 = (MO1.getImm() / Scale) & 0x1f;
646 if (MO2.getReg() != 0)
648 Imm5 = getARMRegisterNumbering(MO2.getReg());
650 return (Imm5 << 3) | Rn;
653 /// getAddrModeS4OpValue - Return encoding for t_addrmode_s4 operands.
654 uint32_t ARMMCCodeEmitter::
655 getAddrModeS4OpValue(const MCInst &MI, unsigned OpIdx,
656 SmallVectorImpl<MCFixup> &) const {
657 return getAddrModeSOpValue(MI, OpIdx, 4);
660 /// getAddrModeS2OpValue - Return encoding for t_addrmode_s2 operands.
661 uint32_t ARMMCCodeEmitter::
662 getAddrModeS2OpValue(const MCInst &MI, unsigned OpIdx,
663 SmallVectorImpl<MCFixup> &) const {
664 return getAddrModeSOpValue(MI, OpIdx, 2);
667 /// getAddrModeS1OpValue - Return encoding for t_addrmode_s1 operands.
668 uint32_t ARMMCCodeEmitter::
669 getAddrModeS1OpValue(const MCInst &MI, unsigned OpIdx,
670 SmallVectorImpl<MCFixup> &) const {
671 return getAddrModeSOpValue(MI, OpIdx, 1);
674 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
675 uint32_t ARMMCCodeEmitter::
676 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
677 SmallVectorImpl<MCFixup> &Fixups) const {
679 // {8} = (U)nsigned (add == '1', sub == '0')
683 // If The first operand isn't a register, we have a label reference.
684 const MCOperand &MO = MI.getOperand(OpIdx);
686 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
688 isAdd = false; // 'U' bit is handled as part of the fixup.
690 assert(MO.isExpr() && "Unexpected machine operand type!");
691 const MCExpr *Expr = MO.getExpr();
692 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
693 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
695 ++MCNumCPRelocations;
697 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
698 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
701 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
702 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
705 Binary |= (Reg << 9);
709 unsigned ARMMCCodeEmitter::
710 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
711 SmallVectorImpl<MCFixup> &Fixups) const {
712 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
713 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
714 // case the imm contains the amount to shift by.
717 // {4} = 1 if reg shift, 0 if imm shift
725 const MCOperand &MO = MI.getOperand(OpIdx);
726 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
727 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
728 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
731 unsigned Binary = getARMRegisterNumbering(MO.getReg());
733 // Encode the shift opcode.
735 unsigned Rs = MO1.getReg();
737 // Set shift operand (bit[7:4]).
742 // RRX - 0110 and bit[11:8] clear.
744 default: llvm_unreachable("Unknown shift opc!");
745 case ARM_AM::lsl: SBits = 0x1; break;
746 case ARM_AM::lsr: SBits = 0x3; break;
747 case ARM_AM::asr: SBits = 0x5; break;
748 case ARM_AM::ror: SBits = 0x7; break;
749 case ARM_AM::rrx: SBits = 0x6; break;
752 // Set shift operand (bit[6:4]).
758 default: llvm_unreachable("Unknown shift opc!");
759 case ARM_AM::lsl: SBits = 0x0; break;
760 case ARM_AM::lsr: SBits = 0x2; break;
761 case ARM_AM::asr: SBits = 0x4; break;
762 case ARM_AM::ror: SBits = 0x6; break;
766 Binary |= SBits << 4;
767 if (SOpc == ARM_AM::rrx)
770 // Encode the shift operation Rs or shift_imm (except rrx).
772 // Encode Rs bit[11:8].
773 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
774 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
777 // Encode shift_imm bit[11:7].
778 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
781 unsigned ARMMCCodeEmitter::
782 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
783 SmallVectorImpl<MCFixup> &Fixups) const {
784 const MCOperand &MO1 = MI.getOperand(OpNum);
785 const MCOperand &MO2 = MI.getOperand(OpNum+1);
786 const MCOperand &MO3 = MI.getOperand(OpNum+2);
788 // Encoded as [Rn, Rm, imm].
789 // FIXME: Needs fixup support.
790 unsigned Value = getARMRegisterNumbering(MO1.getReg());
792 Value |= getARMRegisterNumbering(MO2.getReg());
794 Value |= MO3.getImm();
799 unsigned ARMMCCodeEmitter::
800 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
801 SmallVectorImpl<MCFixup> &Fixups) const {
802 const MCOperand &MO1 = MI.getOperand(OpNum);
803 const MCOperand &MO2 = MI.getOperand(OpNum+1);
805 // FIXME: Needs fixup support.
806 unsigned Value = getARMRegisterNumbering(MO1.getReg());
808 // Even though the immediate is 8 bits long, we need 9 bits in order
809 // to represent the (inverse of the) sign bit.
811 int32_t tmp = (int32_t)MO2.getImm();
815 Value |= 256; // Set the ADD bit
820 unsigned ARMMCCodeEmitter::
821 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
822 SmallVectorImpl<MCFixup> &Fixups) const {
823 const MCOperand &MO1 = MI.getOperand(OpNum);
825 // FIXME: Needs fixup support.
827 int32_t tmp = (int32_t)MO1.getImm();
831 Value |= 256; // Set the ADD bit
836 unsigned ARMMCCodeEmitter::
837 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
838 SmallVectorImpl<MCFixup> &Fixups) const {
839 const MCOperand &MO1 = MI.getOperand(OpNum);
841 // FIXME: Needs fixup support.
843 int32_t tmp = (int32_t)MO1.getImm();
847 Value |= 4096; // Set the ADD bit
852 unsigned ARMMCCodeEmitter::
853 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
854 SmallVectorImpl<MCFixup> &Fixups) const {
855 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
856 // shifted. The second is the amount to shift by.
863 const MCOperand &MO = MI.getOperand(OpIdx);
864 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
865 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
868 unsigned Binary = getARMRegisterNumbering(MO.getReg());
870 // Encode the shift opcode.
872 // Set shift operand (bit[6:4]).
878 default: llvm_unreachable("Unknown shift opc!");
879 case ARM_AM::lsl: SBits = 0x0; break;
880 case ARM_AM::lsr: SBits = 0x2; break;
881 case ARM_AM::asr: SBits = 0x4; break;
882 case ARM_AM::ror: SBits = 0x6; break;
885 Binary |= SBits << 4;
886 if (SOpc == ARM_AM::rrx)
889 // Encode shift_imm bit[11:7].
890 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
893 unsigned ARMMCCodeEmitter::
894 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
895 SmallVectorImpl<MCFixup> &Fixups) const {
896 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
898 const MCOperand &MO = MI.getOperand(Op);
899 uint32_t v = ~MO.getImm();
900 uint32_t lsb = CountTrailingZeros_32(v);
901 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
902 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
903 return lsb | (msb << 5);
906 unsigned ARMMCCodeEmitter::
907 getRegisterListOpValue(const MCInst &MI, unsigned Op,
908 SmallVectorImpl<MCFixup> &Fixups) const {
911 // {7-0} = Number of registers
914 // {15-0} = Bitfield of GPRs.
915 unsigned Reg = MI.getOperand(Op).getReg();
916 bool SPRRegs = ARM::SPRRegClass.contains(Reg);
917 bool DPRRegs = ARM::DPRRegClass.contains(Reg);
921 if (SPRRegs || DPRRegs) {
923 unsigned RegNo = getARMRegisterNumbering(Reg);
924 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
925 Binary |= (RegNo & 0x1f) << 8;
929 Binary |= NumRegs * 2;
931 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
932 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
933 Binary |= 1 << RegNo;
940 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
941 /// with the alignment operand.
942 unsigned ARMMCCodeEmitter::
943 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
944 SmallVectorImpl<MCFixup> &Fixups) const {
945 const MCOperand &Reg = MI.getOperand(Op);
946 const MCOperand &Imm = MI.getOperand(Op + 1);
948 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
951 switch (Imm.getImm()) {
955 case 8: Align = 0x01; break;
956 case 16: Align = 0x02; break;
957 case 32: Align = 0x03; break;
960 return RegNo | (Align << 4);
963 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
964 /// alignment operand for use in VLD-dup instructions. This is the same as
965 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
966 /// different for VLD4-dup.
967 unsigned ARMMCCodeEmitter::
968 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
969 SmallVectorImpl<MCFixup> &Fixups) const {
970 const MCOperand &Reg = MI.getOperand(Op);
971 const MCOperand &Imm = MI.getOperand(Op + 1);
973 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
976 switch (Imm.getImm()) {
980 case 8: Align = 0x01; break;
981 case 16: Align = 0x03; break;
984 return RegNo | (Align << 4);
987 unsigned ARMMCCodeEmitter::
988 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
989 SmallVectorImpl<MCFixup> &Fixups) const {
990 const MCOperand &MO = MI.getOperand(Op);
991 if (MO.getReg() == 0) return 0x0D;
995 void ARMMCCodeEmitter::
996 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
997 SmallVectorImpl<MCFixup> &Fixups) const {
998 // Pseudo instructions don't get encoded.
999 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
1000 uint64_t TSFlags = Desc.TSFlags;
1001 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1004 // Basic size info comes from the TSFlags field.
1005 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
1006 default: llvm_unreachable("Unexpected instruction size!");
1007 case ARMII::Size2Bytes: Size = 2; break;
1008 case ARMII::Size4Bytes: Size = 4; break;
1010 EmitConstant(getBinaryCodeForInstr(MI, Fixups), Size, OS);
1011 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1014 #include "ARMGenMCCodeEmitter.inc"