1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-emitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/raw_ostream.h"
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
30 class ARMMCCodeEmitter : public MCCodeEmitter {
31 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33 const TargetMachine &TM;
34 const TargetInstrInfo &TII;
38 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
42 ~ARMMCCodeEmitter() {}
44 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
46 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
47 const static MCFixupKindInfo Infos[] = {
48 // name offset bits flags
49 { "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel },
50 { "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel },
51 { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
54 if (Kind < FirstTargetFixupKind)
55 return MCCodeEmitter::getFixupKindInfo(Kind);
57 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
59 return Infos[Kind - FirstTargetFixupKind];
61 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
63 // getBinaryCodeForInstr - TableGen'erated function for getting the
64 // binary encoding for an instruction.
65 unsigned getBinaryCodeForInstr(const MCInst &MI,
66 SmallVectorImpl<MCFixup> &Fixups) const;
68 /// getMachineOpValue - Return binary encoding of operand. If the machine
69 /// operand requires relocation, record the relocation and return zero.
70 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
71 SmallVectorImpl<MCFixup> &Fixups) const;
73 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
74 unsigned &Reg, unsigned &Imm,
75 SmallVectorImpl<MCFixup> &Fixups) const;
77 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
79 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
80 SmallVectorImpl<MCFixup> &Fixups) const;
82 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
84 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
85 SmallVectorImpl<MCFixup> &Fixups) const;
87 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
88 /// operand as needed by load/store instructions.
89 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
90 SmallVectorImpl<MCFixup> &Fixups) const;
92 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
93 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
94 SmallVectorImpl<MCFixup> &Fixups) const {
95 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
97 default: assert(0 && "Unknown addressing sub-mode!");
98 case ARM_AM::da: return 0;
99 case ARM_AM::ia: return 1;
100 case ARM_AM::db: return 2;
101 case ARM_AM::ib: return 3;
104 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
105 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
106 SmallVectorImpl<MCFixup> &Fixups) const;
108 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
109 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
110 SmallVectorImpl<MCFixup> &Fixups) const;
112 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
113 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
114 SmallVectorImpl<MCFixup> &Fixups) const;
116 /// getCCOutOpValue - Return encoding of the 's' bit.
117 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
118 SmallVectorImpl<MCFixup> &Fixups) const {
119 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
121 return MI.getOperand(Op).getReg() == ARM::CPSR;
124 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
125 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
126 SmallVectorImpl<MCFixup> &Fixups) const {
127 unsigned SoImm = MI.getOperand(Op).getImm();
128 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
129 assert(SoImmVal != -1 && "Not a valid so_imm value!");
131 // Encode rotate_imm.
132 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
133 << ARMII::SoRotImmShift;
136 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
140 /// getSORegOpValue - Return an encoded so_reg shifted register value.
141 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
142 SmallVectorImpl<MCFixup> &Fixups) const;
144 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
145 SmallVectorImpl<MCFixup> &Fixups) const {
146 switch (MI.getOperand(Op).getImm()) {
147 default: assert (0 && "Not a valid rot_imm value!");
155 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
156 SmallVectorImpl<MCFixup> &Fixups) const {
157 return MI.getOperand(Op).getImm() - 1;
160 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
161 SmallVectorImpl<MCFixup> &Fixups) const {
162 return 64 - MI.getOperand(Op).getImm();
165 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
166 SmallVectorImpl<MCFixup> &Fixups) const;
168 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
169 SmallVectorImpl<MCFixup> &Fixups) const;
170 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
171 SmallVectorImpl<MCFixup> &Fixups) const;
172 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
173 SmallVectorImpl<MCFixup> &Fixups) const;
175 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
176 unsigned EncodedValue) const;
178 void EmitByte(unsigned char C, raw_ostream &OS) const {
182 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
183 // Output the constant in little endian byte order.
184 for (unsigned i = 0; i != Size; ++i) {
185 EmitByte(Val & 255, OS);
190 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
191 SmallVectorImpl<MCFixup> &Fixups) const;
194 } // end anonymous namespace
196 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
198 return new ARMMCCodeEmitter(TM, Ctx);
201 /// NEONThumb2PostEncoder - Post-process encoded NEON data-processing
202 /// instructions, and rewrite them to their Thumb2 form if we are currently in
204 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
205 unsigned EncodedValue) const {
206 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
207 if (Subtarget.isThumb2()) {
208 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
209 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
211 unsigned Bit24 = EncodedValue & 0x01000000;
212 unsigned Bit28 = Bit24 << 4;
213 EncodedValue &= 0xEFFFFFFF;
214 EncodedValue |= Bit28;
215 EncodedValue |= 0x0F000000;
221 /// getMachineOpValue - Return binary encoding of operand. If the machine
222 /// operand requires relocation, record the relocation and return zero.
223 unsigned ARMMCCodeEmitter::
224 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
225 SmallVectorImpl<MCFixup> &Fixups) const {
227 unsigned Reg = MO.getReg();
228 unsigned RegNo = getARMRegisterNumbering(Reg);
230 // Q registers are encodes as 2x their register number.
234 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
235 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
236 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
237 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
240 } else if (MO.isImm()) {
241 return static_cast<unsigned>(MO.getImm());
242 } else if (MO.isFPImm()) {
243 return static_cast<unsigned>(APFloat(MO.getFPImm())
244 .bitcastToAPInt().getHiBits(32).getLimitedValue());
254 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
255 bool ARMMCCodeEmitter::
256 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
257 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
258 const MCOperand &MO = MI.getOperand(OpIdx);
259 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
261 Reg = getARMRegisterNumbering(MO.getReg());
263 int32_t SImm = MO1.getImm();
266 // Special value for #-0
267 if (SImm == INT32_MIN)
270 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
280 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
282 uint32_t ARMMCCodeEmitter::
283 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
284 SmallVectorImpl<MCFixup> &Fixups) const {
285 const MCOperand &MO = MI.getOperand(OpIdx);
287 // If the destination is an immediate, we have nothing to do.
288 if (MO.isImm()) return MO.getImm();
289 assert (MO.isExpr() && "Unexpected branch target type!");
290 const MCExpr *Expr = MO.getExpr();
291 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_branch);
292 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
294 // All of the information is in the fixup.
298 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
299 uint32_t ARMMCCodeEmitter::
300 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
301 SmallVectorImpl<MCFixup> &Fixups) const {
303 // {12} = (U)nsigned (add == '1', sub == '0')
307 // If The first operand isn't a register, we have a label reference.
308 const MCOperand &MO = MI.getOperand(OpIdx);
310 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
313 assert(MO.isExpr() && "Unexpected machine operand type!");
314 const MCExpr *Expr = MO.getExpr();
315 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
316 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
318 ++MCNumCPRelocations;
320 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
322 uint32_t Binary = Imm12 & 0xfff;
323 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
326 Binary |= (Reg << 13);
330 uint32_t ARMMCCodeEmitter::
331 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
332 SmallVectorImpl<MCFixup> &Fixups) const {
333 const MCOperand &MO = MI.getOperand(OpIdx);
334 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
335 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
336 unsigned Rn = getARMRegisterNumbering(MO.getReg());
337 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
338 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
339 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
340 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
347 default: llvm_unreachable("Unknown shift opc!");
348 case ARM_AM::no_shift:
349 assert(ShImm == 0 && "Non-zero shift amount with no shift type!");
351 case ARM_AM::lsl: SBits = 0x0; break;
352 case ARM_AM::lsr: SBits = 0x1; break;
353 case ARM_AM::asr: SBits = 0x2; break;
354 case ARM_AM::ror: SBits = 0x3; break;
364 uint32_t Binary = Rm;
366 Binary |= SBits << 5;
367 Binary |= ShImm << 7;
373 uint32_t ARMMCCodeEmitter::
374 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
375 SmallVectorImpl<MCFixup> &Fixups) const {
376 // {9} 1 == imm8, 0 == Rm
380 const MCOperand &MO = MI.getOperand(OpIdx);
381 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
382 unsigned Imm = MO1.getImm();
383 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
384 bool isImm = MO.getReg() == 0;
385 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
386 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
388 Imm8 = getARMRegisterNumbering(MO.getReg());
389 return Imm8 | (isAdd << 8) | (isImm << 9);
392 uint32_t ARMMCCodeEmitter::
393 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
394 SmallVectorImpl<MCFixup> &Fixups) const {
395 // {13} 1 == imm8, 0 == Rm
400 const MCOperand &MO = MI.getOperand(OpIdx);
401 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
402 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
403 unsigned Rn = getARMRegisterNumbering(MO.getReg());
404 unsigned Imm = MO2.getImm();
405 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
406 bool isImm = MO1.getReg() == 0;
407 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
408 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
410 Imm8 = getARMRegisterNumbering(MO1.getReg());
411 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
414 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
415 uint32_t ARMMCCodeEmitter::
416 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
417 SmallVectorImpl<MCFixup> &Fixups) const {
419 // {8} = (U)nsigned (add == '1', sub == '0')
422 // If The first operand isn't a register, we have a label reference.
423 const MCOperand &MO = MI.getOperand(OpIdx);
425 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
428 assert(MO.isExpr() && "Unexpected machine operand type!");
429 const MCExpr *Expr = MO.getExpr();
430 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_vfp_pcrel_12);
431 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
433 ++MCNumCPRelocations;
435 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
437 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
438 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
439 if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add)
441 Binary |= (Reg << 9);
445 unsigned ARMMCCodeEmitter::
446 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
447 SmallVectorImpl<MCFixup> &Fixups) const {
448 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
449 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
450 // case the imm contains the amount to shift by.
453 // {4} = 1 if reg shift, 0 if imm shift
461 const MCOperand &MO = MI.getOperand(OpIdx);
462 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
463 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
464 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
467 unsigned Binary = getARMRegisterNumbering(MO.getReg());
469 // Encode the shift opcode.
471 unsigned Rs = MO1.getReg();
473 // Set shift operand (bit[7:4]).
478 // RRX - 0110 and bit[11:8] clear.
480 default: llvm_unreachable("Unknown shift opc!");
481 case ARM_AM::lsl: SBits = 0x1; break;
482 case ARM_AM::lsr: SBits = 0x3; break;
483 case ARM_AM::asr: SBits = 0x5; break;
484 case ARM_AM::ror: SBits = 0x7; break;
485 case ARM_AM::rrx: SBits = 0x6; break;
488 // Set shift operand (bit[6:4]).
494 default: llvm_unreachable("Unknown shift opc!");
495 case ARM_AM::lsl: SBits = 0x0; break;
496 case ARM_AM::lsr: SBits = 0x2; break;
497 case ARM_AM::asr: SBits = 0x4; break;
498 case ARM_AM::ror: SBits = 0x6; break;
502 Binary |= SBits << 4;
503 if (SOpc == ARM_AM::rrx)
506 // Encode the shift operation Rs or shift_imm (except rrx).
508 // Encode Rs bit[11:8].
509 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
510 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
513 // Encode shift_imm bit[11:7].
514 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
517 unsigned ARMMCCodeEmitter::
518 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
519 SmallVectorImpl<MCFixup> &Fixups) const {
520 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
522 const MCOperand &MO = MI.getOperand(Op);
523 uint32_t v = ~MO.getImm();
524 uint32_t lsb = CountTrailingZeros_32(v);
525 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
526 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
527 return lsb | (msb << 5);
530 unsigned ARMMCCodeEmitter::
531 getRegisterListOpValue(const MCInst &MI, unsigned Op,
532 SmallVectorImpl<MCFixup> &Fixups) const {
533 // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
534 // register in the list, set the corresponding bit.
536 for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
537 unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
538 Binary |= 1 << regno;
543 unsigned ARMMCCodeEmitter::
544 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
545 SmallVectorImpl<MCFixup> &Fixups) const {
546 const MCOperand &Reg = MI.getOperand(Op);
547 const MCOperand &Imm = MI.getOperand(Op + 1);
549 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
552 switch (Imm.getImm()) {
556 case 8: Align = 0x01; break;
557 case 16: Align = 0x02; break;
558 case 32: Align = 0x03; break;
561 return RegNo | (Align << 4);
564 unsigned ARMMCCodeEmitter::
565 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
566 SmallVectorImpl<MCFixup> &Fixups) const {
567 const MCOperand &MO = MI.getOperand(Op);
568 if (MO.getReg() == 0) return 0x0D;
572 void ARMMCCodeEmitter::
573 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
574 SmallVectorImpl<MCFixup> &Fixups) const {
575 // Pseudo instructions don't get encoded.
576 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
577 if ((Desc.TSFlags & ARMII::FormMask) == ARMII::Pseudo)
580 EmitConstant(getBinaryCodeForInstr(MI, Fixups), 4, OS);
581 ++MCNumEmitted; // Keep track of the # of mi's emitted.
584 #include "ARMGenMCCodeEmitter.inc"