1 //===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ----*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that performs load / store related peephole
11 // optimizations. This pass should be run after register allocation.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-ldst-opt"
17 #include "ARMAddressingModes.h"
18 #include "ARMRegisterInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/RegisterScavenging.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
33 STATISTIC(NumLDMGened , "Number of ldm instructions generated");
34 STATISTIC(NumSTMGened , "Number of stm instructions generated");
35 STATISTIC(NumFLDMGened, "Number of fldm instructions generated");
36 STATISTIC(NumFSTMGened, "Number of fstm instructions generated");
39 struct VISIBILITY_HIDDEN ARMLoadStoreOpt : public MachineFunctionPass {
40 const TargetInstrInfo *TII;
41 const MRegisterInfo *MRI;
44 virtual bool runOnMachineFunction(MachineFunction &Fn);
46 virtual const char *getPassName() const {
47 return "ARM load / store optimization pass";
51 struct MemOpQueueEntry {
54 MachineBasicBlock::iterator MBBI;
56 MemOpQueueEntry(int o, int p, MachineBasicBlock::iterator i)
57 : Offset(o), Position(p), MBBI(i), Merged(false) {};
59 typedef SmallVector<MemOpQueueEntry,8> MemOpQueue;
60 typedef MemOpQueue::iterator MemOpQueueIter;
62 SmallVector<MachineBasicBlock::iterator, 4>
63 MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base,
64 int Opcode, unsigned Size, MemOpQueue &MemOps);
66 bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
67 bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
71 /// createARMLoadStoreOptimizationPass - returns an instance of the load / store
72 /// optimization pass.
73 FunctionPass *llvm::createARMLoadStoreOptimizationPass() {
74 return new ARMLoadStoreOpt();
77 static int getLoadStoreMultipleOpcode(int Opcode) {
102 /// mergeOps - Create and insert a LDM or STM with Base as base register and
103 /// registers in Regs as the register operands that would be loaded / stored.
104 /// It returns true if the transformation is done.
105 static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
106 int Offset, unsigned Base, int Opcode,
107 SmallVector<unsigned, 8> &Regs,
108 const TargetInstrInfo *TII) {
109 // Only a single register to load / store. Don't bother.
110 unsigned NumRegs = Regs.size();
114 ARM_AM::AMSubMode Mode = ARM_AM::ia;
115 bool isAM4 = Opcode == ARM::LDR || Opcode == ARM::STR;
116 if (isAM4 && Offset == 4)
118 else if (isAM4 && Offset == -4 * (int)NumRegs + 4)
120 else if (isAM4 && Offset == -4 * (int)NumRegs)
122 else if (Offset != 0) {
123 // If starting offset isn't zero, insert a MI to materialize a new base.
124 // But only do so if it is cost effective, i.e. merging more than two
130 if (Opcode == ARM::LDR)
131 // If it is a load, then just use one of the destination register to
132 // use as the new base.
133 NewBase = Regs[NumRegs-1];
135 // FIXME: Try scavenging a register to use as a new base.
138 int BaseOpc = ARM::ADDri;
140 BaseOpc = ARM::SUBri;
143 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
144 if (ImmedOffset == -1)
145 return false; // Probably not worth it then.
146 BuildMI(MBB, MBBI, TII->get(BaseOpc), NewBase).addReg(Base).addImm(ImmedOffset);
150 bool isDPR = Opcode == ARM::FLDD || Opcode == ARM::FSTD;
151 bool isDef = Opcode == ARM::LDR || Opcode == ARM::FLDS || Opcode == ARM::FLDD;
152 Opcode = getLoadStoreMultipleOpcode(Opcode);
153 MachineInstrBuilder MIB = (isAM4)
154 ? BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base)
155 .addImm(ARM_AM::getAM4ModeImm(Mode))
156 : BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base)
157 .addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs));
158 for (unsigned i = 0; i != NumRegs; ++i)
159 MIB = MIB.addReg(Regs[i], Opcode == isDef);
164 SmallVector<MachineBasicBlock::iterator, 4>
165 ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB,
166 unsigned SIndex, unsigned Base, int Opcode,
167 unsigned Size, MemOpQueue &MemOps) {
168 bool isAM4 = Opcode == ARM::LDR || Opcode == ARM::STR;
169 SmallVector<MachineBasicBlock::iterator, 4> Merges;
170 int Offset = MemOps[SIndex].Offset;
171 int SOffset = Offset;
172 unsigned Pos = MemOps[SIndex].Position;
173 MachineBasicBlock::iterator Loc = MemOps[SIndex].MBBI;
174 SmallVector<unsigned, 8> Regs;
175 unsigned PReg = MemOps[SIndex].MBBI->getOperand(0).getReg();
176 unsigned PRegNum = ARMRegisterInfo::getRegisterNumbering(PReg);
177 Regs.push_back(PReg);
178 for (unsigned i = SIndex+1, e = MemOps.size(); i != e; ++i) {
179 int NewOffset = MemOps[i].Offset;
180 unsigned Reg = MemOps[i].MBBI->getOperand(0).getReg();
181 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
182 // AM4 - register numbers in ascending order.
183 // AM5 - consecutive register numbers in ascending order.
184 if (NewOffset == Offset + (int)Size &&
185 ((isAM4 && RegNum > PRegNum) || RegNum == PRegNum+1)) {
190 // Can't merge this in. Try merge the earlier ones first.
191 if (mergeOps(MBB, ++Loc, SOffset, Base, Opcode, Regs, TII)) {
192 Merges.push_back(prior(Loc));
193 for (unsigned j = SIndex; j < i; ++j) {
194 MBB.erase(MemOps[j].MBBI);
195 MemOps[j].Merged = true;
198 SmallVector<MachineBasicBlock::iterator, 4> Merges2 =
199 MergeLDR_STR(MBB, i, Base, Opcode, Size, MemOps);
200 Merges.append(Merges2.begin(), Merges2.end());
204 if (MemOps[i].Position > Pos) {
205 Pos = MemOps[i].Position;
206 Loc = MemOps[i].MBBI;
210 if (mergeOps(MBB, ++Loc, SOffset, Base, Opcode, Regs, TII)) {
211 Merges.push_back(prior(Loc));
212 for (unsigned i = SIndex, e = MemOps.size(); i != e; ++i) {
213 MBB.erase(MemOps[i].MBBI);
214 MemOps[i].Merged = true;
221 static inline bool isMatchingDecrement(MachineInstr *MI, unsigned Base,
223 return (MI && MI->getOpcode() == ARM::SUBri &&
224 MI->getOperand(0).getReg() == Base &&
225 MI->getOperand(1).getReg() == Base &&
226 ARM_AM::getAM2Offset(MI->getOperand(2).getImm()) == Bytes);
229 static inline bool isMatchingIncrement(MachineInstr *MI, unsigned Base,
231 return (MI && MI->getOpcode() == ARM::ADDri &&
232 MI->getOperand(0).getReg() == Base &&
233 MI->getOperand(1).getReg() == Base &&
234 ARM_AM::getAM2Offset(MI->getOperand(2).getImm()) == Bytes);
237 static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
238 switch (MI->getOpcode()) {
250 return (MI->getNumOperands() - 2) * 4;
255 return ARM_AM::getAM5Offset(MI->getOperand(1).getImm()) * 4;
259 /// mergeBaseUpdateLSMultiple - Fold proceeding/trailing inc/dec of base
260 /// register into the LDM/STM/FLDM{D|S}/FSTM{D|S} op when possible:
262 /// stmia rn, <ra, rb, rc>
263 /// rn := rn + 4 * 3;
265 /// stmia rn!, <ra, rb, rc>
267 /// rn := rn - 4 * 3;
268 /// ldmia rn, <ra, rb, rc>
270 /// ldmdb rn!, <ra, rb, rc>
271 static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
272 MachineBasicBlock::iterator MBBI) {
273 MachineInstr *MI = MBBI;
274 unsigned Base = MI->getOperand(0).getReg();
275 unsigned Bytes = getLSMultipleTransferSize(MI);
276 int Opcode = MI->getOpcode();
277 bool isAM4 = Opcode == ARM::LDM || Opcode == ARM::STM;
280 if (ARM_AM::getAM4WBFlag(MI->getOperand(1).getImm()))
283 // Can't use the updating AM4 sub-mode if the base register is also a dest
284 // register. e.g. ldmdb r0!, {r0, r1, r2}. The behavior is undefined.
285 for (unsigned i = 2, e = MI->getNumOperands(); i != e; ++i) {
286 if (MI->getOperand(i).getReg() == Base)
290 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(1).getImm());
291 if (MBBI != MBB.begin()) {
292 MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
293 if (Mode == ARM_AM::ia &&
294 isMatchingDecrement(PrevMBBI, Base, Bytes)) {
295 MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::db, true));
298 } else if (Mode == ARM_AM::ib &&
299 isMatchingDecrement(PrevMBBI, Base, Bytes)) {
300 MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::da, true));
306 if (MBBI != MBB.end()) {
307 MachineBasicBlock::iterator NextMBBI = next(MBBI);
308 if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) &&
309 isMatchingIncrement(NextMBBI, Base, Bytes)) {
310 MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
313 } else if ((Mode == ARM_AM::da || Mode == ARM_AM::db) &&
314 isMatchingDecrement(NextMBBI, Base, Bytes)) {
315 MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
321 // FLDM{D|S}, FSTM{D|S} addressing mode 5 ops.
322 if (ARM_AM::getAM5WBFlag(MI->getOperand(1).getImm()))
325 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MI->getOperand(1).getImm());
326 unsigned Offset = ARM_AM::getAM5Offset(MI->getOperand(1).getImm());
327 if (MBBI != MBB.begin()) {
328 MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
329 if (Mode == ARM_AM::ia &&
330 isMatchingDecrement(PrevMBBI, Base, Bytes)) {
331 MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::db, true, Offset));
337 if (MBBI != MBB.end()) {
338 MachineBasicBlock::iterator NextMBBI = next(MBBI);
339 if (Mode == ARM_AM::ia &&
340 isMatchingIncrement(NextMBBI, Base, Bytes)) {
341 MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::ia, true, Offset));
351 static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc) {
353 case ARM::LDR: return ARM::LDR_PRE;
354 case ARM::STR: return ARM::STR_PRE;
355 case ARM::FLDS: return ARM::FLDMS;
356 case ARM::FLDD: return ARM::FLDMD;
357 case ARM::FSTS: return ARM::FSTMS;
358 case ARM::FSTD: return ARM::FSTMD;
364 static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) {
366 case ARM::LDR: return ARM::LDR_POST;
367 case ARM::STR: return ARM::STR_POST;
368 case ARM::FLDS: return ARM::FLDMS;
369 case ARM::FLDD: return ARM::FLDMD;
370 case ARM::FSTS: return ARM::FSTMS;
371 case ARM::FSTD: return ARM::FSTMD;
377 /// mergeBaseUpdateLoadStore - Fold proceeding/trailing inc/dec of base
378 /// register into the LDR/STR/FLD{D|S}/FST{D|S} op when possible:
379 static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
380 MachineBasicBlock::iterator MBBI,
381 const TargetInstrInfo *TII) {
382 MachineInstr *MI = MBBI;
383 unsigned Base = MI->getOperand(1).getReg();
384 unsigned Bytes = getLSMultipleTransferSize(MI);
385 int Opcode = MI->getOpcode();
386 bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR;
387 if ((isAM2 && ARM_AM::getAM2Offset(MI->getOperand(3).getImm()) != 0) ||
388 (!isAM2 && ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0))
391 bool isLd = Opcode == ARM::LDR || Opcode == ARM::FLDS || Opcode == ARM::FLDD;
392 // Can't do the merge if the destination register is the same as the would-be
393 // writeback register.
394 if (isLd && MI->getOperand(0).getReg() == Base)
397 bool DoMerge = false;
398 ARM_AM::AddrOpc AddSub = ARM_AM::add;
400 if (MBBI != MBB.begin()) {
401 MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
402 if (isMatchingDecrement(PrevMBBI, Base, Bytes)) {
404 AddSub = ARM_AM::sub;
405 NewOpc = getPreIndexedLoadStoreOpcode(Opcode);
406 } else if (isAM2 && isMatchingIncrement(PrevMBBI, Base, Bytes)) {
408 NewOpc = getPreIndexedLoadStoreOpcode(Opcode);
414 if (!DoMerge && MBBI != MBB.end()) {
415 MachineBasicBlock::iterator NextMBBI = next(MBBI);
416 if (isAM2 && isMatchingDecrement(NextMBBI, Base, Bytes)) {
418 AddSub = ARM_AM::sub;
419 NewOpc = getPostIndexedLoadStoreOpcode(Opcode);
420 } else if (isMatchingIncrement(NextMBBI, Base, Bytes)) {
422 NewOpc = getPostIndexedLoadStoreOpcode(Opcode);
431 bool isDPR = NewOpc == ARM::FLDMD || NewOpc == ARM::FSTMD;
432 unsigned Offset = isAM2 ? ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift)
433 : ARM_AM::getAM5Opc((AddSub == ARM_AM::sub) ? ARM_AM::db : ARM_AM::ia,
434 true, isDPR ? 2 : 1);
437 BuildMI(MBB, MBBI, TII->get(NewOpc), MI->getOperand(0).getReg())
438 .addReg(Base, true).addReg(Base).addReg(0).addImm(Offset);
440 BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base)
441 .addImm(Offset).addReg(MI->getOperand(0).getReg(), true);
444 BuildMI(MBB, MBBI, TII->get(NewOpc), Base).addReg(MI->getOperand(0).getReg())
445 .addReg(Base).addReg(0).addImm(Offset);
447 BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base)
448 .addImm(Offset).addReg(MI->getOperand(0).getReg(), false);
455 /// isMemoryOp - Returns true if instruction is a memory operations (that this
456 /// pass is capable of operating on).
457 static bool isMemoryOp(MachineInstr *MI) {
458 int Opcode = MI->getOpcode();
463 return MI->getOperand(1).isRegister() && MI->getOperand(2).getReg() == 0;
466 return MI->getOperand(1).isRegister();
469 return MI->getOperand(1).isRegister();
474 /// LoadStoreMultipleOpti - An optimization pass to turn multiple LDR / STR
475 /// ops of the same base and incrementing offset into LDM / STM ops.
476 bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
477 unsigned NumMerges = 0;
478 unsigned NumMemOps = 0;
480 unsigned CurrBase = 0;
482 unsigned CurrSize = 0;
483 unsigned Position = 0;
485 if (RS) RS->enterBasicBlock(&MBB);
486 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
488 bool Advance = false;
489 bool TryMerge = false;
490 bool Clobber = false;
492 bool isMemOp = isMemoryOp(MBBI);
494 int Opcode = MBBI->getOpcode();
495 bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR;
496 unsigned Size = getLSMultipleTransferSize(MBBI);
498 unsigned Base = MBBI->getOperand(1).getReg();
499 unsigned OffIdx = MBBI->getNumOperands()-1;
500 unsigned OffField = MBBI->getOperand(OffIdx).getImm();
502 ? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
504 if (ARM_AM::getAM2Op(OffField) == ARM_AM::sub)
507 if (ARM_AM::getAM5Op(OffField) == ARM_AM::sub)
512 // r5 := ldr [r5, #4]
513 // r6 := ldr [r5, #8]
515 // The second ldr has effectively broken the chain even though it
516 // looks like the later ldr(s) use the same base register. Try to
517 // merge the ldr's so far, including this one. But don't try to
518 // combine the following ldr(s).
519 Clobber = (Opcode == ARM::LDR && Base == MBBI->getOperand(0).getReg());
520 if (CurrBase == 0 && !Clobber) {
521 // Start of a new chain.
525 MemOps.push_back(MemOpQueueEntry(Offset, Position, MBBI));
534 if (CurrOpc == Opcode && CurrBase == Base) {
535 // Continue adding to the queue.
536 if (Offset > MemOps.back().Offset) {
537 MemOps.push_back(MemOpQueueEntry(Offset, Position, MBBI));
541 for (MemOpQueueIter I = MemOps.begin(), E = MemOps.end();
543 if (Offset < I->Offset) {
544 MemOps.insert(I, MemOpQueueEntry(Offset, Position, MBBI));
548 } else if (Offset == I->Offset) {
549 // Collision! This can't be merged!
566 SmallVector<MachineBasicBlock::iterator,4> MBBII =
567 MergeLDR_STR(MBB, 0, CurrBase, CurrOpc, CurrSize,MemOps);
568 // Try folding preceeding/trailing base inc/dec into the generated
570 for (unsigned i = 0, e = MBBII.size(); i < e; ++i)
571 if (mergeBaseUpdateLSMultiple(MBB, MBBII[i]))
573 NumMerges += MBBII.size();
576 // Try folding preceeding/trailing base inc/dec into those load/store
577 // that were not merged to form LDM/STM ops.
578 for (unsigned i = 0; i != NumMemOps; ++i)
579 if (!MemOps[i].Merged)
580 if (mergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII))
590 // If iterator hasn't been advanced and this is not a memory op, skip it.
591 // It can't start a new chain anyway.
592 if (!Advance && !isMemOp && MBBI != E) {
598 return NumMerges > 0;
601 /// MergeReturnIntoLDM - If this is a exit BB, try merging the return op
602 /// (bx lr) into the preceeding stack restore so it directly restore the value
604 /// ldmfd sp!, {r7, lr}
607 /// ldmfd sp!, {r7, pc}
608 bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
609 if (MBB.empty()) return false;
611 MachineBasicBlock::iterator MBBI = prior(MBB.end());
612 if (MBBI->getOpcode() == ARM::BX_RET && MBBI != MBB.begin()) {
613 MachineInstr *PrevMI = prior(MBBI);
614 if (PrevMI->getOpcode() == ARM::LDM) {
615 MachineOperand &MO = PrevMI->getOperand(PrevMI->getNumOperands()-1);
616 if (MO.getReg() == ARM::LR) {
617 PrevMI->setInstrDescriptor(TII->get(ARM::LDM_RET));
627 bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
628 const TargetMachine &TM = Fn.getTarget();
629 TII = TM.getInstrInfo();
630 MRI = TM.getRegisterInfo();
631 RS = MRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL;
633 bool Modified = false;
634 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
636 MachineBasicBlock &MBB = *MFI;
637 Modified |= LoadStoreMultipleOpti(MBB);
638 Modified |= MergeReturnIntoLDM(MBB);