1 //===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ----*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that performs load / store related peephole
11 // optimizations. This pass should be run after register allocation.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-ldst-opt"
17 #include "ARMAddressingModes.h"
18 #include "ARMRegisterInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/RegisterScavenging.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
33 STATISTIC(NumLDMGened , "Number of ldm instructions generated");
34 STATISTIC(NumSTMGened , "Number of stm instructions generated");
35 STATISTIC(NumFLDMGened, "Number of fldm instructions generated");
36 STATISTIC(NumFSTMGened, "Number of fstm instructions generated");
39 struct VISIBILITY_HIDDEN ARMLoadStoreOpt : public MachineFunctionPass {
40 const TargetInstrInfo *TII;
41 const MRegisterInfo *MRI;
43 MachineBasicBlock::iterator RSI;
45 virtual bool runOnMachineFunction(MachineFunction &Fn);
47 virtual const char *getPassName() const {
48 return "ARM load / store optimization pass";
52 struct MemOpQueueEntry {
55 MachineBasicBlock::iterator MBBI;
57 MemOpQueueEntry(int o, int p, MachineBasicBlock::iterator i)
58 : Offset(o), Position(p), MBBI(i), Merged(false) {};
60 typedef SmallVector<MemOpQueueEntry,8> MemOpQueue;
61 typedef MemOpQueue::iterator MemOpQueueIter;
63 SmallVector<MachineBasicBlock::iterator, 4>
64 MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base,
65 int Opcode, unsigned Size, unsigned Scratch,
68 bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
69 bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
73 /// createARMLoadStoreOptimizationPass - returns an instance of the load / store
74 /// optimization pass.
75 FunctionPass *llvm::createARMLoadStoreOptimizationPass() {
76 return new ARMLoadStoreOpt();
79 static int getLoadStoreMultipleOpcode(int Opcode) {
104 /// mergeOps - Create and insert a LDM or STM with Base as base register and
105 /// registers in Regs as the register operands that would be loaded / stored.
106 /// It returns true if the transformation is done.
107 static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
108 int Offset, unsigned Base, bool BaseKill, int Opcode,
110 SmallVector<std::pair<unsigned, bool>, 8> &Regs,
111 const TargetInstrInfo *TII) {
112 // Only a single register to load / store. Don't bother.
113 unsigned NumRegs = Regs.size();
117 ARM_AM::AMSubMode Mode = ARM_AM::ia;
118 bool isAM4 = Opcode == ARM::LDR || Opcode == ARM::STR;
119 if (isAM4 && Offset == 4)
121 else if (isAM4 && Offset == -4 * (int)NumRegs + 4)
123 else if (isAM4 && Offset == -4 * (int)NumRegs)
125 else if (Offset != 0) {
126 // If starting offset isn't zero, insert a MI to materialize a new base.
127 // But only do so if it is cost effective, i.e. merging more than two
133 if (Opcode == ARM::LDR)
134 // If it is a load, then just use one of the destination register to
135 // use as the new base.
136 NewBase = Regs[NumRegs-1].first;
138 // Use the scratch register to use as a new base.
143 int BaseOpc = ARM::ADDri;
145 BaseOpc = ARM::SUBri;
148 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
149 if (ImmedOffset == -1)
150 return false; // Probably not worth it then.
152 BuildMI(MBB, MBBI, TII->get(BaseOpc), NewBase)
153 .addReg(Base, false, false, BaseKill).addImm(ImmedOffset);
155 BaseKill = true; // New base is always killed right its use.
158 bool isDPR = Opcode == ARM::FLDD || Opcode == ARM::FSTD;
159 bool isDef = Opcode == ARM::LDR || Opcode == ARM::FLDS || Opcode == ARM::FLDD;
160 Opcode = getLoadStoreMultipleOpcode(Opcode);
161 MachineInstrBuilder MIB = (isAM4)
162 ? BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill)
163 .addImm(ARM_AM::getAM4ModeImm(Mode))
164 : BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill)
165 .addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs));
166 for (unsigned i = 0; i != NumRegs; ++i)
167 MIB = MIB.addReg(Regs[i].first, isDef, false, Regs[i].second);
172 /// MergeLDR_STR - Merge a number of load / store instructions into one or more
173 /// load / store multiple instructions.
174 SmallVector<MachineBasicBlock::iterator, 4>
175 ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
176 unsigned Base, int Opcode, unsigned Size,
177 unsigned Scratch, MemOpQueue &MemOps) {
178 SmallVector<MachineBasicBlock::iterator, 4> Merges;
179 SmallVector<std::pair<unsigned,bool>, 8> Regs;
180 bool isAM4 = Opcode == ARM::LDR || Opcode == ARM::STR;
181 int Offset = MemOps[SIndex].Offset;
182 int SOffset = Offset;
183 unsigned Pos = MemOps[SIndex].Position;
184 MachineBasicBlock::iterator Loc = MemOps[SIndex].MBBI;
185 unsigned PReg = MemOps[SIndex].MBBI->getOperand(0).getReg();
186 unsigned PRegNum = ARMRegisterInfo::getRegisterNumbering(PReg);
187 bool isKill = MemOps[SIndex].MBBI->getOperand(0).isKill();
188 Regs.push_back(std::make_pair(PReg, isKill));
189 for (unsigned i = SIndex+1, e = MemOps.size(); i != e; ++i) {
190 int NewOffset = MemOps[i].Offset;
191 unsigned Reg = MemOps[i].MBBI->getOperand(0).getReg();
192 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
193 isKill = MemOps[i].MBBI->getOperand(0).isKill();
194 // AM4 - register numbers in ascending order.
195 // AM5 - consecutive register numbers in ascending order.
196 if (NewOffset == Offset + (int)Size &&
197 ((isAM4 && RegNum > PRegNum) || RegNum == PRegNum+1)) {
199 Regs.push_back(std::make_pair(Reg, isKill));
202 // Can't merge this in. Try merge the earlier ones first.
203 if (mergeOps(MBB, ++Loc, SOffset, Base, false, Opcode,Scratch,Regs,TII)) {
204 Merges.push_back(prior(Loc));
205 for (unsigned j = SIndex; j < i; ++j) {
206 MBB.erase(MemOps[j].MBBI);
207 MemOps[j].Merged = true;
210 SmallVector<MachineBasicBlock::iterator, 4> Merges2 =
211 MergeLDR_STR(MBB, i, Base, Opcode, Size, Scratch, MemOps);
212 Merges.append(Merges2.begin(), Merges2.end());
216 if (MemOps[i].Position > Pos) {
217 Pos = MemOps[i].Position;
218 Loc = MemOps[i].MBBI;
222 bool BaseKill = Loc->findRegisterUseOperand(Base, true) != NULL;
223 if (mergeOps(MBB, ++Loc, SOffset, Base, BaseKill, Opcode,Scratch,Regs, TII)) {
224 Merges.push_back(prior(Loc));
225 for (unsigned i = SIndex, e = MemOps.size(); i != e; ++i) {
226 MBB.erase(MemOps[i].MBBI);
227 MemOps[i].Merged = true;
234 static inline bool isMatchingDecrement(MachineInstr *MI, unsigned Base,
236 return (MI && MI->getOpcode() == ARM::SUBri &&
237 MI->getOperand(0).getReg() == Base &&
238 MI->getOperand(1).getReg() == Base &&
239 ARM_AM::getAM2Offset(MI->getOperand(2).getImm()) == Bytes);
242 static inline bool isMatchingIncrement(MachineInstr *MI, unsigned Base,
244 return (MI && MI->getOpcode() == ARM::ADDri &&
245 MI->getOperand(0).getReg() == Base &&
246 MI->getOperand(1).getReg() == Base &&
247 ARM_AM::getAM2Offset(MI->getOperand(2).getImm()) == Bytes);
250 static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
251 switch (MI->getOpcode()) {
263 return (MI->getNumOperands() - 2) * 4;
268 return ARM_AM::getAM5Offset(MI->getOperand(1).getImm()) * 4;
272 /// mergeBaseUpdateLSMultiple - Fold proceeding/trailing inc/dec of base
273 /// register into the LDM/STM/FLDM{D|S}/FSTM{D|S} op when possible:
275 /// stmia rn, <ra, rb, rc>
276 /// rn := rn + 4 * 3;
278 /// stmia rn!, <ra, rb, rc>
280 /// rn := rn - 4 * 3;
281 /// ldmia rn, <ra, rb, rc>
283 /// ldmdb rn!, <ra, rb, rc>
284 static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
285 MachineBasicBlock::iterator MBBI) {
286 MachineInstr *MI = MBBI;
287 unsigned Base = MI->getOperand(0).getReg();
288 unsigned Bytes = getLSMultipleTransferSize(MI);
289 int Opcode = MI->getOpcode();
290 bool isAM4 = Opcode == ARM::LDM || Opcode == ARM::STM;
293 if (ARM_AM::getAM4WBFlag(MI->getOperand(1).getImm()))
296 // Can't use the updating AM4 sub-mode if the base register is also a dest
297 // register. e.g. ldmdb r0!, {r0, r1, r2}. The behavior is undefined.
298 for (unsigned i = 2, e = MI->getNumOperands(); i != e; ++i) {
299 if (MI->getOperand(i).getReg() == Base)
303 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(1).getImm());
304 if (MBBI != MBB.begin()) {
305 MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
306 if (Mode == ARM_AM::ia &&
307 isMatchingDecrement(PrevMBBI, Base, Bytes)) {
308 MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::db, true));
311 } else if (Mode == ARM_AM::ib &&
312 isMatchingDecrement(PrevMBBI, Base, Bytes)) {
313 MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::da, true));
319 if (MBBI != MBB.end()) {
320 MachineBasicBlock::iterator NextMBBI = next(MBBI);
321 if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) &&
322 isMatchingIncrement(NextMBBI, Base, Bytes)) {
323 MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
326 } else if ((Mode == ARM_AM::da || Mode == ARM_AM::db) &&
327 isMatchingDecrement(NextMBBI, Base, Bytes)) {
328 MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
334 // FLDM{D|S}, FSTM{D|S} addressing mode 5 ops.
335 if (ARM_AM::getAM5WBFlag(MI->getOperand(1).getImm()))
338 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MI->getOperand(1).getImm());
339 unsigned Offset = ARM_AM::getAM5Offset(MI->getOperand(1).getImm());
340 if (MBBI != MBB.begin()) {
341 MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
342 if (Mode == ARM_AM::ia &&
343 isMatchingDecrement(PrevMBBI, Base, Bytes)) {
344 MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::db, true, Offset));
350 if (MBBI != MBB.end()) {
351 MachineBasicBlock::iterator NextMBBI = next(MBBI);
352 if (Mode == ARM_AM::ia &&
353 isMatchingIncrement(NextMBBI, Base, Bytes)) {
354 MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::ia, true, Offset));
364 static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc) {
366 case ARM::LDR: return ARM::LDR_PRE;
367 case ARM::STR: return ARM::STR_PRE;
368 case ARM::FLDS: return ARM::FLDMS;
369 case ARM::FLDD: return ARM::FLDMD;
370 case ARM::FSTS: return ARM::FSTMS;
371 case ARM::FSTD: return ARM::FSTMD;
377 static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) {
379 case ARM::LDR: return ARM::LDR_POST;
380 case ARM::STR: return ARM::STR_POST;
381 case ARM::FLDS: return ARM::FLDMS;
382 case ARM::FLDD: return ARM::FLDMD;
383 case ARM::FSTS: return ARM::FSTMS;
384 case ARM::FSTD: return ARM::FSTMD;
390 /// mergeBaseUpdateLoadStore - Fold proceeding/trailing inc/dec of base
391 /// register into the LDR/STR/FLD{D|S}/FST{D|S} op when possible:
392 static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
393 MachineBasicBlock::iterator MBBI,
394 const TargetInstrInfo *TII) {
395 MachineInstr *MI = MBBI;
396 unsigned Base = MI->getOperand(1).getReg();
397 bool BaseKill = MI->getOperand(1).isKill();
398 unsigned Bytes = getLSMultipleTransferSize(MI);
399 int Opcode = MI->getOpcode();
400 bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR;
401 if ((isAM2 && ARM_AM::getAM2Offset(MI->getOperand(3).getImm()) != 0) ||
402 (!isAM2 && ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0))
405 bool isLd = Opcode == ARM::LDR || Opcode == ARM::FLDS || Opcode == ARM::FLDD;
406 // Can't do the merge if the destination register is the same as the would-be
407 // writeback register.
408 if (isLd && MI->getOperand(0).getReg() == Base)
411 bool DoMerge = false;
412 ARM_AM::AddrOpc AddSub = ARM_AM::add;
414 if (MBBI != MBB.begin()) {
415 MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
416 if (isMatchingDecrement(PrevMBBI, Base, Bytes)) {
418 AddSub = ARM_AM::sub;
419 NewOpc = getPreIndexedLoadStoreOpcode(Opcode);
420 } else if (isAM2 && isMatchingIncrement(PrevMBBI, Base, Bytes)) {
422 NewOpc = getPreIndexedLoadStoreOpcode(Opcode);
428 if (!DoMerge && MBBI != MBB.end()) {
429 MachineBasicBlock::iterator NextMBBI = next(MBBI);
430 if (isAM2 && isMatchingDecrement(NextMBBI, Base, Bytes)) {
432 AddSub = ARM_AM::sub;
433 NewOpc = getPostIndexedLoadStoreOpcode(Opcode);
434 } else if (isMatchingIncrement(NextMBBI, Base, Bytes)) {
436 NewOpc = getPostIndexedLoadStoreOpcode(Opcode);
445 bool isDPR = NewOpc == ARM::FLDMD || NewOpc == ARM::FSTMD;
446 unsigned Offset = isAM2 ? ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift)
447 : ARM_AM::getAM5Opc((AddSub == ARM_AM::sub) ? ARM_AM::db : ARM_AM::ia,
448 true, isDPR ? 2 : 1);
451 // LDR_PRE, LDR_POST;
452 BuildMI(MBB, MBBI, TII->get(NewOpc), MI->getOperand(0).getReg())
454 .addReg(Base).addReg(0).addImm(Offset);
456 BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base, false, false, BaseKill)
457 .addImm(Offset).addReg(MI->getOperand(0).getReg(), true);
459 MachineOperand &MO = MI->getOperand(0);
461 // STR_PRE, STR_POST;
462 BuildMI(MBB, MBBI, TII->get(NewOpc), Base)
463 .addReg(MO.getReg(), false, false, MO.isKill())
464 .addReg(Base).addReg(0).addImm(Offset);
466 BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base)
467 .addImm(Offset).addReg(MO.getReg(), false, false, MO.isKill());
474 /// isMemoryOp - Returns true if instruction is a memory operations (that this
475 /// pass is capable of operating on).
476 static bool isMemoryOp(MachineInstr *MI) {
477 int Opcode = MI->getOpcode();
482 return MI->getOperand(1).isRegister() && MI->getOperand(2).getReg() == 0;
485 return MI->getOperand(1).isRegister();
488 return MI->getOperand(1).isRegister();
493 /// LoadStoreMultipleOpti - An optimization pass to turn multiple LDR / STR
494 /// ops of the same base and incrementing offset into LDM / STM ops.
495 bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
496 unsigned NumMerges = 0;
497 unsigned NumMemOps = 0;
499 unsigned CurrBase = 0;
501 unsigned CurrSize = 0;
502 unsigned Position = 0;
504 RS->enterBasicBlock(&MBB);
506 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
508 bool Advance = false;
509 bool TryMerge = false;
510 bool Clobber = false;
512 bool isMemOp = isMemoryOp(MBBI);
514 int Opcode = MBBI->getOpcode();
515 bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR;
516 unsigned Size = getLSMultipleTransferSize(MBBI);
517 unsigned Base = MBBI->getOperand(1).getReg();
518 unsigned OffIdx = MBBI->getNumOperands()-1;
519 unsigned OffField = MBBI->getOperand(OffIdx).getImm();
521 ? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
523 if (ARM_AM::getAM2Op(OffField) == ARM_AM::sub)
526 if (ARM_AM::getAM5Op(OffField) == ARM_AM::sub)
531 // r5 := ldr [r5, #4]
532 // r6 := ldr [r5, #8]
534 // The second ldr has effectively broken the chain even though it
535 // looks like the later ldr(s) use the same base register. Try to
536 // merge the ldr's so far, including this one. But don't try to
537 // combine the following ldr(s).
538 Clobber = (Opcode == ARM::LDR && Base == MBBI->getOperand(0).getReg());
539 if (CurrBase == 0 && !Clobber) {
540 // Start of a new chain.
544 MemOps.push_back(MemOpQueueEntry(Offset, Position, MBBI));
553 if (CurrOpc == Opcode && CurrBase == Base) {
554 // Continue adding to the queue.
555 if (Offset > MemOps.back().Offset) {
556 MemOps.push_back(MemOpQueueEntry(Offset, Position, MBBI));
560 for (MemOpQueueIter I = MemOps.begin(), E = MemOps.end();
562 if (Offset < I->Offset) {
563 MemOps.insert(I, MemOpQueueEntry(Offset, Position, MBBI));
567 } else if (Offset == I->Offset) {
568 // Collision! This can't be merged!
585 // Try to find a free register to use as a new base in case it's needed.
586 unsigned Scratch = ARM::R12;
587 // First advance to the instruction just before the start of the chain.
588 if (RSI != MBB.begin())
589 RS->forward(prior(RSI));
590 // Find a scratch register.
591 Scratch = RS->FindUnusedReg(&ARM::GPRRegClass);
592 // Process the load / store instructions.
593 RS->forward(prior(MBBI));
596 SmallVector<MachineBasicBlock::iterator,4> MBBII =
597 MergeLDR_STR(MBB, 0, CurrBase, CurrOpc, CurrSize, Scratch, MemOps);
599 // Try folding preceeding/trailing base inc/dec into the generated
601 for (unsigned i = 0, e = MBBII.size(); i < e; ++i)
602 if (mergeBaseUpdateLSMultiple(MBB, MBBII[i]))
604 NumMerges += MBBII.size();
606 // Try folding preceeding/trailing base inc/dec into those load/store
607 // that were not merged to form LDM/STM ops.
608 for (unsigned i = 0; i != NumMemOps; ++i)
609 if (!MemOps[i].Merged)
610 if (mergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII))
613 // RS may be pointing to an instruction that's deleted.
614 RS->skipTo(prior(MBBI));
625 // If iterator hasn't been advanced and this is not a memory op, skip it.
626 // It can't start a new chain anyway.
627 if (!Advance && !isMemOp && MBBI != E) {
633 return NumMerges > 0;
636 /// MergeReturnIntoLDM - If this is a exit BB, try merging the return op
637 /// (bx lr) into the preceeding stack restore so it directly restore the value
639 /// ldmfd sp!, {r7, lr}
642 /// ldmfd sp!, {r7, pc}
643 bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
644 if (MBB.empty()) return false;
646 MachineBasicBlock::iterator MBBI = prior(MBB.end());
647 if (MBBI->getOpcode() == ARM::BX_RET && MBBI != MBB.begin()) {
648 MachineInstr *PrevMI = prior(MBBI);
649 if (PrevMI->getOpcode() == ARM::LDM) {
650 MachineOperand &MO = PrevMI->getOperand(PrevMI->getNumOperands()-1);
651 if (MO.getReg() == ARM::LR) {
652 PrevMI->setInstrDescriptor(TII->get(ARM::LDM_RET));
662 bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
663 const TargetMachine &TM = Fn.getTarget();
664 TII = TM.getInstrInfo();
665 MRI = TM.getRegisterInfo();
666 RS = new RegScavenger();
668 bool Modified = false;
669 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
671 MachineBasicBlock &MBB = *MFI;
672 Modified |= LoadStoreMultipleOpti(MBB);
673 Modified |= MergeReturnIntoLDM(MBB);