1 //===- ARMInstrVFP.td - VFP support for ARM ----------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag, SDNPOutFlag]>;
25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutFlag]>;
27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
30 //===----------------------------------------------------------------------===//
31 // Operand Definitions.
34 def vfp_f32imm : Operand<f32>,
35 PatLeaf<(f32 fpimm), [{
36 return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
38 let PrintMethod = "printVFPf32ImmOperand";
41 def vfp_f64imm : Operand<f64>,
42 PatLeaf<(f64 fpimm), [{
43 return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
45 let PrintMethod = "printVFPf64ImmOperand";
49 //===----------------------------------------------------------------------===//
50 // Load / store Instructions.
53 let canFoldAsLoad = 1, isReMaterializable = 1 in {
54 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
55 IIC_fpLoad64, "vldr", ".64\t$Dd, $addr",
56 [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>;
58 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
59 IIC_fpLoad32, "vldr", ".32\t$dst, $addr",
60 [(set SPR:$dst, (load addrmode5:$addr))]>;
63 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
64 IIC_fpStore64, "vstr", ".64\t$src, $addr",
65 [(store (f64 DPR:$src), addrmode5:$addr)]>;
67 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
68 IIC_fpStore32, "vstr", ".32\t$src, $addr",
69 [(store SPR:$src, addrmode5:$addr)]>;
71 //===----------------------------------------------------------------------===//
72 // Load / store multiple Instructions.
75 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
76 def VLDMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
77 variable_ops), IndexModeNone, IIC_fpLoad_m,
78 "vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
82 def VLDMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
83 variable_ops), IndexModeNone, IIC_fpLoad_m,
84 "vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
88 def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
89 reglist:$dsts, variable_ops),
90 IndexModeUpd, IIC_fpLoad_mu,
91 "vldm${addr:submode}${p}\t$addr!, $dsts",
92 "$addr.addr = $wb", []> {
96 def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
97 reglist:$dsts, variable_ops),
98 IndexModeUpd, IIC_fpLoad_mu,
99 "vldm${addr:submode}${p}\t$addr!, $dsts",
100 "$addr.addr = $wb", []> {
103 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
105 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
106 def VSTMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
107 variable_ops), IndexModeNone, IIC_fpStore_m,
108 "vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
112 def VSTMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
113 variable_ops), IndexModeNone, IIC_fpStore_m,
114 "vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
118 def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
119 reglist:$srcs, variable_ops),
120 IndexModeUpd, IIC_fpStore_mu,
121 "vstm${addr:submode}${p}\t$addr!, $srcs",
122 "$addr.addr = $wb", []> {
126 def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
127 reglist:$srcs, variable_ops),
128 IndexModeUpd, IIC_fpStore_mu,
129 "vstm${addr:submode}${p}\t$addr!, $srcs",
130 "$addr.addr = $wb", []> {
133 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
135 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
138 // FIXME: Can these be placed into the base class?
139 class ADbI_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
140 dag iops, InstrItinClass itin, string opc, string asm,
142 : ADbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
143 // Instruction operands.
148 // Encode instruction operands.
149 let Inst{3-0} = Dm{3-0};
151 let Inst{19-16} = Dn{3-0};
153 let Inst{15-12} = Dd{3-0};
154 let Inst{22} = Dd{4};
157 class ADuI_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
158 bits<2> opcod4, bit opcod5, dag oops, dag iops,
159 InstrItinClass itin, string opc, string asm,
161 : ADuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc,
163 // Instruction operands.
167 // Encode instruction operands.
168 let Inst{3-0} = Dm{3-0};
170 let Inst{15-12} = Dd{3-0};
171 let Inst{22} = Dd{4};
174 class ASbI_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
175 dag iops, InstrItinClass itin, string opc, string asm,
177 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
178 // Instruction operands.
183 // Encode instruction operands.
184 let Inst{3-0} = Sm{4-1};
186 let Inst{19-16} = Sn{4-1};
188 let Inst{15-12} = Sd{4-1};
189 let Inst{22} = Sd{0};
192 class ASbIn_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
193 dag iops, InstrItinClass itin, string opc, string asm,
195 : ASbIn<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
196 // Instruction operands.
201 // Encode instruction operands.
202 let Inst{3-0} = Sm{4-1};
204 let Inst{19-16} = Sn{4-1};
206 let Inst{15-12} = Sd{4-1};
207 let Inst{22} = Sd{0};
210 class ASuI_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
211 bits<2> opcod4, bit opcod5, dag oops, dag iops,
212 InstrItinClass itin, string opc, string asm,
214 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc,
216 // Instruction operands.
220 // Encode instruction operands.
221 let Inst{3-0} = Sm{4-1};
223 let Inst{15-12} = Sd{4-1};
224 let Inst{22} = Sd{0};
227 class ASuIn_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
228 bits<2> opcod4, bit opcod5, dag oops, dag iops,
229 InstrItinClass itin, string opc, string asm,
231 : ASuIn<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc,
233 // Instruction operands.
237 // Encode instruction operands.
238 let Inst{3-0} = Sm{4-1};
240 let Inst{15-12} = Sd{4-1};
241 let Inst{22} = Sd{0};
244 //===----------------------------------------------------------------------===//
245 // FP Binary Operations.
248 def VADDD : ADbI_Encode<0b11100, 0b11, 0, 0,
249 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
250 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
251 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
253 def VADDS : ASbIn_Encode<0b11100, 0b11, 0, 0,
254 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
255 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
256 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>;
258 def VSUBD : ADbI_Encode<0b11100, 0b11, 1, 0,
259 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
260 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
261 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
263 def VSUBS : ASbIn_Encode<0b11100, 0b11, 1, 0,
264 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
265 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
266 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>;
268 def VDIVD : ADbI_Encode<0b11101, 0b00, 0, 0,
269 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
270 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
271 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
273 def VDIVS : ASbI_Encode<0b11101, 0b00, 0, 0,
274 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
275 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
276 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
278 def VMULD : ADbI_Encode<0b11100, 0b10, 0, 0,
279 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
280 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
281 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
283 def VMULS : ASbIn_Encode<0b11100, 0b10, 0, 0,
284 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
285 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
286 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>;
288 def VNMULD : ADbI_Encode<0b11100, 0b10, 1, 0,
289 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
290 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
291 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
293 def VNMULS : ASbI_Encode<0b11100, 0b10, 1, 0,
294 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
295 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
296 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>;
298 // Match reassociated forms only if not sign dependent rounding.
299 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
300 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
301 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
302 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
304 // These are encoded as unary instructions.
305 let Defs = [FPSCR] in {
306 def VCMPED : ADuI_Encode<0b11101, 0b11, 0b0100, 0b11, 0,
307 (outs), (ins DPR:$Dd, DPR:$Dm),
308 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
309 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
311 def VCMPES : ASuI_Encode<0b11101, 0b11, 0b0100, 0b11, 0,
312 (outs), (ins SPR:$Sd, SPR:$Sm),
313 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
314 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]>;
316 // FIXME: Verify encoding after integrated assembler is working.
317 def VCMPD : ADuI_Encode<0b11101, 0b11, 0b0100, 0b01, 0,
318 (outs), (ins DPR:$Dd, DPR:$Dm),
319 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
320 [/* For disassembly only; pattern left blank */]>;
322 def VCMPS : ASuI_Encode<0b11101, 0b11, 0b0100, 0b01, 0,
323 (outs), (ins SPR:$Sd, SPR:$Sm),
324 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
325 [/* For disassembly only; pattern left blank */]>;
328 //===----------------------------------------------------------------------===//
329 // FP Unary Operations.
332 def VABSD : ADuI_Encode<0b11101, 0b11, 0b0000, 0b11, 0,
333 (outs DPR:$Dd), (ins DPR:$Dm),
334 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
335 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
337 def VABSS : ASuIn_Encode<0b11101, 0b11, 0b0000, 0b11, 0,
338 (outs SPR:$Sd), (ins SPR:$Sm),
339 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
340 [(set SPR:$Sd, (fabs SPR:$Sm))]>;
342 let Defs = [FPSCR] in {
343 def VCMPEZD : ADuI_Encode<0b11101, 0b11, 0b0101, 0b11, 0,
344 (outs), (ins DPR:$Dd),
345 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
346 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
347 let Inst{3-0} = 0b0000;
351 def VCMPEZS : ASuI_Encode<0b11101, 0b11, 0b0101, 0b11, 0,
352 (outs), (ins SPR:$Sd),
353 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
354 [(arm_cmpfp0 SPR:$Sd)]> {
355 let Inst{3-0} = 0b0000;
359 // FIXME: Verify encoding after integrated assembler is working.
360 def VCMPZD : ADuI_Encode<0b11101, 0b11, 0b0101, 0b01, 0,
361 (outs), (ins DPR:$Dd),
362 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
363 [/* For disassembly only; pattern left blank */]> {
364 let Inst{3-0} = 0b0000;
368 def VCMPZS : ASuI_Encode<0b11101, 0b11, 0b0101, 0b01, 0,
369 (outs), (ins SPR:$Sd),
370 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
371 [/* For disassembly only; pattern left blank */]> {
372 let Inst{3-0} = 0b0000;
377 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
378 (outs DPR:$Dd), (ins SPR:$Sm),
379 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
380 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
381 // Instruction operands.
385 // Encode instruction operands.
386 let Inst{3-0} = Sm{4-1};
388 let Inst{15-12} = Dd{3-0};
389 let Inst{22} = Dd{4};
392 // Special case encoding: bits 11-8 is 0b1011.
393 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
394 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
395 [(set SPR:$Sd, (fround DPR:$Dm))]> {
396 // Instruction operands.
400 // Encode instruction operands.
401 let Inst{3-0} = Dm{3-0};
403 let Inst{15-12} = Sd{4-1};
404 let Inst{22} = Sd{0};
406 let Inst{27-23} = 0b11101;
407 let Inst{21-16} = 0b110111;
408 let Inst{11-8} = 0b1011;
409 let Inst{7-6} = 0b11;
413 // Between half-precision and single-precision. For disassembly only.
415 // FIXME: Verify encoding after integrated assembler is working.
416 def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
417 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$dst, $a",
418 [/* For disassembly only; pattern left blank */]>;
420 def : ARMPat<(f32_to_f16 SPR:$a),
421 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
423 def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
424 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$dst, $a",
425 [/* For disassembly only; pattern left blank */]>;
427 def : ARMPat<(f16_to_f32 GPR:$a),
428 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
430 def VCVTTSH: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
431 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$dst, $a",
432 [/* For disassembly only; pattern left blank */]>;
434 def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
435 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$dst, $a",
436 [/* For disassembly only; pattern left blank */]>;
438 def VNEGD : ADuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0,
439 (outs DPR:$Dd), (ins DPR:$Dm),
440 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
441 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
443 def VNEGS : ASuIn_Encode<0b11101, 0b11, 0b0001, 0b01, 0,
444 (outs SPR:$Sd), (ins SPR:$Sm),
445 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
446 [(set SPR:$Sd, (fneg SPR:$Sm))]>;
448 def VSQRTD : ADuI_Encode<0b11101, 0b11, 0b0001, 0b11, 0,
449 (outs DPR:$Dd), (ins DPR:$Dm),
450 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
451 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
453 def VSQRTS : ASuI_Encode<0b11101, 0b11, 0b0001, 0b11, 0,
454 (outs SPR:$Sd), (ins SPR:$Sm),
455 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
456 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
458 let neverHasSideEffects = 1 in {
459 def VMOVD : ADuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
460 (outs DPR:$Dd), (ins DPR:$Dm),
461 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
463 def VMOVS : ASuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
464 (outs SPR:$Sd), (ins SPR:$Sm),
465 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
466 } // neverHasSideEffects
468 //===----------------------------------------------------------------------===//
469 // FP <-> GPR Copies. Int <-> FP Conversions.
472 def VMOVRS : AVConv2I<0b11100001, 0b1010,
473 (outs GPR:$Rt), (ins SPR:$Sn),
474 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
475 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
476 // Instruction operands.
480 // Encode instruction operands.
481 let Inst{19-16} = Sn{4-1};
483 let Inst{15-12} = Rt;
485 let Inst{6-5} = 0b00;
486 let Inst{3-0} = 0b0000;
489 def VMOVSR : AVConv4I<0b11100000, 0b1010,
490 (outs SPR:$Sn), (ins GPR:$Rt),
491 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
492 [(set SPR:$Sn, (bitconvert GPR:$Rt))]> {
493 // Instruction operands.
497 // Encode instruction operands.
498 let Inst{19-16} = Sn{4-1};
500 let Inst{15-12} = Rt;
502 let Inst{6-5} = 0b00;
503 let Inst{3-0} = 0b0000;
506 let neverHasSideEffects = 1 in {
507 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
508 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
509 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
510 [/* FIXME: Can't write pattern for multiple result instr*/]> {
511 // Instruction operands.
516 // Encode instruction operands.
517 let Inst{3-0} = Dm{3-0};
519 let Inst{15-12} = Rt;
520 let Inst{19-16} = Rt2;
522 let Inst{7-6} = 0b00;
525 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
526 (outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2),
527 IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
528 [/* For disassembly only; pattern left blank */]> {
529 let Inst{7-6} = 0b00;
531 } // neverHasSideEffects
536 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
537 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
538 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
539 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
540 // Instruction operands.
545 // Encode instruction operands.
546 let Inst{3-0} = Dm{3-0};
548 let Inst{15-12} = Rt;
549 let Inst{19-16} = Rt2;
551 let Inst{7-6} = 0b00;
554 let neverHasSideEffects = 1 in
555 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
556 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
557 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
558 [/* For disassembly only; pattern left blank */]> {
559 let Inst{7-6} = 0b00;
565 // FMRX: SPR system reg -> GPR
567 // FMXR: GPR -> VFP system reg
572 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
573 bits<4> opcod4, dag oops, dag iops,
574 InstrItinClass itin, string opc, string asm,
576 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
578 // Instruction operands.
582 // Encode instruction operands.
583 let Inst{3-0} = Sm{4-1};
585 let Inst{15-12} = Dd{3-0};
586 let Inst{22} = Dd{4};
589 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
590 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
591 string opc, string asm, list<dag> pattern>
592 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
594 // Instruction operands.
598 // Encode instruction operands.
599 let Inst{3-0} = Sm{4-1};
601 let Inst{15-12} = Sd{4-1};
602 let Inst{22} = Sd{0};
605 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
606 (outs DPR:$Dd), (ins SPR:$Sm),
607 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
608 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
609 let Inst{7} = 1; // s32
612 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
613 (outs SPR:$Sd),(ins SPR:$Sm),
614 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
615 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
616 let Inst{7} = 1; // s32
619 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
620 (outs DPR:$Dd), (ins SPR:$Sm),
621 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
622 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
623 let Inst{7} = 0; // u32
626 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
627 (outs SPR:$Sd), (ins SPR:$Sm),
628 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
629 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
630 let Inst{7} = 0; // u32
635 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
636 bits<4> opcod4, dag oops, dag iops,
637 InstrItinClass itin, string opc, string asm,
639 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
641 // Instruction operands.
645 // Encode instruction operands.
646 let Inst{3-0} = Dm{3-0};
648 let Inst{15-12} = Sd{4-1};
649 let Inst{22} = Sd{0};
652 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
653 bits<4> opcod4, dag oops, dag iops,
654 InstrItinClass itin, string opc, string asm,
656 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
658 // Instruction operands.
662 // Encode instruction operands.
663 let Inst{3-0} = Sm{4-1};
665 let Inst{15-12} = Sd{4-1};
666 let Inst{22} = Sd{0};
669 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
670 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
671 (outs SPR:$Sd), (ins DPR:$Dm),
672 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
673 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
674 let Inst{7} = 1; // Z bit
677 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
678 (outs SPR:$Sd), (ins SPR:$Sm),
679 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
680 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
681 let Inst{7} = 1; // Z bit
684 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
685 (outs SPR:$Sd), (ins DPR:$Dm),
686 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
687 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
688 let Inst{7} = 1; // Z bit
691 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
692 (outs SPR:$Sd), (ins SPR:$Sm),
693 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
694 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
695 let Inst{7} = 1; // Z bit
698 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
699 // For disassembly only.
700 let Uses = [FPSCR] in {
701 // FIXME: Verify encoding after integrated assembler is working.
702 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
703 (outs SPR:$Sd), (ins DPR:$Dm),
704 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
705 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
706 let Inst{7} = 0; // Z bit
709 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
710 (outs SPR:$Sd), (ins SPR:$Sm),
711 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
712 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
713 let Inst{7} = 0; // Z bit
716 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
717 (outs SPR:$Sd), (ins DPR:$Dm),
718 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
719 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
720 let Inst{7} = 0; // Z bit
723 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
724 (outs SPR:$Sd), (ins SPR:$Sm),
725 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
726 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
727 let Inst{7} = 0; // Z bit
731 // Convert between floating-point and fixed-point
732 // Data type for fixed-point naming convention:
733 // S16 (U=0, sx=0) -> SH
734 // U16 (U=1, sx=0) -> UH
735 // S32 (U=0, sx=1) -> SL
736 // U32 (U=1, sx=1) -> UL
738 let Constraints = "$a = $dst" in {
740 // FP to Fixed-Point:
742 // FIXME: Marking these as codegen only seems wrong. They are real
744 let isCodeGenOnly = 1 in {
745 def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0,
746 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
747 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits",
748 [/* For disassembly only; pattern left blank */]>;
750 def VTOUHS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 0,
751 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
752 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits",
753 [/* For disassembly only; pattern left blank */]>;
755 def VTOSLS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 1,
756 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
757 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits",
758 [/* For disassembly only; pattern left blank */]>;
760 def VTOULS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 1,
761 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
762 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits",
763 [/* For disassembly only; pattern left blank */]>;
765 def VTOSHD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 0,
766 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
767 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits",
768 [/* For disassembly only; pattern left blank */]>;
770 def VTOUHD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 0,
771 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
772 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits",
773 [/* For disassembly only; pattern left blank */]>;
775 def VTOSLD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 1,
776 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
777 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits",
778 [/* For disassembly only; pattern left blank */]>;
780 def VTOULD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 1,
781 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
782 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits",
783 [/* For disassembly only; pattern left blank */]>;
784 } // End of 'let isCodeGenOnly = 1 in'
786 // Fixed-Point to FP:
788 let isCodeGenOnly = 1 in {
789 def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0,
790 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
791 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits",
792 [/* For disassembly only; pattern left blank */]>;
794 def VUHTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 0,
795 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
796 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits",
797 [/* For disassembly only; pattern left blank */]>;
799 def VSLTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 1,
800 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
801 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits",
802 [/* For disassembly only; pattern left blank */]>;
804 def VULTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 1,
805 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
806 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits",
807 [/* For disassembly only; pattern left blank */]>;
809 def VSHTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 0,
810 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
811 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits",
812 [/* For disassembly only; pattern left blank */]>;
814 def VUHTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 0,
815 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
816 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits",
817 [/* For disassembly only; pattern left blank */]>;
819 def VSLTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 1,
820 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
821 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits",
822 [/* For disassembly only; pattern left blank */]>;
824 def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
825 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
826 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits",
827 [/* For disassembly only; pattern left blank */]>;
828 } // End of 'let isCodeGenOnly = 1 in'
830 } // End of 'let Constraints = "$src = $dst" in'
832 //===----------------------------------------------------------------------===//
833 // FP FMA Operations.
836 class ADbI_vmlX_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4,
837 dag oops, dag iops, InstrItinClass itin, string opc,
838 string asm, list<dag> pattern>
839 : ADbI_vmlX<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
840 // Instruction operands.
845 // Encode instruction operands.
846 let Inst{19-16} = Dn{3-0};
848 let Inst{15-12} = Dd{3-0};
849 let Inst{22} = Dd{4};
850 let Inst{3-0} = Dm{3-0};
854 def VMLAD : ADbI_vmlX_Encode<0b11100, 0b00, 0, 0,
855 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
856 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
857 [(set DPR:$Dd, (fadd (fmul DPR:$Dn, DPR:$Dm),
859 RegConstraint<"$Ddin = $Dd">;
861 def VMLAS : ASbIn_Encode<0b11100, 0b00, 0, 0,
862 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
863 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
864 [(set SPR:$Sd, (fadd (fmul SPR:$Sn, SPR:$Sm),
866 RegConstraint<"$Sdin = $Sd">;
868 def : Pat<(fadd DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
869 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
870 def : Pat<(fadd SPR:$dstin, (fmul SPR:$a, SPR:$b)),
871 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
873 def VMLSD : ADbI_vmlX_Encode<0b11100, 0b00, 1, 0,
874 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
875 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
876 [(set DPR:$Dd, (fadd (fneg (fmul DPR:$Dn,DPR:$Dm)),
878 RegConstraint<"$Ddin = $Dd">;
880 def VMLSS : ASbIn_Encode<0b11100, 0b00, 1, 0,
881 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
882 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
883 [(set SPR:$Sd, (fadd (fneg (fmul SPR:$Sn, SPR:$Sm)),
885 RegConstraint<"$Sdin = $Sd">;
887 def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
888 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
889 def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
890 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
892 def VNMLAD : ADbI_vmlX_Encode<0b11100, 0b01, 1, 0,
893 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
894 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
895 [(set DPR:$Dd,(fsub (fneg (fmul DPR:$Dn,DPR:$Dm)),
897 RegConstraint<"$Ddin = $Dd">;
899 def VNMLAS : ASbI_Encode<0b11100, 0b01, 1, 0,
900 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
901 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
902 [(set SPR:$Sd, (fsub (fneg (fmul SPR:$Sn, SPR:$Sm)),
904 RegConstraint<"$Sdin = $Sd">;
906 def : Pat<(fsub (fneg (fmul DPR:$a, (f64 DPR:$b))), DPR:$dstin),
907 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
908 def : Pat<(fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin),
909 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
911 def VNMLSD : ADbI_vmlX_Encode<0b11100, 0b01, 0, 0,
912 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
913 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
914 [(set DPR:$Dd, (fsub (fmul DPR:$Dn, DPR:$Dm),
916 RegConstraint<"$Ddin = $Dd">;
918 def VNMLSS : ASbI_Encode<0b11100, 0b01, 0, 0,
919 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
920 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
921 [(set SPR:$Sd, (fsub (fmul SPR:$Sn, SPR:$Sm),
923 RegConstraint<"$Sdin = $Sd">;
925 def : Pat<(fsub (fmul DPR:$a, (f64 DPR:$b)), DPR:$dstin),
926 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
927 def : Pat<(fsub (fmul SPR:$a, SPR:$b), SPR:$dstin),
928 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
931 //===----------------------------------------------------------------------===//
932 // FP Conditional moves.
935 let neverHasSideEffects = 1 in {
936 def VMOVDcc : ADuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
937 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
938 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm",
939 [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
940 RegConstraint<"$Dn = $Dd">;
942 def VMOVScc : ASuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
943 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
944 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm",
945 [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
946 RegConstraint<"$Sn = $Sd">;
948 def VNEGDcc : ADuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0,
949 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
950 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
951 [/*(set DPR:$Dd, (ARMcneg DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
952 RegConstraint<"$Dn = $Dd">;
954 def VNEGScc : ASuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0,
955 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
956 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
957 [/*(set SPR:$Sd, (ARMcneg SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
958 RegConstraint<"$Sn = $Sd">;
959 } // neverHasSideEffects
961 //===----------------------------------------------------------------------===//
965 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
967 let Defs = [CPSR], Uses = [FPSCR] in
968 def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT, "vmrs",
969 "\tapsr_nzcv, fpscr",
971 let Inst{27-20} = 0b11101111;
972 let Inst{19-16} = 0b0001;
973 let Inst{15-12} = 0b1111;
974 let Inst{11-8} = 0b1010;
976 let Inst{6-5} = 0b00;
978 let Inst{3-0} = 0b0000;
982 let hasSideEffects = 1, Uses = [FPSCR] in
983 def VMRS : VFPAI<(outs GPR:$Rt), (ins), VFPMiscFrm, IIC_fpSTAT,
984 "vmrs", "\t$Rt, fpscr",
985 [(set GPR:$Rt, (int_arm_get_fpscr))]> {
986 // Instruction operand.
989 // Encode instruction operand.
990 let Inst{15-12} = Rt;
992 let Inst{27-20} = 0b11101111;
993 let Inst{19-16} = 0b0001;
994 let Inst{11-8} = 0b1010;
996 let Inst{6-5} = 0b00;
998 let Inst{3-0} = 0b0000;
1001 let Defs = [FPSCR] in
1002 def VMSR : VFPAI<(outs), (ins GPR:$src), VFPMiscFrm, IIC_fpSTAT,
1003 "vmsr", "\tfpscr, $src",
1004 [(int_arm_set_fpscr GPR:$src)]> {
1005 // Instruction operand.
1008 // Encode instruction operand.
1009 let Inst{15-12} = src;
1011 let Inst{27-20} = 0b11101110;
1012 let Inst{19-16} = 0b0001;
1013 let Inst{11-8} = 0b1010;
1018 // Materialize FP immediates. VFP3 only.
1019 let isReMaterializable = 1 in {
1020 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1021 VFPMiscFrm, IIC_fpUNA64,
1022 "vmov", ".f64\t$Dd, $imm",
1023 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
1024 // Instruction operands.
1028 // Encode instruction operands.
1029 let Inst{15-12} = Dd{3-0};
1030 let Inst{22} = Dd{4};
1031 let Inst{19} = imm{31};
1032 let Inst{18-16} = imm{22-20};
1033 let Inst{3-0} = imm{19-16};
1035 // Encode remaining instruction bits.
1036 let Inst{27-23} = 0b11101;
1037 let Inst{21-20} = 0b11;
1038 let Inst{11-9} = 0b101;
1039 let Inst{8} = 1; // Double precision.
1040 let Inst{7-4} = 0b0000;
1043 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1044 VFPMiscFrm, IIC_fpUNA32,
1045 "vmov", ".f32\t$Sd, $imm",
1046 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1047 // Instruction operands.
1051 // Encode instruction operands.
1052 let Inst{15-12} = Sd{4-1};
1053 let Inst{22} = Sd{0};
1054 let Inst{19} = imm{31}; // The immediate is handled as a double.
1055 let Inst{18-16} = imm{22-20};
1056 let Inst{3-0} = imm{19-16};
1058 // Encode remaining instruction bits.
1059 let Inst{27-23} = 0b11101;
1060 let Inst{21-20} = 0b11;
1061 let Inst{11-9} = 0b101;
1062 let Inst{8} = 0; // Single precision.
1063 let Inst{7-4} = 0b0000;