1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
30 //===----------------------------------------------------------------------===//
31 // Operand Definitions.
34 // 8-bit floating-point immediate encodings.
35 def FPImmOperand : AsmOperandClass {
37 let ParserMethod = "parseFPImm";
40 def vfp_f32imm : Operand<f32>,
41 PatLeaf<(f32 fpimm), [{
42 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
43 }], SDNodeXForm<fpimm, [{
44 APFloat InVal = N->getValueAPF();
45 uint32_t enc = ARM_AM::getFP32Imm(InVal);
46 return CurDAG->getTargetConstant(enc, MVT::i32);
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
52 def vfp_f64imm : Operand<f64>,
53 PatLeaf<(f64 fpimm), [{
54 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;
55 }], SDNodeXForm<fpimm, [{
56 APFloat InVal = N->getValueAPF();
57 uint32_t enc = ARM_AM::getFP64Imm(InVal);
58 return CurDAG->getTargetConstant(enc, MVT::i32);
60 let PrintMethod = "printFPImmOperand";
61 let ParserMatchClass = FPImmOperand;
64 def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
65 return cast<LoadSDNode>(N)->getAlignment() >= 4;
68 def alignedstore32 : PatFrag<(ops node:$val, node:$ptr),
69 (store node:$val, node:$ptr), [{
70 return cast<StoreSDNode>(N)->getAlignment() >= 4;
73 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
74 // (the number of fixed bits) differently than it appears in the assembly
75 // source. It's encoded as "Size - fbits" where Size is the size of the
76 // fixed-point representation (32 or 16) and fbits is the value appearing
77 // in the assembly source, an integer in [0,16] or (0,32], depending on size.
78 def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; }
79 def fbits32 : Operand<i32> {
80 let PrintMethod = "printFBits32";
81 let ParserMatchClass = fbits32_asm_operand;
84 def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; }
85 def fbits16 : Operand<i32> {
86 let PrintMethod = "printFBits16";
87 let ParserMatchClass = fbits16_asm_operand;
90 //===----------------------------------------------------------------------===//
91 // Load / store Instructions.
94 let canFoldAsLoad = 1, isReMaterializable = 1 in {
96 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
97 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
98 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>;
100 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
101 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
102 [(set SPR:$Sd, (load addrmode5:$addr))]> {
103 // Some single precision VFP instructions may be executed on both NEON and VFP
105 let D = VFPNeonDomain;
108 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
110 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
111 IIC_fpStore64, "vstr", "\t$Dd, $addr",
112 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>;
114 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
115 IIC_fpStore32, "vstr", "\t$Sd, $addr",
116 [(store SPR:$Sd, addrmode5:$addr)]> {
117 // Some single precision VFP instructions may be executed on both NEON and VFP
119 let D = VFPNeonDomain;
122 //===----------------------------------------------------------------------===//
123 // Load / store multiple Instructions.
126 multiclass vfp_ldst_mult<string asm, bit L_bit,
127 InstrItinClass itin, InstrItinClass itin_upd> {
130 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
132 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
133 let Inst{24-23} = 0b01; // Increment After
134 let Inst{21} = 0; // No writeback
135 let Inst{20} = L_bit;
138 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
140 IndexModeUpd, itin_upd,
141 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
142 let Inst{24-23} = 0b01; // Increment After
143 let Inst{21} = 1; // Writeback
144 let Inst{20} = L_bit;
147 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
149 IndexModeUpd, itin_upd,
150 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
151 let Inst{24-23} = 0b10; // Decrement Before
152 let Inst{21} = 1; // Writeback
153 let Inst{20} = L_bit;
158 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
160 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
161 let Inst{24-23} = 0b01; // Increment After
162 let Inst{21} = 0; // No writeback
163 let Inst{20} = L_bit;
165 // Some single precision VFP instructions may be executed on both NEON and
167 let D = VFPNeonDomain;
170 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
172 IndexModeUpd, itin_upd,
173 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
174 let Inst{24-23} = 0b01; // Increment After
175 let Inst{21} = 1; // Writeback
176 let Inst{20} = L_bit;
178 // Some single precision VFP instructions may be executed on both NEON and
180 let D = VFPNeonDomain;
183 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
185 IndexModeUpd, itin_upd,
186 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
187 let Inst{24-23} = 0b10; // Decrement Before
188 let Inst{21} = 1; // Writeback
189 let Inst{20} = L_bit;
191 // Some single precision VFP instructions may be executed on both NEON and
193 let D = VFPNeonDomain;
197 let neverHasSideEffects = 1 in {
199 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
200 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
202 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
203 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpLoad_m, IIC_fpLoad_mu>;
205 } // neverHasSideEffects
207 def : MnemonicAlias<"vldm", "vldmia">;
208 def : MnemonicAlias<"vstm", "vstmia">;
210 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
212 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
214 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
216 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
218 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
219 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
220 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
221 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>;
222 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
223 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>;
224 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
225 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;
227 // FLDMX, FSTMX - Load and store multiple unknown precision registers for
229 // These instruction are deprecated so we don't want them to get selected.
230 multiclass vfp_ldstx_mult<string asm, bit L_bit> {
233 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
234 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> {
235 let Inst{24-23} = 0b01; // Increment After
236 let Inst{21} = 0; // No writeback
237 let Inst{20} = L_bit;
240 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
241 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
242 let Inst{24-23} = 0b01; // Increment After
243 let Inst{21} = 1; // Writeback
244 let Inst{20} = L_bit;
247 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
248 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
249 let Inst{24-23} = 0b10; // Decrement Before
251 let Inst{20} = L_bit;
255 defm FLDM : vfp_ldstx_mult<"fldm", 1>;
256 defm FSTM : vfp_ldstx_mult<"fstm", 0>;
258 //===----------------------------------------------------------------------===//
259 // FP Binary Operations.
262 let TwoOperandAliasConstraint = "$Dn = $Dd" in
263 def VADDD : ADbI<0b11100, 0b11, 0, 0,
264 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
265 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
266 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
268 let TwoOperandAliasConstraint = "$Sn = $Sd" in
269 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
270 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
271 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
272 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
273 // Some single precision VFP instructions may be executed on both NEON and
274 // VFP pipelines on A8.
275 let D = VFPNeonA8Domain;
278 let TwoOperandAliasConstraint = "$Dn = $Dd" in
279 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
280 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
281 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
282 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
284 let TwoOperandAliasConstraint = "$Sn = $Sd" in
285 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
286 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
287 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
288 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
289 // Some single precision VFP instructions may be executed on both NEON and
290 // VFP pipelines on A8.
291 let D = VFPNeonA8Domain;
294 let TwoOperandAliasConstraint = "$Dn = $Dd" in
295 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
296 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
297 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
298 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
300 let TwoOperandAliasConstraint = "$Sn = $Sd" in
301 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
302 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
303 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
304 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
306 let TwoOperandAliasConstraint = "$Dn = $Dd" in
307 def VMULD : ADbI<0b11100, 0b10, 0, 0,
308 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
309 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
310 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
312 let TwoOperandAliasConstraint = "$Sn = $Sd" in
313 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
314 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
315 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
316 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
317 // Some single precision VFP instructions may be executed on both NEON and
318 // VFP pipelines on A8.
319 let D = VFPNeonA8Domain;
322 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
323 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
324 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
325 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
327 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
328 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
329 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
330 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
331 // Some single precision VFP instructions may be executed on both NEON and
332 // VFP pipelines on A8.
333 let D = VFPNeonA8Domain;
336 // Match reassociated forms only if not sign dependent rounding.
337 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
338 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
339 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
340 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
342 // These are encoded as unary instructions.
343 let Defs = [FPSCR_NZCV] in {
344 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
345 (outs), (ins DPR:$Dd, DPR:$Dm),
346 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
347 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
349 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
350 (outs), (ins SPR:$Sd, SPR:$Sm),
351 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
352 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
353 // Some single precision VFP instructions may be executed on both NEON and
354 // VFP pipelines on A8.
355 let D = VFPNeonA8Domain;
358 // FIXME: Verify encoding after integrated assembler is working.
359 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
360 (outs), (ins DPR:$Dd, DPR:$Dm),
361 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
362 [/* For disassembly only; pattern left blank */]>;
364 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
365 (outs), (ins SPR:$Sd, SPR:$Sm),
366 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
367 [/* For disassembly only; pattern left blank */]> {
368 // Some single precision VFP instructions may be executed on both NEON and
369 // VFP pipelines on A8.
370 let D = VFPNeonA8Domain;
372 } // Defs = [FPSCR_NZCV]
374 //===----------------------------------------------------------------------===//
375 // FP Unary Operations.
378 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
379 (outs DPR:$Dd), (ins DPR:$Dm),
380 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
381 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
383 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
384 (outs SPR:$Sd), (ins SPR:$Sm),
385 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
386 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
387 // Some single precision VFP instructions may be executed on both NEON and
388 // VFP pipelines on A8.
389 let D = VFPNeonA8Domain;
392 let Defs = [FPSCR_NZCV] in {
393 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
394 (outs), (ins DPR:$Dd),
395 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
396 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
397 let Inst{3-0} = 0b0000;
401 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
402 (outs), (ins SPR:$Sd),
403 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
404 [(arm_cmpfp0 SPR:$Sd)]> {
405 let Inst{3-0} = 0b0000;
408 // Some single precision VFP instructions may be executed on both NEON and
409 // VFP pipelines on A8.
410 let D = VFPNeonA8Domain;
413 // FIXME: Verify encoding after integrated assembler is working.
414 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
415 (outs), (ins DPR:$Dd),
416 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
417 [/* For disassembly only; pattern left blank */]> {
418 let Inst{3-0} = 0b0000;
422 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
423 (outs), (ins SPR:$Sd),
424 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
425 [/* For disassembly only; pattern left blank */]> {
426 let Inst{3-0} = 0b0000;
429 // Some single precision VFP instructions may be executed on both NEON and
430 // VFP pipelines on A8.
431 let D = VFPNeonA8Domain;
433 } // Defs = [FPSCR_NZCV]
435 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
436 (outs DPR:$Dd), (ins SPR:$Sm),
437 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
438 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
439 // Instruction operands.
443 // Encode instruction operands.
444 let Inst{3-0} = Sm{4-1};
446 let Inst{15-12} = Dd{3-0};
447 let Inst{22} = Dd{4};
450 // Special case encoding: bits 11-8 is 0b1011.
451 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
452 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
453 [(set SPR:$Sd, (fround DPR:$Dm))]> {
454 // Instruction operands.
458 // Encode instruction operands.
459 let Inst{3-0} = Dm{3-0};
461 let Inst{15-12} = Sd{4-1};
462 let Inst{22} = Sd{0};
464 let Inst{27-23} = 0b11101;
465 let Inst{21-16} = 0b110111;
466 let Inst{11-8} = 0b1011;
467 let Inst{7-6} = 0b11;
471 // Between half, single and double-precision. For disassembly only.
473 // FIXME: Verify encoding after integrated assembler is working.
474 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
475 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
476 [/* For disassembly only; pattern left blank */]>;
478 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
479 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
480 [/* For disassembly only; pattern left blank */]>;
482 def : Pat<(f32_to_f16 SPR:$a),
483 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
485 def : Pat<(f16_to_f32 GPR:$a),
486 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
488 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
489 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
490 [/* For disassembly only; pattern left blank */]>;
492 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
493 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
494 [/* For disassembly only; pattern left blank */]>;
496 def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
497 (outs DPR:$Dd), (ins SPR:$Sm),
498 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
499 []>, Requires<[HasV8FP]> {
500 // Instruction operands.
503 // Encode instruction operands.
504 let Inst{3-0} = Sm{4-1};
508 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
509 (outs SPR:$Sd), (ins DPR:$Dm),
510 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
511 []>, Requires<[HasV8FP]> {
512 // Instruction operands.
516 // Encode instruction operands.
517 let Inst{3-0} = Dm{3-0};
519 let Inst{15-12} = Sd{4-1};
520 let Inst{22} = Sd{0};
523 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
524 (outs DPR:$Dd), (ins SPR:$Sm),
525 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
526 []>, Requires<[HasV8FP]> {
527 // Instruction operands.
530 // Encode instruction operands.
531 let Inst{3-0} = Sm{4-1};
535 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
536 (outs SPR:$Sd), (ins DPR:$Dm),
537 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
538 []>, Requires<[HasV8FP]> {
539 // Instruction operands.
543 // Encode instruction operands.
544 let Inst{15-12} = Sd{4-1};
545 let Inst{22} = Sd{0};
546 let Inst{3-0} = Dm{3-0};
550 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
551 (outs DPR:$Dd), (ins DPR:$Dm),
552 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
553 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
555 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
556 (outs SPR:$Sd), (ins SPR:$Sm),
557 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
558 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
559 // Some single precision VFP instructions may be executed on both NEON and
560 // VFP pipelines on A8.
561 let D = VFPNeonA8Domain;
564 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
565 (outs DPR:$Dd), (ins DPR:$Dm),
566 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
567 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
569 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
570 (outs SPR:$Sd), (ins SPR:$Sm),
571 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
572 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
574 let neverHasSideEffects = 1 in {
575 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
576 (outs DPR:$Dd), (ins DPR:$Dm),
577 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
579 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
580 (outs SPR:$Sd), (ins SPR:$Sm),
581 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
582 } // neverHasSideEffects
584 //===----------------------------------------------------------------------===//
585 // FP <-> GPR Copies. Int <-> FP Conversions.
588 def VMOVRS : AVConv2I<0b11100001, 0b1010,
589 (outs GPR:$Rt), (ins SPR:$Sn),
590 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
591 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
592 // Instruction operands.
596 // Encode instruction operands.
597 let Inst{19-16} = Sn{4-1};
599 let Inst{15-12} = Rt;
601 let Inst{6-5} = 0b00;
602 let Inst{3-0} = 0b0000;
604 // Some single precision VFP instructions may be executed on both NEON and VFP
606 let D = VFPNeonDomain;
609 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
610 def VMOVSR : AVConv4I<0b11100000, 0b1010,
611 (outs SPR:$Sn), (ins GPR:$Rt),
612 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
613 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
614 Requires<[HasVFP2, UseVMOVSR]> {
615 // Instruction operands.
619 // Encode instruction operands.
620 let Inst{19-16} = Sn{4-1};
622 let Inst{15-12} = Rt;
624 let Inst{6-5} = 0b00;
625 let Inst{3-0} = 0b0000;
627 // Some single precision VFP instructions may be executed on both NEON and VFP
629 let D = VFPNeonDomain;
632 let neverHasSideEffects = 1 in {
633 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
634 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
635 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
636 [/* FIXME: Can't write pattern for multiple result instr*/]> {
637 // Instruction operands.
642 // Encode instruction operands.
643 let Inst{3-0} = Dm{3-0};
645 let Inst{15-12} = Rt;
646 let Inst{19-16} = Rt2;
648 let Inst{7-6} = 0b00;
650 // Some single precision VFP instructions may be executed on both NEON and VFP
652 let D = VFPNeonDomain;
655 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
656 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
657 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
658 [/* For disassembly only; pattern left blank */]> {
663 // Encode instruction operands.
664 let Inst{3-0} = src1{4-1};
665 let Inst{5} = src1{0};
666 let Inst{15-12} = Rt;
667 let Inst{19-16} = Rt2;
669 let Inst{7-6} = 0b00;
671 // Some single precision VFP instructions may be executed on both NEON and VFP
673 let D = VFPNeonDomain;
674 let DecoderMethod = "DecodeVMOVRRS";
676 } // neverHasSideEffects
681 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
682 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
683 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
684 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
685 // Instruction operands.
690 // Encode instruction operands.
691 let Inst{3-0} = Dm{3-0};
693 let Inst{15-12} = Rt;
694 let Inst{19-16} = Rt2;
696 let Inst{7-6} = 0b00;
698 // Some single precision VFP instructions may be executed on both NEON and VFP
700 let D = VFPNeonDomain;
703 let neverHasSideEffects = 1 in
704 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
705 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
706 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
707 [/* For disassembly only; pattern left blank */]> {
708 // Instruction operands.
713 // Encode instruction operands.
714 let Inst{3-0} = dst1{4-1};
715 let Inst{5} = dst1{0};
716 let Inst{15-12} = src1;
717 let Inst{19-16} = src2;
719 let Inst{7-6} = 0b00;
721 // Some single precision VFP instructions may be executed on both NEON and VFP
723 let D = VFPNeonDomain;
725 let DecoderMethod = "DecodeVMOVSRR";
731 // FMRX: SPR system reg -> GPR
733 // FMXR: GPR -> VFP system reg
738 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
739 bits<4> opcod4, dag oops, dag iops,
740 InstrItinClass itin, string opc, string asm,
742 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
744 // Instruction operands.
748 // Encode instruction operands.
749 let Inst{3-0} = Sm{4-1};
751 let Inst{15-12} = Dd{3-0};
752 let Inst{22} = Dd{4};
755 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
756 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
757 string opc, string asm, list<dag> pattern>
758 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
760 // Instruction operands.
764 // Encode instruction operands.
765 let Inst{3-0} = Sm{4-1};
767 let Inst{15-12} = Sd{4-1};
768 let Inst{22} = Sd{0};
771 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
772 (outs DPR:$Dd), (ins SPR:$Sm),
773 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
774 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
775 let Inst{7} = 1; // s32
778 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
779 (outs SPR:$Sd),(ins SPR:$Sm),
780 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
781 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
782 let Inst{7} = 1; // s32
784 // Some single precision VFP instructions may be executed on both NEON and
785 // VFP pipelines on A8.
786 let D = VFPNeonA8Domain;
789 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
790 (outs DPR:$Dd), (ins SPR:$Sm),
791 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
792 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
793 let Inst{7} = 0; // u32
796 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
797 (outs SPR:$Sd), (ins SPR:$Sm),
798 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
799 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
800 let Inst{7} = 0; // u32
802 // Some single precision VFP instructions may be executed on both NEON and
803 // VFP pipelines on A8.
804 let D = VFPNeonA8Domain;
809 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
810 bits<4> opcod4, dag oops, dag iops,
811 InstrItinClass itin, string opc, string asm,
813 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
815 // Instruction operands.
819 // Encode instruction operands.
820 let Inst{3-0} = Dm{3-0};
822 let Inst{15-12} = Sd{4-1};
823 let Inst{22} = Sd{0};
826 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
827 bits<4> opcod4, dag oops, dag iops,
828 InstrItinClass itin, string opc, string asm,
830 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
832 // Instruction operands.
836 // Encode instruction operands.
837 let Inst{3-0} = Sm{4-1};
839 let Inst{15-12} = Sd{4-1};
840 let Inst{22} = Sd{0};
843 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
844 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
845 (outs SPR:$Sd), (ins DPR:$Dm),
846 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
847 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
848 let Inst{7} = 1; // Z bit
851 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
852 (outs SPR:$Sd), (ins SPR:$Sm),
853 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
854 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
855 let Inst{7} = 1; // Z bit
857 // Some single precision VFP instructions may be executed on both NEON and
858 // VFP pipelines on A8.
859 let D = VFPNeonA8Domain;
862 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
863 (outs SPR:$Sd), (ins DPR:$Dm),
864 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
865 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
866 let Inst{7} = 1; // Z bit
869 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
870 (outs SPR:$Sd), (ins SPR:$Sm),
871 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
872 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
873 let Inst{7} = 1; // Z bit
875 // Some single precision VFP instructions may be executed on both NEON and
876 // VFP pipelines on A8.
877 let D = VFPNeonA8Domain;
880 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
881 let Uses = [FPSCR] in {
882 // FIXME: Verify encoding after integrated assembler is working.
883 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
884 (outs SPR:$Sd), (ins DPR:$Dm),
885 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
886 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
887 let Inst{7} = 0; // Z bit
890 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
891 (outs SPR:$Sd), (ins SPR:$Sm),
892 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
893 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
894 let Inst{7} = 0; // Z bit
897 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
898 (outs SPR:$Sd), (ins DPR:$Dm),
899 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
900 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
901 let Inst{7} = 0; // Z bit
904 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
905 (outs SPR:$Sd), (ins SPR:$Sm),
906 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
907 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
908 let Inst{7} = 0; // Z bit
912 // Convert between floating-point and fixed-point
913 // Data type for fixed-point naming convention:
914 // S16 (U=0, sx=0) -> SH
915 // U16 (U=1, sx=0) -> UH
916 // S32 (U=0, sx=1) -> SL
917 // U32 (U=1, sx=1) -> UL
919 let Constraints = "$a = $dst" in {
921 // FP to Fixed-Point:
923 // Single Precision register
924 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
925 bit op5, dag oops, dag iops, InstrItinClass itin,
926 string opc, string asm, list<dag> pattern>
927 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
928 Sched<[WriteCvtFP]> {
930 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
931 let Inst{22} = dst{0};
932 let Inst{15-12} = dst{4-1};
935 // Double Precision register
936 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
937 bit op5, dag oops, dag iops, InstrItinClass itin,
938 string opc, string asm, list<dag> pattern>
939 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
940 Sched<[WriteCvtFP]> {
942 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
943 let Inst{22} = dst{4};
944 let Inst{15-12} = dst{3-0};
947 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,
948 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
949 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> {
950 // Some single precision VFP instructions may be executed on both NEON and
951 // VFP pipelines on A8.
952 let D = VFPNeonA8Domain;
955 def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0,
956 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
957 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> {
958 // Some single precision VFP instructions may be executed on both NEON and
959 // VFP pipelines on A8.
960 let D = VFPNeonA8Domain;
963 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1,
964 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
965 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> {
966 // Some single precision VFP instructions may be executed on both NEON and
967 // VFP pipelines on A8.
968 let D = VFPNeonA8Domain;
971 def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1,
972 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
973 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> {
974 // Some single precision VFP instructions may be executed on both NEON and
975 // VFP pipelines on A8.
976 let D = VFPNeonA8Domain;
979 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0,
980 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
981 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>;
983 def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0,
984 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
985 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>;
987 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1,
988 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
989 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>;
991 def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1,
992 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
993 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>;
995 // Fixed-Point to FP:
997 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,
998 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
999 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> {
1000 // Some single precision VFP instructions may be executed on both NEON and
1001 // VFP pipelines on A8.
1002 let D = VFPNeonA8Domain;
1005 def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0,
1006 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1007 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> {
1008 // Some single precision VFP instructions may be executed on both NEON and
1009 // VFP pipelines on A8.
1010 let D = VFPNeonA8Domain;
1013 def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1,
1014 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1015 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> {
1016 // Some single precision VFP instructions may be executed on both NEON and
1017 // VFP pipelines on A8.
1018 let D = VFPNeonA8Domain;
1021 def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1,
1022 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1023 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> {
1024 // Some single precision VFP instructions may be executed on both NEON and
1025 // VFP pipelines on A8.
1026 let D = VFPNeonA8Domain;
1029 def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0,
1030 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1031 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>;
1033 def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0,
1034 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1035 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>;
1037 def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1,
1038 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1039 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>;
1041 def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1,
1042 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1043 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>;
1045 } // End of 'let Constraints = "$a = $dst" in'
1047 //===----------------------------------------------------------------------===//
1048 // FP Multiply-Accumulate Operations.
1051 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
1052 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1053 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
1054 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1055 (f64 DPR:$Ddin)))]>,
1056 RegConstraint<"$Ddin = $Dd">,
1057 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1059 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
1060 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1061 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
1062 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1064 RegConstraint<"$Sdin = $Sd">,
1065 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1066 // Some single precision VFP instructions may be executed on both NEON and
1067 // VFP pipelines on A8.
1068 let D = VFPNeonA8Domain;
1071 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1072 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1073 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1074 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1075 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1076 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
1078 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
1079 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1080 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
1081 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1082 (f64 DPR:$Ddin)))]>,
1083 RegConstraint<"$Ddin = $Dd">,
1084 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1086 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
1087 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1088 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
1089 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1091 RegConstraint<"$Sdin = $Sd">,
1092 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1093 // Some single precision VFP instructions may be executed on both NEON and
1094 // VFP pipelines on A8.
1095 let D = VFPNeonA8Domain;
1098 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1099 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1100 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1101 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1102 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1103 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1105 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
1106 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1107 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
1108 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1109 (f64 DPR:$Ddin)))]>,
1110 RegConstraint<"$Ddin = $Dd">,
1111 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1113 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
1114 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1115 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
1116 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1118 RegConstraint<"$Sdin = $Sd">,
1119 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1120 // Some single precision VFP instructions may be executed on both NEON and
1121 // VFP pipelines on A8.
1122 let D = VFPNeonA8Domain;
1125 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1126 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1127 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1128 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1129 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1130 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1132 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
1133 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1134 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
1135 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1136 (f64 DPR:$Ddin)))]>,
1137 RegConstraint<"$Ddin = $Dd">,
1138 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1140 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
1141 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1142 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1143 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1144 RegConstraint<"$Sdin = $Sd">,
1145 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1146 // Some single precision VFP instructions may be executed on both NEON and
1147 // VFP pipelines on A8.
1148 let D = VFPNeonA8Domain;
1151 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1152 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1153 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1154 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1155 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1156 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1158 //===----------------------------------------------------------------------===//
1159 // Fused FP Multiply-Accumulate Operations.
1161 def VFMAD : ADbI<0b11101, 0b10, 0, 0,
1162 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1163 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
1164 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1165 (f64 DPR:$Ddin)))]>,
1166 RegConstraint<"$Ddin = $Dd">,
1167 Requires<[HasVFP4,UseFusedMAC]>;
1169 def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
1170 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1171 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
1172 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1174 RegConstraint<"$Sdin = $Sd">,
1175 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1176 // Some single precision VFP instructions may be executed on both NEON and
1180 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1181 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1182 Requires<[HasVFP4,UseFusedMAC]>;
1183 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1184 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1185 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1187 // Match @llvm.fma.* intrinsics
1188 // (fma x, y, z) -> (vfms z, x, y)
1189 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
1190 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1191 Requires<[HasVFP4]>;
1192 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1193 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1194 Requires<[HasVFP4]>;
1196 def VFMSD : ADbI<0b11101, 0b10, 1, 0,
1197 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1198 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
1199 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1200 (f64 DPR:$Ddin)))]>,
1201 RegConstraint<"$Ddin = $Dd">,
1202 Requires<[HasVFP4,UseFusedMAC]>;
1204 def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
1205 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1206 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
1207 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1209 RegConstraint<"$Sdin = $Sd">,
1210 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1211 // Some single precision VFP instructions may be executed on both NEON and
1215 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1216 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1217 Requires<[HasVFP4,UseFusedMAC]>;
1218 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1219 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1220 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1222 // Match @llvm.fma.* intrinsics
1223 // (fma (fneg x), y, z) -> (vfms z, x, y)
1224 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
1225 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1226 Requires<[HasVFP4]>;
1227 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1228 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1229 Requires<[HasVFP4]>;
1230 // (fma x, (fneg y), z) -> (vfms z, x, y)
1231 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
1232 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1233 Requires<[HasVFP4]>;
1234 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1235 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1236 Requires<[HasVFP4]>;
1238 def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
1239 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1240 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
1241 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1242 (f64 DPR:$Ddin)))]>,
1243 RegConstraint<"$Ddin = $Dd">,
1244 Requires<[HasVFP4,UseFusedMAC]>;
1246 def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
1247 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1248 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
1249 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1251 RegConstraint<"$Sdin = $Sd">,
1252 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1253 // Some single precision VFP instructions may be executed on both NEON and
1257 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1258 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1259 Requires<[HasVFP4,UseFusedMAC]>;
1260 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1261 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1262 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1264 // Match @llvm.fma.* intrinsics
1265 // (fneg (fma x, y, z)) -> (vfnma z, x, y)
1266 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
1267 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1268 Requires<[HasVFP4]>;
1269 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1270 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1271 Requires<[HasVFP4]>;
1272 // (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)
1273 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
1274 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1275 Requires<[HasVFP4]>;
1276 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1277 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1278 Requires<[HasVFP4]>;
1280 def VFNMSD : ADbI<0b11101, 0b01, 0, 0,
1281 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1282 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
1283 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1284 (f64 DPR:$Ddin)))]>,
1285 RegConstraint<"$Ddin = $Dd">,
1286 Requires<[HasVFP4,UseFusedMAC]>;
1288 def VFNMSS : ASbI<0b11101, 0b01, 0, 0,
1289 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1290 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1291 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1292 RegConstraint<"$Sdin = $Sd">,
1293 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1294 // Some single precision VFP instructions may be executed on both NEON and
1298 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1299 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1300 Requires<[HasVFP4,UseFusedMAC]>;
1301 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1302 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1303 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1305 // Match @llvm.fma.* intrinsics
1307 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
1308 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
1309 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1310 Requires<[HasVFP4]>;
1311 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
1312 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1313 Requires<[HasVFP4]>;
1314 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
1315 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
1316 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1317 Requires<[HasVFP4]>;
1318 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
1319 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1320 Requires<[HasVFP4]>;
1321 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
1322 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
1323 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1324 Requires<[HasVFP4]>;
1325 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
1326 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1327 Requires<[HasVFP4]>;
1329 //===----------------------------------------------------------------------===//
1330 // FP Conditional moves.
1333 let neverHasSideEffects = 1 in {
1334 def VMOVDcc : ARMPseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, pred:$p),
1336 [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
1337 RegConstraint<"$Dn = $Dd">;
1339 def VMOVScc : ARMPseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, pred:$p),
1341 [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
1342 RegConstraint<"$Sn = $Sd">;
1343 } // neverHasSideEffects
1345 //===----------------------------------------------------------------------===//
1346 // Move from VFP System Register to ARM core register.
1349 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1351 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1353 // Instruction operand.
1356 let Inst{27-20} = 0b11101111;
1357 let Inst{19-16} = opc19_16;
1358 let Inst{15-12} = Rt;
1359 let Inst{11-8} = 0b1010;
1361 let Inst{6-5} = 0b00;
1363 let Inst{3-0} = 0b0000;
1366 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1368 let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
1369 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
1370 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
1372 // Application level FPSCR -> GPR
1373 let hasSideEffects = 1, Uses = [FPSCR] in
1374 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
1375 "vmrs", "\t$Rt, fpscr",
1376 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
1378 // System level FPEXC, FPSID -> GPR
1379 let Uses = [FPSCR] in {
1380 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1381 "vmrs", "\t$Rt, fpexc", []>;
1382 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
1383 "vmrs", "\t$Rt, fpsid", []>;
1384 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
1385 "vmrs", "\t$Rt, mvfr0", []>;
1386 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
1387 "vmrs", "\t$Rt, mvfr1", []>;
1388 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
1389 "vmrs", "\t$Rt, fpinst", []>;
1390 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),
1391 "vmrs", "\t$Rt, fpinst2", []>;
1394 //===----------------------------------------------------------------------===//
1395 // Move from ARM core register to VFP System Register.
1398 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1400 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1402 // Instruction operand.
1405 // Encode instruction operand.
1406 let Inst{15-12} = src;
1408 let Inst{27-20} = 0b11101110;
1409 let Inst{19-16} = opc19_16;
1410 let Inst{11-8} = 0b1010;
1415 let Defs = [FPSCR] in {
1416 // Application level GPR -> FPSCR
1417 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
1418 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1419 // System level GPR -> FPEXC
1420 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
1421 "vmsr", "\tfpexc, $src", []>;
1422 // System level GPR -> FPSID
1423 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
1424 "vmsr", "\tfpsid, $src", []>;
1426 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src),
1427 "vmsr", "\tfpinst, $src", []>;
1428 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src),
1429 "vmsr", "\tfpinst2, $src", []>;
1432 //===----------------------------------------------------------------------===//
1436 // Materialize FP immediates. VFP3 only.
1437 let isReMaterializable = 1 in {
1438 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1439 VFPMiscFrm, IIC_fpUNA64,
1440 "vmov", ".f64\t$Dd, $imm",
1441 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
1445 let Inst{27-23} = 0b11101;
1446 let Inst{22} = Dd{4};
1447 let Inst{21-20} = 0b11;
1448 let Inst{19-16} = imm{7-4};
1449 let Inst{15-12} = Dd{3-0};
1450 let Inst{11-9} = 0b101;
1451 let Inst{8} = 1; // Double precision.
1452 let Inst{7-4} = 0b0000;
1453 let Inst{3-0} = imm{3-0};
1456 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1457 VFPMiscFrm, IIC_fpUNA32,
1458 "vmov", ".f32\t$Sd, $imm",
1459 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1463 let Inst{27-23} = 0b11101;
1464 let Inst{22} = Sd{0};
1465 let Inst{21-20} = 0b11;
1466 let Inst{19-16} = imm{7-4};
1467 let Inst{15-12} = Sd{4-1};
1468 let Inst{11-9} = 0b101;
1469 let Inst{8} = 0; // Single precision.
1470 let Inst{7-4} = 0b0000;
1471 let Inst{3-0} = imm{3-0};
1475 //===----------------------------------------------------------------------===//
1476 // Assembler aliases.
1478 // A few mnemnoic aliases for pre-unifixed syntax. We don't guarantee to
1479 // support them all, but supporting at least some of the basics is
1480 // good to be friendly.
1481 def : VFP2MnemonicAlias<"flds", "vldr">;
1482 def : VFP2MnemonicAlias<"fldd", "vldr">;
1483 def : VFP2MnemonicAlias<"fmrs", "vmov">;
1484 def : VFP2MnemonicAlias<"fmsr", "vmov">;
1485 def : VFP2MnemonicAlias<"fsqrts", "vsqrt">;
1486 def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">;
1487 def : VFP2MnemonicAlias<"fadds", "vadd.f32">;
1488 def : VFP2MnemonicAlias<"faddd", "vadd.f64">;
1489 def : VFP2MnemonicAlias<"fmrdd", "vmov">;
1490 def : VFP2MnemonicAlias<"fmrds", "vmov">;
1491 def : VFP2MnemonicAlias<"fmrrd", "vmov">;
1492 def : VFP2MnemonicAlias<"fmdrr", "vmov">;
1493 def : VFP2MnemonicAlias<"fmuls", "vmul.f32">;
1494 def : VFP2MnemonicAlias<"fmuld", "vmul.f64">;
1495 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;
1496 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;
1497 def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">;
1498 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;
1499 def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">;
1500 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;
1501 def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">;
1502 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;
1503 def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">;
1504 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;
1505 def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">;
1506 def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">;
1507 def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">;
1508 def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">;
1509 def : VFP2MnemonicAlias<"fsts", "vstr">;
1510 def : VFP2MnemonicAlias<"fstd", "vstr">;
1511 def : VFP2MnemonicAlias<"fmacd", "vmla.f64">;
1512 def : VFP2MnemonicAlias<"fmacs", "vmla.f32">;
1513 def : VFP2MnemonicAlias<"fcpys", "vmov.f32">;
1514 def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">;
1515 def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">;
1516 def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">;
1517 def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">;
1518 def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">;
1519 def : VFP2MnemonicAlias<"fmrx", "vmrs">;
1520 def : VFP2MnemonicAlias<"fmxr", "vmsr">;
1522 // Be friendly and accept the old form of zero-compare
1523 def : VFP2InstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;
1524 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
1527 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
1528 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
1529 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1530 def : VFP2InstAlias<"faddd${p} $Dd, $Dn, $Dm",
1531 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1532 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
1533 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1534 def : VFP2InstAlias<"fsubd${p} $Dd, $Dn, $Dm",
1535 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1537 // No need for the size suffix on VSQRT. It's implied by the register classes.
1538 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1539 def : VFP2InstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
1541 // VLDR/VSTR accept an optional type suffix.
1542 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
1543 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1544 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
1545 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1546 def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
1547 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1548 def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",
1549 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1551 // VMOV can accept optional 32-bit or less data type suffix suffix.
1552 def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",
1553 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1554 def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn",
1555 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1556 def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn",
1557 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1558 def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt",
1559 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1560 def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt",
1561 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1562 def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt",
1563 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1565 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
1566 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
1567 def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",
1568 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
1570 // VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way
1572 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
1573 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;