1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
15 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
18 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
19 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
20 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
21 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
23 //===----------------------------------------------------------------------===//
24 // Operand Definitions.
27 // 8-bit floating-point immediate encodings.
28 def FPImmOperand : AsmOperandClass {
30 let ParserMethod = "parseFPImm";
33 def vfp_f16imm : Operand<f16>,
34 PatLeaf<(f16 fpimm), [{
35 return ARM_AM::getFP16Imm(N->getValueAPF()) != -1;
36 }], SDNodeXForm<fpimm, [{
37 APFloat InVal = N->getValueAPF();
38 uint32_t enc = ARM_AM::getFP16Imm(InVal);
39 return CurDAG->getTargetConstant(enc, MVT::i32);
41 let PrintMethod = "printFPImmOperand";
42 let ParserMatchClass = FPImmOperand;
45 def vfp_f32imm : Operand<f32>,
46 PatLeaf<(f32 fpimm), [{
47 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
48 }], SDNodeXForm<fpimm, [{
49 APFloat InVal = N->getValueAPF();
50 uint32_t enc = ARM_AM::getFP32Imm(InVal);
51 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
53 let PrintMethod = "printFPImmOperand";
54 let ParserMatchClass = FPImmOperand;
57 def vfp_f64imm : Operand<f64>,
58 PatLeaf<(f64 fpimm), [{
59 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;
60 }], SDNodeXForm<fpimm, [{
61 APFloat InVal = N->getValueAPF();
62 uint32_t enc = ARM_AM::getFP64Imm(InVal);
63 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
65 let PrintMethod = "printFPImmOperand";
66 let ParserMatchClass = FPImmOperand;
69 def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
70 return cast<LoadSDNode>(N)->getAlignment() >= 4;
73 def alignedstore32 : PatFrag<(ops node:$val, node:$ptr),
74 (store node:$val, node:$ptr), [{
75 return cast<StoreSDNode>(N)->getAlignment() >= 4;
78 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
79 // (the number of fixed bits) differently than it appears in the assembly
80 // source. It's encoded as "Size - fbits" where Size is the size of the
81 // fixed-point representation (32 or 16) and fbits is the value appearing
82 // in the assembly source, an integer in [0,16] or (0,32], depending on size.
83 def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; }
84 def fbits32 : Operand<i32> {
85 let PrintMethod = "printFBits32";
86 let ParserMatchClass = fbits32_asm_operand;
89 def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; }
90 def fbits16 : Operand<i32> {
91 let PrintMethod = "printFBits16";
92 let ParserMatchClass = fbits16_asm_operand;
95 //===----------------------------------------------------------------------===//
96 // Load / store Instructions.
99 let canFoldAsLoad = 1, isReMaterializable = 1 in {
101 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
102 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
103 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>;
105 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
106 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
107 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]> {
108 // Some single precision VFP instructions may be executed on both NEON and VFP
110 let D = VFPNeonDomain;
113 def VLDRH : AHI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5fp16:$addr),
114 IIC_fpLoad16, "vldr", ".16\t$Sd, $addr",
116 Requires<[HasFullFP16]>;
118 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
120 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
121 IIC_fpStore64, "vstr", "\t$Dd, $addr",
122 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>;
124 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
125 IIC_fpStore32, "vstr", "\t$Sd, $addr",
126 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]> {
127 // Some single precision VFP instructions may be executed on both NEON and VFP
129 let D = VFPNeonDomain;
132 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5fp16:$addr),
133 IIC_fpStore16, "vstr", ".16\t$Sd, $addr",
135 Requires<[HasFullFP16]>;
137 //===----------------------------------------------------------------------===//
138 // Load / store multiple Instructions.
141 multiclass vfp_ldst_mult<string asm, bit L_bit,
142 InstrItinClass itin, InstrItinClass itin_upd> {
145 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
147 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
148 let Inst{24-23} = 0b01; // Increment After
149 let Inst{21} = 0; // No writeback
150 let Inst{20} = L_bit;
153 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
155 IndexModeUpd, itin_upd,
156 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
157 let Inst{24-23} = 0b01; // Increment After
158 let Inst{21} = 1; // Writeback
159 let Inst{20} = L_bit;
162 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
164 IndexModeUpd, itin_upd,
165 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
166 let Inst{24-23} = 0b10; // Decrement Before
167 let Inst{21} = 1; // Writeback
168 let Inst{20} = L_bit;
173 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
175 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
176 let Inst{24-23} = 0b01; // Increment After
177 let Inst{21} = 0; // No writeback
178 let Inst{20} = L_bit;
180 // Some single precision VFP instructions may be executed on both NEON and
182 let D = VFPNeonDomain;
185 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
187 IndexModeUpd, itin_upd,
188 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
189 let Inst{24-23} = 0b01; // Increment After
190 let Inst{21} = 1; // Writeback
191 let Inst{20} = L_bit;
193 // Some single precision VFP instructions may be executed on both NEON and
195 let D = VFPNeonDomain;
198 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
200 IndexModeUpd, itin_upd,
201 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
202 let Inst{24-23} = 0b10; // Decrement Before
203 let Inst{21} = 1; // Writeback
204 let Inst{20} = L_bit;
206 // Some single precision VFP instructions may be executed on both NEON and
208 let D = VFPNeonDomain;
212 let hasSideEffects = 0 in {
214 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
215 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
217 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
218 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>;
222 def : MnemonicAlias<"vldm", "vldmia">;
223 def : MnemonicAlias<"vstm", "vstmia">;
225 // FLDM/FSTM - Load / Store multiple single / double precision registers for
227 // These instructions are deprecated!
228 def : VFP2MnemonicAlias<"fldmias", "vldmia">;
229 def : VFP2MnemonicAlias<"fldmdbs", "vldmdb">;
230 def : VFP2MnemonicAlias<"fldmeas", "vldmdb">;
231 def : VFP2MnemonicAlias<"fldmfds", "vldmia">;
232 def : VFP2MnemonicAlias<"fldmiad", "vldmia">;
233 def : VFP2MnemonicAlias<"fldmdbd", "vldmdb">;
234 def : VFP2MnemonicAlias<"fldmead", "vldmdb">;
235 def : VFP2MnemonicAlias<"fldmfdd", "vldmia">;
237 def : VFP2MnemonicAlias<"fstmias", "vstmia">;
238 def : VFP2MnemonicAlias<"fstmdbs", "vstmdb">;
239 def : VFP2MnemonicAlias<"fstmeas", "vstmia">;
240 def : VFP2MnemonicAlias<"fstmfds", "vstmdb">;
241 def : VFP2MnemonicAlias<"fstmiad", "vstmia">;
242 def : VFP2MnemonicAlias<"fstmdbd", "vstmdb">;
243 def : VFP2MnemonicAlias<"fstmead", "vstmia">;
244 def : VFP2MnemonicAlias<"fstmfdd", "vstmdb">;
246 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
248 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
250 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
252 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
254 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
255 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
256 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
257 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>;
258 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
259 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>;
260 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
261 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;
263 // FLDMX, FSTMX - Load and store multiple unknown precision registers for
265 // These instruction are deprecated so we don't want them to get selected.
266 multiclass vfp_ldstx_mult<string asm, bit L_bit> {
269 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
270 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> {
271 let Inst{24-23} = 0b01; // Increment After
272 let Inst{21} = 0; // No writeback
273 let Inst{20} = L_bit;
276 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
277 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
278 let Inst{24-23} = 0b01; // Increment After
279 let Inst{21} = 1; // Writeback
280 let Inst{20} = L_bit;
283 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
284 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
285 let Inst{24-23} = 0b10; // Decrement Before
286 let Inst{21} = 1; // Writeback
287 let Inst{20} = L_bit;
291 defm FLDM : vfp_ldstx_mult<"fldm", 1>;
292 defm FSTM : vfp_ldstx_mult<"fstm", 0>;
294 def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">;
295 def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">;
297 def : VFP2MnemonicAlias<"fstmeax", "fstmiax">;
298 def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">;
300 //===----------------------------------------------------------------------===//
301 // FP Binary Operations.
304 let TwoOperandAliasConstraint = "$Dn = $Dd" in
305 def VADDD : ADbI<0b11100, 0b11, 0, 0,
306 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
307 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
308 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
310 let TwoOperandAliasConstraint = "$Sn = $Sd" in
311 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
312 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
313 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
314 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
315 // Some single precision VFP instructions may be executed on both NEON and
316 // VFP pipelines on A8.
317 let D = VFPNeonA8Domain;
320 let TwoOperandAliasConstraint = "$Sn = $Sd" in
321 def VADDH : AHbI<0b11100, 0b11, 0, 0,
322 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
323 IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm",
326 let TwoOperandAliasConstraint = "$Dn = $Dd" in
327 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
328 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
329 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
330 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
332 let TwoOperandAliasConstraint = "$Sn = $Sd" in
333 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
334 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
335 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
336 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
337 // Some single precision VFP instructions may be executed on both NEON and
338 // VFP pipelines on A8.
339 let D = VFPNeonA8Domain;
342 let TwoOperandAliasConstraint = "$Sn = $Sd" in
343 def VSUBH : AHbI<0b11100, 0b11, 1, 0,
344 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
345 IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm",
348 let TwoOperandAliasConstraint = "$Dn = $Dd" in
349 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
350 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
351 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
352 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
354 let TwoOperandAliasConstraint = "$Sn = $Sd" in
355 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
356 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
357 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
358 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
360 let TwoOperandAliasConstraint = "$Sn = $Sd" in
361 def VDIVH : AHbI<0b11101, 0b00, 0, 0,
362 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
363 IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm",
366 let TwoOperandAliasConstraint = "$Dn = $Dd" in
367 def VMULD : ADbI<0b11100, 0b10, 0, 0,
368 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
369 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
370 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
372 let TwoOperandAliasConstraint = "$Sn = $Sd" in
373 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
374 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
375 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
376 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
377 // Some single precision VFP instructions may be executed on both NEON and
378 // VFP pipelines on A8.
379 let D = VFPNeonA8Domain;
382 let TwoOperandAliasConstraint = "$Sn = $Sd" in
383 def VMULH : AHbI<0b11100, 0b10, 0, 0,
384 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
385 IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm",
388 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
389 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
390 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
391 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
393 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
394 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
395 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
396 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
397 // Some single precision VFP instructions may be executed on both NEON and
398 // VFP pipelines on A8.
399 let D = VFPNeonA8Domain;
402 def VNMULH : AHbI<0b11100, 0b10, 1, 0,
403 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
404 IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm",
407 multiclass vsel_inst<string op, bits<2> opc, int CC> {
408 let DecoderNamespace = "VFPV8", PostEncoderMethod = "",
409 Uses = [CPSR], AddedComplexity = 4 in {
410 def H : AHbInp<0b11100, opc, 0,
411 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
412 NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"),
414 Requires<[HasFullFP16]>;
416 def S : ASbInp<0b11100, opc, 0,
417 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
418 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
419 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
420 Requires<[HasFPARMv8]>;
422 def D : ADbInp<0b11100, opc, 0,
423 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
424 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
425 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
426 Requires<[HasFPARMv8, HasDPVFP]>;
430 // The CC constants here match ARMCC::CondCodes.
431 defm VSELGT : vsel_inst<"gt", 0b11, 12>;
432 defm VSELGE : vsel_inst<"ge", 0b10, 10>;
433 defm VSELEQ : vsel_inst<"eq", 0b00, 0>;
434 defm VSELVS : vsel_inst<"vs", 0b01, 6>;
436 multiclass vmaxmin_inst<string op, bit opc, SDNode SD> {
437 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
438 def H : AHbInp<0b11101, 0b00, opc,
439 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
440 NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"),
442 Requires<[HasFullFP16]>;
444 def S : ASbInp<0b11101, 0b00, opc,
445 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
446 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
447 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
448 Requires<[HasFPARMv8]>;
450 def D : ADbInp<0b11101, 0b00, opc,
451 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
452 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
453 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
454 Requires<[HasFPARMv8, HasDPVFP]>;
458 defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, fmaxnum>;
459 defm VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>;
461 // Match reassociated forms only if not sign dependent rounding.
462 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
463 (VNMULD DPR:$a, DPR:$b)>,
464 Requires<[NoHonorSignDependentRounding,HasDPVFP]>;
465 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
466 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
468 // These are encoded as unary instructions.
469 let Defs = [FPSCR_NZCV] in {
470 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
471 (outs), (ins DPR:$Dd, DPR:$Dm),
472 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
473 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
475 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
476 (outs), (ins SPR:$Sd, SPR:$Sm),
477 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
478 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
479 // Some single precision VFP instructions may be executed on both NEON and
480 // VFP pipelines on A8.
481 let D = VFPNeonA8Domain;
484 def VCMPEH : AHuI<0b11101, 0b11, 0b0100, 0b11, 0,
485 (outs), (ins SPR:$Sd, SPR:$Sm),
486 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm",
490 // FIXME: Verify encoding after integrated assembler is working.
491 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
492 (outs), (ins DPR:$Dd, DPR:$Dm),
493 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
494 [/* For disassembly only; pattern left blank */]>;
496 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
497 (outs), (ins SPR:$Sd, SPR:$Sm),
498 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
499 [/* For disassembly only; pattern left blank */]> {
500 // Some single precision VFP instructions may be executed on both NEON and
501 // VFP pipelines on A8.
502 let D = VFPNeonA8Domain;
505 def VCMPH : AHuI<0b11101, 0b11, 0b0100, 0b01, 0,
506 (outs), (ins SPR:$Sd, SPR:$Sm),
507 IIC_fpCMP16, "vcmp", ".f16\t$Sd, $Sm",
509 } // Defs = [FPSCR_NZCV]
511 //===----------------------------------------------------------------------===//
512 // FP Unary Operations.
515 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
516 (outs DPR:$Dd), (ins DPR:$Dm),
517 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
518 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
520 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
521 (outs SPR:$Sd), (ins SPR:$Sm),
522 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
523 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
524 // Some single precision VFP instructions may be executed on both NEON and
525 // VFP pipelines on A8.
526 let D = VFPNeonA8Domain;
529 def VABSH : AHuI<0b11101, 0b11, 0b0000, 0b11, 0,
530 (outs SPR:$Sd), (ins SPR:$Sm),
531 IIC_fpUNA16, "vabs", ".f16\t$Sd, $Sm",
534 let Defs = [FPSCR_NZCV] in {
535 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
536 (outs), (ins DPR:$Dd),
537 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
538 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
539 let Inst{3-0} = 0b0000;
543 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
544 (outs), (ins SPR:$Sd),
545 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
546 [(arm_cmpfp0 SPR:$Sd)]> {
547 let Inst{3-0} = 0b0000;
550 // Some single precision VFP instructions may be executed on both NEON and
551 // VFP pipelines on A8.
552 let D = VFPNeonA8Domain;
555 def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0,
556 (outs), (ins SPR:$Sd),
557 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, #0",
559 let Inst{3-0} = 0b0000;
563 // FIXME: Verify encoding after integrated assembler is working.
564 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
565 (outs), (ins DPR:$Dd),
566 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
567 [/* For disassembly only; pattern left blank */]> {
568 let Inst{3-0} = 0b0000;
572 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
573 (outs), (ins SPR:$Sd),
574 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
575 [/* For disassembly only; pattern left blank */]> {
576 let Inst{3-0} = 0b0000;
579 // Some single precision VFP instructions may be executed on both NEON and
580 // VFP pipelines on A8.
581 let D = VFPNeonA8Domain;
584 def VCMPZH : AHuI<0b11101, 0b11, 0b0101, 0b01, 0,
585 (outs), (ins SPR:$Sd),
586 IIC_fpCMP16, "vcmp", ".f16\t$Sd, #0",
588 let Inst{3-0} = 0b0000;
591 } // Defs = [FPSCR_NZCV]
593 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
594 (outs DPR:$Dd), (ins SPR:$Sm),
595 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
596 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
597 // Instruction operands.
601 // Encode instruction operands.
602 let Inst{3-0} = Sm{4-1};
604 let Inst{15-12} = Dd{3-0};
605 let Inst{22} = Dd{4};
607 let Predicates = [HasVFP2, HasDPVFP];
610 // Special case encoding: bits 11-8 is 0b1011.
611 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
612 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
613 [(set SPR:$Sd, (fround DPR:$Dm))]> {
614 // Instruction operands.
618 // Encode instruction operands.
619 let Inst{3-0} = Dm{3-0};
621 let Inst{15-12} = Sd{4-1};
622 let Inst{22} = Sd{0};
624 let Inst{27-23} = 0b11101;
625 let Inst{21-16} = 0b110111;
626 let Inst{11-8} = 0b1011;
627 let Inst{7-6} = 0b11;
630 let Predicates = [HasVFP2, HasDPVFP];
633 // Between half, single and double-precision. For disassembly only.
635 // FIXME: Verify encoding after integrated assembler is working.
636 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
637 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
638 [/* For disassembly only; pattern left blank */]>,
641 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
642 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
643 [/* For disassembly only; pattern left blank */]>,
646 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
647 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
648 [/* For disassembly only; pattern left blank */]>,
651 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
652 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
653 [/* For disassembly only; pattern left blank */]>,
656 def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
657 (outs DPR:$Dd), (ins SPR:$Sm),
658 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
659 []>, Requires<[HasFPARMv8, HasDPVFP]> {
660 // Instruction operands.
663 // Encode instruction operands.
664 let Inst{3-0} = Sm{4-1};
668 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
669 (outs SPR:$Sd), (ins DPR:$Dm),
670 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
671 []>, Requires<[HasFPARMv8, HasDPVFP]> {
672 // Instruction operands.
676 // Encode instruction operands.
677 let Inst{3-0} = Dm{3-0};
679 let Inst{15-12} = Sd{4-1};
680 let Inst{22} = Sd{0};
683 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
684 (outs DPR:$Dd), (ins SPR:$Sm),
685 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
686 []>, Requires<[HasFPARMv8, HasDPVFP]> {
687 // Instruction operands.
690 // Encode instruction operands.
691 let Inst{3-0} = Sm{4-1};
695 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
696 (outs SPR:$Sd), (ins DPR:$Dm),
697 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
698 []>, Requires<[HasFPARMv8, HasDPVFP]> {
699 // Instruction operands.
703 // Encode instruction operands.
704 let Inst{15-12} = Sd{4-1};
705 let Inst{22} = Sd{0};
706 let Inst{3-0} = Dm{3-0};
710 def : Pat<(fp_to_f16 SPR:$a),
711 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
713 def : Pat<(fp_to_f16 (f64 DPR:$a)),
714 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
716 def : Pat<(f16_to_fp GPR:$a),
717 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
719 def : Pat<(f64 (f16_to_fp GPR:$a)),
720 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
722 multiclass vcvt_inst<string opc, bits<2> rm,
723 SDPatternOperator node = null_frag> {
724 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
725 def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0,
726 (outs SPR:$Sd), (ins SPR:$Sm),
727 NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"),
729 Requires<[HasFullFP16]> {
730 let Inst{17-16} = rm;
733 def UH : AHuInp<0b11101, 0b11, 0b1100, 0b01, 0,
734 (outs SPR:$Sd), (ins SPR:$Sm),
735 NoItinerary, !strconcat("vcvt", opc, ".u32.f16\t$Sd, $Sm"),
737 Requires<[HasFullFP16]> {
738 let Inst{17-16} = rm;
741 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
742 (outs SPR:$Sd), (ins SPR:$Sm),
743 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
745 Requires<[HasFPARMv8]> {
746 let Inst{17-16} = rm;
749 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
750 (outs SPR:$Sd), (ins SPR:$Sm),
751 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
753 Requires<[HasFPARMv8]> {
754 let Inst{17-16} = rm;
757 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
758 (outs SPR:$Sd), (ins DPR:$Dm),
759 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
761 Requires<[HasFPARMv8, HasDPVFP]> {
764 let Inst{17-16} = rm;
766 // Encode instruction operands
767 let Inst{3-0} = Dm{3-0};
772 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
773 (outs SPR:$Sd), (ins DPR:$Dm),
774 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
776 Requires<[HasFPARMv8, HasDPVFP]> {
779 let Inst{17-16} = rm;
781 // Encode instruction operands
782 let Inst{3-0} = Dm{3-0};
788 let Predicates = [HasFPARMv8] in {
789 def : Pat<(i32 (fp_to_sint (node SPR:$a))),
791 (!cast<Instruction>(NAME#"SS") SPR:$a),
793 def : Pat<(i32 (fp_to_uint (node SPR:$a))),
795 (!cast<Instruction>(NAME#"US") SPR:$a),
798 let Predicates = [HasFPARMv8, HasDPVFP] in {
799 def : Pat<(i32 (fp_to_sint (node (f64 DPR:$a)))),
801 (!cast<Instruction>(NAME#"SD") DPR:$a),
803 def : Pat<(i32 (fp_to_uint (node (f64 DPR:$a)))),
805 (!cast<Instruction>(NAME#"UD") DPR:$a),
810 defm VCVTA : vcvt_inst<"a", 0b00, frnd>;
811 defm VCVTN : vcvt_inst<"n", 0b01>;
812 defm VCVTP : vcvt_inst<"p", 0b10, fceil>;
813 defm VCVTM : vcvt_inst<"m", 0b11, ffloor>;
815 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
816 (outs DPR:$Dd), (ins DPR:$Dm),
817 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
818 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
820 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
821 (outs SPR:$Sd), (ins SPR:$Sm),
822 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
823 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
824 // Some single precision VFP instructions may be executed on both NEON and
825 // VFP pipelines on A8.
826 let D = VFPNeonA8Domain;
829 def VNEGH : AHuI<0b11101, 0b11, 0b0001, 0b01, 0,
830 (outs SPR:$Sd), (ins SPR:$Sm),
831 IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm",
834 multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> {
835 def H : AHuI<0b11101, 0b11, 0b0110, 0b11, 0,
836 (outs SPR:$Sd), (ins SPR:$Sm),
837 NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm",
839 Requires<[HasFullFP16]> {
844 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
845 (outs SPR:$Sd), (ins SPR:$Sm),
846 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
847 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
848 Requires<[HasFPARMv8]> {
852 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,
853 (outs DPR:$Dd), (ins DPR:$Dm),
854 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
855 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
856 Requires<[HasFPARMv8, HasDPVFP]> {
861 def : InstAlias<!strconcat("vrint", opc, "$p.f16.f16\t$Sd, $Sm"),
862 (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p)>,
863 Requires<[HasFullFP16]>;
864 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
865 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>,
866 Requires<[HasFPARMv8]>;
867 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
868 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>,
869 Requires<[HasFPARMv8,HasDPVFP]>;
872 defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc>;
873 defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint>;
874 defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>;
876 multiclass vrint_inst_anpm<string opc, bits<2> rm,
877 SDPatternOperator node = null_frag> {
878 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
879 def H : AHuInp<0b11101, 0b11, 0b1000, 0b01, 0,
880 (outs SPR:$Sd), (ins SPR:$Sm),
881 NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"),
883 Requires<[HasFullFP16]> {
884 let Inst{17-16} = rm;
886 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,
887 (outs SPR:$Sd), (ins SPR:$Sm),
888 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
889 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
890 Requires<[HasFPARMv8]> {
891 let Inst{17-16} = rm;
893 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,
894 (outs DPR:$Dd), (ins DPR:$Dm),
895 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
896 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
897 Requires<[HasFPARMv8, HasDPVFP]> {
898 let Inst{17-16} = rm;
902 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
903 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>,
904 Requires<[HasFPARMv8]>;
905 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
906 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>,
907 Requires<[HasFPARMv8,HasDPVFP]>;
910 defm VRINTA : vrint_inst_anpm<"a", 0b00, frnd>;
911 defm VRINTN : vrint_inst_anpm<"n", 0b01>;
912 defm VRINTP : vrint_inst_anpm<"p", 0b10, fceil>;
913 defm VRINTM : vrint_inst_anpm<"m", 0b11, ffloor>;
915 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
916 (outs DPR:$Dd), (ins DPR:$Dm),
917 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
918 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
920 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
921 (outs SPR:$Sd), (ins SPR:$Sm),
922 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
923 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
925 def VSQRTH : AHuI<0b11101, 0b11, 0b0001, 0b11, 0,
926 (outs SPR:$Sd), (ins SPR:$Sm),
927 IIC_fpSQRT16, "vsqrt", ".f16\t$Sd, $Sm",
930 let hasSideEffects = 0 in {
931 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
932 (outs DPR:$Dd), (ins DPR:$Dm),
933 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
935 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
936 (outs SPR:$Sd), (ins SPR:$Sm),
937 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
939 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
940 def VMOVH : ASuInp<0b11101, 0b11, 0b0000, 0b01, 0,
941 (outs SPR:$Sd), (ins SPR:$Sm),
942 IIC_fpUNA16, "vmovx.f16\t$Sd, $Sm", []>,
943 Requires<[HasFullFP16]>;
945 def VINSH : ASuInp<0b11101, 0b11, 0b0000, 0b11, 0,
946 (outs SPR:$Sd), (ins SPR:$Sm),
947 IIC_fpUNA16, "vins.f16\t$Sd, $Sm", []>,
948 Requires<[HasFullFP16]>;
949 } // PostEncoderMethod
952 //===----------------------------------------------------------------------===//
953 // FP <-> GPR Copies. Int <-> FP Conversions.
956 def VMOVRS : AVConv2I<0b11100001, 0b1010,
957 (outs GPR:$Rt), (ins SPR:$Sn),
958 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
959 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
960 // Instruction operands.
964 // Encode instruction operands.
965 let Inst{19-16} = Sn{4-1};
967 let Inst{15-12} = Rt;
969 let Inst{6-5} = 0b00;
970 let Inst{3-0} = 0b0000;
972 // Some single precision VFP instructions may be executed on both NEON and VFP
974 let D = VFPNeonDomain;
977 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
978 def VMOVSR : AVConv4I<0b11100000, 0b1010,
979 (outs SPR:$Sn), (ins GPR:$Rt),
980 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
981 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
982 Requires<[HasVFP2, UseVMOVSR]> {
983 // Instruction operands.
987 // Encode instruction operands.
988 let Inst{19-16} = Sn{4-1};
990 let Inst{15-12} = Rt;
992 let Inst{6-5} = 0b00;
993 let Inst{3-0} = 0b0000;
995 // Some single precision VFP instructions may be executed on both NEON and VFP
997 let D = VFPNeonDomain;
1000 let hasSideEffects = 0 in {
1001 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
1002 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
1003 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
1004 [/* FIXME: Can't write pattern for multiple result instr*/]> {
1005 // Instruction operands.
1010 // Encode instruction operands.
1011 let Inst{3-0} = Dm{3-0};
1012 let Inst{5} = Dm{4};
1013 let Inst{15-12} = Rt;
1014 let Inst{19-16} = Rt2;
1016 let Inst{7-6} = 0b00;
1018 // Some single precision VFP instructions may be executed on both NEON and VFP
1020 let D = VFPNeonDomain;
1022 // This instruction is equivalent to
1023 // $Rt = EXTRACT_SUBREG $Dm, ssub_0
1024 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
1025 let isExtractSubreg = 1;
1028 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
1029 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
1030 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
1031 [/* For disassembly only; pattern left blank */]> {
1036 // Encode instruction operands.
1037 let Inst{3-0} = src1{4-1};
1038 let Inst{5} = src1{0};
1039 let Inst{15-12} = Rt;
1040 let Inst{19-16} = Rt2;
1042 let Inst{7-6} = 0b00;
1044 // Some single precision VFP instructions may be executed on both NEON and VFP
1046 let D = VFPNeonDomain;
1047 let DecoderMethod = "DecodeVMOVRRS";
1051 // FMDHR: GPR -> SPR
1052 // FMDLR: GPR -> SPR
1054 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
1055 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
1056 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
1057 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
1058 // Instruction operands.
1063 // Encode instruction operands.
1064 let Inst{3-0} = Dm{3-0};
1065 let Inst{5} = Dm{4};
1066 let Inst{15-12} = Rt;
1067 let Inst{19-16} = Rt2;
1069 let Inst{7-6} = 0b00;
1071 // Some single precision VFP instructions may be executed on both NEON and VFP
1073 let D = VFPNeonDomain;
1075 // This instruction is equivalent to
1076 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1
1077 let isRegSequence = 1;
1080 // Hoist an fabs or a fneg of a value coming from integer registers
1081 // and do the fabs/fneg on the integer value. This is never a lose
1082 // and could enable the conversion to float to be removed completely.
1083 def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)),
1084 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1086 def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)),
1087 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1088 Requires<[IsThumb2]>;
1089 def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)),
1090 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>,
1092 def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)),
1093 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>,
1094 Requires<[IsThumb2]>;
1096 let hasSideEffects = 0 in
1097 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
1098 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
1099 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
1100 [/* For disassembly only; pattern left blank */]> {
1101 // Instruction operands.
1106 // Encode instruction operands.
1107 let Inst{3-0} = dst1{4-1};
1108 let Inst{5} = dst1{0};
1109 let Inst{15-12} = src1;
1110 let Inst{19-16} = src2;
1112 let Inst{7-6} = 0b00;
1114 // Some single precision VFP instructions may be executed on both NEON and VFP
1116 let D = VFPNeonDomain;
1118 let DecoderMethod = "DecodeVMOVSRR";
1121 // Move H->R, clearing top 16 bits
1122 def VMOVRH : AVConv2I<0b11100001, 0b1001,
1123 (outs GPR:$Rt), (ins SPR:$Sn),
1124 IIC_fpMOVSI, "vmov", ".f16\t$Rt, $Sn",
1126 Requires<[HasFullFP16]> {
1127 // Instruction operands.
1131 // Encode instruction operands.
1132 let Inst{19-16} = Sn{4-1};
1133 let Inst{7} = Sn{0};
1134 let Inst{15-12} = Rt;
1136 let Inst{6-5} = 0b00;
1137 let Inst{3-0} = 0b0000;
1140 // Move R->H, clearing top 16 bits
1141 def VMOVHR : AVConv4I<0b11100000, 0b1001,
1142 (outs SPR:$Sn), (ins GPR:$Rt),
1143 IIC_fpMOVIS, "vmov", ".f16\t$Sn, $Rt",
1145 Requires<[HasFullFP16]> {
1146 // Instruction operands.
1150 // Encode instruction operands.
1151 let Inst{19-16} = Sn{4-1};
1152 let Inst{7} = Sn{0};
1153 let Inst{15-12} = Rt;
1155 let Inst{6-5} = 0b00;
1156 let Inst{3-0} = 0b0000;
1159 // FMRDH: SPR -> GPR
1160 // FMRDL: SPR -> GPR
1161 // FMRRS: SPR -> GPR
1162 // FMRX: SPR system reg -> GPR
1163 // FMSRR: GPR -> SPR
1164 // FMXR: GPR -> VFP system reg
1169 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1170 bits<4> opcod4, dag oops, dag iops,
1171 InstrItinClass itin, string opc, string asm,
1173 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1175 // Instruction operands.
1179 // Encode instruction operands.
1180 let Inst{3-0} = Sm{4-1};
1181 let Inst{5} = Sm{0};
1182 let Inst{15-12} = Dd{3-0};
1183 let Inst{22} = Dd{4};
1185 let Predicates = [HasVFP2, HasDPVFP];
1188 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1189 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
1190 string opc, string asm, list<dag> pattern>
1191 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1193 // Instruction operands.
1197 // Encode instruction operands.
1198 let Inst{3-0} = Sm{4-1};
1199 let Inst{5} = Sm{0};
1200 let Inst{15-12} = Sd{4-1};
1201 let Inst{22} = Sd{0};
1204 class AVConv1IHs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1205 bits<4> opcod4, dag oops, dag iops,
1206 InstrItinClass itin, string opc, string asm,
1208 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1210 // Instruction operands.
1214 // Encode instruction operands.
1215 let Inst{3-0} = Sm{4-1};
1216 let Inst{5} = Sm{0};
1217 let Inst{15-12} = Sd{4-1};
1218 let Inst{22} = Sd{0};
1220 let Predicates = [HasFullFP16];
1223 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1224 (outs DPR:$Dd), (ins SPR:$Sm),
1225 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
1227 let Inst{7} = 1; // s32
1230 let Predicates=[HasVFP2, HasDPVFP] in {
1231 def : VFPPat<(f64 (sint_to_fp GPR:$a)),
1232 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1234 def : VFPPat<(f64 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))),
1235 (VSITOD (VLDRS addrmode5:$a))>;
1238 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
1239 (outs SPR:$Sd),(ins SPR:$Sm),
1240 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
1242 let Inst{7} = 1; // s32
1244 // Some single precision VFP instructions may be executed on both NEON and
1245 // VFP pipelines on A8.
1246 let D = VFPNeonA8Domain;
1249 def : VFPNoNEONPat<(f32 (sint_to_fp GPR:$a)),
1250 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1252 def : VFPNoNEONPat<(f32 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))),
1253 (VSITOS (VLDRS addrmode5:$a))>;
1255 def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1256 (outs SPR:$Sd), (ins SPR:$Sm),
1257 IIC_fpCVTIH, "vcvt", ".f16.s32\t$Sd, $Sm",
1259 let Inst{7} = 1; // s32
1262 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1263 (outs DPR:$Dd), (ins SPR:$Sm),
1264 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
1266 let Inst{7} = 0; // u32
1269 let Predicates=[HasVFP2, HasDPVFP] in {
1270 def : VFPPat<(f64 (uint_to_fp GPR:$a)),
1271 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1273 def : VFPPat<(f64 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))),
1274 (VUITOD (VLDRS addrmode5:$a))>;
1277 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
1278 (outs SPR:$Sd), (ins SPR:$Sm),
1279 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
1281 let Inst{7} = 0; // u32
1283 // Some single precision VFP instructions may be executed on both NEON and
1284 // VFP pipelines on A8.
1285 let D = VFPNeonA8Domain;
1288 def : VFPNoNEONPat<(f32 (uint_to_fp GPR:$a)),
1289 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1291 def : VFPNoNEONPat<(f32 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))),
1292 (VUITOS (VLDRS addrmode5:$a))>;
1294 def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1295 (outs SPR:$Sd), (ins SPR:$Sm),
1296 IIC_fpCVTIH, "vcvt", ".f16.u32\t$Sd, $Sm",
1298 let Inst{7} = 0; // u32
1303 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1304 bits<4> opcod4, dag oops, dag iops,
1305 InstrItinClass itin, string opc, string asm,
1307 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1309 // Instruction operands.
1313 // Encode instruction operands.
1314 let Inst{3-0} = Dm{3-0};
1315 let Inst{5} = Dm{4};
1316 let Inst{15-12} = Sd{4-1};
1317 let Inst{22} = Sd{0};
1319 let Predicates = [HasVFP2, HasDPVFP];
1322 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1323 bits<4> opcod4, dag oops, dag iops,
1324 InstrItinClass itin, string opc, string asm,
1326 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1328 // Instruction operands.
1332 // Encode instruction operands.
1333 let Inst{3-0} = Sm{4-1};
1334 let Inst{5} = Sm{0};
1335 let Inst{15-12} = Sd{4-1};
1336 let Inst{22} = Sd{0};
1339 class AVConv1IsH_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1340 bits<4> opcod4, dag oops, dag iops,
1341 InstrItinClass itin, string opc, string asm,
1343 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1345 // Instruction operands.
1349 // Encode instruction operands.
1350 let Inst{3-0} = Sm{4-1};
1351 let Inst{5} = Sm{0};
1352 let Inst{15-12} = Sd{4-1};
1353 let Inst{22} = Sd{0};
1355 let Predicates = [HasFullFP16];
1358 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
1359 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1360 (outs SPR:$Sd), (ins DPR:$Dm),
1361 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
1363 let Inst{7} = 1; // Z bit
1366 let Predicates=[HasVFP2, HasDPVFP] in {
1367 def : VFPPat<(i32 (fp_to_sint (f64 DPR:$a))),
1368 (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>;
1370 def : VFPPat<(alignedstore32 (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr),
1371 (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>;
1374 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1375 (outs SPR:$Sd), (ins SPR:$Sm),
1376 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
1378 let Inst{7} = 1; // Z bit
1380 // Some single precision VFP instructions may be executed on both NEON and
1381 // VFP pipelines on A8.
1382 let D = VFPNeonA8Domain;
1385 def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
1386 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
1388 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))),
1390 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
1392 def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
1393 (outs SPR:$Sd), (ins SPR:$Sm),
1394 IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm",
1396 let Inst{7} = 1; // Z bit
1399 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1400 (outs SPR:$Sd), (ins DPR:$Dm),
1401 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1403 let Inst{7} = 1; // Z bit
1406 let Predicates=[HasVFP2, HasDPVFP] in {
1407 def : VFPPat<(i32 (fp_to_uint (f64 DPR:$a))),
1408 (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>;
1410 def : VFPPat<(alignedstore32 (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr),
1411 (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>;
1414 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1415 (outs SPR:$Sd), (ins SPR:$Sm),
1416 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
1418 let Inst{7} = 1; // Z bit
1420 // Some single precision VFP instructions may be executed on both NEON and
1421 // VFP pipelines on A8.
1422 let D = VFPNeonA8Domain;
1425 def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
1426 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
1428 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))),
1430 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
1432 def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1433 (outs SPR:$Sd), (ins SPR:$Sm),
1434 IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm",
1436 let Inst{7} = 1; // Z bit
1439 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
1440 let Uses = [FPSCR] in {
1441 // FIXME: Verify encoding after integrated assembler is working.
1442 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1443 (outs SPR:$Sd), (ins DPR:$Dm),
1444 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1445 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
1446 let Inst{7} = 0; // Z bit
1449 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1450 (outs SPR:$Sd), (ins SPR:$Sm),
1451 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1452 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
1453 let Inst{7} = 0; // Z bit
1456 def VTOSIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
1457 (outs SPR:$Sd), (ins SPR:$Sm),
1458 IIC_fpCVTHI, "vcvtr", ".s32.f16\t$Sd, $Sm",
1460 let Inst{7} = 0; // Z bit
1463 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1464 (outs SPR:$Sd), (ins DPR:$Dm),
1465 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1466 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1467 let Inst{7} = 0; // Z bit
1470 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1471 (outs SPR:$Sd), (ins SPR:$Sm),
1472 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1473 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1474 let Inst{7} = 0; // Z bit
1477 def VTOUIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1478 (outs SPR:$Sd), (ins SPR:$Sm),
1479 IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm",
1481 let Inst{7} = 0; // Z bit
1485 // Convert between floating-point and fixed-point
1486 // Data type for fixed-point naming convention:
1487 // S16 (U=0, sx=0) -> SH
1488 // U16 (U=1, sx=0) -> UH
1489 // S32 (U=0, sx=1) -> SL
1490 // U32 (U=1, sx=1) -> UL
1492 let Constraints = "$a = $dst" in {
1494 // FP to Fixed-Point:
1496 // Single Precision register
1497 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1498 bit op5, dag oops, dag iops, InstrItinClass itin,
1499 string opc, string asm, list<dag> pattern>
1500 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1501 Sched<[WriteCvtFP]> {
1503 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1504 let Inst{22} = dst{0};
1505 let Inst{15-12} = dst{4-1};
1508 // Double Precision register
1509 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1510 bit op5, dag oops, dag iops, InstrItinClass itin,
1511 string opc, string asm, list<dag> pattern>
1512 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1513 Sched<[WriteCvtFP]> {
1515 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1516 let Inst{22} = dst{4};
1517 let Inst{15-12} = dst{3-0};
1519 let Predicates = [HasVFP2, HasDPVFP];
1522 def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0,
1523 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1524 IIC_fpCVTHI, "vcvt", ".s16.f16\t$dst, $a, $fbits", []>,
1525 Requires<[HasFullFP16]>;
1527 def VTOUHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 0,
1528 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1529 IIC_fpCVTHI, "vcvt", ".u16.f16\t$dst, $a, $fbits", []>,
1530 Requires<[HasFullFP16]>;
1532 def VTOSLH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 1,
1533 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1534 IIC_fpCVTHI, "vcvt", ".s32.f16\t$dst, $a, $fbits", []>,
1535 Requires<[HasFullFP16]>;
1537 def VTOULH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 1,
1538 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1539 IIC_fpCVTHI, "vcvt", ".u32.f16\t$dst, $a, $fbits", []>,
1540 Requires<[HasFullFP16]>;
1542 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,
1543 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1544 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> {
1545 // Some single precision VFP instructions may be executed on both NEON and
1546 // VFP pipelines on A8.
1547 let D = VFPNeonA8Domain;
1550 def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0,
1551 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1552 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> {
1553 // Some single precision VFP instructions may be executed on both NEON and
1554 // VFP pipelines on A8.
1555 let D = VFPNeonA8Domain;
1558 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1,
1559 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1560 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> {
1561 // Some single precision VFP instructions may be executed on both NEON and
1562 // VFP pipelines on A8.
1563 let D = VFPNeonA8Domain;
1566 def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1,
1567 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1568 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> {
1569 // Some single precision VFP instructions may be executed on both NEON and
1570 // VFP pipelines on A8.
1571 let D = VFPNeonA8Domain;
1574 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0,
1575 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1576 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>;
1578 def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0,
1579 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1580 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>;
1582 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1,
1583 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1584 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>;
1586 def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1,
1587 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1588 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>;
1590 // Fixed-Point to FP:
1592 def VSHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 0,
1593 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1594 IIC_fpCVTIH, "vcvt", ".f16.s16\t$dst, $a, $fbits", []>,
1595 Requires<[HasFullFP16]>;
1597 def VUHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 0,
1598 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1599 IIC_fpCVTIH, "vcvt", ".f16.u16\t$dst, $a, $fbits", []>,
1600 Requires<[HasFullFP16]>;
1602 def VSLTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 1,
1603 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1604 IIC_fpCVTIH, "vcvt", ".f16.s32\t$dst, $a, $fbits", []>,
1605 Requires<[HasFullFP16]>;
1607 def VULTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 1,
1608 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1609 IIC_fpCVTIH, "vcvt", ".f16.u32\t$dst, $a, $fbits", []>,
1610 Requires<[HasFullFP16]>;
1612 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,
1613 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1614 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> {
1615 // Some single precision VFP instructions may be executed on both NEON and
1616 // VFP pipelines on A8.
1617 let D = VFPNeonA8Domain;
1620 def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0,
1621 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1622 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> {
1623 // Some single precision VFP instructions may be executed on both NEON and
1624 // VFP pipelines on A8.
1625 let D = VFPNeonA8Domain;
1628 def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1,
1629 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1630 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> {
1631 // Some single precision VFP instructions may be executed on both NEON and
1632 // VFP pipelines on A8.
1633 let D = VFPNeonA8Domain;
1636 def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1,
1637 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1638 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> {
1639 // Some single precision VFP instructions may be executed on both NEON and
1640 // VFP pipelines on A8.
1641 let D = VFPNeonA8Domain;
1644 def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0,
1645 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1646 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>;
1648 def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0,
1649 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1650 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>;
1652 def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1,
1653 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1654 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>;
1656 def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1,
1657 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1658 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>;
1660 } // End of 'let Constraints = "$a = $dst" in'
1662 //===----------------------------------------------------------------------===//
1663 // FP Multiply-Accumulate Operations.
1666 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
1667 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1668 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
1669 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1670 (f64 DPR:$Ddin)))]>,
1671 RegConstraint<"$Ddin = $Dd">,
1672 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1674 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
1675 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1676 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
1677 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1679 RegConstraint<"$Sdin = $Sd">,
1680 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1681 // Some single precision VFP instructions may be executed on both NEON and
1682 // VFP pipelines on A8.
1683 let D = VFPNeonA8Domain;
1686 def VMLAH : AHbI<0b11100, 0b00, 0, 0,
1687 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1688 IIC_fpMAC16, "vmla", ".f16\t$Sd, $Sn, $Sm",
1690 RegConstraint<"$Sdin = $Sd">,
1691 Requires<[HasFullFP16,UseFPVMLx,DontUseFusedMAC]>;
1693 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1694 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1695 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1696 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1697 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1698 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
1700 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
1701 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1702 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
1703 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1704 (f64 DPR:$Ddin)))]>,
1705 RegConstraint<"$Ddin = $Dd">,
1706 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1708 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
1709 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1710 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
1711 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1713 RegConstraint<"$Sdin = $Sd">,
1714 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1715 // Some single precision VFP instructions may be executed on both NEON and
1716 // VFP pipelines on A8.
1717 let D = VFPNeonA8Domain;
1720 def VMLSH : AHbI<0b11100, 0b00, 1, 0,
1721 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1722 IIC_fpMAC16, "vmls", ".f16\t$Sd, $Sn, $Sm",
1724 RegConstraint<"$Sdin = $Sd">,
1725 Requires<[HasFullFP16,UseFPVMLx,DontUseFusedMAC]>;
1727 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1728 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1729 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1730 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1731 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1732 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1734 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
1735 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1736 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
1737 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1738 (f64 DPR:$Ddin)))]>,
1739 RegConstraint<"$Ddin = $Dd">,
1740 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1742 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
1743 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1744 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
1745 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1747 RegConstraint<"$Sdin = $Sd">,
1748 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1749 // Some single precision VFP instructions may be executed on both NEON and
1750 // VFP pipelines on A8.
1751 let D = VFPNeonA8Domain;
1754 def VNMLAH : AHbI<0b11100, 0b01, 1, 0,
1755 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1756 IIC_fpMAC16, "vnmla", ".f16\t$Sd, $Sn, $Sm",
1758 RegConstraint<"$Sdin = $Sd">,
1759 Requires<[HasFullFP16,UseFPVMLx,DontUseFusedMAC]>;
1761 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1762 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1763 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1764 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1765 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1766 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1768 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
1769 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1770 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
1771 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1772 (f64 DPR:$Ddin)))]>,
1773 RegConstraint<"$Ddin = $Dd">,
1774 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1776 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
1777 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1778 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1779 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1780 RegConstraint<"$Sdin = $Sd">,
1781 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1782 // Some single precision VFP instructions may be executed on both NEON and
1783 // VFP pipelines on A8.
1784 let D = VFPNeonA8Domain;
1787 def VNMLSH : AHbI<0b11100, 0b01, 0, 0,
1788 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1789 IIC_fpMAC16, "vnmls", ".f16\t$Sd, $Sn, $Sm",
1791 RegConstraint<"$Sdin = $Sd">,
1792 Requires<[HasFullFP16,UseFPVMLx,DontUseFusedMAC]>;
1794 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1795 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1796 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1797 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1798 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1799 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1801 //===----------------------------------------------------------------------===//
1802 // Fused FP Multiply-Accumulate Operations.
1804 def VFMAD : ADbI<0b11101, 0b10, 0, 0,
1805 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1806 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
1807 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1808 (f64 DPR:$Ddin)))]>,
1809 RegConstraint<"$Ddin = $Dd">,
1810 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1812 def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
1813 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1814 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
1815 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1817 RegConstraint<"$Sdin = $Sd">,
1818 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1819 // Some single precision VFP instructions may be executed on both NEON and
1823 def VFMAH : AHbI<0b11101, 0b10, 0, 0,
1824 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1825 IIC_fpFMAC16, "vfma", ".f16\t$Sd, $Sn, $Sm",
1827 RegConstraint<"$Sdin = $Sd">,
1828 Requires<[HasFullFP16,UseFusedMAC]>;
1830 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1831 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1832 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1833 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1834 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1835 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1837 // Match @llvm.fma.* intrinsics
1838 // (fma x, y, z) -> (vfms z, x, y)
1839 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
1840 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1841 Requires<[HasVFP4,HasDPVFP]>;
1842 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1843 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1844 Requires<[HasVFP4]>;
1846 def VFMSD : ADbI<0b11101, 0b10, 1, 0,
1847 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1848 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
1849 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1850 (f64 DPR:$Ddin)))]>,
1851 RegConstraint<"$Ddin = $Dd">,
1852 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1854 def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
1855 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1856 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
1857 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1859 RegConstraint<"$Sdin = $Sd">,
1860 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1861 // Some single precision VFP instructions may be executed on both NEON and
1865 def VFMSH : AHbI<0b11101, 0b10, 1, 0,
1866 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1867 IIC_fpFMAC16, "vfms", ".f16\t$Sd, $Sn, $Sm",
1869 RegConstraint<"$Sdin = $Sd">,
1870 Requires<[HasFullFP16,UseFusedMAC]>;
1872 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1873 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1874 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1875 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1876 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1877 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1879 // Match @llvm.fma.* intrinsics
1880 // (fma (fneg x), y, z) -> (vfms z, x, y)
1881 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
1882 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1883 Requires<[HasVFP4,HasDPVFP]>;
1884 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1885 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1886 Requires<[HasVFP4]>;
1887 // (fma x, (fneg y), z) -> (vfms z, x, y)
1888 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
1889 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1890 Requires<[HasVFP4,HasDPVFP]>;
1891 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1892 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1893 Requires<[HasVFP4]>;
1895 def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
1896 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1897 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
1898 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1899 (f64 DPR:$Ddin)))]>,
1900 RegConstraint<"$Ddin = $Dd">,
1901 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1903 def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
1904 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1905 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
1906 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1908 RegConstraint<"$Sdin = $Sd">,
1909 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1910 // Some single precision VFP instructions may be executed on both NEON and
1914 def VFNMAH : AHbI<0b11101, 0b01, 1, 0,
1915 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1916 IIC_fpFMAC16, "vfnma", ".f16\t$Sd, $Sn, $Sm",
1918 RegConstraint<"$Sdin = $Sd">,
1919 Requires<[HasFullFP16,UseFusedMAC]>;
1921 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1922 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1923 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1924 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1925 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1926 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1928 // Match @llvm.fma.* intrinsics
1929 // (fneg (fma x, y, z)) -> (vfnma z, x, y)
1930 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
1931 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1932 Requires<[HasVFP4,HasDPVFP]>;
1933 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1934 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1935 Requires<[HasVFP4]>;
1936 // (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)
1937 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
1938 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1939 Requires<[HasVFP4,HasDPVFP]>;
1940 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1941 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1942 Requires<[HasVFP4]>;
1944 def VFNMSD : ADbI<0b11101, 0b01, 0, 0,
1945 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1946 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
1947 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1948 (f64 DPR:$Ddin)))]>,
1949 RegConstraint<"$Ddin = $Dd">,
1950 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1952 def VFNMSS : ASbI<0b11101, 0b01, 0, 0,
1953 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1954 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1955 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1956 RegConstraint<"$Sdin = $Sd">,
1957 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1958 // Some single precision VFP instructions may be executed on both NEON and
1962 def VFNMSH : AHbI<0b11101, 0b01, 0, 0,
1963 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1964 IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm",
1966 RegConstraint<"$Sdin = $Sd">,
1967 Requires<[HasFullFP16,UseFusedMAC]>;
1969 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1970 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1971 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1972 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1973 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1974 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1976 // Match @llvm.fma.* intrinsics
1978 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
1979 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
1980 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1981 Requires<[HasVFP4,HasDPVFP]>;
1982 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
1983 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1984 Requires<[HasVFP4]>;
1985 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
1986 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
1987 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1988 Requires<[HasVFP4,HasDPVFP]>;
1989 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
1990 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1991 Requires<[HasVFP4]>;
1992 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
1993 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
1994 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1995 Requires<[HasVFP4,HasDPVFP]>;
1996 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
1997 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1998 Requires<[HasVFP4]>;
2000 //===----------------------------------------------------------------------===//
2001 // FP Conditional moves.
2004 let hasSideEffects = 0 in {
2005 def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
2007 [(set (f64 DPR:$Dd),
2008 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
2009 RegConstraint<"$Dn = $Dd">, Requires<[HasVFP2,HasDPVFP]>;
2011 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
2013 [(set (f32 SPR:$Sd),
2014 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
2015 RegConstraint<"$Sn = $Sd">, Requires<[HasVFP2]>;
2018 //===----------------------------------------------------------------------===//
2019 // Move from VFP System Register to ARM core register.
2022 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
2024 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
2026 // Instruction operand.
2029 let Inst{27-20} = 0b11101111;
2030 let Inst{19-16} = opc19_16;
2031 let Inst{15-12} = Rt;
2032 let Inst{11-8} = 0b1010;
2034 let Inst{6-5} = 0b00;
2036 let Inst{3-0} = 0b0000;
2039 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
2041 let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
2042 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
2043 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
2045 // Application level FPSCR -> GPR
2046 let hasSideEffects = 1, Uses = [FPSCR] in
2047 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
2048 "vmrs", "\t$Rt, fpscr",
2049 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
2051 // System level FPEXC, FPSID -> GPR
2052 let Uses = [FPSCR] in {
2053 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
2054 "vmrs", "\t$Rt, fpexc", []>;
2055 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
2056 "vmrs", "\t$Rt, fpsid", []>;
2057 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
2058 "vmrs", "\t$Rt, mvfr0", []>;
2059 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
2060 "vmrs", "\t$Rt, mvfr1", []>;
2061 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins),
2062 "vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>;
2063 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
2064 "vmrs", "\t$Rt, fpinst", []>;
2065 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),
2066 "vmrs", "\t$Rt, fpinst2", []>;
2069 //===----------------------------------------------------------------------===//
2070 // Move from ARM core register to VFP System Register.
2073 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
2075 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
2077 // Instruction operand.
2080 // Encode instruction operand.
2081 let Inst{15-12} = src;
2083 let Inst{27-20} = 0b11101110;
2084 let Inst{19-16} = opc19_16;
2085 let Inst{11-8} = 0b1010;
2090 let Defs = [FPSCR] in {
2091 // Application level GPR -> FPSCR
2092 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
2093 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
2094 // System level GPR -> FPEXC
2095 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
2096 "vmsr", "\tfpexc, $src", []>;
2097 // System level GPR -> FPSID
2098 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
2099 "vmsr", "\tfpsid, $src", []>;
2101 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src),
2102 "vmsr", "\tfpinst, $src", []>;
2103 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src),
2104 "vmsr", "\tfpinst2, $src", []>;
2107 //===----------------------------------------------------------------------===//
2111 // Materialize FP immediates. VFP3 only.
2112 let isReMaterializable = 1 in {
2113 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
2114 VFPMiscFrm, IIC_fpUNA64,
2115 "vmov", ".f64\t$Dd, $imm",
2116 [(set DPR:$Dd, vfp_f64imm:$imm)]>,
2117 Requires<[HasVFP3,HasDPVFP]> {
2121 let Inst{27-23} = 0b11101;
2122 let Inst{22} = Dd{4};
2123 let Inst{21-20} = 0b11;
2124 let Inst{19-16} = imm{7-4};
2125 let Inst{15-12} = Dd{3-0};
2126 let Inst{11-9} = 0b101;
2127 let Inst{8} = 1; // Double precision.
2128 let Inst{7-4} = 0b0000;
2129 let Inst{3-0} = imm{3-0};
2132 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
2133 VFPMiscFrm, IIC_fpUNA32,
2134 "vmov", ".f32\t$Sd, $imm",
2135 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
2139 let Inst{27-23} = 0b11101;
2140 let Inst{22} = Sd{0};
2141 let Inst{21-20} = 0b11;
2142 let Inst{19-16} = imm{7-4};
2143 let Inst{15-12} = Sd{4-1};
2144 let Inst{11-9} = 0b101;
2145 let Inst{8} = 0; // Single precision.
2146 let Inst{7-4} = 0b0000;
2147 let Inst{3-0} = imm{3-0};
2150 def FCONSTH : VFPAI<(outs SPR:$Sd), (ins vfp_f16imm:$imm),
2151 VFPMiscFrm, IIC_fpUNA16,
2152 "vmov", ".f16\t$Sd, $imm",
2153 []>, Requires<[HasFullFP16]> {
2157 let Inst{27-23} = 0b11101;
2158 let Inst{22} = Sd{0};
2159 let Inst{21-20} = 0b11;
2160 let Inst{19-16} = imm{7-4};
2161 let Inst{15-12} = Sd{4-1};
2162 let Inst{11-8} = 0b1001; // Half precision
2163 let Inst{7-4} = 0b0000;
2164 let Inst{3-0} = imm{3-0};
2168 //===----------------------------------------------------------------------===//
2169 // Assembler aliases.
2171 // A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to
2172 // support them all, but supporting at least some of the basics is
2173 // good to be friendly.
2174 def : VFP2MnemonicAlias<"flds", "vldr">;
2175 def : VFP2MnemonicAlias<"fldd", "vldr">;
2176 def : VFP2MnemonicAlias<"fmrs", "vmov">;
2177 def : VFP2MnemonicAlias<"fmsr", "vmov">;
2178 def : VFP2MnemonicAlias<"fsqrts", "vsqrt">;
2179 def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">;
2180 def : VFP2MnemonicAlias<"fadds", "vadd.f32">;
2181 def : VFP2MnemonicAlias<"faddd", "vadd.f64">;
2182 def : VFP2MnemonicAlias<"fmrdd", "vmov">;
2183 def : VFP2MnemonicAlias<"fmrds", "vmov">;
2184 def : VFP2MnemonicAlias<"fmrrd", "vmov">;
2185 def : VFP2MnemonicAlias<"fmdrr", "vmov">;
2186 def : VFP2MnemonicAlias<"fmuls", "vmul.f32">;
2187 def : VFP2MnemonicAlias<"fmuld", "vmul.f64">;
2188 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;
2189 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;
2190 def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">;
2191 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;
2192 def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">;
2193 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;
2194 def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">;
2195 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;
2196 def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">;
2197 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;
2198 def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">;
2199 def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">;
2200 def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">;
2201 def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">;
2202 def : VFP2MnemonicAlias<"fsts", "vstr">;
2203 def : VFP2MnemonicAlias<"fstd", "vstr">;
2204 def : VFP2MnemonicAlias<"fmacd", "vmla.f64">;
2205 def : VFP2MnemonicAlias<"fmacs", "vmla.f32">;
2206 def : VFP2MnemonicAlias<"fcpys", "vmov.f32">;
2207 def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">;
2208 def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">;
2209 def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">;
2210 def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">;
2211 def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">;
2212 def : VFP2MnemonicAlias<"fmrx", "vmrs">;
2213 def : VFP2MnemonicAlias<"fmxr", "vmsr">;
2215 // Be friendly and accept the old form of zero-compare
2216 def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;
2217 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
2220 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
2221 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
2222 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2223 def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm",
2224 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
2225 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
2226 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2227 def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm",
2228 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
2230 // No need for the size suffix on VSQRT. It's implied by the register classes.
2231 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
2232 def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
2234 // VLDR/VSTR accept an optional type suffix.
2235 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
2236 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2237 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
2238 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2239 def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
2240 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
2241 def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",
2242 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
2244 // VMOV can accept optional 32-bit or less data type suffix suffix.
2245 def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",
2246 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
2247 def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn",
2248 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
2249 def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn",
2250 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
2251 def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt",
2252 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2253 def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt",
2254 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2255 def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt",
2256 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2258 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
2259 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
2260 def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",
2261 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
2263 // VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way
2265 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
2266 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
2268 // FCONSTD/FCONSTS alias for vmov.f64/vmov.f32
2269 // These aliases provide added functionality over vmov.f instructions by
2270 // allowing users to write assembly containing encoded floating point constants
2271 // (e.g. #0x70 vs #1.0). Without these alises there is no way for the
2272 // assembler to accept encoded fp constants (but the equivalent fp-literal is
2273 // accepted directly by vmovf).
2274 def : VFP3InstAlias<"fconstd${p} $Dd, $val",
2275 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>;
2276 def : VFP3InstAlias<"fconsts${p} $Sd, $val",
2277 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;