1 //===- ARMInstrVFP.td - VFP support for ARM ----------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
30 //===----------------------------------------------------------------------===//
31 // Operand Definitions.
34 def vfp_f32imm : Operand<f32>,
35 PatLeaf<(f32 fpimm), [{
36 return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
38 let PrintMethod = "printVFPf32ImmOperand";
39 let DecoderMethod = "DecodeVFPfpImm";
42 def vfp_f64imm : Operand<f64>,
43 PatLeaf<(f64 fpimm), [{
44 return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
46 let PrintMethod = "printVFPf64ImmOperand";
47 let DecoderMethod = "DecodeVFPfpImm";
51 //===----------------------------------------------------------------------===//
52 // Load / store Instructions.
55 let canFoldAsLoad = 1, isReMaterializable = 1 in {
57 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
58 IIC_fpLoad64, "vldr", ".64\t$Dd, $addr",
59 [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>;
61 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
62 IIC_fpLoad32, "vldr", ".32\t$Sd, $addr",
63 [(set SPR:$Sd, (load addrmode5:$addr))]> {
64 // Some single precision VFP instructions may be executed on both NEON and VFP
66 let D = VFPNeonDomain;
69 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
71 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
72 IIC_fpStore64, "vstr", ".64\t$Dd, $addr",
73 [(store (f64 DPR:$Dd), addrmode5:$addr)]>;
75 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
76 IIC_fpStore32, "vstr", ".32\t$Sd, $addr",
77 [(store SPR:$Sd, addrmode5:$addr)]> {
78 // Some single precision VFP instructions may be executed on both NEON and VFP
80 let D = VFPNeonDomain;
83 //===----------------------------------------------------------------------===//
84 // Load / store multiple Instructions.
87 multiclass vfp_ldst_mult<string asm, bit L_bit,
88 InstrItinClass itin, InstrItinClass itin_upd> {
91 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
93 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
94 let Inst{24-23} = 0b01; // Increment After
95 let Inst{21} = 0; // No writeback
99 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
101 IndexModeUpd, itin_upd,
102 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
103 let Inst{24-23} = 0b01; // Increment After
104 let Inst{21} = 1; // Writeback
105 let Inst{20} = L_bit;
108 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
110 IndexModeUpd, itin_upd,
111 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
112 let Inst{24-23} = 0b10; // Decrement Before
113 let Inst{21} = 1; // Writeback
114 let Inst{20} = L_bit;
119 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
121 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
122 let Inst{24-23} = 0b01; // Increment After
123 let Inst{21} = 0; // No writeback
124 let Inst{20} = L_bit;
126 // Some single precision VFP instructions may be executed on both NEON and
128 let D = VFPNeonDomain;
131 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
133 IndexModeUpd, itin_upd,
134 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
135 let Inst{24-23} = 0b01; // Increment After
136 let Inst{21} = 1; // Writeback
137 let Inst{20} = L_bit;
139 // Some single precision VFP instructions may be executed on both NEON and
141 let D = VFPNeonDomain;
144 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
146 IndexModeUpd, itin_upd,
147 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
148 let Inst{24-23} = 0b10; // Decrement Before
149 let Inst{21} = 1; // Writeback
150 let Inst{20} = L_bit;
152 // Some single precision VFP instructions may be executed on both NEON and
154 let D = VFPNeonDomain;
158 let neverHasSideEffects = 1 in {
160 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
161 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
163 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
164 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpLoad_m, IIC_fpLoad_mu>;
166 } // neverHasSideEffects
168 def : MnemonicAlias<"vldm", "vldmia">;
169 def : MnemonicAlias<"vstm", "vstmia">;
171 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
173 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
175 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
177 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
180 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
182 //===----------------------------------------------------------------------===//
183 // FP Binary Operations.
186 def VADDD : ADbI<0b11100, 0b11, 0, 0,
187 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
188 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
189 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
191 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
192 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
193 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
194 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
195 // Some single precision VFP instructions may be executed on both NEON and
196 // VFP pipelines on A8.
197 let D = VFPNeonA8Domain;
200 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
201 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
202 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
203 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
205 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
206 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
207 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
208 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
209 // Some single precision VFP instructions may be executed on both NEON and
210 // VFP pipelines on A8.
211 let D = VFPNeonA8Domain;
214 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
215 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
216 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
217 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
219 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
220 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
221 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
222 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
224 def VMULD : ADbI<0b11100, 0b10, 0, 0,
225 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
226 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
227 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
229 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
230 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
231 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
232 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
233 // Some single precision VFP instructions may be executed on both NEON and
234 // VFP pipelines on A8.
235 let D = VFPNeonA8Domain;
238 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
239 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
240 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
241 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
243 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
244 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
245 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
246 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
247 // Some single precision VFP instructions may be executed on both NEON and
248 // VFP pipelines on A8.
249 let D = VFPNeonA8Domain;
252 // Match reassociated forms only if not sign dependent rounding.
253 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
254 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
255 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
256 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
258 // These are encoded as unary instructions.
259 let Defs = [FPSCR] in {
260 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
261 (outs), (ins DPR:$Dd, DPR:$Dm),
262 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
263 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
265 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
266 (outs), (ins SPR:$Sd, SPR:$Sm),
267 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
268 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
269 // Some single precision VFP instructions may be executed on both NEON and
270 // VFP pipelines on A8.
271 let D = VFPNeonA8Domain;
274 // FIXME: Verify encoding after integrated assembler is working.
275 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
276 (outs), (ins DPR:$Dd, DPR:$Dm),
277 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
278 [/* For disassembly only; pattern left blank */]>;
280 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
281 (outs), (ins SPR:$Sd, SPR:$Sm),
282 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
283 [/* For disassembly only; pattern left blank */]> {
284 // Some single precision VFP instructions may be executed on both NEON and
285 // VFP pipelines on A8.
286 let D = VFPNeonA8Domain;
290 //===----------------------------------------------------------------------===//
291 // FP Unary Operations.
294 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
295 (outs DPR:$Dd), (ins DPR:$Dm),
296 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
297 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
299 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
300 (outs SPR:$Sd), (ins SPR:$Sm),
301 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
302 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
303 // Some single precision VFP instructions may be executed on both NEON and
304 // VFP pipelines on A8.
305 let D = VFPNeonA8Domain;
308 let Defs = [FPSCR] in {
309 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
310 (outs), (ins DPR:$Dd),
311 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
312 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
313 let Inst{3-0} = 0b0000;
317 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
318 (outs), (ins SPR:$Sd),
319 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
320 [(arm_cmpfp0 SPR:$Sd)]> {
321 let Inst{3-0} = 0b0000;
324 // Some single precision VFP instructions may be executed on both NEON and
325 // VFP pipelines on A8.
326 let D = VFPNeonA8Domain;
329 // FIXME: Verify encoding after integrated assembler is working.
330 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
331 (outs), (ins DPR:$Dd),
332 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
333 [/* For disassembly only; pattern left blank */]> {
334 let Inst{3-0} = 0b0000;
338 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
339 (outs), (ins SPR:$Sd),
340 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
341 [/* For disassembly only; pattern left blank */]> {
342 let Inst{3-0} = 0b0000;
345 // Some single precision VFP instructions may be executed on both NEON and
346 // VFP pipelines on A8.
347 let D = VFPNeonA8Domain;
351 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
352 (outs DPR:$Dd), (ins SPR:$Sm),
353 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
354 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
355 // Instruction operands.
359 // Encode instruction operands.
360 let Inst{3-0} = Sm{4-1};
362 let Inst{15-12} = Dd{3-0};
363 let Inst{22} = Dd{4};
366 // Special case encoding: bits 11-8 is 0b1011.
367 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
368 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
369 [(set SPR:$Sd, (fround DPR:$Dm))]> {
370 // Instruction operands.
374 // Encode instruction operands.
375 let Inst{3-0} = Dm{3-0};
377 let Inst{15-12} = Sd{4-1};
378 let Inst{22} = Sd{0};
380 let Inst{27-23} = 0b11101;
381 let Inst{21-16} = 0b110111;
382 let Inst{11-8} = 0b1011;
383 let Inst{7-6} = 0b11;
387 // Between half-precision and single-precision. For disassembly only.
389 // FIXME: Verify encoding after integrated assembler is working.
390 def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
391 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$dst, $a",
392 [/* For disassembly only; pattern left blank */]>;
394 def : ARMPat<(f32_to_f16 SPR:$a),
395 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
397 def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
398 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$dst, $a",
399 [/* For disassembly only; pattern left blank */]>;
401 def : ARMPat<(f16_to_f32 GPR:$a),
402 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
404 def VCVTTSH: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
405 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$dst, $a",
406 [/* For disassembly only; pattern left blank */]>;
408 def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
409 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$dst, $a",
410 [/* For disassembly only; pattern left blank */]>;
412 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
413 (outs DPR:$Dd), (ins DPR:$Dm),
414 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
415 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
417 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
418 (outs SPR:$Sd), (ins SPR:$Sm),
419 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
420 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
421 // Some single precision VFP instructions may be executed on both NEON and
422 // VFP pipelines on A8.
423 let D = VFPNeonA8Domain;
426 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
427 (outs DPR:$Dd), (ins DPR:$Dm),
428 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
429 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
431 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
432 (outs SPR:$Sd), (ins SPR:$Sm),
433 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
434 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
436 let neverHasSideEffects = 1 in {
437 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
438 (outs DPR:$Dd), (ins DPR:$Dm),
439 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
441 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
442 (outs SPR:$Sd), (ins SPR:$Sm),
443 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
444 } // neverHasSideEffects
446 //===----------------------------------------------------------------------===//
447 // FP <-> GPR Copies. Int <-> FP Conversions.
450 def VMOVRS : AVConv2I<0b11100001, 0b1010,
451 (outs GPR:$Rt), (ins SPR:$Sn),
452 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
453 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
454 // Instruction operands.
458 // Encode instruction operands.
459 let Inst{19-16} = Sn{4-1};
461 let Inst{15-12} = Rt;
463 let Inst{6-5} = 0b00;
464 let Inst{3-0} = 0b0000;
466 // Some single precision VFP instructions may be executed on both NEON and VFP
468 let D = VFPNeonDomain;
471 def VMOVSR : AVConv4I<0b11100000, 0b1010,
472 (outs SPR:$Sn), (ins GPR:$Rt),
473 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
474 [(set SPR:$Sn, (bitconvert GPR:$Rt))]> {
475 // Instruction operands.
479 // Encode instruction operands.
480 let Inst{19-16} = Sn{4-1};
482 let Inst{15-12} = Rt;
484 let Inst{6-5} = 0b00;
485 let Inst{3-0} = 0b0000;
487 // Some single precision VFP instructions may be executed on both NEON and VFP
489 let D = VFPNeonDomain;
492 let neverHasSideEffects = 1 in {
493 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
494 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
495 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
496 [/* FIXME: Can't write pattern for multiple result instr*/]> {
497 // Instruction operands.
502 // Encode instruction operands.
503 let Inst{3-0} = Dm{3-0};
505 let Inst{15-12} = Rt;
506 let Inst{19-16} = Rt2;
508 let Inst{7-6} = 0b00;
510 // Some single precision VFP instructions may be executed on both NEON and VFP
512 let D = VFPNeonDomain;
515 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
516 (outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2),
517 IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
518 [/* For disassembly only; pattern left blank */]> {
519 let Inst{7-6} = 0b00;
521 // Some single precision VFP instructions may be executed on both NEON and VFP
523 let D = VFPNeonDomain;
525 } // neverHasSideEffects
530 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
531 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
532 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
533 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
534 // Instruction operands.
539 // Encode instruction operands.
540 let Inst{3-0} = Dm{3-0};
542 let Inst{15-12} = Rt;
543 let Inst{19-16} = Rt2;
545 let Inst{7-6} = 0b00;
547 // Some single precision VFP instructions may be executed on both NEON and VFP
549 let D = VFPNeonDomain;
552 let neverHasSideEffects = 1 in
553 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
554 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
555 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
556 [/* For disassembly only; pattern left blank */]> {
557 let Inst{7-6} = 0b00;
559 // Some single precision VFP instructions may be executed on both NEON and VFP
561 let D = VFPNeonDomain;
567 // FMRX: SPR system reg -> GPR
569 // FMXR: GPR -> VFP system reg
574 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
575 bits<4> opcod4, dag oops, dag iops,
576 InstrItinClass itin, string opc, string asm,
578 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
580 // Instruction operands.
584 // Encode instruction operands.
585 let Inst{3-0} = Sm{4-1};
587 let Inst{15-12} = Dd{3-0};
588 let Inst{22} = Dd{4};
591 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
592 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
593 string opc, string asm, list<dag> pattern>
594 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
596 // Instruction operands.
600 // Encode instruction operands.
601 let Inst{3-0} = Sm{4-1};
603 let Inst{15-12} = Sd{4-1};
604 let Inst{22} = Sd{0};
607 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
608 (outs DPR:$Dd), (ins SPR:$Sm),
609 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
610 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
611 let Inst{7} = 1; // s32
614 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
615 (outs SPR:$Sd),(ins SPR:$Sm),
616 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
617 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
618 let Inst{7} = 1; // s32
620 // Some single precision VFP instructions may be executed on both NEON and
621 // VFP pipelines on A8.
622 let D = VFPNeonA8Domain;
625 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
626 (outs DPR:$Dd), (ins SPR:$Sm),
627 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
628 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
629 let Inst{7} = 0; // u32
632 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
633 (outs SPR:$Sd), (ins SPR:$Sm),
634 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
635 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
636 let Inst{7} = 0; // u32
638 // Some single precision VFP instructions may be executed on both NEON and
639 // VFP pipelines on A8.
640 let D = VFPNeonA8Domain;
645 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
646 bits<4> opcod4, dag oops, dag iops,
647 InstrItinClass itin, string opc, string asm,
649 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
651 // Instruction operands.
655 // Encode instruction operands.
656 let Inst{3-0} = Dm{3-0};
658 let Inst{15-12} = Sd{4-1};
659 let Inst{22} = Sd{0};
662 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
663 bits<4> opcod4, dag oops, dag iops,
664 InstrItinClass itin, string opc, string asm,
666 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
668 // Instruction operands.
672 // Encode instruction operands.
673 let Inst{3-0} = Sm{4-1};
675 let Inst{15-12} = Sd{4-1};
676 let Inst{22} = Sd{0};
679 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
680 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
681 (outs SPR:$Sd), (ins DPR:$Dm),
682 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
683 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
684 let Inst{7} = 1; // Z bit
687 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
688 (outs SPR:$Sd), (ins SPR:$Sm),
689 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
690 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
691 let Inst{7} = 1; // Z bit
693 // Some single precision VFP instructions may be executed on both NEON and
694 // VFP pipelines on A8.
695 let D = VFPNeonA8Domain;
698 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
699 (outs SPR:$Sd), (ins DPR:$Dm),
700 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
701 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
702 let Inst{7} = 1; // Z bit
705 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
706 (outs SPR:$Sd), (ins SPR:$Sm),
707 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
708 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
709 let Inst{7} = 1; // Z bit
711 // Some single precision VFP instructions may be executed on both NEON and
712 // VFP pipelines on A8.
713 let D = VFPNeonA8Domain;
716 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
717 let Uses = [FPSCR] in {
718 // FIXME: Verify encoding after integrated assembler is working.
719 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
720 (outs SPR:$Sd), (ins DPR:$Dm),
721 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
722 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
723 let Inst{7} = 0; // Z bit
726 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
727 (outs SPR:$Sd), (ins SPR:$Sm),
728 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
729 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
730 let Inst{7} = 0; // Z bit
733 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
734 (outs SPR:$Sd), (ins DPR:$Dm),
735 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
736 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
737 let Inst{7} = 0; // Z bit
740 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
741 (outs SPR:$Sd), (ins SPR:$Sm),
742 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
743 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
744 let Inst{7} = 0; // Z bit
748 // Convert between floating-point and fixed-point
749 // Data type for fixed-point naming convention:
750 // S16 (U=0, sx=0) -> SH
751 // U16 (U=1, sx=0) -> UH
752 // S32 (U=0, sx=1) -> SL
753 // U32 (U=1, sx=1) -> UL
755 // FIXME: Marking these as codegen only seems wrong. They are real
757 let Constraints = "$a = $dst", isCodeGenOnly = 1 in {
759 // FP to Fixed-Point:
761 def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0,
762 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
763 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits",
764 [/* For disassembly only; pattern left blank */]> {
765 // Some single precision VFP instructions may be executed on both NEON and
766 // VFP pipelines on A8.
767 let D = VFPNeonA8Domain;
770 def VTOUHS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 0,
771 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
772 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits",
773 [/* For disassembly only; pattern left blank */]> {
774 // Some single precision VFP instructions may be executed on both NEON and
775 // VFP pipelines on A8.
776 let D = VFPNeonA8Domain;
779 def VTOSLS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 1,
780 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
781 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits",
782 [/* For disassembly only; pattern left blank */]> {
783 // Some single precision VFP instructions may be executed on both NEON and
784 // VFP pipelines on A8.
785 let D = VFPNeonA8Domain;
788 def VTOULS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 1,
789 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
790 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits",
791 [/* For disassembly only; pattern left blank */]> {
792 // Some single precision VFP instructions may be executed on both NEON and
793 // VFP pipelines on A8.
794 let D = VFPNeonA8Domain;
797 def VTOSHD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 0,
798 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
799 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits",
800 [/* For disassembly only; pattern left blank */]>;
802 def VTOUHD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 0,
803 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
804 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits",
805 [/* For disassembly only; pattern left blank */]>;
807 def VTOSLD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 1,
808 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
809 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits",
810 [/* For disassembly only; pattern left blank */]>;
812 def VTOULD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 1,
813 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
814 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits",
815 [/* For disassembly only; pattern left blank */]>;
817 // Fixed-Point to FP:
819 def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0,
820 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
821 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits",
822 [/* For disassembly only; pattern left blank */]> {
823 // Some single precision VFP instructions may be executed on both NEON and
824 // VFP pipelines on A8.
825 let D = VFPNeonA8Domain;
828 def VUHTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 0,
829 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
830 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits",
831 [/* For disassembly only; pattern left blank */]> {
832 // Some single precision VFP instructions may be executed on both NEON and
833 // VFP pipelines on A8.
834 let D = VFPNeonA8Domain;
837 def VSLTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 1,
838 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
839 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits",
840 [/* For disassembly only; pattern left blank */]> {
841 // Some single precision VFP instructions may be executed on both NEON and
842 // VFP pipelines on A8.
843 let D = VFPNeonA8Domain;
846 def VULTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 1,
847 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
848 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits",
849 [/* For disassembly only; pattern left blank */]> {
850 // Some single precision VFP instructions may be executed on both NEON and
851 // VFP pipelines on A8.
852 let D = VFPNeonA8Domain;
855 def VSHTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 0,
856 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
857 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits",
858 [/* For disassembly only; pattern left blank */]>;
860 def VUHTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 0,
861 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
862 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits",
863 [/* For disassembly only; pattern left blank */]>;
865 def VSLTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 1,
866 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
867 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits",
868 [/* For disassembly only; pattern left blank */]>;
870 def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
871 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
872 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits",
873 [/* For disassembly only; pattern left blank */]>;
875 } // End of 'let Constraints = "$a = $dst", isCodeGenOnly = 1 in'
877 //===----------------------------------------------------------------------===//
878 // FP Multiply-Accumulate Operations.
881 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
882 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
883 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
884 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
886 RegConstraint<"$Ddin = $Dd">,
887 Requires<[HasVFP2,UseFPVMLx]>;
889 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
890 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
891 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
892 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
894 RegConstraint<"$Sdin = $Sd">,
895 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
896 // Some single precision VFP instructions may be executed on both NEON and
897 // VFP pipelines on A8.
898 let D = VFPNeonA8Domain;
901 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
902 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
903 Requires<[HasVFP2,UseFPVMLx]>;
904 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
905 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
906 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx]>;
908 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
909 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
910 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
911 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
913 RegConstraint<"$Ddin = $Dd">,
914 Requires<[HasVFP2,UseFPVMLx]>;
916 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
917 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
918 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
919 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
921 RegConstraint<"$Sdin = $Sd">,
922 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
923 // Some single precision VFP instructions may be executed on both NEON and
924 // VFP pipelines on A8.
925 let D = VFPNeonA8Domain;
928 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
929 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
930 Requires<[HasVFP2,UseFPVMLx]>;
931 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
932 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
933 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>;
935 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
936 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
937 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
938 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
940 RegConstraint<"$Ddin = $Dd">,
941 Requires<[HasVFP2,UseFPVMLx]>;
943 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
944 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
945 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
946 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
948 RegConstraint<"$Sdin = $Sd">,
949 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
950 // Some single precision VFP instructions may be executed on both NEON and
951 // VFP pipelines on A8.
952 let D = VFPNeonA8Domain;
955 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
956 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
957 Requires<[HasVFP2,UseFPVMLx]>;
958 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
959 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
960 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>;
962 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
963 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
964 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
965 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
967 RegConstraint<"$Ddin = $Dd">,
968 Requires<[HasVFP2,UseFPVMLx]>;
970 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
971 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
972 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
973 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
974 RegConstraint<"$Sdin = $Sd">,
975 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
976 // Some single precision VFP instructions may be executed on both NEON and
977 // VFP pipelines on A8.
978 let D = VFPNeonA8Domain;
981 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
982 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
983 Requires<[HasVFP2,UseFPVMLx]>;
984 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
985 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
986 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>;
989 //===----------------------------------------------------------------------===//
990 // FP Conditional moves.
993 let neverHasSideEffects = 1 in {
994 def VMOVDcc : ARMPseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, pred:$p),
996 [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
997 RegConstraint<"$Dn = $Dd">;
999 def VMOVScc : ARMPseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, pred:$p),
1001 [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
1002 RegConstraint<"$Sn = $Sd">;
1003 } // neverHasSideEffects
1005 //===----------------------------------------------------------------------===//
1006 // Move from VFP System Register to ARM core register.
1009 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1011 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1013 // Instruction operand.
1016 let Inst{27-20} = 0b11101111;
1017 let Inst{19-16} = opc19_16;
1018 let Inst{15-12} = Rt;
1019 let Inst{11-8} = 0b1010;
1021 let Inst{6-5} = 0b00;
1023 let Inst{3-0} = 0b0000;
1026 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1028 let Defs = [CPSR], Uses = [FPSCR], Rt = 0b1111 /* apsr_nzcv */ in
1029 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
1030 "vmrs", "\tapsr_nzcv, fpscr", [(arm_fmstat)]>;
1032 // Application level FPSCR -> GPR
1033 let hasSideEffects = 1, Uses = [FPSCR] in
1034 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
1035 "vmrs", "\t$Rt, fpscr",
1036 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
1038 // System level FPEXC, FPSID -> GPR
1039 let Uses = [FPSCR] in {
1040 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1041 "vmrs", "\t$Rt, fpexc", []>;
1042 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
1043 "vmrs", "\t$Rt, fpsid", []>;
1046 //===----------------------------------------------------------------------===//
1047 // Move from ARM core register to VFP System Register.
1050 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1052 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1054 // Instruction operand.
1057 // Encode instruction operand.
1058 let Inst{15-12} = src;
1060 let Inst{27-20} = 0b11101110;
1061 let Inst{19-16} = opc19_16;
1062 let Inst{11-8} = 0b1010;
1067 let Defs = [FPSCR] in {
1068 // Application level GPR -> FPSCR
1069 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
1070 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1071 // System level GPR -> FPEXC
1072 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
1073 "vmsr", "\tfpexc, $src", []>;
1074 // System level GPR -> FPSID
1075 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
1076 "vmsr", "\tfpsid, $src", []>;
1079 //===----------------------------------------------------------------------===//
1083 // Materialize FP immediates. VFP3 only.
1084 let isReMaterializable = 1 in {
1085 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1086 VFPMiscFrm, IIC_fpUNA64,
1087 "vmov", ".f64\t$Dd, $imm",
1088 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
1089 // Instruction operands.
1093 // Encode instruction operands.
1094 let Inst{15-12} = Dd{3-0};
1095 let Inst{22} = Dd{4};
1096 let Inst{19} = imm{31}; // The immediate is handled as a float.
1097 let Inst{18-16} = imm{25-23};
1098 let Inst{3-0} = imm{22-19};
1100 // Encode remaining instruction bits.
1101 let Inst{27-23} = 0b11101;
1102 let Inst{21-20} = 0b11;
1103 let Inst{11-9} = 0b101;
1104 let Inst{8} = 1; // Double precision.
1105 let Inst{7-4} = 0b0000;
1108 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1109 VFPMiscFrm, IIC_fpUNA32,
1110 "vmov", ".f32\t$Sd, $imm",
1111 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1112 // Instruction operands.
1116 // Encode instruction operands.
1117 let Inst{15-12} = Sd{4-1};
1118 let Inst{22} = Sd{0};
1119 let Inst{19} = imm{31}; // The immediate is handled as a float.
1120 let Inst{18-16} = imm{25-23};
1121 let Inst{3-0} = imm{22-19};
1123 // Encode remaining instruction bits.
1124 let Inst{27-23} = 0b11101;
1125 let Inst{21-20} = 0b11;
1126 let Inst{11-9} = 0b101;
1127 let Inst{8} = 0; // Single precision.
1128 let Inst{7-4} = 0b0000;