1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops rGPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant
53 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>,
56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
59 // t2_so_imm_not - Match an immediate that is a complement
61 def t2_so_imm_not : Operand<i32>,
63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
64 }], t2_so_imm_not_XFORM>;
66 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
67 def t2_so_imm_neg : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
70 }], t2_so_imm_neg_XFORM>;
72 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
73 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
74 // to get the first/second pieces.
75 def t2_so_imm2part : Operand<i32>,
77 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
81 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
82 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
83 return CurDAG->getTargetConstant(V, MVT::i32);
86 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
87 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
88 return CurDAG->getTargetConstant(V, MVT::i32);
91 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
92 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
96 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
97 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
98 return CurDAG->getTargetConstant(V, MVT::i32);
101 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
102 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
103 return CurDAG->getTargetConstant(V, MVT::i32);
106 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
107 def imm1_31 : PatLeaf<(i32 imm), [{
108 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
111 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
112 def imm0_4095 : Operand<i32>,
113 PatLeaf<(i32 imm), [{
114 return (uint32_t)N->getZExtValue() < 4096;
117 def imm0_4095_neg : PatLeaf<(i32 imm), [{
118 return (uint32_t)(-N->getZExtValue()) < 4096;
121 def imm0_255_neg : PatLeaf<(i32 imm), [{
122 return (uint32_t)(-N->getZExtValue()) < 255;
125 def imm0_255_not : PatLeaf<(i32 imm), [{
126 return (uint32_t)(~N->getZExtValue()) < 255;
129 // Define Thumb2 specific addressing modes.
131 // t2addrmode_imm12 := reg + imm12
132 def t2addrmode_imm12 : Operand<i32>,
133 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
134 let PrintMethod = "printT2AddrModeImm12Operand";
135 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
138 // t2addrmode_imm8 := reg +/- imm8
139 def t2addrmode_imm8 : Operand<i32>,
140 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
141 let PrintMethod = "printT2AddrModeImm8Operand";
142 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
145 def t2am_imm8_offset : Operand<i32>,
146 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
147 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
150 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
151 def t2addrmode_imm8s4 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
153 let PrintMethod = "printT2AddrModeImm8s4Operand";
154 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
157 def t2am_imm8s4_offset : Operand<i32> {
158 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
161 // t2addrmode_so_reg := reg + (reg << imm2)
162 def t2addrmode_so_reg : Operand<i32>,
163 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
164 let PrintMethod = "printT2AddrModeSoRegOperand";
165 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
169 //===----------------------------------------------------------------------===//
170 // Multiclass helpers...
173 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
174 /// unary operation that produces a value. These are predicable and can be
175 /// changed to modify CPSR.
176 multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode,
177 bit Cheap = 0, bit ReMat = 0> {
179 def i : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
181 [(set rGPR:$dst, (opnode t2_so_imm:$src))]> {
182 let isAsCheapAsAMove = Cheap;
183 let isReMaterializable = ReMat;
184 let Inst{31-27} = 0b11110;
186 let Inst{24-21} = opcod;
187 let Inst{20} = ?; // The S bit.
188 let Inst{19-16} = 0b1111; // Rn
192 def r : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVr,
193 opc, ".w\t$dst, $src",
194 [(set rGPR:$dst, (opnode rGPR:$src))]> {
195 let Inst{31-27} = 0b11101;
196 let Inst{26-25} = 0b01;
197 let Inst{24-21} = opcod;
198 let Inst{20} = ?; // The S bit.
199 let Inst{19-16} = 0b1111; // Rn
200 let Inst{14-12} = 0b000; // imm3
201 let Inst{7-6} = 0b00; // imm2
202 let Inst{5-4} = 0b00; // type
205 def s : T2sI<(outs rGPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
206 opc, ".w\t$dst, $src",
207 [(set rGPR:$dst, (opnode t2_so_reg:$src))]> {
208 let Inst{31-27} = 0b11101;
209 let Inst{26-25} = 0b01;
210 let Inst{24-21} = opcod;
211 let Inst{20} = ?; // The S bit.
212 let Inst{19-16} = 0b1111; // Rn
216 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
217 /// binary operation that produces a value. These are predicable and can be
218 /// changed to modify CPSR.
219 multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
220 bit Commutable = 0, string wide =""> {
222 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
223 opc, "\t$dst, $lhs, $rhs",
224 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> {
225 let Inst{31-27} = 0b11110;
227 let Inst{24-21} = opcod;
228 let Inst{20} = ?; // The S bit.
232 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
233 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
234 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
235 let isCommutable = Commutable;
236 let Inst{31-27} = 0b11101;
237 let Inst{26-25} = 0b01;
238 let Inst{24-21} = opcod;
239 let Inst{20} = ?; // The S bit.
240 let Inst{14-12} = 0b000; // imm3
241 let Inst{7-6} = 0b00; // imm2
242 let Inst{5-4} = 0b00; // type
245 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
246 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
247 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> {
248 let Inst{31-27} = 0b11101;
249 let Inst{26-25} = 0b01;
250 let Inst{24-21} = opcod;
251 let Inst{20} = ?; // The S bit.
255 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
256 // the ".w" prefix to indicate that they are wide.
257 multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
258 bit Commutable = 0> :
259 T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
261 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
262 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
263 /// it is equivalent to the T2I_bin_irs counterpart.
264 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
266 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
267 opc, ".w\t$dst, $rhs, $lhs",
268 [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> {
269 let Inst{31-27} = 0b11110;
271 let Inst{24-21} = opcod;
272 let Inst{20} = ?; // The S bit.
276 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, rGPR:$lhs), IIC_iALUr,
277 opc, "\t$dst, $rhs, $lhs",
278 [/* For disassembly only; pattern left blank */]> {
279 let Inst{31-27} = 0b11101;
280 let Inst{26-25} = 0b01;
281 let Inst{24-21} = opcod;
282 let Inst{20} = ?; // The S bit.
283 let Inst{14-12} = 0b000; // imm3
284 let Inst{7-6} = 0b00; // imm2
285 let Inst{5-4} = 0b00; // type
288 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
289 opc, "\t$dst, $rhs, $lhs",
290 [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> {
291 let Inst{31-27} = 0b11101;
292 let Inst{26-25} = 0b01;
293 let Inst{24-21} = opcod;
294 let Inst{20} = ?; // The S bit.
298 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
299 /// instruction modifies the CPSR register.
300 let Defs = [CPSR] in {
301 multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
302 bit Commutable = 0> {
304 def ri : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
305 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
306 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
307 let Inst{31-27} = 0b11110;
309 let Inst{24-21} = opcod;
310 let Inst{20} = 1; // The S bit.
314 def rr : T2I<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr,
315 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
316 [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> {
317 let isCommutable = Commutable;
318 let Inst{31-27} = 0b11101;
319 let Inst{26-25} = 0b01;
320 let Inst{24-21} = opcod;
321 let Inst{20} = 1; // The S bit.
322 let Inst{14-12} = 0b000; // imm3
323 let Inst{7-6} = 0b00; // imm2
324 let Inst{5-4} = 0b00; // type
327 def rs : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
328 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
329 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
330 let Inst{31-27} = 0b11101;
331 let Inst{26-25} = 0b01;
332 let Inst{24-21} = opcod;
333 let Inst{20} = 1; // The S bit.
338 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
339 /// patterns for a binary operation that produces a value.
340 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
341 bit Commutable = 0> {
343 def ri : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
344 opc, ".w\t$dst, $lhs, $rhs",
345 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
346 let Inst{31-27} = 0b11110;
349 let Inst{23-21} = op23_21;
350 let Inst{20} = 0; // The S bit.
354 def ri12 : T2I<(outs rGPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
355 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
356 [(set rGPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
357 let Inst{31-27} = 0b11110;
360 let Inst{23-21} = op23_21;
361 let Inst{20} = 0; // The S bit.
365 def rr : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr,
366 opc, ".w\t$dst, $lhs, $rhs",
367 [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> {
368 let isCommutable = Commutable;
369 let Inst{31-27} = 0b11101;
370 let Inst{26-25} = 0b01;
372 let Inst{23-21} = op23_21;
373 let Inst{20} = 0; // The S bit.
374 let Inst{14-12} = 0b000; // imm3
375 let Inst{7-6} = 0b00; // imm2
376 let Inst{5-4} = 0b00; // type
379 def rs : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
380 opc, ".w\t$dst, $lhs, $rhs",
381 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
382 let Inst{31-27} = 0b11101;
383 let Inst{26-25} = 0b01;
385 let Inst{23-21} = op23_21;
386 let Inst{20} = 0; // The S bit.
390 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
391 /// for a binary operation that produces a value and use the carry
392 /// bit. It's not predicable.
393 let Uses = [CPSR] in {
394 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
395 bit Commutable = 0> {
397 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
398 opc, "\t$dst, $lhs, $rhs",
399 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>,
400 Requires<[IsThumb2]> {
401 let Inst{31-27} = 0b11110;
403 let Inst{24-21} = opcod;
404 let Inst{20} = 0; // The S bit.
408 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
409 opc, ".w\t$dst, $lhs, $rhs",
410 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>,
411 Requires<[IsThumb2]> {
412 let isCommutable = Commutable;
413 let Inst{31-27} = 0b11101;
414 let Inst{26-25} = 0b01;
415 let Inst{24-21} = opcod;
416 let Inst{20} = 0; // The S bit.
417 let Inst{14-12} = 0b000; // imm3
418 let Inst{7-6} = 0b00; // imm2
419 let Inst{5-4} = 0b00; // type
422 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
423 opc, ".w\t$dst, $lhs, $rhs",
424 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>,
425 Requires<[IsThumb2]> {
426 let Inst{31-27} = 0b11101;
427 let Inst{26-25} = 0b01;
428 let Inst{24-21} = opcod;
429 let Inst{20} = 0; // The S bit.
433 // Carry setting variants
434 let Defs = [CPSR] in {
435 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
436 bit Commutable = 0> {
438 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
439 opc, "\t$dst, $lhs, $rhs",
440 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>,
441 Requires<[IsThumb2]> {
442 let Inst{31-27} = 0b11110;
444 let Inst{24-21} = opcod;
445 let Inst{20} = 1; // The S bit.
449 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
450 opc, ".w\t$dst, $lhs, $rhs",
451 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>,
452 Requires<[IsThumb2]> {
453 let isCommutable = Commutable;
454 let Inst{31-27} = 0b11101;
455 let Inst{26-25} = 0b01;
456 let Inst{24-21} = opcod;
457 let Inst{20} = 1; // The S bit.
458 let Inst{14-12} = 0b000; // imm3
459 let Inst{7-6} = 0b00; // imm2
460 let Inst{5-4} = 0b00; // type
463 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
464 opc, ".w\t$dst, $lhs, $rhs",
465 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>,
466 Requires<[IsThumb2]> {
467 let Inst{31-27} = 0b11101;
468 let Inst{26-25} = 0b01;
469 let Inst{24-21} = opcod;
470 let Inst{20} = 1; // The S bit.
476 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
477 /// version is not needed since this is only for codegen.
478 let Defs = [CPSR] in {
479 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
481 def ri : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
482 !strconcat(opc, "s"), ".w\t$dst, $rhs, $lhs",
483 [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> {
484 let Inst{31-27} = 0b11110;
486 let Inst{24-21} = opcod;
487 let Inst{20} = 1; // The S bit.
491 def rs : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
492 !strconcat(opc, "s"), "\t$dst, $rhs, $lhs",
493 [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> {
494 let Inst{31-27} = 0b11101;
495 let Inst{26-25} = 0b01;
496 let Inst{24-21} = opcod;
497 let Inst{20} = 1; // The S bit.
502 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
503 // rotate operation that produces a value.
504 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
506 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
507 opc, ".w\t$dst, $lhs, $rhs",
508 [(set rGPR:$dst, (opnode rGPR:$lhs, imm1_31:$rhs))]> {
509 let Inst{31-27} = 0b11101;
510 let Inst{26-21} = 0b010010;
511 let Inst{19-16} = 0b1111; // Rn
512 let Inst{5-4} = opcod;
515 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iMOVsr,
516 opc, ".w\t$dst, $lhs, $rhs",
517 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
518 let Inst{31-27} = 0b11111;
519 let Inst{26-23} = 0b0100;
520 let Inst{22-21} = opcod;
521 let Inst{15-12} = 0b1111;
522 let Inst{7-4} = 0b0000;
526 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
527 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
528 /// a explicit result, only implicitly set CPSR.
529 let Defs = [CPSR] in {
530 multiclass T2I_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
532 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
533 opc, ".w\t$lhs, $rhs",
534 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> {
535 let Inst{31-27} = 0b11110;
537 let Inst{24-21} = opcod;
538 let Inst{20} = 1; // The S bit.
540 let Inst{11-8} = 0b1111; // Rd
543 def rr : T2I<(outs), (ins GPR:$lhs, rGPR:$rhs), IIC_iCMPr,
544 opc, ".w\t$lhs, $rhs",
545 [(opnode GPR:$lhs, rGPR:$rhs)]> {
546 let Inst{31-27} = 0b11101;
547 let Inst{26-25} = 0b01;
548 let Inst{24-21} = opcod;
549 let Inst{20} = 1; // The S bit.
550 let Inst{14-12} = 0b000; // imm3
551 let Inst{11-8} = 0b1111; // Rd
552 let Inst{7-6} = 0b00; // imm2
553 let Inst{5-4} = 0b00; // type
556 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
557 opc, ".w\t$lhs, $rhs",
558 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> {
559 let Inst{31-27} = 0b11101;
560 let Inst{26-25} = 0b01;
561 let Inst{24-21} = opcod;
562 let Inst{20} = 1; // The S bit.
563 let Inst{11-8} = 0b1111; // Rd
568 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
569 multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> {
570 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
571 opc, ".w\t$dst, $addr",
572 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
573 let Inst{31-27} = 0b11111;
574 let Inst{26-25} = 0b00;
575 let Inst{24} = signed;
577 let Inst{22-21} = opcod;
578 let Inst{20} = 1; // load
580 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
581 opc, "\t$dst, $addr",
582 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
583 let Inst{31-27} = 0b11111;
584 let Inst{26-25} = 0b00;
585 let Inst{24} = signed;
587 let Inst{22-21} = opcod;
588 let Inst{20} = 1; // load
590 // Offset: index==TRUE, wback==FALSE
591 let Inst{10} = 1; // The P bit.
592 let Inst{8} = 0; // The W bit.
594 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
595 opc, ".w\t$dst, $addr",
596 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
597 let Inst{31-27} = 0b11111;
598 let Inst{26-25} = 0b00;
599 let Inst{24} = signed;
601 let Inst{22-21} = opcod;
602 let Inst{20} = 1; // load
603 let Inst{11-6} = 0b000000;
605 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
606 opc, ".w\t$dst, $addr",
607 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
608 let isReMaterializable = 1;
609 let Inst{31-27} = 0b11111;
610 let Inst{26-25} = 0b00;
611 let Inst{24} = signed;
612 let Inst{23} = ?; // add = (U == '1')
613 let Inst{22-21} = opcod;
614 let Inst{20} = 1; // load
615 let Inst{19-16} = 0b1111; // Rn
619 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
620 multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> {
621 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
622 opc, ".w\t$src, $addr",
623 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
624 let Inst{31-27} = 0b11111;
625 let Inst{26-23} = 0b0001;
626 let Inst{22-21} = opcod;
627 let Inst{20} = 0; // !load
629 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
630 opc, "\t$src, $addr",
631 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
632 let Inst{31-27} = 0b11111;
633 let Inst{26-23} = 0b0000;
634 let Inst{22-21} = opcod;
635 let Inst{20} = 0; // !load
637 // Offset: index==TRUE, wback==FALSE
638 let Inst{10} = 1; // The P bit.
639 let Inst{8} = 0; // The W bit.
641 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
642 opc, ".w\t$src, $addr",
643 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
644 let Inst{31-27} = 0b11111;
645 let Inst{26-23} = 0b0000;
646 let Inst{22-21} = opcod;
647 let Inst{20} = 0; // !load
648 let Inst{11-6} = 0b000000;
652 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
653 /// register and one whose operand is a register rotated by 8/16/24.
654 multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
655 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
656 opc, ".w\t$dst, $src",
657 [(set rGPR:$dst, (opnode rGPR:$src))]> {
658 let Inst{31-27} = 0b11111;
659 let Inst{26-23} = 0b0100;
660 let Inst{22-20} = opcod;
661 let Inst{19-16} = 0b1111; // Rn
662 let Inst{15-12} = 0b1111;
664 let Inst{5-4} = 0b00; // rotate
666 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
667 opc, ".w\t$dst, $src, ror $rot",
668 [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]> {
669 let Inst{31-27} = 0b11111;
670 let Inst{26-23} = 0b0100;
671 let Inst{22-20} = opcod;
672 let Inst{19-16} = 0b1111; // Rn
673 let Inst{15-12} = 0b1111;
675 let Inst{5-4} = {?,?}; // rotate
679 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
680 multiclass T2I_unary_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
681 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
683 [(set rGPR:$dst, (opnode rGPR:$src))]>,
684 Requires<[HasT2ExtractPack]> {
685 let Inst{31-27} = 0b11111;
686 let Inst{26-23} = 0b0100;
687 let Inst{22-20} = opcod;
688 let Inst{19-16} = 0b1111; // Rn
689 let Inst{15-12} = 0b1111;
691 let Inst{5-4} = 0b00; // rotate
693 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
694 opc, "\t$dst, $src, ror $rot",
695 [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]>,
696 Requires<[HasT2ExtractPack]> {
697 let Inst{31-27} = 0b11111;
698 let Inst{26-23} = 0b0100;
699 let Inst{22-20} = opcod;
700 let Inst{19-16} = 0b1111; // Rn
701 let Inst{15-12} = 0b1111;
703 let Inst{5-4} = {?,?}; // rotate
707 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
709 multiclass T2I_unary_rrot_sxtb16<bits<3> opcod, string opc> {
710 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
711 opc, "\t$dst, $src", []> {
712 let Inst{31-27} = 0b11111;
713 let Inst{26-23} = 0b0100;
714 let Inst{22-20} = opcod;
715 let Inst{19-16} = 0b1111; // Rn
716 let Inst{15-12} = 0b1111;
718 let Inst{5-4} = 0b00; // rotate
720 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
721 opc, "\t$dst, $src, ror $rot", []> {
722 let Inst{31-27} = 0b11111;
723 let Inst{26-23} = 0b0100;
724 let Inst{22-20} = opcod;
725 let Inst{19-16} = 0b1111; // Rn
726 let Inst{15-12} = 0b1111;
728 let Inst{5-4} = {?,?}; // rotate
732 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
733 /// register and one whose operand is a register rotated by 8/16/24.
734 multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
735 def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iALUr,
736 opc, "\t$dst, $LHS, $RHS",
737 [(set rGPR:$dst, (opnode rGPR:$LHS, rGPR:$RHS))]>,
738 Requires<[HasT2ExtractPack]> {
739 let Inst{31-27} = 0b11111;
740 let Inst{26-23} = 0b0100;
741 let Inst{22-20} = opcod;
742 let Inst{15-12} = 0b1111;
744 let Inst{5-4} = 0b00; // rotate
746 def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot),
747 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
748 [(set rGPR:$dst, (opnode rGPR:$LHS,
749 (rotr rGPR:$RHS, rot_imm:$rot)))]>,
750 Requires<[HasT2ExtractPack]> {
751 let Inst{31-27} = 0b11111;
752 let Inst{26-23} = 0b0100;
753 let Inst{22-20} = opcod;
754 let Inst{15-12} = 0b1111;
756 let Inst{5-4} = {?,?}; // rotate
760 // DO variant - disassembly only, no pattern
762 multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> {
763 def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iALUr,
764 opc, "\t$dst, $LHS, $RHS", []> {
765 let Inst{31-27} = 0b11111;
766 let Inst{26-23} = 0b0100;
767 let Inst{22-20} = opcod;
768 let Inst{15-12} = 0b1111;
770 let Inst{5-4} = 0b00; // rotate
772 def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot),
773 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> {
774 let Inst{31-27} = 0b11111;
775 let Inst{26-23} = 0b0100;
776 let Inst{22-20} = opcod;
777 let Inst{15-12} = 0b1111;
779 let Inst{5-4} = {?,?}; // rotate
783 //===----------------------------------------------------------------------===//
785 //===----------------------------------------------------------------------===//
787 //===----------------------------------------------------------------------===//
788 // Miscellaneous Instructions.
791 // LEApcrel - Load a pc-relative address into a register without offending the
793 let neverHasSideEffects = 1 in {
794 let isReMaterializable = 1 in
795 def t2LEApcrel : T2XI<(outs rGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
796 "adr${p}.w\t$dst, #$label", []> {
797 let Inst{31-27} = 0b11110;
798 let Inst{25-24} = 0b10;
799 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
802 let Inst{19-16} = 0b1111; // Rn
805 } // neverHasSideEffects
806 def t2LEApcrelJT : T2XI<(outs rGPR:$dst),
807 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
808 "adr${p}.w\t$dst, #${label}_${id}", []> {
809 let Inst{31-27} = 0b11110;
810 let Inst{25-24} = 0b10;
811 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
814 let Inst{19-16} = 0b1111; // Rn
818 // ADD r, sp, {so_imm|i12}
819 def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
820 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> {
821 let Inst{31-27} = 0b11110;
823 let Inst{24-21} = 0b1000;
824 let Inst{20} = ?; // The S bit.
825 let Inst{19-16} = 0b1101; // Rn = sp
828 def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
829 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> {
830 let Inst{31-27} = 0b11110;
832 let Inst{24-21} = 0b0000;
833 let Inst{20} = 0; // The S bit.
834 let Inst{19-16} = 0b1101; // Rn = sp
839 def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
840 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> {
841 let Inst{31-27} = 0b11101;
842 let Inst{26-25} = 0b01;
843 let Inst{24-21} = 0b1000;
844 let Inst{20} = ?; // The S bit.
845 let Inst{19-16} = 0b1101; // Rn = sp
849 // SUB r, sp, {so_imm|i12}
850 def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
851 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> {
852 let Inst{31-27} = 0b11110;
854 let Inst{24-21} = 0b1101;
855 let Inst{20} = ?; // The S bit.
856 let Inst{19-16} = 0b1101; // Rn = sp
859 def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
860 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> {
861 let Inst{31-27} = 0b11110;
863 let Inst{24-21} = 0b0101;
864 let Inst{20} = 0; // The S bit.
865 let Inst{19-16} = 0b1101; // Rn = sp
870 def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
872 "sub", "\t$dst, $sp, $rhs", []> {
873 let Inst{31-27} = 0b11101;
874 let Inst{26-25} = 0b01;
875 let Inst{24-21} = 0b1101;
876 let Inst{20} = ?; // The S bit.
877 let Inst{19-16} = 0b1101; // Rn = sp
881 // Signed and unsigned division on v7-M
882 def t2SDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
883 "sdiv", "\t$dst, $a, $b",
884 [(set rGPR:$dst, (sdiv rGPR:$a, rGPR:$b))]>,
885 Requires<[HasDivide]> {
886 let Inst{31-27} = 0b11111;
887 let Inst{26-21} = 0b011100;
889 let Inst{15-12} = 0b1111;
890 let Inst{7-4} = 0b1111;
893 def t2UDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
894 "udiv", "\t$dst, $a, $b",
895 [(set rGPR:$dst, (udiv rGPR:$a, rGPR:$b))]>,
896 Requires<[HasDivide]> {
897 let Inst{31-27} = 0b11111;
898 let Inst{26-21} = 0b011101;
900 let Inst{15-12} = 0b1111;
901 let Inst{7-4} = 0b1111;
904 //===----------------------------------------------------------------------===//
905 // Load / store Instructions.
909 let canFoldAsLoad = 1, isReMaterializable = 1 in
910 defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>;
912 // Loads with zero extension
913 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
914 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
916 // Loads with sign extension
917 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
918 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
920 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
922 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
923 (ins t2addrmode_imm8s4:$addr),
924 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
925 def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
926 (ins i32imm:$addr), IIC_iLoadi,
927 "ldrd", "\t$dst1, $addr", []> {
928 let Inst{19-16} = 0b1111; // Rn
930 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
932 // zextload i1 -> zextload i8
933 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
934 (t2LDRBi12 t2addrmode_imm12:$addr)>;
935 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
936 (t2LDRBi8 t2addrmode_imm8:$addr)>;
937 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
938 (t2LDRBs t2addrmode_so_reg:$addr)>;
939 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
940 (t2LDRBpci tconstpool:$addr)>;
942 // extload -> zextload
943 // FIXME: Reduce the number of patterns by legalizing extload to zextload
945 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
946 (t2LDRBi12 t2addrmode_imm12:$addr)>;
947 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
948 (t2LDRBi8 t2addrmode_imm8:$addr)>;
949 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
950 (t2LDRBs t2addrmode_so_reg:$addr)>;
951 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
952 (t2LDRBpci tconstpool:$addr)>;
954 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
955 (t2LDRBi12 t2addrmode_imm12:$addr)>;
956 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
957 (t2LDRBi8 t2addrmode_imm8:$addr)>;
958 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
959 (t2LDRBs t2addrmode_so_reg:$addr)>;
960 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
961 (t2LDRBpci tconstpool:$addr)>;
963 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
964 (t2LDRHi12 t2addrmode_imm12:$addr)>;
965 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
966 (t2LDRHi8 t2addrmode_imm8:$addr)>;
967 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
968 (t2LDRHs t2addrmode_so_reg:$addr)>;
969 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
970 (t2LDRHpci tconstpool:$addr)>;
972 // FIXME: The destination register of the loads and stores can't be PC, but
973 // can be SP. We need another regclass (similar to rGPR) to represent
974 // that. Not a pressing issue since these are selected manually,
978 let mayLoad = 1, neverHasSideEffects = 1 in {
979 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
980 (ins t2addrmode_imm8:$addr),
981 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
982 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
985 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb),
986 (ins GPR:$base, t2am_imm8_offset:$offset),
987 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
988 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
991 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
992 (ins t2addrmode_imm8:$addr),
993 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
994 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
996 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
997 (ins GPR:$base, t2am_imm8_offset:$offset),
998 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
999 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
1002 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1003 (ins t2addrmode_imm8:$addr),
1004 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1005 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
1007 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1008 (ins GPR:$base, t2am_imm8_offset:$offset),
1009 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1010 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
1013 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1014 (ins t2addrmode_imm8:$addr),
1015 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1016 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
1018 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1019 (ins GPR:$base, t2am_imm8_offset:$offset),
1020 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1021 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
1024 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1025 (ins t2addrmode_imm8:$addr),
1026 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1027 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
1029 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1030 (ins GPR:$base, t2am_imm8_offset:$offset),
1031 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1032 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
1034 } // mayLoad = 1, neverHasSideEffects = 1
1036 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1037 // for disassembly only.
1038 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1039 class T2IldT<bit signed, bits<2> type, string opc>
1040 : T2Ii8<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, opc,
1041 "\t$dst, $addr", []> {
1042 let Inst{31-27} = 0b11111;
1043 let Inst{26-25} = 0b00;
1044 let Inst{24} = signed;
1046 let Inst{22-21} = type;
1047 let Inst{20} = 1; // load
1049 let Inst{10-8} = 0b110; // PUW.
1052 def t2LDRT : T2IldT<0, 0b10, "ldrt">;
1053 def t2LDRBT : T2IldT<0, 0b00, "ldrbt">;
1054 def t2LDRHT : T2IldT<0, 0b01, "ldrht">;
1055 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt">;
1056 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht">;
1059 defm t2STR :T2I_st<0b10,"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
1060 defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1061 defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1064 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1065 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1066 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
1067 IIC_iStorer, "strd", "\t$src1, $addr", []>;
1070 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1071 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1072 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1073 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1075 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1077 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1078 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1079 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1080 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1082 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1084 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1085 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1086 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1087 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1089 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1091 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1092 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1093 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1094 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1096 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1098 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1099 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1100 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1101 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1103 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1105 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1106 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1107 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1108 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1110 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1112 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1114 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1115 class T2IstT<bits<2> type, string opc>
1116 : T2Ii8<(outs GPR:$src), (ins t2addrmode_imm8:$addr), IIC_iStorei, opc,
1117 "\t$src, $addr", []> {
1118 let Inst{31-27} = 0b11111;
1119 let Inst{26-25} = 0b00;
1120 let Inst{24} = 0; // not signed
1122 let Inst{22-21} = type;
1123 let Inst{20} = 0; // store
1125 let Inst{10-8} = 0b110; // PUW
1128 def t2STRT : T2IstT<0b10, "strt">;
1129 def t2STRBT : T2IstT<0b00, "strbt">;
1130 def t2STRHT : T2IstT<0b01, "strht">;
1132 // ldrd / strd pre / post variants
1133 // For disassembly only.
1135 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1136 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1137 "ldrd", "\t$dst1, $dst2, [$base, $imm]!", []>;
1139 def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1140 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1141 "ldrd", "\t$dst1, $dst2, [$base], $imm", []>;
1143 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
1144 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1145 NoItinerary, "strd", "\t$src1, $src2, [$base, $imm]!", []>;
1147 def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1148 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1149 NoItinerary, "strd", "\t$src1, $src2, [$base], $imm", []>;
1151 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1152 // data/instruction access. These are for disassembly only.
1154 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
1155 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
1156 multiclass T2Ipl<bit instr, bit write, string opc> {
1158 def i12 : T2I<(outs), (ins GPR:$base, i32imm:$imm), IIC_iLoadi, opc,
1159 "\t[$base, $imm]", []> {
1160 let Inst{31-25} = 0b1111100;
1161 let Inst{24} = instr;
1162 let Inst{23} = 1; // U = 1
1164 let Inst{21} = write;
1166 let Inst{15-12} = 0b1111;
1169 def i8 : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1170 "\t[$base, $imm]", []> {
1171 let Inst{31-25} = 0b1111100;
1172 let Inst{24} = instr;
1173 let Inst{23} = 0; // U = 0
1175 let Inst{21} = write;
1177 let Inst{15-12} = 0b1111;
1178 let Inst{11-8} = 0b1100;
1181 def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1182 "\t[pc, $imm]", []> {
1183 let Inst{31-25} = 0b1111100;
1184 let Inst{24} = instr;
1185 let Inst{23} = ?; // add = (U == 1)
1187 let Inst{21} = write;
1189 let Inst{19-16} = 0b1111; // Rn = 0b1111
1190 let Inst{15-12} = 0b1111;
1193 def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoadi, opc,
1194 "\t[$base, $a]", []> {
1195 let Inst{31-25} = 0b1111100;
1196 let Inst{24} = instr;
1197 let Inst{23} = 0; // add = TRUE for T1
1199 let Inst{21} = write;
1201 let Inst{15-12} = 0b1111;
1202 let Inst{11-6} = 0000000;
1203 let Inst{5-4} = 0b00; // no shift is applied
1206 def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoadi, opc,
1207 "\t[$base, $a, lsl $shamt]", []> {
1208 let Inst{31-25} = 0b1111100;
1209 let Inst{24} = instr;
1210 let Inst{23} = 0; // add = TRUE for T1
1212 let Inst{21} = write;
1214 let Inst{15-12} = 0b1111;
1215 let Inst{11-6} = 0000000;
1219 defm t2PLD : T2Ipl<0, 0, "pld">;
1220 defm t2PLDW : T2Ipl<0, 1, "pldw">;
1221 defm t2PLI : T2Ipl<1, 0, "pli">;
1223 //===----------------------------------------------------------------------===//
1224 // Load / store multiple Instructions.
1227 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1228 def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1229 reglist:$dsts, variable_ops), IIC_iLoadm,
1230 "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> {
1231 let Inst{31-27} = 0b11101;
1232 let Inst{26-25} = 0b00;
1233 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1235 let Inst{21} = 0; // The W bit.
1236 let Inst{20} = 1; // Load
1239 def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1240 reglist:$dsts, variable_ops), IIC_iLoadm,
1241 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
1242 "$addr.addr = $wb", []> {
1243 let Inst{31-27} = 0b11101;
1244 let Inst{26-25} = 0b00;
1245 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1247 let Inst{21} = 1; // The W bit.
1248 let Inst{20} = 1; // Load
1250 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1252 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1253 def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1254 reglist:$srcs, variable_ops), IIC_iStorem,
1255 "stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> {
1256 let Inst{31-27} = 0b11101;
1257 let Inst{26-25} = 0b00;
1258 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1260 let Inst{21} = 0; // The W bit.
1261 let Inst{20} = 0; // Store
1264 def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1265 reglist:$srcs, variable_ops),
1267 "stm${addr:submode}${p}${addr:wide}\t$addr!, $srcs",
1268 "$addr.addr = $wb", []> {
1269 let Inst{31-27} = 0b11101;
1270 let Inst{26-25} = 0b00;
1271 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1273 let Inst{21} = 1; // The W bit.
1274 let Inst{20} = 0; // Store
1276 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1278 //===----------------------------------------------------------------------===//
1279 // Move Instructions.
1282 let neverHasSideEffects = 1 in
1283 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
1284 "mov", ".w\t$dst, $src", []> {
1285 let Inst{31-27} = 0b11101;
1286 let Inst{26-25} = 0b01;
1287 let Inst{24-21} = 0b0010;
1288 let Inst{20} = ?; // The S bit.
1289 let Inst{19-16} = 0b1111; // Rn
1290 let Inst{14-12} = 0b000;
1291 let Inst{7-4} = 0b0000;
1294 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1295 let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
1296 def t2MOVi : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
1297 "mov", ".w\t$dst, $src",
1298 [(set rGPR:$dst, t2_so_imm:$src)]> {
1299 let Inst{31-27} = 0b11110;
1301 let Inst{24-21} = 0b0010;
1302 let Inst{20} = ?; // The S bit.
1303 let Inst{19-16} = 0b1111; // Rn
1307 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1308 def t2MOVi16 : T2I<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1309 "movw", "\t$dst, $src",
1310 [(set rGPR:$dst, imm0_65535:$src)]> {
1311 let Inst{31-27} = 0b11110;
1313 let Inst{24-21} = 0b0010;
1314 let Inst{20} = 0; // The S bit.
1318 let Constraints = "$src = $dst" in
1319 def t2MOVTi16 : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$imm), IIC_iMOVi,
1320 "movt", "\t$dst, $imm",
1322 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1323 let Inst{31-27} = 0b11110;
1325 let Inst{24-21} = 0b0110;
1326 let Inst{20} = 0; // The S bit.
1330 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1332 //===----------------------------------------------------------------------===//
1333 // Extend Instructions.
1338 defm t2SXTB : T2I_unary_rrot<0b100, "sxtb",
1339 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1340 defm t2SXTH : T2I_unary_rrot<0b000, "sxth",
1341 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1342 defm t2SXTB16 : T2I_unary_rrot_sxtb16<0b010, "sxtb16">;
1344 defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab",
1345 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1346 defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah",
1347 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1348 defm t2SXTAB16 : T2I_bin_rrot_DO<0b010, "sxtab16">;
1350 // TODO: SXT(A){B|H}16 - done for disassembly only
1354 let AddedComplexity = 16 in {
1355 defm t2UXTB : T2I_unary_rrot<0b101, "uxtb",
1356 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1357 defm t2UXTH : T2I_unary_rrot<0b001, "uxth",
1358 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1359 defm t2UXTB16 : T2I_unary_rrot_uxtb16<0b011, "uxtb16",
1360 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1362 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1363 // The transformation should probably be done as a combiner action
1364 // instead so we can include a check for masking back in the upper
1365 // eight bits of the source into the lower eight bits of the result.
1366 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1367 // (t2UXTB16r_rot rGPR:$Src, 24)>, Requires<[HasT2ExtractPack]>;
1368 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1369 (t2UXTB16r_rot rGPR:$Src, 8)>, Requires<[HasT2ExtractPack]>;
1371 defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
1372 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1373 defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah",
1374 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1375 defm t2UXTAB16 : T2I_bin_rrot_DO<0b011, "uxtab16">;
1378 //===----------------------------------------------------------------------===//
1379 // Arithmetic Instructions.
1382 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1383 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1384 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1385 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1387 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1388 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1389 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1390 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1391 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1393 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1394 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1395 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1396 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1397 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1398 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1399 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1400 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1403 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1404 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1405 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1406 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1408 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1409 // The assume-no-carry-in form uses the negation of the input since add/sub
1410 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1411 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1413 // The AddedComplexity preferences the first variant over the others since
1414 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1415 let AddedComplexity = 1 in
1416 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1417 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1418 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1419 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1420 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1421 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1422 let AddedComplexity = 1 in
1423 def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm),
1424 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1425 def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm),
1426 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1427 // The with-carry-in form matches bitwise not instead of the negation.
1428 // Effectively, the inverse interpretation of the carry flag already accounts
1429 // for part of the negation.
1430 let AddedComplexity = 1 in
1431 def : T2Pat<(adde rGPR:$src, imm0_255_not:$imm),
1432 (t2SBCSri rGPR:$src, imm0_255_not:$imm)>;
1433 def : T2Pat<(adde rGPR:$src, t2_so_imm_not:$imm),
1434 (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>;
1436 // Select Bytes -- for disassembly only
1438 def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel",
1439 "\t$dst, $a, $b", []> {
1440 let Inst{31-27} = 0b11111;
1441 let Inst{26-24} = 0b010;
1443 let Inst{22-20} = 0b010;
1444 let Inst{15-12} = 0b1111;
1446 let Inst{6-4} = 0b000;
1449 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1450 // And Miscellaneous operations -- for disassembly only
1451 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1452 list<dag> pat = [/* For disassembly only; pattern left blank */]>
1453 : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), NoItinerary, opc,
1454 "\t$dst, $a, $b", pat> {
1455 let Inst{31-27} = 0b11111;
1456 let Inst{26-23} = 0b0101;
1457 let Inst{22-20} = op22_20;
1458 let Inst{15-12} = 0b1111;
1459 let Inst{7-4} = op7_4;
1462 // Saturating add/subtract -- for disassembly only
1464 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1465 [(set rGPR:$dst, (int_arm_qadd rGPR:$a, rGPR:$b))]>;
1466 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1467 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1468 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1469 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1470 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1471 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1472 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1473 [(set rGPR:$dst, (int_arm_qsub rGPR:$a, rGPR:$b))]>;
1474 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1475 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1476 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1477 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1478 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1479 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1480 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1481 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1483 // Signed/Unsigned add/subtract -- for disassembly only
1485 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1486 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1487 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1488 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1489 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1490 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1491 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1492 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1493 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1494 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1495 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1496 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1498 // Signed/Unsigned halving add/subtract -- for disassembly only
1500 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1501 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1502 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1503 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1504 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1505 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1506 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1507 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1508 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1509 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1510 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1511 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1513 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1515 def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst),
1516 (ins rGPR:$a, rGPR:$b),
1517 NoItinerary, "usad8", "\t$dst, $a, $b", []> {
1518 let Inst{15-12} = 0b1111;
1520 def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst),
1521 (ins rGPR:$a, rGPR:$b, rGPR:$acc), NoItinerary, "usada8",
1522 "\t$dst, $a, $b, $acc", []>;
1524 // Signed/Unsigned saturate -- for disassembly only
1526 def t2SSAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, shift_imm:$sh),
1527 NoItinerary, "ssat", "\t$dst, $bit_pos, $a$sh",
1528 [/* For disassembly only; pattern left blank */]> {
1529 let Inst{31-27} = 0b11110;
1530 let Inst{25-22} = 0b1100;
1535 def t2SSAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary,
1536 "ssat16", "\t$dst, $bit_pos, $a",
1537 [/* For disassembly only; pattern left blank */]> {
1538 let Inst{31-27} = 0b11110;
1539 let Inst{25-22} = 0b1100;
1542 let Inst{21} = 1; // sh = '1'
1543 let Inst{14-12} = 0b000; // imm3 = '000'
1544 let Inst{7-6} = 0b00; // imm2 = '00'
1547 def t2USAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, shift_imm:$sh),
1548 NoItinerary, "usat", "\t$dst, $bit_pos, $a$sh",
1549 [/* For disassembly only; pattern left blank */]> {
1550 let Inst{31-27} = 0b11110;
1551 let Inst{25-22} = 0b1110;
1556 def t2USAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary,
1557 "usat16", "\t$dst, $bit_pos, $a",
1558 [/* For disassembly only; pattern left blank */]> {
1559 let Inst{31-27} = 0b11110;
1560 let Inst{25-22} = 0b1110;
1563 let Inst{21} = 1; // sh = '1'
1564 let Inst{14-12} = 0b000; // imm3 = '000'
1565 let Inst{7-6} = 0b00; // imm2 = '00'
1568 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
1569 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
1571 //===----------------------------------------------------------------------===//
1572 // Shift and rotate Instructions.
1575 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1576 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1577 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1578 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1580 let Uses = [CPSR] in {
1581 def t2MOVrx : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1582 "rrx", "\t$dst, $src",
1583 [(set rGPR:$dst, (ARMrrx rGPR:$src))]> {
1584 let Inst{31-27} = 0b11101;
1585 let Inst{26-25} = 0b01;
1586 let Inst{24-21} = 0b0010;
1587 let Inst{20} = ?; // The S bit.
1588 let Inst{19-16} = 0b1111; // Rn
1589 let Inst{14-12} = 0b000;
1590 let Inst{7-4} = 0b0011;
1594 let Defs = [CPSR] in {
1595 def t2MOVsrl_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1596 "lsrs", ".w\t$dst, $src, #1",
1597 [(set rGPR:$dst, (ARMsrl_flag rGPR:$src))]> {
1598 let Inst{31-27} = 0b11101;
1599 let Inst{26-25} = 0b01;
1600 let Inst{24-21} = 0b0010;
1601 let Inst{20} = 1; // The S bit.
1602 let Inst{19-16} = 0b1111; // Rn
1603 let Inst{5-4} = 0b01; // Shift type.
1604 // Shift amount = Inst{14-12:7-6} = 1.
1605 let Inst{14-12} = 0b000;
1606 let Inst{7-6} = 0b01;
1608 def t2MOVsra_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1609 "asrs", ".w\t$dst, $src, #1",
1610 [(set rGPR:$dst, (ARMsra_flag rGPR:$src))]> {
1611 let Inst{31-27} = 0b11101;
1612 let Inst{26-25} = 0b01;
1613 let Inst{24-21} = 0b0010;
1614 let Inst{20} = 1; // The S bit.
1615 let Inst{19-16} = 0b1111; // Rn
1616 let Inst{5-4} = 0b10; // Shift type.
1617 // Shift amount = Inst{14-12:7-6} = 1.
1618 let Inst{14-12} = 0b000;
1619 let Inst{7-6} = 0b01;
1623 //===----------------------------------------------------------------------===//
1624 // Bitwise Instructions.
1627 defm t2AND : T2I_bin_w_irs<0b0000, "and",
1628 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1629 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1630 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1631 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1632 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1634 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1635 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1637 let Constraints = "$src = $dst" in
1638 def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm),
1639 IIC_iUNAsi, "bfc", "\t$dst, $imm",
1640 [(set rGPR:$dst, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
1641 let Inst{31-27} = 0b11110;
1643 let Inst{24-20} = 0b10110;
1644 let Inst{19-16} = 0b1111; // Rn
1648 def t2SBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
1649 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
1650 let Inst{31-27} = 0b11110;
1652 let Inst{24-20} = 0b10100;
1656 def t2UBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
1657 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
1658 let Inst{31-27} = 0b11110;
1660 let Inst{24-20} = 0b11100;
1664 // A8.6.18 BFI - Bitfield insert (Encoding T1)
1665 let Constraints = "$src = $dst" in
1666 def t2BFI : T2I<(outs rGPR:$dst),
1667 (ins rGPR:$src, rGPR:$val, bf_inv_mask_imm:$imm),
1668 IIC_iALUi, "bfi", "\t$dst, $val, $imm",
1669 [(set rGPR:$dst, (ARMbfi rGPR:$src, rGPR:$val,
1670 bf_inv_mask_imm:$imm))]> {
1671 let Inst{31-27} = 0b11110;
1673 let Inst{24-20} = 0b10110;
1677 defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS,
1680 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
1681 let AddedComplexity = 1 in
1682 defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
1685 let AddedComplexity = 1 in
1686 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
1687 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
1689 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
1690 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
1691 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
1692 Requires<[IsThumb2]>;
1694 def : T2Pat<(t2_so_imm_not:$src),
1695 (t2MVNi t2_so_imm_not:$src)>;
1697 //===----------------------------------------------------------------------===//
1698 // Multiply Instructions.
1700 let isCommutable = 1 in
1701 def t2MUL: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1702 "mul", "\t$dst, $a, $b",
1703 [(set rGPR:$dst, (mul rGPR:$a, rGPR:$b))]> {
1704 let Inst{31-27} = 0b11111;
1705 let Inst{26-23} = 0b0110;
1706 let Inst{22-20} = 0b000;
1707 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1708 let Inst{7-4} = 0b0000; // Multiply
1711 def t2MLA: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1712 "mla", "\t$dst, $a, $b, $c",
1713 [(set rGPR:$dst, (add (mul rGPR:$a, rGPR:$b), rGPR:$c))]> {
1714 let Inst{31-27} = 0b11111;
1715 let Inst{26-23} = 0b0110;
1716 let Inst{22-20} = 0b000;
1717 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1718 let Inst{7-4} = 0b0000; // Multiply
1721 def t2MLS: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1722 "mls", "\t$dst, $a, $b, $c",
1723 [(set rGPR:$dst, (sub rGPR:$c, (mul rGPR:$a, rGPR:$b)))]> {
1724 let Inst{31-27} = 0b11111;
1725 let Inst{26-23} = 0b0110;
1726 let Inst{22-20} = 0b000;
1727 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1728 let Inst{7-4} = 0b0001; // Multiply and Subtract
1731 // Extra precision multiplies with low / high results
1732 let neverHasSideEffects = 1 in {
1733 let isCommutable = 1 in {
1734 def t2SMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
1735 "smull", "\t$ldst, $hdst, $a, $b", []> {
1736 let Inst{31-27} = 0b11111;
1737 let Inst{26-23} = 0b0111;
1738 let Inst{22-20} = 0b000;
1739 let Inst{7-4} = 0b0000;
1742 def t2UMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
1743 "umull", "\t$ldst, $hdst, $a, $b", []> {
1744 let Inst{31-27} = 0b11111;
1745 let Inst{26-23} = 0b0111;
1746 let Inst{22-20} = 0b010;
1747 let Inst{7-4} = 0b0000;
1751 // Multiply + accumulate
1752 def t2SMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1753 "smlal", "\t$ldst, $hdst, $a, $b", []>{
1754 let Inst{31-27} = 0b11111;
1755 let Inst{26-23} = 0b0111;
1756 let Inst{22-20} = 0b100;
1757 let Inst{7-4} = 0b0000;
1760 def t2UMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1761 "umlal", "\t$ldst, $hdst, $a, $b", []>{
1762 let Inst{31-27} = 0b11111;
1763 let Inst{26-23} = 0b0111;
1764 let Inst{22-20} = 0b110;
1765 let Inst{7-4} = 0b0000;
1768 def t2UMAAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1769 "umaal", "\t$ldst, $hdst, $a, $b", []>{
1770 let Inst{31-27} = 0b11111;
1771 let Inst{26-23} = 0b0111;
1772 let Inst{22-20} = 0b110;
1773 let Inst{7-4} = 0b0110;
1775 } // neverHasSideEffects
1777 // Rounding variants of the below included for disassembly only
1779 // Most significant word multiply
1780 def t2SMMUL : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1781 "smmul", "\t$dst, $a, $b",
1782 [(set rGPR:$dst, (mulhs rGPR:$a, rGPR:$b))]> {
1783 let Inst{31-27} = 0b11111;
1784 let Inst{26-23} = 0b0110;
1785 let Inst{22-20} = 0b101;
1786 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1787 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1790 def t2SMMULR : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1791 "smmulr", "\t$dst, $a, $b", []> {
1792 let Inst{31-27} = 0b11111;
1793 let Inst{26-23} = 0b0110;
1794 let Inst{22-20} = 0b101;
1795 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1796 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1799 def t2SMMLA : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1800 "smmla", "\t$dst, $a, $b, $c",
1801 [(set rGPR:$dst, (add (mulhs rGPR:$a, rGPR:$b), rGPR:$c))]> {
1802 let Inst{31-27} = 0b11111;
1803 let Inst{26-23} = 0b0110;
1804 let Inst{22-20} = 0b101;
1805 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1806 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1809 def t2SMMLAR : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1810 "smmlar", "\t$dst, $a, $b, $c", []> {
1811 let Inst{31-27} = 0b11111;
1812 let Inst{26-23} = 0b0110;
1813 let Inst{22-20} = 0b101;
1814 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1815 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1818 def t2SMMLS : T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1819 "smmls", "\t$dst, $a, $b, $c",
1820 [(set rGPR:$dst, (sub rGPR:$c, (mulhs rGPR:$a, rGPR:$b)))]> {
1821 let Inst{31-27} = 0b11111;
1822 let Inst{26-23} = 0b0110;
1823 let Inst{22-20} = 0b110;
1824 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1825 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1828 def t2SMMLSR : T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1829 "smmlsr", "\t$dst, $a, $b, $c", []> {
1830 let Inst{31-27} = 0b11111;
1831 let Inst{26-23} = 0b0110;
1832 let Inst{22-20} = 0b110;
1833 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1834 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1837 multiclass T2I_smul<string opc, PatFrag opnode> {
1838 def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1839 !strconcat(opc, "bb"), "\t$dst, $a, $b",
1840 [(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16),
1841 (sext_inreg rGPR:$b, i16)))]> {
1842 let Inst{31-27} = 0b11111;
1843 let Inst{26-23} = 0b0110;
1844 let Inst{22-20} = 0b001;
1845 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1846 let Inst{7-6} = 0b00;
1847 let Inst{5-4} = 0b00;
1850 def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1851 !strconcat(opc, "bt"), "\t$dst, $a, $b",
1852 [(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16),
1853 (sra rGPR:$b, (i32 16))))]> {
1854 let Inst{31-27} = 0b11111;
1855 let Inst{26-23} = 0b0110;
1856 let Inst{22-20} = 0b001;
1857 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1858 let Inst{7-6} = 0b00;
1859 let Inst{5-4} = 0b01;
1862 def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1863 !strconcat(opc, "tb"), "\t$dst, $a, $b",
1864 [(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)),
1865 (sext_inreg rGPR:$b, i16)))]> {
1866 let Inst{31-27} = 0b11111;
1867 let Inst{26-23} = 0b0110;
1868 let Inst{22-20} = 0b001;
1869 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1870 let Inst{7-6} = 0b00;
1871 let Inst{5-4} = 0b10;
1874 def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1875 !strconcat(opc, "tt"), "\t$dst, $a, $b",
1876 [(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)),
1877 (sra rGPR:$b, (i32 16))))]> {
1878 let Inst{31-27} = 0b11111;
1879 let Inst{26-23} = 0b0110;
1880 let Inst{22-20} = 0b001;
1881 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1882 let Inst{7-6} = 0b00;
1883 let Inst{5-4} = 0b11;
1886 def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
1887 !strconcat(opc, "wb"), "\t$dst, $a, $b",
1888 [(set rGPR:$dst, (sra (opnode rGPR:$a,
1889 (sext_inreg rGPR:$b, i16)), (i32 16)))]> {
1890 let Inst{31-27} = 0b11111;
1891 let Inst{26-23} = 0b0110;
1892 let Inst{22-20} = 0b011;
1893 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1894 let Inst{7-6} = 0b00;
1895 let Inst{5-4} = 0b00;
1898 def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
1899 !strconcat(opc, "wt"), "\t$dst, $a, $b",
1900 [(set rGPR:$dst, (sra (opnode rGPR:$a,
1901 (sra rGPR:$b, (i32 16))), (i32 16)))]> {
1902 let Inst{31-27} = 0b11111;
1903 let Inst{26-23} = 0b0110;
1904 let Inst{22-20} = 0b011;
1905 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1906 let Inst{7-6} = 0b00;
1907 let Inst{5-4} = 0b01;
1912 multiclass T2I_smla<string opc, PatFrag opnode> {
1913 def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1914 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1915 [(set rGPR:$dst, (add rGPR:$acc,
1916 (opnode (sext_inreg rGPR:$a, i16),
1917 (sext_inreg rGPR:$b, i16))))]> {
1918 let Inst{31-27} = 0b11111;
1919 let Inst{26-23} = 0b0110;
1920 let Inst{22-20} = 0b001;
1921 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1922 let Inst{7-6} = 0b00;
1923 let Inst{5-4} = 0b00;
1926 def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1927 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1928 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sext_inreg rGPR:$a, i16),
1929 (sra rGPR:$b, (i32 16)))))]> {
1930 let Inst{31-27} = 0b11111;
1931 let Inst{26-23} = 0b0110;
1932 let Inst{22-20} = 0b001;
1933 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1934 let Inst{7-6} = 0b00;
1935 let Inst{5-4} = 0b01;
1938 def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1939 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1940 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
1941 (sext_inreg rGPR:$b, i16))))]> {
1942 let Inst{31-27} = 0b11111;
1943 let Inst{26-23} = 0b0110;
1944 let Inst{22-20} = 0b001;
1945 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1946 let Inst{7-6} = 0b00;
1947 let Inst{5-4} = 0b10;
1950 def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1951 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1952 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
1953 (sra rGPR:$b, (i32 16)))))]> {
1954 let Inst{31-27} = 0b11111;
1955 let Inst{26-23} = 0b0110;
1956 let Inst{22-20} = 0b001;
1957 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1958 let Inst{7-6} = 0b00;
1959 let Inst{5-4} = 0b11;
1962 def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1963 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1964 [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
1965 (sext_inreg rGPR:$b, i16)), (i32 16))))]> {
1966 let Inst{31-27} = 0b11111;
1967 let Inst{26-23} = 0b0110;
1968 let Inst{22-20} = 0b011;
1969 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1970 let Inst{7-6} = 0b00;
1971 let Inst{5-4} = 0b00;
1974 def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1975 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1976 [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
1977 (sra rGPR:$b, (i32 16))), (i32 16))))]> {
1978 let Inst{31-27} = 0b11111;
1979 let Inst{26-23} = 0b0110;
1980 let Inst{22-20} = 0b011;
1981 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1982 let Inst{7-6} = 0b00;
1983 let Inst{5-4} = 0b01;
1987 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1988 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1990 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
1991 def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs rGPR:$ldst,rGPR:$hdst),
1992 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
1993 [/* For disassembly only; pattern left blank */]>;
1994 def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs rGPR:$ldst,rGPR:$hdst),
1995 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
1996 [/* For disassembly only; pattern left blank */]>;
1997 def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs rGPR:$ldst,rGPR:$hdst),
1998 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
1999 [/* For disassembly only; pattern left blank */]>;
2000 def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs rGPR:$ldst,rGPR:$hdst),
2001 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
2002 [/* For disassembly only; pattern left blank */]>;
2004 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2005 // These are for disassembly only.
2007 def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2008 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
2009 let Inst{15-12} = 0b1111;
2011 def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2012 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
2013 let Inst{15-12} = 0b1111;
2015 def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2016 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
2017 let Inst{15-12} = 0b1111;
2019 def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2020 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
2021 let Inst{15-12} = 0b1111;
2023 def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst),
2024 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlad",
2025 "\t$dst, $a, $b, $acc", []>;
2026 def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst),
2027 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smladx",
2028 "\t$dst, $a, $b, $acc", []>;
2029 def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst),
2030 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsd",
2031 "\t$dst, $a, $b, $acc", []>;
2032 def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst),
2033 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsdx",
2034 "\t$dst, $a, $b, $acc", []>;
2035 def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs rGPR:$ldst,rGPR:$hdst),
2036 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlald",
2037 "\t$ldst, $hdst, $a, $b", []>;
2038 def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs rGPR:$ldst,rGPR:$hdst),
2039 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaldx",
2040 "\t$ldst, $hdst, $a, $b", []>;
2041 def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs rGPR:$ldst,rGPR:$hdst),
2042 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsld",
2043 "\t$ldst, $hdst, $a, $b", []>;
2044 def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs rGPR:$ldst,rGPR:$hdst),
2045 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsldx",
2046 "\t$ldst, $hdst, $a, $b", []>;
2048 //===----------------------------------------------------------------------===//
2049 // Misc. Arithmetic Instructions.
2052 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2053 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2054 : T2I<oops, iops, itin, opc, asm, pattern> {
2055 let Inst{31-27} = 0b11111;
2056 let Inst{26-22} = 0b01010;
2057 let Inst{21-20} = op1;
2058 let Inst{15-12} = 0b1111;
2059 let Inst{7-6} = 0b10;
2060 let Inst{5-4} = op2;
2063 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2064 "clz", "\t$dst, $src", [(set rGPR:$dst, (ctlz rGPR:$src))]>;
2066 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2067 "rbit", "\t$dst, $src",
2068 [(set rGPR:$dst, (ARMrbit rGPR:$src))]>;
2070 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2071 "rev", ".w\t$dst, $src", [(set rGPR:$dst, (bswap rGPR:$src))]>;
2073 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2074 "rev16", ".w\t$dst, $src",
2076 (or (and (srl rGPR:$src, (i32 8)), 0xFF),
2077 (or (and (shl rGPR:$src, (i32 8)), 0xFF00),
2078 (or (and (srl rGPR:$src, (i32 8)), 0xFF0000),
2079 (and (shl rGPR:$src, (i32 8)), 0xFF000000)))))]>;
2081 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2082 "revsh", ".w\t$dst, $src",
2085 (or (srl (and rGPR:$src, 0xFF00), (i32 8)),
2086 (shl rGPR:$src, (i32 8))), i16))]>;
2088 def t2PKHBT : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh),
2089 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2$sh",
2090 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF),
2091 (and (shl rGPR:$src2, lsl_amt:$sh),
2093 Requires<[HasT2ExtractPack]> {
2094 let Inst{31-27} = 0b11101;
2095 let Inst{26-25} = 0b01;
2096 let Inst{24-20} = 0b01100;
2097 let Inst{5} = 0; // BT form
2101 // Alternate cases for PKHBT where identities eliminate some nodes.
2102 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2103 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2104 Requires<[HasT2ExtractPack]>;
2105 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2106 (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>,
2107 Requires<[HasT2ExtractPack]>;
2109 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2110 // will match the pattern below.
2111 def t2PKHTB : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh),
2112 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2$sh",
2113 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF0000),
2114 (and (sra rGPR:$src2, asr_amt:$sh),
2116 Requires<[HasT2ExtractPack]> {
2117 let Inst{31-27} = 0b11101;
2118 let Inst{26-25} = 0b01;
2119 let Inst{24-20} = 0b01100;
2120 let Inst{5} = 1; // TB form
2124 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2125 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2126 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2127 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>,
2128 Requires<[HasT2ExtractPack]>;
2129 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2130 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2131 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>,
2132 Requires<[HasT2ExtractPack]>;
2134 //===----------------------------------------------------------------------===//
2135 // Comparison Instructions...
2137 let isCompare = 1 in {
2138 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2139 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2140 defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
2141 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2144 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2145 // Compare-to-zero still works out, just not the relationals
2146 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2147 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2148 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2149 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2151 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2152 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2154 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2155 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2157 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2158 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
2159 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2160 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
2162 // Conditional moves
2163 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2164 // a two-value operand where a dag node expects two operands. :(
2165 let neverHasSideEffects = 1 in {
2166 def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr,
2167 "mov", ".w\t$dst, $true",
2168 [/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>,
2169 RegConstraint<"$false = $dst"> {
2170 let Inst{31-27} = 0b11101;
2171 let Inst{26-25} = 0b01;
2172 let Inst{24-21} = 0b0010;
2173 let Inst{20} = 0; // The S bit.
2174 let Inst{19-16} = 0b1111; // Rn
2175 let Inst{14-12} = 0b000;
2176 let Inst{7-4} = 0b0000;
2179 def t2MOVCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true),
2180 IIC_iCMOVi, "mov", ".w\t$dst, $true",
2181 [/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
2182 RegConstraint<"$false = $dst"> {
2183 let Inst{31-27} = 0b11110;
2185 let Inst{24-21} = 0b0010;
2186 let Inst{20} = 0; // The S bit.
2187 let Inst{19-16} = 0b1111; // Rn
2191 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2192 string opc, string asm, list<dag> pattern>
2193 : T2I<oops, iops, itin, opc, asm, pattern> {
2194 let Inst{31-27} = 0b11101;
2195 let Inst{26-25} = 0b01;
2196 let Inst{24-21} = 0b0010;
2197 let Inst{20} = 0; // The S bit.
2198 let Inst{19-16} = 0b1111; // Rn
2199 let Inst{5-4} = opcod; // Shift type.
2201 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$dst),
2202 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2203 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
2204 RegConstraint<"$false = $dst">;
2205 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$dst),
2206 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2207 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
2208 RegConstraint<"$false = $dst">;
2209 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$dst),
2210 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2211 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
2212 RegConstraint<"$false = $dst">;
2213 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$dst),
2214 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2215 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
2216 RegConstraint<"$false = $dst">;
2217 } // neverHasSideEffects
2219 //===----------------------------------------------------------------------===//
2220 // Atomic operations intrinsics
2223 // memory barriers protect the atomic sequences
2224 let hasSideEffects = 1 in {
2225 def t2DMBsy : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "dmb", "",
2226 [(ARMMemBarrier)]>, Requires<[IsThumb, HasDB]> {
2227 let Inst{31-4} = 0xF3BF8F5;
2228 // FIXME: add support for options other than a full system DMB
2229 let Inst{3-0} = 0b1111;
2232 def t2DSBsy : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "dsb", "",
2233 [(ARMSyncBarrier)]>, Requires<[IsThumb, HasDB]> {
2234 let Inst{31-4} = 0xF3BF8F4;
2235 // FIXME: add support for options other than a full system DSB
2236 let Inst{3-0} = 0b1111;
2240 // Helper class for multiclass T2MemB -- for disassembly only
2241 class T2I_memb<string opc, string asm>
2242 : T2I<(outs), (ins), NoItinerary, opc, asm,
2243 [/* For disassembly only; pattern left blank */]>,
2244 Requires<[IsThumb2, HasV7]> {
2245 let Inst{31-20} = 0xf3b;
2246 let Inst{15-14} = 0b10;
2250 multiclass T2MemB<bits<4> op7_4, string opc> {
2252 def st : T2I_memb<opc, "\tst"> {
2253 let Inst{7-4} = op7_4;
2254 let Inst{3-0} = 0b1110;
2257 def ish : T2I_memb<opc, "\tish"> {
2258 let Inst{7-4} = op7_4;
2259 let Inst{3-0} = 0b1011;
2262 def ishst : T2I_memb<opc, "\tishst"> {
2263 let Inst{7-4} = op7_4;
2264 let Inst{3-0} = 0b1010;
2267 def nsh : T2I_memb<opc, "\tnsh"> {
2268 let Inst{7-4} = op7_4;
2269 let Inst{3-0} = 0b0111;
2272 def nshst : T2I_memb<opc, "\tnshst"> {
2273 let Inst{7-4} = op7_4;
2274 let Inst{3-0} = 0b0110;
2277 def osh : T2I_memb<opc, "\tosh"> {
2278 let Inst{7-4} = op7_4;
2279 let Inst{3-0} = 0b0011;
2282 def oshst : T2I_memb<opc, "\toshst"> {
2283 let Inst{7-4} = op7_4;
2284 let Inst{3-0} = 0b0010;
2288 // These DMB variants are for disassembly only.
2289 defm t2DMB : T2MemB<0b0101, "dmb">;
2291 // These DSB variants are for disassembly only.
2292 defm t2DSB : T2MemB<0b0100, "dsb">;
2294 // ISB has only full system option -- for disassembly only
2295 def t2ISBsy : T2I_memb<"isb", ""> {
2296 let Inst{7-4} = 0b0110;
2297 let Inst{3-0} = 0b1111;
2300 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2301 InstrItinClass itin, string opc, string asm, string cstr,
2302 list<dag> pattern, bits<4> rt2 = 0b1111>
2303 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2304 let Inst{31-27} = 0b11101;
2305 let Inst{26-20} = 0b0001101;
2306 let Inst{11-8} = rt2;
2307 let Inst{7-6} = 0b01;
2308 let Inst{5-4} = opcod;
2309 let Inst{3-0} = 0b1111;
2311 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2312 InstrItinClass itin, string opc, string asm, string cstr,
2313 list<dag> pattern, bits<4> rt2 = 0b1111>
2314 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2315 let Inst{31-27} = 0b11101;
2316 let Inst{26-20} = 0b0001100;
2317 let Inst{11-8} = rt2;
2318 let Inst{7-6} = 0b01;
2319 let Inst{5-4} = opcod;
2322 let mayLoad = 1 in {
2323 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2324 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
2326 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2327 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
2329 def t2LDREX : Thumb2I<(outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2330 Size4Bytes, NoItinerary,
2331 "ldrex", "\t$dest, [$ptr]", "",
2333 let Inst{31-27} = 0b11101;
2334 let Inst{26-20} = 0b0000101;
2335 let Inst{11-8} = 0b1111;
2336 let Inst{7-0} = 0b00000000; // imm8 = 0
2338 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$dest, rGPR:$dest2), (ins rGPR:$ptr),
2339 AddrModeNone, Size4Bytes, NoItinerary,
2340 "ldrexd", "\t$dest, $dest2, [$ptr]", "",
2344 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2345 def t2STREXB : T2I_strex<0b00, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2346 AddrModeNone, Size4Bytes, NoItinerary,
2347 "strexb", "\t$success, $src, [$ptr]", "", []>;
2348 def t2STREXH : T2I_strex<0b01, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2349 AddrModeNone, Size4Bytes, NoItinerary,
2350 "strexh", "\t$success, $src, [$ptr]", "", []>;
2351 def t2STREX : Thumb2I<(outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2352 AddrModeNone, Size4Bytes, NoItinerary,
2353 "strex", "\t$success, $src, [$ptr]", "",
2355 let Inst{31-27} = 0b11101;
2356 let Inst{26-20} = 0b0000100;
2357 let Inst{7-0} = 0b00000000; // imm8 = 0
2359 def t2STREXD : T2I_strex<0b11, (outs rGPR:$success),
2360 (ins rGPR:$src, rGPR:$src2, rGPR:$ptr),
2361 AddrModeNone, Size4Bytes, NoItinerary,
2362 "strexd", "\t$success, $src, $src2, [$ptr]", "", [],
2366 // Clear-Exclusive is for disassembly only.
2367 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2368 [/* For disassembly only; pattern left blank */]>,
2369 Requires<[IsARM, HasV7]> {
2370 let Inst{31-20} = 0xf3b;
2371 let Inst{15-14} = 0b10;
2373 let Inst{7-4} = 0b0010;
2376 //===----------------------------------------------------------------------===//
2380 // __aeabi_read_tp preserves the registers r1-r3.
2382 Defs = [R0, R12, LR, CPSR] in {
2383 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2384 "bl\t__aeabi_read_tp",
2385 [(set R0, ARMthread_pointer)]> {
2386 let Inst{31-27} = 0b11110;
2387 let Inst{15-14} = 0b11;
2392 //===----------------------------------------------------------------------===//
2393 // SJLJ Exception handling intrinsics
2394 // eh_sjlj_setjmp() is an instruction sequence to store the return
2395 // address and save #0 in R0 for the non-longjmp case.
2396 // Since by its nature we may be coming from some other function to get
2397 // here, and we're using the stack frame for the containing function to
2398 // save/restore registers, we can't keep anything live in regs across
2399 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2400 // when we get here from a longjmp(). We force everthing out of registers
2401 // except for our own input by listing the relevant registers in Defs. By
2402 // doing so, we also cause the prologue/epilogue code to actively preserve
2403 // all of the callee-saved resgisters, which is exactly what we want.
2404 // $val is a scratch register for our use.
2406 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2407 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2408 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2409 D31 ], hasSideEffects = 1, isBarrier = 1 in {
2410 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
2411 AddrModeNone, SizeSpecial, NoItinerary,
2412 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
2413 "adds\t$val, #7\n\t"
2414 "str\t$val, [$src, #4]\n\t"
2417 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
2419 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>,
2420 Requires<[IsThumb2, HasVFP2]>;
2424 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2425 hasSideEffects = 1, isBarrier = 1 in {
2426 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
2427 AddrModeNone, SizeSpecial, NoItinerary,
2428 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
2429 "adds\t$val, #7\n\t"
2430 "str\t$val, [$src, #4]\n\t"
2433 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
2435 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>,
2436 Requires<[IsThumb2, NoVFP]>;
2440 //===----------------------------------------------------------------------===//
2441 // Control-Flow Instructions
2444 // FIXME: remove when we have a way to marking a MI with these properties.
2445 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2447 // FIXME: Should pc be an implicit operand like PICADD, etc?
2448 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2449 hasExtraDefRegAllocReq = 1 in
2450 def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
2451 reglist:$dsts, variable_ops), IIC_Br,
2452 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
2453 "$addr.addr = $wb", []> {
2454 let Inst{31-27} = 0b11101;
2455 let Inst{26-25} = 0b00;
2456 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
2458 let Inst{21} = 1; // The W bit.
2459 let Inst{20} = 1; // Load
2462 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2463 let isPredicable = 1 in
2464 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2466 [(br bb:$target)]> {
2467 let Inst{31-27} = 0b11110;
2468 let Inst{15-14} = 0b10;
2472 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2475 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
2476 IIC_Br, "mov\tpc, $target$jt",
2477 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
2478 let Inst{31-27} = 0b11101;
2479 let Inst{26-20} = 0b0100100;
2480 let Inst{19-16} = 0b1111;
2481 let Inst{14-12} = 0b000;
2482 let Inst{11-8} = 0b1111; // Rd = pc
2483 let Inst{7-4} = 0b0000;
2486 // FIXME: Add a non-pc based case that can be predicated.
2489 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2490 IIC_Br, "tbb\t$index$jt", []> {
2491 let Inst{31-27} = 0b11101;
2492 let Inst{26-20} = 0b0001101;
2493 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2494 let Inst{15-8} = 0b11110000;
2495 let Inst{7-4} = 0b0000; // B form
2500 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2501 IIC_Br, "tbh\t$index$jt", []> {
2502 let Inst{31-27} = 0b11101;
2503 let Inst{26-20} = 0b0001101;
2504 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2505 let Inst{15-8} = 0b11110000;
2506 let Inst{7-4} = 0b0001; // H form
2509 // Generic versions of the above two instructions, for disassembly only
2511 def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2512 "tbb", "\t[$a, $b]", []>{
2513 let Inst{31-27} = 0b11101;
2514 let Inst{26-20} = 0b0001101;
2515 let Inst{15-8} = 0b11110000;
2516 let Inst{7-4} = 0b0000; // B form
2519 def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2520 "tbh", "\t[$a, $b, lsl #1]", []> {
2521 let Inst{31-27} = 0b11101;
2522 let Inst{26-20} = 0b0001101;
2523 let Inst{15-8} = 0b11110000;
2524 let Inst{7-4} = 0b0001; // H form
2526 } // isNotDuplicable, isIndirectBranch
2528 } // isBranch, isTerminator, isBarrier
2530 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2531 // a two-value operand where a dag node expects two operands. :(
2532 let isBranch = 1, isTerminator = 1 in
2533 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
2535 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
2536 let Inst{31-27} = 0b11110;
2537 let Inst{15-14} = 0b10;
2543 let Defs = [ITSTATE] in
2544 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
2545 AddrModeNone, Size2Bytes, IIC_iALUx,
2546 "it$mask\t$cc", "", []> {
2547 // 16-bit instruction.
2548 let Inst{31-16} = 0x0000;
2549 let Inst{15-8} = 0b10111111;
2552 // Branch and Exchange Jazelle -- for disassembly only
2554 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
2555 [/* For disassembly only; pattern left blank */]> {
2556 let Inst{31-27} = 0b11110;
2558 let Inst{25-20} = 0b111100;
2559 let Inst{15-14} = 0b10;
2563 // Change Processor State is a system instruction -- for disassembly only.
2564 // The singleton $opt operand contains the following information:
2565 // opt{4-0} = mode from Inst{4-0}
2566 // opt{5} = changemode from Inst{17}
2567 // opt{8-6} = AIF from Inst{8-6}
2568 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
2569 def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
2570 [/* For disassembly only; pattern left blank */]> {
2571 let Inst{31-27} = 0b11110;
2573 let Inst{25-20} = 0b111010;
2574 let Inst{15-14} = 0b10;
2578 // A6.3.4 Branches and miscellaneous control
2579 // Table A6-14 Change Processor State, and hint instructions
2580 // Helper class for disassembly only.
2581 class T2I_hint<bits<8> op7_0, string opc, string asm>
2582 : T2I<(outs), (ins), NoItinerary, opc, asm,
2583 [/* For disassembly only; pattern left blank */]> {
2584 let Inst{31-20} = 0xf3a;
2585 let Inst{15-14} = 0b10;
2587 let Inst{10-8} = 0b000;
2588 let Inst{7-0} = op7_0;
2591 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
2592 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
2593 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
2594 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
2595 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
2597 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
2598 [/* For disassembly only; pattern left blank */]> {
2599 let Inst{31-20} = 0xf3a;
2600 let Inst{15-14} = 0b10;
2602 let Inst{10-8} = 0b000;
2603 let Inst{7-4} = 0b1111;
2606 // Secure Monitor Call is a system instruction -- for disassembly only
2607 // Option = Inst{19-16}
2608 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
2609 [/* For disassembly only; pattern left blank */]> {
2610 let Inst{31-27} = 0b11110;
2611 let Inst{26-20} = 0b1111111;
2612 let Inst{15-12} = 0b1000;
2615 // Store Return State is a system instruction -- for disassembly only
2616 def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
2617 [/* For disassembly only; pattern left blank */]> {
2618 let Inst{31-27} = 0b11101;
2619 let Inst{26-20} = 0b0000010; // W = 1
2622 def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
2623 [/* For disassembly only; pattern left blank */]> {
2624 let Inst{31-27} = 0b11101;
2625 let Inst{26-20} = 0b0000000; // W = 0
2628 def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
2629 [/* For disassembly only; pattern left blank */]> {
2630 let Inst{31-27} = 0b11101;
2631 let Inst{26-20} = 0b0011010; // W = 1
2634 def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
2635 [/* For disassembly only; pattern left blank */]> {
2636 let Inst{31-27} = 0b11101;
2637 let Inst{26-20} = 0b0011000; // W = 0
2640 // Return From Exception is a system instruction -- for disassembly only
2641 def t2RFEDBW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfedb", "\t$base!",
2642 [/* For disassembly only; pattern left blank */]> {
2643 let Inst{31-27} = 0b11101;
2644 let Inst{26-20} = 0b0000011; // W = 1
2647 def t2RFEDB : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeab", "\t$base",
2648 [/* For disassembly only; pattern left blank */]> {
2649 let Inst{31-27} = 0b11101;
2650 let Inst{26-20} = 0b0000001; // W = 0
2653 def t2RFEIAW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base!",
2654 [/* For disassembly only; pattern left blank */]> {
2655 let Inst{31-27} = 0b11101;
2656 let Inst{26-20} = 0b0011011; // W = 1
2659 def t2RFEIA : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base",
2660 [/* For disassembly only; pattern left blank */]> {
2661 let Inst{31-27} = 0b11101;
2662 let Inst{26-20} = 0b0011001; // W = 0
2665 //===----------------------------------------------------------------------===//
2666 // Non-Instruction Patterns
2669 // Two piece so_imms.
2670 def : T2Pat<(or rGPR:$LHS, t2_so_imm2part:$RHS),
2671 (t2ORRri (t2ORRri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2672 (t2_so_imm2part_2 imm:$RHS))>;
2673 def : T2Pat<(xor rGPR:$LHS, t2_so_imm2part:$RHS),
2674 (t2EORri (t2EORri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2675 (t2_so_imm2part_2 imm:$RHS))>;
2676 def : T2Pat<(add rGPR:$LHS, t2_so_imm2part:$RHS),
2677 (t2ADDri (t2ADDri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2678 (t2_so_imm2part_2 imm:$RHS))>;
2679 def : T2Pat<(add rGPR:$LHS, t2_so_neg_imm2part:$RHS),
2680 (t2SUBri (t2SUBri rGPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
2681 (t2_so_neg_imm2part_2 imm:$RHS))>;
2683 // 32-bit immediate using movw + movt.
2684 // This is a single pseudo instruction to make it re-materializable. Remove
2685 // when we can do generalized remat.
2686 let isReMaterializable = 1 in
2687 def t2MOVi32imm : T2Ix2<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
2688 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2689 [(set rGPR:$dst, (i32 imm:$src))]>;
2691 // ConstantPool, GlobalAddress, and JumpTable
2692 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
2693 Requires<[IsThumb2, DontUseMovt]>;
2694 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
2695 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
2696 Requires<[IsThumb2, UseMovt]>;
2698 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2699 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
2701 // Pseudo instruction that combines ldr from constpool and add pc. This should
2702 // be expanded into two instructions late to allow if-conversion and
2704 let canFoldAsLoad = 1, isReMaterializable = 1 in
2705 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
2707 "${:comment} ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
2708 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
2710 Requires<[IsThumb2]>;
2712 //===----------------------------------------------------------------------===//
2713 // Move between special register and ARM core register -- for disassembly only
2717 def t2MRS : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
2718 [/* For disassembly only; pattern left blank */]> {
2719 let Inst{31-27} = 0b11110;
2721 let Inst{25-21} = 0b11111;
2722 let Inst{20} = 0; // The R bit.
2723 let Inst{15-14} = 0b10;
2728 def t2MRSsys : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
2729 [/* For disassembly only; pattern left blank */]> {
2730 let Inst{31-27} = 0b11110;
2732 let Inst{25-21} = 0b11111;
2733 let Inst{20} = 1; // The R bit.
2734 let Inst{15-14} = 0b10;
2739 def t2MSR : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
2740 "\tcpsr$mask, $src",
2741 [/* For disassembly only; pattern left blank */]> {
2742 let Inst{31-27} = 0b11110;
2744 let Inst{25-21} = 0b11100;
2745 let Inst{20} = 0; // The R bit.
2746 let Inst{15-14} = 0b10;
2751 def t2MSRsys : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
2752 "\tspsr$mask, $src",
2753 [/* For disassembly only; pattern left blank */]> {
2754 let Inst{31-27} = 0b11110;
2756 let Inst{25-21} = 0b11100;
2757 let Inst{20} = 1; // The R bit.
2758 let Inst{15-14} = 0b10;