1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops rGPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant
53 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>,
56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
59 // t2_so_imm_not - Match an immediate that is a complement
61 def t2_so_imm_not : Operand<i32>,
63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
64 }], t2_so_imm_not_XFORM>;
66 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
67 def t2_so_imm_neg : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
70 }], t2_so_imm_neg_XFORM>;
72 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
73 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
74 // to get the first/second pieces.
75 def t2_so_imm2part : Operand<i32>,
77 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
81 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
82 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
83 return CurDAG->getTargetConstant(V, MVT::i32);
86 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
87 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
88 return CurDAG->getTargetConstant(V, MVT::i32);
91 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
92 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
96 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
97 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
98 return CurDAG->getTargetConstant(V, MVT::i32);
101 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
102 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
103 return CurDAG->getTargetConstant(V, MVT::i32);
106 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
107 def imm1_31 : PatLeaf<(i32 imm), [{
108 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
111 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
112 def imm0_4095 : Operand<i32>,
113 PatLeaf<(i32 imm), [{
114 return (uint32_t)N->getZExtValue() < 4096;
117 def imm0_4095_neg : PatLeaf<(i32 imm), [{
118 return (uint32_t)(-N->getZExtValue()) < 4096;
121 def imm0_255_neg : PatLeaf<(i32 imm), [{
122 return (uint32_t)(-N->getZExtValue()) < 255;
125 def imm0_255_not : PatLeaf<(i32 imm), [{
126 return (uint32_t)(~N->getZExtValue()) < 255;
129 // Define Thumb2 specific addressing modes.
131 // t2addrmode_imm12 := reg + imm12
132 def t2addrmode_imm12 : Operand<i32>,
133 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
134 let PrintMethod = "printT2AddrModeImm12Operand";
135 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
138 // t2addrmode_imm8 := reg +/- imm8
139 def t2addrmode_imm8 : Operand<i32>,
140 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
141 let PrintMethod = "printT2AddrModeImm8Operand";
142 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
145 def t2am_imm8_offset : Operand<i32>,
146 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
147 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
150 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
151 def t2addrmode_imm8s4 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
153 let PrintMethod = "printT2AddrModeImm8s4Operand";
154 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
157 def t2am_imm8s4_offset : Operand<i32> {
158 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
161 // t2addrmode_so_reg := reg + (reg << imm2)
162 def t2addrmode_so_reg : Operand<i32>,
163 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
164 let PrintMethod = "printT2AddrModeSoRegOperand";
165 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
169 //===----------------------------------------------------------------------===//
170 // Multiclass helpers...
173 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
174 /// unary operation that produces a value. These are predicable and can be
175 /// changed to modify CPSR.
176 multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode,
177 bit Cheap = 0, bit ReMat = 0> {
179 def i : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
181 [(set rGPR:$dst, (opnode t2_so_imm:$src))]> {
182 let isAsCheapAsAMove = Cheap;
183 let isReMaterializable = ReMat;
184 let Inst{31-27} = 0b11110;
186 let Inst{24-21} = opcod;
187 let Inst{20} = ?; // The S bit.
188 let Inst{19-16} = 0b1111; // Rn
192 def r : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVr,
193 opc, ".w\t$dst, $src",
194 [(set rGPR:$dst, (opnode rGPR:$src))]> {
195 let Inst{31-27} = 0b11101;
196 let Inst{26-25} = 0b01;
197 let Inst{24-21} = opcod;
198 let Inst{20} = ?; // The S bit.
199 let Inst{19-16} = 0b1111; // Rn
200 let Inst{14-12} = 0b000; // imm3
201 let Inst{7-6} = 0b00; // imm2
202 let Inst{5-4} = 0b00; // type
205 def s : T2sI<(outs rGPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
206 opc, ".w\t$dst, $src",
207 [(set rGPR:$dst, (opnode t2_so_reg:$src))]> {
208 let Inst{31-27} = 0b11101;
209 let Inst{26-25} = 0b01;
210 let Inst{24-21} = opcod;
211 let Inst{20} = ?; // The S bit.
212 let Inst{19-16} = 0b1111; // Rn
216 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
217 /// binary operation that produces a value. These are predicable and can be
218 /// changed to modify CPSR.
219 multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
220 bit Commutable = 0, string wide =""> {
222 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
223 opc, "\t$dst, $lhs, $rhs",
224 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> {
225 let Inst{31-27} = 0b11110;
227 let Inst{24-21} = opcod;
228 let Inst{20} = ?; // The S bit.
232 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
233 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
234 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
235 let isCommutable = Commutable;
236 let Inst{31-27} = 0b11101;
237 let Inst{26-25} = 0b01;
238 let Inst{24-21} = opcod;
239 let Inst{20} = ?; // The S bit.
240 let Inst{14-12} = 0b000; // imm3
241 let Inst{7-6} = 0b00; // imm2
242 let Inst{5-4} = 0b00; // type
245 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
246 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
247 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> {
248 let Inst{31-27} = 0b11101;
249 let Inst{26-25} = 0b01;
250 let Inst{24-21} = opcod;
251 let Inst{20} = ?; // The S bit.
255 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
256 // the ".w" prefix to indicate that they are wide.
257 multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
258 bit Commutable = 0> :
259 T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
261 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
262 /// reversed. It doesn't define the 'rr' form since it's handled by its
263 /// T2I_bin_irs counterpart.
264 multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> {
266 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
267 opc, ".w\t$dst, $rhs, $lhs",
268 [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> {
269 let Inst{31-27} = 0b11110;
271 let Inst{24-21} = opcod;
272 let Inst{20} = ?; // The S bit.
276 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
277 opc, "\t$dst, $rhs, $lhs",
278 [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> {
279 let Inst{31-27} = 0b11101;
280 let Inst{26-25} = 0b01;
281 let Inst{24-21} = opcod;
282 let Inst{20} = ?; // The S bit.
286 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
287 /// instruction modifies the CPSR register.
288 let Defs = [CPSR] in {
289 multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
290 bit Commutable = 0> {
292 def ri : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
293 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
294 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
295 let Inst{31-27} = 0b11110;
297 let Inst{24-21} = opcod;
298 let Inst{20} = 1; // The S bit.
302 def rr : T2I<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr,
303 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
304 [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> {
305 let isCommutable = Commutable;
306 let Inst{31-27} = 0b11101;
307 let Inst{26-25} = 0b01;
308 let Inst{24-21} = opcod;
309 let Inst{20} = 1; // The S bit.
310 let Inst{14-12} = 0b000; // imm3
311 let Inst{7-6} = 0b00; // imm2
312 let Inst{5-4} = 0b00; // type
315 def rs : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
316 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
317 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
318 let Inst{31-27} = 0b11101;
319 let Inst{26-25} = 0b01;
320 let Inst{24-21} = opcod;
321 let Inst{20} = 1; // The S bit.
326 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
327 /// patterns for a binary operation that produces a value.
328 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
329 bit Commutable = 0> {
331 def ri : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
332 opc, ".w\t$dst, $lhs, $rhs",
333 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
334 let Inst{31-27} = 0b11110;
337 let Inst{23-21} = op23_21;
338 let Inst{20} = 0; // The S bit.
342 def ri12 : T2I<(outs rGPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
343 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
344 [(set rGPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
345 let Inst{31-27} = 0b11110;
348 let Inst{23-21} = op23_21;
349 let Inst{20} = 0; // The S bit.
353 def rr : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr,
354 opc, ".w\t$dst, $lhs, $rhs",
355 [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> {
356 let isCommutable = Commutable;
357 let Inst{31-27} = 0b11101;
358 let Inst{26-25} = 0b01;
360 let Inst{23-21} = op23_21;
361 let Inst{20} = 0; // The S bit.
362 let Inst{14-12} = 0b000; // imm3
363 let Inst{7-6} = 0b00; // imm2
364 let Inst{5-4} = 0b00; // type
367 def rs : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
368 opc, ".w\t$dst, $lhs, $rhs",
369 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
370 let Inst{31-27} = 0b11101;
371 let Inst{26-25} = 0b01;
373 let Inst{23-21} = op23_21;
374 let Inst{20} = 0; // The S bit.
378 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
379 /// for a binary operation that produces a value and use the carry
380 /// bit. It's not predicable.
381 let Uses = [CPSR] in {
382 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
383 bit Commutable = 0> {
385 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
386 opc, "\t$dst, $lhs, $rhs",
387 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>,
388 Requires<[IsThumb2]> {
389 let Inst{31-27} = 0b11110;
391 let Inst{24-21} = opcod;
392 let Inst{20} = 0; // The S bit.
396 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
397 opc, ".w\t$dst, $lhs, $rhs",
398 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>,
399 Requires<[IsThumb2]> {
400 let isCommutable = Commutable;
401 let Inst{31-27} = 0b11101;
402 let Inst{26-25} = 0b01;
403 let Inst{24-21} = opcod;
404 let Inst{20} = 0; // The S bit.
405 let Inst{14-12} = 0b000; // imm3
406 let Inst{7-6} = 0b00; // imm2
407 let Inst{5-4} = 0b00; // type
410 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
411 opc, ".w\t$dst, $lhs, $rhs",
412 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>,
413 Requires<[IsThumb2]> {
414 let Inst{31-27} = 0b11101;
415 let Inst{26-25} = 0b01;
416 let Inst{24-21} = opcod;
417 let Inst{20} = 0; // The S bit.
421 // Carry setting variants
422 let Defs = [CPSR] in {
423 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
424 bit Commutable = 0> {
426 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
427 opc, "\t$dst, $lhs, $rhs",
428 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>,
429 Requires<[IsThumb2]> {
430 let Inst{31-27} = 0b11110;
432 let Inst{24-21} = opcod;
433 let Inst{20} = 1; // The S bit.
437 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
438 opc, ".w\t$dst, $lhs, $rhs",
439 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>,
440 Requires<[IsThumb2]> {
441 let isCommutable = Commutable;
442 let Inst{31-27} = 0b11101;
443 let Inst{26-25} = 0b01;
444 let Inst{24-21} = opcod;
445 let Inst{20} = 1; // The S bit.
446 let Inst{14-12} = 0b000; // imm3
447 let Inst{7-6} = 0b00; // imm2
448 let Inst{5-4} = 0b00; // type
451 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
452 opc, ".w\t$dst, $lhs, $rhs",
453 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>,
454 Requires<[IsThumb2]> {
455 let Inst{31-27} = 0b11101;
456 let Inst{26-25} = 0b01;
457 let Inst{24-21} = opcod;
458 let Inst{20} = 1; // The S bit.
464 /// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
465 let Defs = [CPSR] in {
466 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
468 def ri : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
469 !strconcat(opc, "s"), ".w\t$dst, $rhs, $lhs",
470 [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> {
471 let Inst{31-27} = 0b11110;
473 let Inst{24-21} = opcod;
474 let Inst{20} = 1; // The S bit.
478 def rs : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
479 !strconcat(opc, "s"), "\t$dst, $rhs, $lhs",
480 [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> {
481 let Inst{31-27} = 0b11101;
482 let Inst{26-25} = 0b01;
483 let Inst{24-21} = opcod;
484 let Inst{20} = 1; // The S bit.
489 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
490 // rotate operation that produces a value.
491 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
493 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
494 opc, ".w\t$dst, $lhs, $rhs",
495 [(set rGPR:$dst, (opnode rGPR:$lhs, imm1_31:$rhs))]> {
496 let Inst{31-27} = 0b11101;
497 let Inst{26-21} = 0b010010;
498 let Inst{19-16} = 0b1111; // Rn
499 let Inst{5-4} = opcod;
502 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iMOVsr,
503 opc, ".w\t$dst, $lhs, $rhs",
504 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
505 let Inst{31-27} = 0b11111;
506 let Inst{26-23} = 0b0100;
507 let Inst{22-21} = opcod;
508 let Inst{15-12} = 0b1111;
509 let Inst{7-4} = 0b0000;
513 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
514 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
515 /// a explicit result, only implicitly set CPSR.
516 let Defs = [CPSR] in {
517 multiclass T2I_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
519 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
520 opc, ".w\t$lhs, $rhs",
521 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> {
522 let Inst{31-27} = 0b11110;
524 let Inst{24-21} = opcod;
525 let Inst{20} = 1; // The S bit.
527 let Inst{11-8} = 0b1111; // Rd
530 def rr : T2I<(outs), (ins GPR:$lhs, rGPR:$rhs), IIC_iCMPr,
531 opc, ".w\t$lhs, $rhs",
532 [(opnode GPR:$lhs, rGPR:$rhs)]> {
533 let Inst{31-27} = 0b11101;
534 let Inst{26-25} = 0b01;
535 let Inst{24-21} = opcod;
536 let Inst{20} = 1; // The S bit.
537 let Inst{14-12} = 0b000; // imm3
538 let Inst{11-8} = 0b1111; // Rd
539 let Inst{7-6} = 0b00; // imm2
540 let Inst{5-4} = 0b00; // type
543 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
544 opc, ".w\t$lhs, $rhs",
545 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> {
546 let Inst{31-27} = 0b11101;
547 let Inst{26-25} = 0b01;
548 let Inst{24-21} = opcod;
549 let Inst{20} = 1; // The S bit.
550 let Inst{11-8} = 0b1111; // Rd
555 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
556 multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> {
557 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
558 opc, ".w\t$dst, $addr",
559 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
560 let Inst{31-27} = 0b11111;
561 let Inst{26-25} = 0b00;
562 let Inst{24} = signed;
564 let Inst{22-21} = opcod;
565 let Inst{20} = 1; // load
567 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
568 opc, "\t$dst, $addr",
569 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
570 let Inst{31-27} = 0b11111;
571 let Inst{26-25} = 0b00;
572 let Inst{24} = signed;
574 let Inst{22-21} = opcod;
575 let Inst{20} = 1; // load
577 // Offset: index==TRUE, wback==FALSE
578 let Inst{10} = 1; // The P bit.
579 let Inst{8} = 0; // The W bit.
581 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
582 opc, ".w\t$dst, $addr",
583 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
584 let Inst{31-27} = 0b11111;
585 let Inst{26-25} = 0b00;
586 let Inst{24} = signed;
588 let Inst{22-21} = opcod;
589 let Inst{20} = 1; // load
590 let Inst{11-6} = 0b000000;
592 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
593 opc, ".w\t$dst, $addr",
594 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
595 let isReMaterializable = 1;
596 let Inst{31-27} = 0b11111;
597 let Inst{26-25} = 0b00;
598 let Inst{24} = signed;
599 let Inst{23} = ?; // add = (U == '1')
600 let Inst{22-21} = opcod;
601 let Inst{20} = 1; // load
602 let Inst{19-16} = 0b1111; // Rn
606 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
607 multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> {
608 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
609 opc, ".w\t$src, $addr",
610 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
611 let Inst{31-27} = 0b11111;
612 let Inst{26-23} = 0b0001;
613 let Inst{22-21} = opcod;
614 let Inst{20} = 0; // !load
616 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
617 opc, "\t$src, $addr",
618 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
619 let Inst{31-27} = 0b11111;
620 let Inst{26-23} = 0b0000;
621 let Inst{22-21} = opcod;
622 let Inst{20} = 0; // !load
624 // Offset: index==TRUE, wback==FALSE
625 let Inst{10} = 1; // The P bit.
626 let Inst{8} = 0; // The W bit.
628 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
629 opc, ".w\t$src, $addr",
630 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
631 let Inst{31-27} = 0b11111;
632 let Inst{26-23} = 0b0000;
633 let Inst{22-21} = opcod;
634 let Inst{20} = 0; // !load
635 let Inst{11-6} = 0b000000;
639 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
640 /// register and one whose operand is a register rotated by 8/16/24.
641 multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
642 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
643 opc, ".w\t$dst, $src",
644 [(set rGPR:$dst, (opnode rGPR:$src))]> {
645 let Inst{31-27} = 0b11111;
646 let Inst{26-23} = 0b0100;
647 let Inst{22-20} = opcod;
648 let Inst{19-16} = 0b1111; // Rn
649 let Inst{15-12} = 0b1111;
651 let Inst{5-4} = 0b00; // rotate
653 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
654 opc, ".w\t$dst, $src, ror $rot",
655 [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]> {
656 let Inst{31-27} = 0b11111;
657 let Inst{26-23} = 0b0100;
658 let Inst{22-20} = opcod;
659 let Inst{19-16} = 0b1111; // Rn
660 let Inst{15-12} = 0b1111;
662 let Inst{5-4} = {?,?}; // rotate
666 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
667 multiclass T2I_unary_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
668 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
670 [(set rGPR:$dst, (opnode rGPR:$src))]>,
671 Requires<[HasT2ExtractPack]> {
672 let Inst{31-27} = 0b11111;
673 let Inst{26-23} = 0b0100;
674 let Inst{22-20} = opcod;
675 let Inst{19-16} = 0b1111; // Rn
676 let Inst{15-12} = 0b1111;
678 let Inst{5-4} = 0b00; // rotate
680 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
681 opc, "\t$dst, $src, ror $rot",
682 [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]>,
683 Requires<[HasT2ExtractPack]> {
684 let Inst{31-27} = 0b11111;
685 let Inst{26-23} = 0b0100;
686 let Inst{22-20} = opcod;
687 let Inst{19-16} = 0b1111; // Rn
688 let Inst{15-12} = 0b1111;
690 let Inst{5-4} = {?,?}; // rotate
694 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
696 multiclass T2I_unary_rrot_sxtb16<bits<3> opcod, string opc> {
697 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
698 opc, "\t$dst, $src", []> {
699 let Inst{31-27} = 0b11111;
700 let Inst{26-23} = 0b0100;
701 let Inst{22-20} = opcod;
702 let Inst{19-16} = 0b1111; // Rn
703 let Inst{15-12} = 0b1111;
705 let Inst{5-4} = 0b00; // rotate
707 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
708 opc, "\t$dst, $src, ror $rot", []> {
709 let Inst{31-27} = 0b11111;
710 let Inst{26-23} = 0b0100;
711 let Inst{22-20} = opcod;
712 let Inst{19-16} = 0b1111; // Rn
713 let Inst{15-12} = 0b1111;
715 let Inst{5-4} = {?,?}; // rotate
719 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
720 /// register and one whose operand is a register rotated by 8/16/24.
721 multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
722 def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iALUr,
723 opc, "\t$dst, $LHS, $RHS",
724 [(set rGPR:$dst, (opnode rGPR:$LHS, rGPR:$RHS))]>,
725 Requires<[HasT2ExtractPack]> {
726 let Inst{31-27} = 0b11111;
727 let Inst{26-23} = 0b0100;
728 let Inst{22-20} = opcod;
729 let Inst{15-12} = 0b1111;
731 let Inst{5-4} = 0b00; // rotate
733 def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot),
734 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
735 [(set rGPR:$dst, (opnode rGPR:$LHS,
736 (rotr rGPR:$RHS, rot_imm:$rot)))]>,
737 Requires<[HasT2ExtractPack]> {
738 let Inst{31-27} = 0b11111;
739 let Inst{26-23} = 0b0100;
740 let Inst{22-20} = opcod;
741 let Inst{15-12} = 0b1111;
743 let Inst{5-4} = {?,?}; // rotate
747 // DO variant - disassembly only, no pattern
749 multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> {
750 def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iALUr,
751 opc, "\t$dst, $LHS, $RHS", []> {
752 let Inst{31-27} = 0b11111;
753 let Inst{26-23} = 0b0100;
754 let Inst{22-20} = opcod;
755 let Inst{15-12} = 0b1111;
757 let Inst{5-4} = 0b00; // rotate
759 def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot),
760 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> {
761 let Inst{31-27} = 0b11111;
762 let Inst{26-23} = 0b0100;
763 let Inst{22-20} = opcod;
764 let Inst{15-12} = 0b1111;
766 let Inst{5-4} = {?,?}; // rotate
770 //===----------------------------------------------------------------------===//
772 //===----------------------------------------------------------------------===//
774 //===----------------------------------------------------------------------===//
775 // Miscellaneous Instructions.
778 // LEApcrel - Load a pc-relative address into a register without offending the
780 let neverHasSideEffects = 1 in {
781 let isReMaterializable = 1 in
782 def t2LEApcrel : T2XI<(outs rGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
783 "adr$p.w\t$dst, #$label", []> {
784 let Inst{31-27} = 0b11110;
785 let Inst{25-24} = 0b10;
786 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
789 let Inst{19-16} = 0b1111; // Rn
792 } // neverHasSideEffects
793 def t2LEApcrelJT : T2XI<(outs rGPR:$dst),
794 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
795 "adr$p.w\t$dst, #${label}_${id}", []> {
796 let Inst{31-27} = 0b11110;
797 let Inst{25-24} = 0b10;
798 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
801 let Inst{19-16} = 0b1111; // Rn
805 // ADD r, sp, {so_imm|i12}
806 def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
807 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> {
808 let Inst{31-27} = 0b11110;
810 let Inst{24-21} = 0b1000;
811 let Inst{20} = ?; // The S bit.
812 let Inst{19-16} = 0b1101; // Rn = sp
815 def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
816 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> {
817 let Inst{31-27} = 0b11110;
819 let Inst{24-21} = 0b0000;
820 let Inst{20} = 0; // The S bit.
821 let Inst{19-16} = 0b1101; // Rn = sp
826 def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
827 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> {
828 let Inst{31-27} = 0b11101;
829 let Inst{26-25} = 0b01;
830 let Inst{24-21} = 0b1000;
831 let Inst{20} = ?; // The S bit.
832 let Inst{19-16} = 0b1101; // Rn = sp
836 // SUB r, sp, {so_imm|i12}
837 def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
838 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> {
839 let Inst{31-27} = 0b11110;
841 let Inst{24-21} = 0b1101;
842 let Inst{20} = ?; // The S bit.
843 let Inst{19-16} = 0b1101; // Rn = sp
846 def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
847 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> {
848 let Inst{31-27} = 0b11110;
850 let Inst{24-21} = 0b0101;
851 let Inst{20} = 0; // The S bit.
852 let Inst{19-16} = 0b1101; // Rn = sp
857 def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
859 "sub", "\t$dst, $sp, $rhs", []> {
860 let Inst{31-27} = 0b11101;
861 let Inst{26-25} = 0b01;
862 let Inst{24-21} = 0b1101;
863 let Inst{20} = ?; // The S bit.
864 let Inst{19-16} = 0b1101; // Rn = sp
868 // Signed and unsigned division on v7-M
869 def t2SDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
870 "sdiv", "\t$dst, $a, $b",
871 [(set rGPR:$dst, (sdiv rGPR:$a, rGPR:$b))]>,
872 Requires<[HasDivide]> {
873 let Inst{31-27} = 0b11111;
874 let Inst{26-21} = 0b011100;
876 let Inst{15-12} = 0b1111;
877 let Inst{7-4} = 0b1111;
880 def t2UDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
881 "udiv", "\t$dst, $a, $b",
882 [(set rGPR:$dst, (udiv rGPR:$a, rGPR:$b))]>,
883 Requires<[HasDivide]> {
884 let Inst{31-27} = 0b11111;
885 let Inst{26-21} = 0b011101;
887 let Inst{15-12} = 0b1111;
888 let Inst{7-4} = 0b1111;
891 // Pseudo instruction that will expand into a t2SUBrSPi + a copy.
892 // FIXME: Now that we have rGPR, do we need these pseudos? It seems
893 // that the coalescer will now properly know how to do the right
894 // thing without them.
895 let usesCustomInserter = 1 in { // Expanded after instruction selection.
896 def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
897 NoItinerary, "${:comment} sub.w\t$dst, $sp, $imm", []>;
898 def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
899 NoItinerary, "${:comment} subw\t$dst, $sp, $imm", []>;
900 def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
901 NoItinerary, "${:comment} sub\t$dst, $sp, $rhs", []>;
902 } // usesCustomInserter
905 //===----------------------------------------------------------------------===//
906 // Load / store Instructions.
910 let canFoldAsLoad = 1, isReMaterializable = 1 in
911 defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>;
913 // Loads with zero extension
914 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
915 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
917 // Loads with sign extension
918 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
919 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
921 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
923 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
924 (ins t2addrmode_imm8s4:$addr),
925 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
926 def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
927 (ins i32imm:$addr), IIC_iLoadi,
928 "ldrd", "\t$dst1, $addr", []> {
929 let Inst{19-16} = 0b1111; // Rn
931 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
933 // zextload i1 -> zextload i8
934 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
935 (t2LDRBi12 t2addrmode_imm12:$addr)>;
936 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
937 (t2LDRBi8 t2addrmode_imm8:$addr)>;
938 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
939 (t2LDRBs t2addrmode_so_reg:$addr)>;
940 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
941 (t2LDRBpci tconstpool:$addr)>;
943 // extload -> zextload
944 // FIXME: Reduce the number of patterns by legalizing extload to zextload
946 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
947 (t2LDRBi12 t2addrmode_imm12:$addr)>;
948 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
949 (t2LDRBi8 t2addrmode_imm8:$addr)>;
950 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
951 (t2LDRBs t2addrmode_so_reg:$addr)>;
952 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
953 (t2LDRBpci tconstpool:$addr)>;
955 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
956 (t2LDRBi12 t2addrmode_imm12:$addr)>;
957 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
958 (t2LDRBi8 t2addrmode_imm8:$addr)>;
959 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
960 (t2LDRBs t2addrmode_so_reg:$addr)>;
961 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
962 (t2LDRBpci tconstpool:$addr)>;
964 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
965 (t2LDRHi12 t2addrmode_imm12:$addr)>;
966 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
967 (t2LDRHi8 t2addrmode_imm8:$addr)>;
968 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
969 (t2LDRHs t2addrmode_so_reg:$addr)>;
970 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
971 (t2LDRHpci tconstpool:$addr)>;
973 // FIXME: The destination register of the loads and stores can't be PC, but
974 // can be SP. We need another regclass (similar to rGPR) to represent
975 // that. Not a pressing issue since these are selected manually,
979 let mayLoad = 1, neverHasSideEffects = 1 in {
980 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
981 (ins t2addrmode_imm8:$addr),
982 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
983 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
986 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb),
987 (ins GPR:$base, t2am_imm8_offset:$offset),
988 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
989 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
992 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
993 (ins t2addrmode_imm8:$addr),
994 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
995 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
997 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
998 (ins GPR:$base, t2am_imm8_offset:$offset),
999 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1000 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
1003 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1004 (ins t2addrmode_imm8:$addr),
1005 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1006 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
1008 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1009 (ins GPR:$base, t2am_imm8_offset:$offset),
1010 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1011 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
1014 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1015 (ins t2addrmode_imm8:$addr),
1016 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1017 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
1019 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1020 (ins GPR:$base, t2am_imm8_offset:$offset),
1021 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1022 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
1025 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1026 (ins t2addrmode_imm8:$addr),
1027 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1028 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
1030 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1031 (ins GPR:$base, t2am_imm8_offset:$offset),
1032 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1033 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
1035 } // mayLoad = 1, neverHasSideEffects = 1
1037 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1038 // for disassembly only.
1039 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1040 class T2IldT<bit signed, bits<2> type, string opc>
1041 : T2Ii8<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, opc,
1042 "\t$dst, $addr", []> {
1043 let Inst{31-27} = 0b11111;
1044 let Inst{26-25} = 0b00;
1045 let Inst{24} = signed;
1047 let Inst{22-21} = type;
1048 let Inst{20} = 1; // load
1050 let Inst{10-8} = 0b110; // PUW.
1053 def t2LDRT : T2IldT<0, 0b10, "ldrt">;
1054 def t2LDRBT : T2IldT<0, 0b00, "ldrbt">;
1055 def t2LDRHT : T2IldT<0, 0b01, "ldrht">;
1056 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt">;
1057 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht">;
1060 defm t2STR :T2I_st<0b10,"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
1061 defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1062 defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1065 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1066 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1067 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
1068 IIC_iStorer, "strd", "\t$src1, $addr", []>;
1071 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1072 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1073 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1074 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1076 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1078 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1079 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1080 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1081 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1083 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1085 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1086 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1087 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1088 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1090 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1092 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1093 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1094 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1095 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1097 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1099 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1100 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1101 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1102 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1104 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1106 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1107 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1108 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1109 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1111 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1113 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1115 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1116 class T2IstT<bits<2> type, string opc>
1117 : T2Ii8<(outs GPR:$src), (ins t2addrmode_imm8:$addr), IIC_iStorei, opc,
1118 "\t$src, $addr", []> {
1119 let Inst{31-27} = 0b11111;
1120 let Inst{26-25} = 0b00;
1121 let Inst{24} = 0; // not signed
1123 let Inst{22-21} = type;
1124 let Inst{20} = 0; // store
1126 let Inst{10-8} = 0b110; // PUW
1129 def t2STRT : T2IstT<0b10, "strt">;
1130 def t2STRBT : T2IstT<0b00, "strbt">;
1131 def t2STRHT : T2IstT<0b01, "strht">;
1133 // ldrd / strd pre / post variants
1134 // For disassembly only.
1136 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1137 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1138 "ldrd", "\t$dst1, $dst2, [$base, $imm]!", []>;
1140 def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1141 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1142 "ldrd", "\t$dst1, $dst2, [$base], $imm", []>;
1144 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
1145 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1146 NoItinerary, "strd", "\t$src1, $src2, [$base, $imm]!", []>;
1148 def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1149 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1150 NoItinerary, "strd", "\t$src1, $src2, [$base], $imm", []>;
1152 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1153 // data/instruction access. These are for disassembly only.
1155 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
1156 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
1157 multiclass T2Ipl<bit instr, bit write, string opc> {
1159 def i12 : T2I<(outs), (ins GPR:$base, i32imm:$imm), IIC_iLoadi, opc,
1160 "\t[$base, $imm]", []> {
1161 let Inst{31-25} = 0b1111100;
1162 let Inst{24} = instr;
1163 let Inst{23} = 1; // U = 1
1165 let Inst{21} = write;
1167 let Inst{15-12} = 0b1111;
1170 def i8 : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1171 "\t[$base, $imm]", []> {
1172 let Inst{31-25} = 0b1111100;
1173 let Inst{24} = instr;
1174 let Inst{23} = 0; // U = 0
1176 let Inst{21} = write;
1178 let Inst{15-12} = 0b1111;
1179 let Inst{11-8} = 0b1100;
1182 def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1183 "\t[pc, $imm]", []> {
1184 let Inst{31-25} = 0b1111100;
1185 let Inst{24} = instr;
1186 let Inst{23} = ?; // add = (U == 1)
1188 let Inst{21} = write;
1190 let Inst{19-16} = 0b1111; // Rn = 0b1111
1191 let Inst{15-12} = 0b1111;
1194 def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoadi, opc,
1195 "\t[$base, $a]", []> {
1196 let Inst{31-25} = 0b1111100;
1197 let Inst{24} = instr;
1198 let Inst{23} = 0; // add = TRUE for T1
1200 let Inst{21} = write;
1202 let Inst{15-12} = 0b1111;
1203 let Inst{11-6} = 0000000;
1204 let Inst{5-4} = 0b00; // no shift is applied
1207 def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoadi, opc,
1208 "\t[$base, $a, lsl $shamt]", []> {
1209 let Inst{31-25} = 0b1111100;
1210 let Inst{24} = instr;
1211 let Inst{23} = 0; // add = TRUE for T1
1213 let Inst{21} = write;
1215 let Inst{15-12} = 0b1111;
1216 let Inst{11-6} = 0000000;
1220 defm t2PLD : T2Ipl<0, 0, "pld">;
1221 defm t2PLDW : T2Ipl<0, 1, "pldw">;
1222 defm t2PLI : T2Ipl<1, 0, "pli">;
1224 //===----------------------------------------------------------------------===//
1225 // Load / store multiple Instructions.
1228 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1229 def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1230 reglist:$dsts, variable_ops), IIC_iLoadm,
1231 "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> {
1232 let Inst{31-27} = 0b11101;
1233 let Inst{26-25} = 0b00;
1234 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1236 let Inst{21} = 0; // The W bit.
1237 let Inst{20} = 1; // Load
1240 def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1241 reglist:$dsts, variable_ops), IIC_iLoadm,
1242 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
1243 "$addr.addr = $wb", []> {
1244 let Inst{31-27} = 0b11101;
1245 let Inst{26-25} = 0b00;
1246 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1248 let Inst{21} = 1; // The W bit.
1249 let Inst{20} = 1; // Load
1251 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1253 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1254 def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1255 reglist:$srcs, variable_ops), IIC_iStorem,
1256 "stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> {
1257 let Inst{31-27} = 0b11101;
1258 let Inst{26-25} = 0b00;
1259 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1261 let Inst{21} = 0; // The W bit.
1262 let Inst{20} = 0; // Store
1265 def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1266 reglist:$srcs, variable_ops),
1268 "stm${addr:submode}${p}${addr:wide}\t$addr!, $srcs",
1269 "$addr.addr = $wb", []> {
1270 let Inst{31-27} = 0b11101;
1271 let Inst{26-25} = 0b00;
1272 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1274 let Inst{21} = 1; // The W bit.
1275 let Inst{20} = 0; // Store
1277 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1279 //===----------------------------------------------------------------------===//
1280 // Move Instructions.
1283 let neverHasSideEffects = 1 in
1284 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
1285 "mov", ".w\t$dst, $src", []> {
1286 let Inst{31-27} = 0b11101;
1287 let Inst{26-25} = 0b01;
1288 let Inst{24-21} = 0b0010;
1289 let Inst{20} = ?; // The S bit.
1290 let Inst{19-16} = 0b1111; // Rn
1291 let Inst{14-12} = 0b000;
1292 let Inst{7-4} = 0b0000;
1295 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1296 let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
1297 def t2MOVi : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
1298 "mov", ".w\t$dst, $src",
1299 [(set rGPR:$dst, t2_so_imm:$src)]> {
1300 let Inst{31-27} = 0b11110;
1302 let Inst{24-21} = 0b0010;
1303 let Inst{20} = ?; // The S bit.
1304 let Inst{19-16} = 0b1111; // Rn
1308 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1309 def t2MOVi16 : T2I<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1310 "movw", "\t$dst, $src",
1311 [(set rGPR:$dst, imm0_65535:$src)]> {
1312 let Inst{31-27} = 0b11110;
1314 let Inst{24-21} = 0b0010;
1315 let Inst{20} = 0; // The S bit.
1319 let Constraints = "$src = $dst" in
1320 def t2MOVTi16 : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$imm), IIC_iMOVi,
1321 "movt", "\t$dst, $imm",
1323 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1324 let Inst{31-27} = 0b11110;
1326 let Inst{24-21} = 0b0110;
1327 let Inst{20} = 0; // The S bit.
1331 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1333 //===----------------------------------------------------------------------===//
1334 // Extend Instructions.
1339 defm t2SXTB : T2I_unary_rrot<0b100, "sxtb",
1340 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1341 defm t2SXTH : T2I_unary_rrot<0b000, "sxth",
1342 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1343 defm t2SXTB16 : T2I_unary_rrot_sxtb16<0b010, "sxtb16">;
1345 defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab",
1346 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1347 defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah",
1348 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1349 defm t2SXTAB16 : T2I_bin_rrot_DO<0b010, "sxtab16">;
1351 // TODO: SXT(A){B|H}16 - done for disassembly only
1355 let AddedComplexity = 16 in {
1356 defm t2UXTB : T2I_unary_rrot<0b101, "uxtb",
1357 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1358 defm t2UXTH : T2I_unary_rrot<0b001, "uxth",
1359 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1360 defm t2UXTB16 : T2I_unary_rrot_uxtb16<0b011, "uxtb16",
1361 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1363 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1364 // The transformation should probably be done as a combiner action
1365 // instead so we can include a check for masking back in the upper
1366 // eight bits of the source into the lower eight bits of the result.
1367 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1368 // (t2UXTB16r_rot rGPR:$Src, 24)>, Requires<[HasT2ExtractPack]>;
1369 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1370 (t2UXTB16r_rot rGPR:$Src, 8)>, Requires<[HasT2ExtractPack]>;
1372 defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
1373 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1374 defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah",
1375 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1376 defm t2UXTAB16 : T2I_bin_rrot_DO<0b011, "uxtab16">;
1379 //===----------------------------------------------------------------------===//
1380 // Arithmetic Instructions.
1383 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1384 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1385 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1386 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1388 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1389 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1390 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1391 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1392 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1394 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1395 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1396 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1397 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1398 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1399 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1400 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1401 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1404 defm t2RSB : T2I_rbin_is <0b1110, "rsb",
1405 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1406 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1407 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1409 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1410 // The assume-no-carry-in form uses the negation of the input since add/sub
1411 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1412 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1414 // The AddedComplexity preferences the first variant over the others since
1415 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1416 let AddedComplexity = 1 in
1417 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1418 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1419 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1420 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1421 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1422 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1423 let AddedComplexity = 1 in
1424 def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm),
1425 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1426 def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm),
1427 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1428 // The with-carry-in form matches bitwise not instead of the negation.
1429 // Effectively, the inverse interpretation of the carry flag already accounts
1430 // for part of the negation.
1431 let AddedComplexity = 1 in
1432 def : T2Pat<(adde rGPR:$src, imm0_255_not:$imm),
1433 (t2SBCSri rGPR:$src, imm0_255_not:$imm)>;
1434 def : T2Pat<(adde rGPR:$src, t2_so_imm_not:$imm),
1435 (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>;
1437 // Select Bytes -- for disassembly only
1439 def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel",
1440 "\t$dst, $a, $b", []> {
1441 let Inst{31-27} = 0b11111;
1442 let Inst{26-24} = 0b010;
1444 let Inst{22-20} = 0b010;
1445 let Inst{15-12} = 0b1111;
1447 let Inst{6-4} = 0b000;
1450 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1451 // And Miscellaneous operations -- for disassembly only
1452 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1453 list<dag> pat = [/* For disassembly only; pattern left blank */]>
1454 : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), NoItinerary, opc,
1455 "\t$dst, $a, $b", pat> {
1456 let Inst{31-27} = 0b11111;
1457 let Inst{26-23} = 0b0101;
1458 let Inst{22-20} = op22_20;
1459 let Inst{15-12} = 0b1111;
1460 let Inst{7-4} = op7_4;
1463 // Saturating add/subtract -- for disassembly only
1465 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1466 [(set rGPR:$dst, (int_arm_qadd rGPR:$a, rGPR:$b))]>;
1467 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1468 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1469 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1470 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1471 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1472 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1473 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1474 [(set rGPR:$dst, (int_arm_qsub rGPR:$a, rGPR:$b))]>;
1475 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1476 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1477 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1478 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1479 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1480 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1481 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1482 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1484 // Signed/Unsigned add/subtract -- for disassembly only
1486 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1487 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1488 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1489 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1490 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1491 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1492 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1493 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1494 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1495 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1496 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1497 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1499 // Signed/Unsigned halving add/subtract -- for disassembly only
1501 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1502 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1503 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1504 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1505 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1506 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1507 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1508 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1509 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1510 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1511 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1512 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1514 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1516 def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst),
1517 (ins rGPR:$a, rGPR:$b),
1518 NoItinerary, "usad8", "\t$dst, $a, $b", []> {
1519 let Inst{15-12} = 0b1111;
1521 def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst),
1522 (ins rGPR:$a, rGPR:$b, rGPR:$acc), NoItinerary, "usada8",
1523 "\t$dst, $a, $b, $acc", []>;
1525 // Signed/Unsigned saturate -- for disassembly only
1527 def t2SSATlsl:T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos,rGPR:$a,i32imm:$shamt),
1528 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
1529 [/* For disassembly only; pattern left blank */]> {
1530 let Inst{31-27} = 0b11110;
1531 let Inst{25-22} = 0b1100;
1534 let Inst{21} = 0; // sh = '0'
1537 def t2SSATasr:T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos,rGPR:$a,i32imm:$shamt),
1538 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt",
1539 [/* For disassembly only; pattern left blank */]> {
1540 let Inst{31-27} = 0b11110;
1541 let Inst{25-22} = 0b1100;
1544 let Inst{21} = 1; // sh = '1'
1547 def t2SSAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary,
1548 "ssat16", "\t$dst, $bit_pos, $a",
1549 [/* For disassembly only; pattern left blank */]> {
1550 let Inst{31-27} = 0b11110;
1551 let Inst{25-22} = 0b1100;
1554 let Inst{21} = 1; // sh = '1'
1555 let Inst{14-12} = 0b000; // imm3 = '000'
1556 let Inst{7-6} = 0b00; // imm2 = '00'
1559 def t2USATlsl:T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos,rGPR:$a,i32imm:$shamt),
1560 NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt",
1561 [/* For disassembly only; pattern left blank */]> {
1562 let Inst{31-27} = 0b11110;
1563 let Inst{25-22} = 0b1110;
1566 let Inst{21} = 0; // sh = '0'
1569 def t2USATasr:T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos,rGPR:$a,i32imm:$shamt),
1570 NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt",
1571 [/* For disassembly only; pattern left blank */]> {
1572 let Inst{31-27} = 0b11110;
1573 let Inst{25-22} = 0b1110;
1576 let Inst{21} = 1; // sh = '1'
1579 def t2USAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary,
1580 "usat16", "\t$dst, $bit_pos, $a",
1581 [/* For disassembly only; pattern left blank */]> {
1582 let Inst{31-27} = 0b11110;
1583 let Inst{25-22} = 0b1110;
1586 let Inst{21} = 1; // sh = '1'
1587 let Inst{14-12} = 0b000; // imm3 = '000'
1588 let Inst{7-6} = 0b00; // imm2 = '00'
1591 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSATlsl imm:$pos, GPR:$a, 0)>;
1592 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USATlsl imm:$pos, GPR:$a, 0)>;
1594 //===----------------------------------------------------------------------===//
1595 // Shift and rotate Instructions.
1598 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1599 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1600 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1601 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1603 let Uses = [CPSR] in {
1604 def t2MOVrx : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1605 "rrx", "\t$dst, $src",
1606 [(set rGPR:$dst, (ARMrrx rGPR:$src))]> {
1607 let Inst{31-27} = 0b11101;
1608 let Inst{26-25} = 0b01;
1609 let Inst{24-21} = 0b0010;
1610 let Inst{20} = ?; // The S bit.
1611 let Inst{19-16} = 0b1111; // Rn
1612 let Inst{14-12} = 0b000;
1613 let Inst{7-4} = 0b0011;
1617 let Defs = [CPSR] in {
1618 def t2MOVsrl_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1619 "lsrs", ".w\t$dst, $src, #1",
1620 [(set rGPR:$dst, (ARMsrl_flag rGPR:$src))]> {
1621 let Inst{31-27} = 0b11101;
1622 let Inst{26-25} = 0b01;
1623 let Inst{24-21} = 0b0010;
1624 let Inst{20} = 1; // The S bit.
1625 let Inst{19-16} = 0b1111; // Rn
1626 let Inst{5-4} = 0b01; // Shift type.
1627 // Shift amount = Inst{14-12:7-6} = 1.
1628 let Inst{14-12} = 0b000;
1629 let Inst{7-6} = 0b01;
1631 def t2MOVsra_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1632 "asrs", ".w\t$dst, $src, #1",
1633 [(set rGPR:$dst, (ARMsra_flag rGPR:$src))]> {
1634 let Inst{31-27} = 0b11101;
1635 let Inst{26-25} = 0b01;
1636 let Inst{24-21} = 0b0010;
1637 let Inst{20} = 1; // The S bit.
1638 let Inst{19-16} = 0b1111; // Rn
1639 let Inst{5-4} = 0b10; // Shift type.
1640 // Shift amount = Inst{14-12:7-6} = 1.
1641 let Inst{14-12} = 0b000;
1642 let Inst{7-6} = 0b01;
1646 //===----------------------------------------------------------------------===//
1647 // Bitwise Instructions.
1650 defm t2AND : T2I_bin_w_irs<0b0000, "and",
1651 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1652 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1653 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1654 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1655 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1657 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1658 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1660 let Constraints = "$src = $dst" in
1661 def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm),
1662 IIC_iUNAsi, "bfc", "\t$dst, $imm",
1663 [(set rGPR:$dst, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
1664 let Inst{31-27} = 0b11110;
1666 let Inst{24-20} = 0b10110;
1667 let Inst{19-16} = 0b1111; // Rn
1671 def t2SBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
1672 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
1673 let Inst{31-27} = 0b11110;
1675 let Inst{24-20} = 0b10100;
1679 def t2UBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
1680 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
1681 let Inst{31-27} = 0b11110;
1683 let Inst{24-20} = 0b11100;
1687 // A8.6.18 BFI - Bitfield insert (Encoding T1)
1688 let Constraints = "$src = $dst" in
1689 def t2BFI : T2I<(outs rGPR:$dst),
1690 (ins rGPR:$src, rGPR:$val, bf_inv_mask_imm:$imm),
1691 IIC_iALUi, "bfi", "\t$dst, $val, $imm",
1692 [(set rGPR:$dst, (ARMbfi rGPR:$src, rGPR:$val,
1693 bf_inv_mask_imm:$imm))]> {
1694 let Inst{31-27} = 0b11110;
1696 let Inst{24-20} = 0b10110;
1700 defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS,
1703 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
1704 let AddedComplexity = 1 in
1705 defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
1708 let AddedComplexity = 1 in
1709 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
1710 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
1712 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
1713 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
1714 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
1715 Requires<[IsThumb2]>;
1717 def : T2Pat<(t2_so_imm_not:$src),
1718 (t2MVNi t2_so_imm_not:$src)>;
1720 //===----------------------------------------------------------------------===//
1721 // Multiply Instructions.
1723 let isCommutable = 1 in
1724 def t2MUL: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1725 "mul", "\t$dst, $a, $b",
1726 [(set rGPR:$dst, (mul rGPR:$a, rGPR:$b))]> {
1727 let Inst{31-27} = 0b11111;
1728 let Inst{26-23} = 0b0110;
1729 let Inst{22-20} = 0b000;
1730 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1731 let Inst{7-4} = 0b0000; // Multiply
1734 def t2MLA: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1735 "mla", "\t$dst, $a, $b, $c",
1736 [(set rGPR:$dst, (add (mul rGPR:$a, rGPR:$b), rGPR:$c))]> {
1737 let Inst{31-27} = 0b11111;
1738 let Inst{26-23} = 0b0110;
1739 let Inst{22-20} = 0b000;
1740 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1741 let Inst{7-4} = 0b0000; // Multiply
1744 def t2MLS: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1745 "mls", "\t$dst, $a, $b, $c",
1746 [(set rGPR:$dst, (sub rGPR:$c, (mul rGPR:$a, rGPR:$b)))]> {
1747 let Inst{31-27} = 0b11111;
1748 let Inst{26-23} = 0b0110;
1749 let Inst{22-20} = 0b000;
1750 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1751 let Inst{7-4} = 0b0001; // Multiply and Subtract
1754 // Extra precision multiplies with low / high results
1755 let neverHasSideEffects = 1 in {
1756 let isCommutable = 1 in {
1757 def t2SMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
1758 "smull", "\t$ldst, $hdst, $a, $b", []> {
1759 let Inst{31-27} = 0b11111;
1760 let Inst{26-23} = 0b0111;
1761 let Inst{22-20} = 0b000;
1762 let Inst{7-4} = 0b0000;
1765 def t2UMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
1766 "umull", "\t$ldst, $hdst, $a, $b", []> {
1767 let Inst{31-27} = 0b11111;
1768 let Inst{26-23} = 0b0111;
1769 let Inst{22-20} = 0b010;
1770 let Inst{7-4} = 0b0000;
1774 // Multiply + accumulate
1775 def t2SMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1776 "smlal", "\t$ldst, $hdst, $a, $b", []>{
1777 let Inst{31-27} = 0b11111;
1778 let Inst{26-23} = 0b0111;
1779 let Inst{22-20} = 0b100;
1780 let Inst{7-4} = 0b0000;
1783 def t2UMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1784 "umlal", "\t$ldst, $hdst, $a, $b", []>{
1785 let Inst{31-27} = 0b11111;
1786 let Inst{26-23} = 0b0111;
1787 let Inst{22-20} = 0b110;
1788 let Inst{7-4} = 0b0000;
1791 def t2UMAAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1792 "umaal", "\t$ldst, $hdst, $a, $b", []>{
1793 let Inst{31-27} = 0b11111;
1794 let Inst{26-23} = 0b0111;
1795 let Inst{22-20} = 0b110;
1796 let Inst{7-4} = 0b0110;
1798 } // neverHasSideEffects
1800 // Rounding variants of the below included for disassembly only
1802 // Most significant word multiply
1803 def t2SMMUL : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1804 "smmul", "\t$dst, $a, $b",
1805 [(set rGPR:$dst, (mulhs rGPR:$a, rGPR:$b))]> {
1806 let Inst{31-27} = 0b11111;
1807 let Inst{26-23} = 0b0110;
1808 let Inst{22-20} = 0b101;
1809 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1810 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1813 def t2SMMULR : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1814 "smmulr", "\t$dst, $a, $b", []> {
1815 let Inst{31-27} = 0b11111;
1816 let Inst{26-23} = 0b0110;
1817 let Inst{22-20} = 0b101;
1818 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1819 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1822 def t2SMMLA : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1823 "smmla", "\t$dst, $a, $b, $c",
1824 [(set rGPR:$dst, (add (mulhs rGPR:$a, rGPR:$b), rGPR:$c))]> {
1825 let Inst{31-27} = 0b11111;
1826 let Inst{26-23} = 0b0110;
1827 let Inst{22-20} = 0b101;
1828 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1829 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1832 def t2SMMLAR : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1833 "smmlar", "\t$dst, $a, $b, $c", []> {
1834 let Inst{31-27} = 0b11111;
1835 let Inst{26-23} = 0b0110;
1836 let Inst{22-20} = 0b101;
1837 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1838 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1841 def t2SMMLS : T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1842 "smmls", "\t$dst, $a, $b, $c",
1843 [(set rGPR:$dst, (sub rGPR:$c, (mulhs rGPR:$a, rGPR:$b)))]> {
1844 let Inst{31-27} = 0b11111;
1845 let Inst{26-23} = 0b0110;
1846 let Inst{22-20} = 0b110;
1847 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1848 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1851 def t2SMMLSR : T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1852 "smmlsr", "\t$dst, $a, $b, $c", []> {
1853 let Inst{31-27} = 0b11111;
1854 let Inst{26-23} = 0b0110;
1855 let Inst{22-20} = 0b110;
1856 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1857 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1860 multiclass T2I_smul<string opc, PatFrag opnode> {
1861 def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1862 !strconcat(opc, "bb"), "\t$dst, $a, $b",
1863 [(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16),
1864 (sext_inreg rGPR:$b, i16)))]> {
1865 let Inst{31-27} = 0b11111;
1866 let Inst{26-23} = 0b0110;
1867 let Inst{22-20} = 0b001;
1868 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1869 let Inst{7-6} = 0b00;
1870 let Inst{5-4} = 0b00;
1873 def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1874 !strconcat(opc, "bt"), "\t$dst, $a, $b",
1875 [(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16),
1876 (sra rGPR:$b, (i32 16))))]> {
1877 let Inst{31-27} = 0b11111;
1878 let Inst{26-23} = 0b0110;
1879 let Inst{22-20} = 0b001;
1880 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1881 let Inst{7-6} = 0b00;
1882 let Inst{5-4} = 0b01;
1885 def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1886 !strconcat(opc, "tb"), "\t$dst, $a, $b",
1887 [(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)),
1888 (sext_inreg rGPR:$b, i16)))]> {
1889 let Inst{31-27} = 0b11111;
1890 let Inst{26-23} = 0b0110;
1891 let Inst{22-20} = 0b001;
1892 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1893 let Inst{7-6} = 0b00;
1894 let Inst{5-4} = 0b10;
1897 def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1898 !strconcat(opc, "tt"), "\t$dst, $a, $b",
1899 [(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)),
1900 (sra rGPR:$b, (i32 16))))]> {
1901 let Inst{31-27} = 0b11111;
1902 let Inst{26-23} = 0b0110;
1903 let Inst{22-20} = 0b001;
1904 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1905 let Inst{7-6} = 0b00;
1906 let Inst{5-4} = 0b11;
1909 def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
1910 !strconcat(opc, "wb"), "\t$dst, $a, $b",
1911 [(set rGPR:$dst, (sra (opnode rGPR:$a,
1912 (sext_inreg rGPR:$b, i16)), (i32 16)))]> {
1913 let Inst{31-27} = 0b11111;
1914 let Inst{26-23} = 0b0110;
1915 let Inst{22-20} = 0b011;
1916 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1917 let Inst{7-6} = 0b00;
1918 let Inst{5-4} = 0b00;
1921 def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
1922 !strconcat(opc, "wt"), "\t$dst, $a, $b",
1923 [(set rGPR:$dst, (sra (opnode rGPR:$a,
1924 (sra rGPR:$b, (i32 16))), (i32 16)))]> {
1925 let Inst{31-27} = 0b11111;
1926 let Inst{26-23} = 0b0110;
1927 let Inst{22-20} = 0b011;
1928 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1929 let Inst{7-6} = 0b00;
1930 let Inst{5-4} = 0b01;
1935 multiclass T2I_smla<string opc, PatFrag opnode> {
1936 def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1937 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1938 [(set rGPR:$dst, (add rGPR:$acc,
1939 (opnode (sext_inreg rGPR:$a, i16),
1940 (sext_inreg rGPR:$b, i16))))]> {
1941 let Inst{31-27} = 0b11111;
1942 let Inst{26-23} = 0b0110;
1943 let Inst{22-20} = 0b001;
1944 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1945 let Inst{7-6} = 0b00;
1946 let Inst{5-4} = 0b00;
1949 def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1950 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1951 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sext_inreg rGPR:$a, i16),
1952 (sra rGPR:$b, (i32 16)))))]> {
1953 let Inst{31-27} = 0b11111;
1954 let Inst{26-23} = 0b0110;
1955 let Inst{22-20} = 0b001;
1956 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1957 let Inst{7-6} = 0b00;
1958 let Inst{5-4} = 0b01;
1961 def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1962 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1963 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
1964 (sext_inreg rGPR:$b, i16))))]> {
1965 let Inst{31-27} = 0b11111;
1966 let Inst{26-23} = 0b0110;
1967 let Inst{22-20} = 0b001;
1968 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1969 let Inst{7-6} = 0b00;
1970 let Inst{5-4} = 0b10;
1973 def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1974 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1975 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
1976 (sra rGPR:$b, (i32 16)))))]> {
1977 let Inst{31-27} = 0b11111;
1978 let Inst{26-23} = 0b0110;
1979 let Inst{22-20} = 0b001;
1980 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1981 let Inst{7-6} = 0b00;
1982 let Inst{5-4} = 0b11;
1985 def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1986 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1987 [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
1988 (sext_inreg rGPR:$b, i16)), (i32 16))))]> {
1989 let Inst{31-27} = 0b11111;
1990 let Inst{26-23} = 0b0110;
1991 let Inst{22-20} = 0b011;
1992 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1993 let Inst{7-6} = 0b00;
1994 let Inst{5-4} = 0b00;
1997 def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1998 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1999 [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
2000 (sra rGPR:$b, (i32 16))), (i32 16))))]> {
2001 let Inst{31-27} = 0b11111;
2002 let Inst{26-23} = 0b0110;
2003 let Inst{22-20} = 0b011;
2004 let Inst{15-12} = {?, ?, ?, ?}; // Ra
2005 let Inst{7-6} = 0b00;
2006 let Inst{5-4} = 0b01;
2010 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2011 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2013 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2014 def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs rGPR:$ldst,rGPR:$hdst),
2015 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
2016 [/* For disassembly only; pattern left blank */]>;
2017 def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs rGPR:$ldst,rGPR:$hdst),
2018 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
2019 [/* For disassembly only; pattern left blank */]>;
2020 def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs rGPR:$ldst,rGPR:$hdst),
2021 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
2022 [/* For disassembly only; pattern left blank */]>;
2023 def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs rGPR:$ldst,rGPR:$hdst),
2024 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
2025 [/* For disassembly only; pattern left blank */]>;
2027 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2028 // These are for disassembly only.
2030 def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2031 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
2032 let Inst{15-12} = 0b1111;
2034 def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2035 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
2036 let Inst{15-12} = 0b1111;
2038 def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2039 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
2040 let Inst{15-12} = 0b1111;
2042 def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2043 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
2044 let Inst{15-12} = 0b1111;
2046 def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst),
2047 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlad",
2048 "\t$dst, $a, $b, $acc", []>;
2049 def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst),
2050 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smladx",
2051 "\t$dst, $a, $b, $acc", []>;
2052 def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst),
2053 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsd",
2054 "\t$dst, $a, $b, $acc", []>;
2055 def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst),
2056 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsdx",
2057 "\t$dst, $a, $b, $acc", []>;
2058 def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs rGPR:$ldst,rGPR:$hdst),
2059 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlald",
2060 "\t$ldst, $hdst, $a, $b", []>;
2061 def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs rGPR:$ldst,rGPR:$hdst),
2062 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaldx",
2063 "\t$ldst, $hdst, $a, $b", []>;
2064 def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs rGPR:$ldst,rGPR:$hdst),
2065 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsld",
2066 "\t$ldst, $hdst, $a, $b", []>;
2067 def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs rGPR:$ldst,rGPR:$hdst),
2068 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsldx",
2069 "\t$ldst, $hdst, $a, $b", []>;
2071 //===----------------------------------------------------------------------===//
2072 // Misc. Arithmetic Instructions.
2075 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2076 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2077 : T2I<oops, iops, itin, opc, asm, pattern> {
2078 let Inst{31-27} = 0b11111;
2079 let Inst{26-22} = 0b01010;
2080 let Inst{21-20} = op1;
2081 let Inst{15-12} = 0b1111;
2082 let Inst{7-6} = 0b10;
2083 let Inst{5-4} = op2;
2086 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2087 "clz", "\t$dst, $src", [(set rGPR:$dst, (ctlz rGPR:$src))]>;
2089 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2090 "rbit", "\t$dst, $src",
2091 [(set rGPR:$dst, (ARMrbit rGPR:$src))]>;
2093 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2094 "rev", ".w\t$dst, $src", [(set rGPR:$dst, (bswap rGPR:$src))]>;
2096 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2097 "rev16", ".w\t$dst, $src",
2099 (or (and (srl rGPR:$src, (i32 8)), 0xFF),
2100 (or (and (shl rGPR:$src, (i32 8)), 0xFF00),
2101 (or (and (srl rGPR:$src, (i32 8)), 0xFF0000),
2102 (and (shl rGPR:$src, (i32 8)), 0xFF000000)))))]>;
2104 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2105 "revsh", ".w\t$dst, $src",
2108 (or (srl (and rGPR:$src, 0xFF00), (i32 8)),
2109 (shl rGPR:$src, (i32 8))), i16))]>;
2111 def t2PKHBT : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, i32imm:$shamt),
2112 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt",
2113 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF),
2114 (and (shl rGPR:$src2, (i32 imm:$shamt)),
2116 Requires<[HasT2ExtractPack]> {
2117 let Inst{31-27} = 0b11101;
2118 let Inst{26-25} = 0b01;
2119 let Inst{24-20} = 0b01100;
2120 let Inst{5} = 0; // BT form
2124 // Alternate cases for PKHBT where identities eliminate some nodes.
2125 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2126 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2127 Requires<[HasT2ExtractPack]>;
2128 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$shamt)),
2129 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$shamt)>,
2130 Requires<[HasT2ExtractPack]>;
2132 def t2PKHTB : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, i32imm:$shamt),
2133 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
2134 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF0000),
2135 (and (sra rGPR:$src2, imm16_31:$shamt),
2137 Requires<[HasT2ExtractPack]> {
2138 let Inst{31-27} = 0b11101;
2139 let Inst{26-25} = 0b01;
2140 let Inst{24-20} = 0b01100;
2141 let Inst{5} = 1; // TB form
2145 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2146 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2147 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, (i32 16))),
2148 (t2PKHTB rGPR:$src1, rGPR:$src2, 16)>,
2149 Requires<[HasT2ExtractPack]>;
2150 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2151 (and (srl rGPR:$src2, imm1_15:$shamt), 0xFFFF)),
2152 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$shamt)>,
2153 Requires<[HasT2ExtractPack]>;
2155 //===----------------------------------------------------------------------===//
2156 // Comparison Instructions...
2159 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2160 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2161 defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
2162 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2164 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2165 // Compare-to-zero still works out, just not the relationals
2166 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2167 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2168 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2169 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2171 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2172 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2174 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2175 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2177 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2178 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
2179 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2180 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
2182 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
2183 // Short range conditional branch. Looks awesome for loops. Need to figure
2184 // out how to use this one.
2187 // Conditional moves
2188 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2189 // a two-value operand where a dag node expects two operands. :(
2190 let neverHasSideEffects = 1 in {
2191 def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr,
2192 "mov", ".w\t$dst, $true",
2193 [/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>,
2194 RegConstraint<"$false = $dst"> {
2195 let Inst{31-27} = 0b11101;
2196 let Inst{26-25} = 0b01;
2197 let Inst{24-21} = 0b0010;
2198 let Inst{20} = 0; // The S bit.
2199 let Inst{19-16} = 0b1111; // Rn
2200 let Inst{14-12} = 0b000;
2201 let Inst{7-4} = 0b0000;
2204 def t2MOVCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true),
2205 IIC_iCMOVi, "mov", ".w\t$dst, $true",
2206 [/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
2207 RegConstraint<"$false = $dst"> {
2208 let Inst{31-27} = 0b11110;
2210 let Inst{24-21} = 0b0010;
2211 let Inst{20} = 0; // The S bit.
2212 let Inst{19-16} = 0b1111; // Rn
2216 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2217 string opc, string asm, list<dag> pattern>
2218 : T2I<oops, iops, itin, opc, asm, pattern> {
2219 let Inst{31-27} = 0b11101;
2220 let Inst{26-25} = 0b01;
2221 let Inst{24-21} = 0b0010;
2222 let Inst{20} = 0; // The S bit.
2223 let Inst{19-16} = 0b1111; // Rn
2224 let Inst{5-4} = opcod; // Shift type.
2226 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$dst),
2227 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2228 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
2229 RegConstraint<"$false = $dst">;
2230 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$dst),
2231 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2232 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
2233 RegConstraint<"$false = $dst">;
2234 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$dst),
2235 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2236 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
2237 RegConstraint<"$false = $dst">;
2238 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$dst),
2239 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2240 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
2241 RegConstraint<"$false = $dst">;
2242 } // neverHasSideEffects
2244 //===----------------------------------------------------------------------===//
2245 // Atomic operations intrinsics
2248 // memory barriers protect the atomic sequences
2249 let hasSideEffects = 1 in {
2250 def t2Int_MemBarrierV7 : AInoP<(outs), (ins),
2251 ThumbFrm, NoItinerary,
2253 [(ARMMemBarrierV7)]>,
2254 Requires<[IsThumb2]> {
2255 let Inst{31-4} = 0xF3BF8F5;
2256 // FIXME: add support for options other than a full system DMB
2257 let Inst{3-0} = 0b1111;
2260 def t2Int_SyncBarrierV7 : AInoP<(outs), (ins),
2261 ThumbFrm, NoItinerary,
2263 [(ARMSyncBarrierV7)]>,
2264 Requires<[IsThumb2]> {
2265 let Inst{31-4} = 0xF3BF8F4;
2266 // FIXME: add support for options other than a full system DSB
2267 let Inst{3-0} = 0b1111;
2271 // Helper class for multiclass T2MemB -- for disassembly only
2272 class T2I_memb<string opc, string asm>
2273 : T2I<(outs), (ins), NoItinerary, opc, asm,
2274 [/* For disassembly only; pattern left blank */]>,
2275 Requires<[IsThumb2, HasV7]> {
2276 let Inst{31-20} = 0xf3b;
2277 let Inst{15-14} = 0b10;
2281 multiclass T2MemB<bits<4> op7_4, string opc> {
2283 def st : T2I_memb<opc, "\tst"> {
2284 let Inst{7-4} = op7_4;
2285 let Inst{3-0} = 0b1110;
2288 def ish : T2I_memb<opc, "\tish"> {
2289 let Inst{7-4} = op7_4;
2290 let Inst{3-0} = 0b1011;
2293 def ishst : T2I_memb<opc, "\tishst"> {
2294 let Inst{7-4} = op7_4;
2295 let Inst{3-0} = 0b1010;
2298 def nsh : T2I_memb<opc, "\tnsh"> {
2299 let Inst{7-4} = op7_4;
2300 let Inst{3-0} = 0b0111;
2303 def nshst : T2I_memb<opc, "\tnshst"> {
2304 let Inst{7-4} = op7_4;
2305 let Inst{3-0} = 0b0110;
2308 def osh : T2I_memb<opc, "\tosh"> {
2309 let Inst{7-4} = op7_4;
2310 let Inst{3-0} = 0b0011;
2313 def oshst : T2I_memb<opc, "\toshst"> {
2314 let Inst{7-4} = op7_4;
2315 let Inst{3-0} = 0b0010;
2319 // These DMB variants are for disassembly only.
2320 defm t2DMB : T2MemB<0b0101, "dmb">;
2322 // These DSB variants are for disassembly only.
2323 defm t2DSB : T2MemB<0b0100, "dsb">;
2325 // ISB has only full system option -- for disassembly only
2326 def t2ISBsy : T2I_memb<"isb", ""> {
2327 let Inst{7-4} = 0b0110;
2328 let Inst{3-0} = 0b1111;
2331 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2332 InstrItinClass itin, string opc, string asm, string cstr,
2333 list<dag> pattern, bits<4> rt2 = 0b1111>
2334 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2335 let Inst{31-27} = 0b11101;
2336 let Inst{26-20} = 0b0001101;
2337 let Inst{11-8} = rt2;
2338 let Inst{7-6} = 0b01;
2339 let Inst{5-4} = opcod;
2340 let Inst{3-0} = 0b1111;
2342 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2343 InstrItinClass itin, string opc, string asm, string cstr,
2344 list<dag> pattern, bits<4> rt2 = 0b1111>
2345 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2346 let Inst{31-27} = 0b11101;
2347 let Inst{26-20} = 0b0001100;
2348 let Inst{11-8} = rt2;
2349 let Inst{7-6} = 0b01;
2350 let Inst{5-4} = opcod;
2353 let mayLoad = 1 in {
2354 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2355 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
2357 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2358 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
2360 def t2LDREX : Thumb2I<(outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2361 Size4Bytes, NoItinerary,
2362 "ldrex", "\t$dest, [$ptr]", "",
2364 let Inst{31-27} = 0b11101;
2365 let Inst{26-20} = 0b0000101;
2366 let Inst{11-8} = 0b1111;
2367 let Inst{7-0} = 0b00000000; // imm8 = 0
2369 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$dest, rGPR:$dest2), (ins rGPR:$ptr),
2370 AddrModeNone, Size4Bytes, NoItinerary,
2371 "ldrexd", "\t$dest, $dest2, [$ptr]", "",
2375 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2376 def t2STREXB : T2I_strex<0b00, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2377 AddrModeNone, Size4Bytes, NoItinerary,
2378 "strexb", "\t$success, $src, [$ptr]", "", []>;
2379 def t2STREXH : T2I_strex<0b01, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2380 AddrModeNone, Size4Bytes, NoItinerary,
2381 "strexh", "\t$success, $src, [$ptr]", "", []>;
2382 def t2STREX : Thumb2I<(outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2383 AddrModeNone, Size4Bytes, NoItinerary,
2384 "strex", "\t$success, $src, [$ptr]", "",
2386 let Inst{31-27} = 0b11101;
2387 let Inst{26-20} = 0b0000100;
2388 let Inst{7-0} = 0b00000000; // imm8 = 0
2390 def t2STREXD : T2I_strex<0b11, (outs rGPR:$success),
2391 (ins rGPR:$src, rGPR:$src2, rGPR:$ptr),
2392 AddrModeNone, Size4Bytes, NoItinerary,
2393 "strexd", "\t$success, $src, $src2, [$ptr]", "", [],
2397 // Clear-Exclusive is for disassembly only.
2398 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2399 [/* For disassembly only; pattern left blank */]>,
2400 Requires<[IsARM, HasV7]> {
2401 let Inst{31-20} = 0xf3b;
2402 let Inst{15-14} = 0b10;
2404 let Inst{7-4} = 0b0010;
2407 //===----------------------------------------------------------------------===//
2411 // __aeabi_read_tp preserves the registers r1-r3.
2413 Defs = [R0, R12, LR, CPSR] in {
2414 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2415 "bl\t__aeabi_read_tp",
2416 [(set R0, ARMthread_pointer)]> {
2417 let Inst{31-27} = 0b11110;
2418 let Inst{15-14} = 0b11;
2423 //===----------------------------------------------------------------------===//
2424 // SJLJ Exception handling intrinsics
2425 // eh_sjlj_setjmp() is an instruction sequence to store the return
2426 // address and save #0 in R0 for the non-longjmp case.
2427 // Since by its nature we may be coming from some other function to get
2428 // here, and we're using the stack frame for the containing function to
2429 // save/restore registers, we can't keep anything live in regs across
2430 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2431 // when we get here from a longjmp(). We force everthing out of registers
2432 // except for our own input by listing the relevant registers in Defs. By
2433 // doing so, we also cause the prologue/epilogue code to actively preserve
2434 // all of the callee-saved resgisters, which is exactly what we want.
2435 // $val is a scratch register for our use.
2437 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2438 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2439 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2440 D31 ], hasSideEffects = 1, isBarrier = 1 in {
2441 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
2442 AddrModeNone, SizeSpecial, NoItinerary,
2443 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
2444 "adds\t$val, #7\n\t"
2445 "str\t$val, [$src, #4]\n\t"
2448 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
2450 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>,
2451 Requires<[IsThumb2, HasVFP2]>;
2455 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2456 hasSideEffects = 1, isBarrier = 1 in {
2457 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
2458 AddrModeNone, SizeSpecial, NoItinerary,
2459 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
2460 "adds\t$val, #7\n\t"
2461 "str\t$val, [$src, #4]\n\t"
2464 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
2466 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>,
2467 Requires<[IsThumb2, NoVFP]>;
2471 //===----------------------------------------------------------------------===//
2472 // Control-Flow Instructions
2475 // FIXME: remove when we have a way to marking a MI with these properties.
2476 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2478 // FIXME: Should pc be an implicit operand like PICADD, etc?
2479 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2480 hasExtraDefRegAllocReq = 1 in
2481 def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
2482 reglist:$dsts, variable_ops), IIC_Br,
2483 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
2484 "$addr.addr = $wb", []> {
2485 let Inst{31-27} = 0b11101;
2486 let Inst{26-25} = 0b00;
2487 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
2489 let Inst{21} = 1; // The W bit.
2490 let Inst{20} = 1; // Load
2493 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2494 let isPredicable = 1 in
2495 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2497 [(br bb:$target)]> {
2498 let Inst{31-27} = 0b11110;
2499 let Inst{15-14} = 0b10;
2503 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2506 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
2507 IIC_Br, "mov\tpc, $target$jt",
2508 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
2509 let Inst{31-27} = 0b11101;
2510 let Inst{26-20} = 0b0100100;
2511 let Inst{19-16} = 0b1111;
2512 let Inst{14-12} = 0b000;
2513 let Inst{11-8} = 0b1111; // Rd = pc
2514 let Inst{7-4} = 0b0000;
2517 // FIXME: Add a non-pc based case that can be predicated.
2520 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2521 IIC_Br, "tbb\t$index$jt", []> {
2522 let Inst{31-27} = 0b11101;
2523 let Inst{26-20} = 0b0001101;
2524 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2525 let Inst{15-8} = 0b11110000;
2526 let Inst{7-4} = 0b0000; // B form
2531 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2532 IIC_Br, "tbh\t$index$jt", []> {
2533 let Inst{31-27} = 0b11101;
2534 let Inst{26-20} = 0b0001101;
2535 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2536 let Inst{15-8} = 0b11110000;
2537 let Inst{7-4} = 0b0001; // H form
2540 // Generic versions of the above two instructions, for disassembly only
2542 def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2543 "tbb", "\t[$a, $b]", []>{
2544 let Inst{31-27} = 0b11101;
2545 let Inst{26-20} = 0b0001101;
2546 let Inst{15-8} = 0b11110000;
2547 let Inst{7-4} = 0b0000; // B form
2550 def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2551 "tbh", "\t[$a, $b, lsl #1]", []> {
2552 let Inst{31-27} = 0b11101;
2553 let Inst{26-20} = 0b0001101;
2554 let Inst{15-8} = 0b11110000;
2555 let Inst{7-4} = 0b0001; // H form
2557 } // isNotDuplicable, isIndirectBranch
2559 } // isBranch, isTerminator, isBarrier
2561 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2562 // a two-value operand where a dag node expects two operands. :(
2563 let isBranch = 1, isTerminator = 1 in
2564 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
2566 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
2567 let Inst{31-27} = 0b11110;
2568 let Inst{15-14} = 0b10;
2574 let Defs = [ITSTATE] in
2575 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
2576 AddrModeNone, Size2Bytes, IIC_iALUx,
2577 "it$mask\t$cc", "", []> {
2578 // 16-bit instruction.
2579 let Inst{31-16} = 0x0000;
2580 let Inst{15-8} = 0b10111111;
2583 // Branch and Exchange Jazelle -- for disassembly only
2585 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
2586 [/* For disassembly only; pattern left blank */]> {
2587 let Inst{31-27} = 0b11110;
2589 let Inst{25-20} = 0b111100;
2590 let Inst{15-14} = 0b10;
2594 // Change Processor State is a system instruction -- for disassembly only.
2595 // The singleton $opt operand contains the following information:
2596 // opt{4-0} = mode from Inst{4-0}
2597 // opt{5} = changemode from Inst{17}
2598 // opt{8-6} = AIF from Inst{8-6}
2599 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
2600 def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
2601 [/* For disassembly only; pattern left blank */]> {
2602 let Inst{31-27} = 0b11110;
2604 let Inst{25-20} = 0b111010;
2605 let Inst{15-14} = 0b10;
2609 // A6.3.4 Branches and miscellaneous control
2610 // Table A6-14 Change Processor State, and hint instructions
2611 // Helper class for disassembly only.
2612 class T2I_hint<bits<8> op7_0, string opc, string asm>
2613 : T2I<(outs), (ins), NoItinerary, opc, asm,
2614 [/* For disassembly only; pattern left blank */]> {
2615 let Inst{31-20} = 0xf3a;
2616 let Inst{15-14} = 0b10;
2618 let Inst{10-8} = 0b000;
2619 let Inst{7-0} = op7_0;
2622 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
2623 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
2624 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
2625 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
2626 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
2628 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
2629 [/* For disassembly only; pattern left blank */]> {
2630 let Inst{31-20} = 0xf3a;
2631 let Inst{15-14} = 0b10;
2633 let Inst{10-8} = 0b000;
2634 let Inst{7-4} = 0b1111;
2637 // Secure Monitor Call is a system instruction -- for disassembly only
2638 // Option = Inst{19-16}
2639 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
2640 [/* For disassembly only; pattern left blank */]> {
2641 let Inst{31-27} = 0b11110;
2642 let Inst{26-20} = 0b1111111;
2643 let Inst{15-12} = 0b1000;
2646 // Store Return State is a system instruction -- for disassembly only
2647 def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
2648 [/* For disassembly only; pattern left blank */]> {
2649 let Inst{31-27} = 0b11101;
2650 let Inst{26-20} = 0b0000010; // W = 1
2653 def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
2654 [/* For disassembly only; pattern left blank */]> {
2655 let Inst{31-27} = 0b11101;
2656 let Inst{26-20} = 0b0000000; // W = 0
2659 def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
2660 [/* For disassembly only; pattern left blank */]> {
2661 let Inst{31-27} = 0b11101;
2662 let Inst{26-20} = 0b0011010; // W = 1
2665 def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
2666 [/* For disassembly only; pattern left blank */]> {
2667 let Inst{31-27} = 0b11101;
2668 let Inst{26-20} = 0b0011000; // W = 0
2671 // Return From Exception is a system instruction -- for disassembly only
2672 def t2RFEDBW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfedb", "\t$base!",
2673 [/* For disassembly only; pattern left blank */]> {
2674 let Inst{31-27} = 0b11101;
2675 let Inst{26-20} = 0b0000011; // W = 1
2678 def t2RFEDB : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeab", "\t$base",
2679 [/* For disassembly only; pattern left blank */]> {
2680 let Inst{31-27} = 0b11101;
2681 let Inst{26-20} = 0b0000001; // W = 0
2684 def t2RFEIAW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base!",
2685 [/* For disassembly only; pattern left blank */]> {
2686 let Inst{31-27} = 0b11101;
2687 let Inst{26-20} = 0b0011011; // W = 1
2690 def t2RFEIA : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base",
2691 [/* For disassembly only; pattern left blank */]> {
2692 let Inst{31-27} = 0b11101;
2693 let Inst{26-20} = 0b0011001; // W = 0
2696 //===----------------------------------------------------------------------===//
2697 // Non-Instruction Patterns
2700 // Two piece so_imms.
2701 def : T2Pat<(or rGPR:$LHS, t2_so_imm2part:$RHS),
2702 (t2ORRri (t2ORRri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2703 (t2_so_imm2part_2 imm:$RHS))>;
2704 def : T2Pat<(xor rGPR:$LHS, t2_so_imm2part:$RHS),
2705 (t2EORri (t2EORri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2706 (t2_so_imm2part_2 imm:$RHS))>;
2707 def : T2Pat<(add rGPR:$LHS, t2_so_imm2part:$RHS),
2708 (t2ADDri (t2ADDri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2709 (t2_so_imm2part_2 imm:$RHS))>;
2710 def : T2Pat<(add rGPR:$LHS, t2_so_neg_imm2part:$RHS),
2711 (t2SUBri (t2SUBri rGPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
2712 (t2_so_neg_imm2part_2 imm:$RHS))>;
2714 // 32-bit immediate using movw + movt.
2715 // This is a single pseudo instruction to make it re-materializable. Remove
2716 // when we can do generalized remat.
2717 let isReMaterializable = 1 in
2718 def t2MOVi32imm : T2Ix2<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
2719 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2720 [(set rGPR:$dst, (i32 imm:$src))]>;
2722 // ConstantPool, GlobalAddress, and JumpTable
2723 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
2724 Requires<[IsThumb2, DontUseMovt]>;
2725 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
2726 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
2727 Requires<[IsThumb2, UseMovt]>;
2729 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2730 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
2732 // Pseudo instruction that combines ldr from constpool and add pc. This should
2733 // be expanded into two instructions late to allow if-conversion and
2735 let canFoldAsLoad = 1, isReMaterializable = 1 in
2736 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
2738 "${:comment} ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
2739 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
2741 Requires<[IsThumb2]>;
2743 //===----------------------------------------------------------------------===//
2744 // Move between special register and ARM core register -- for disassembly only
2748 def t2MRS : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
2749 [/* For disassembly only; pattern left blank */]> {
2750 let Inst{31-27} = 0b11110;
2752 let Inst{25-21} = 0b11111;
2753 let Inst{20} = 0; // The R bit.
2754 let Inst{15-14} = 0b10;
2759 def t2MRSsys : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
2760 [/* For disassembly only; pattern left blank */]> {
2761 let Inst{31-27} = 0b11110;
2763 let Inst{25-21} = 0b11111;
2764 let Inst{20} = 1; // The R bit.
2765 let Inst{15-14} = 0b10;
2770 def t2MSR : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
2771 "\tcpsr$mask, $src",
2772 [/* For disassembly only; pattern left blank */]> {
2773 let Inst{31-27} = 0b11110;
2775 let Inst{25-21} = 0b11100;
2776 let Inst{20} = 0; // The R bit.
2777 let Inst{15-14} = 0b10;
2782 def t2MSRsys : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
2783 "\tspsr$mask, $src",
2784 [/* For disassembly only; pattern left blank */]> {
2785 let Inst{31-27} = 0b11110;
2787 let Inst{25-21} = 0b11100;
2788 let Inst{20} = 1; // The R bit.
2789 let Inst{15-14} = 0b10;