1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops GPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant
53 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>,
56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
59 // t2_so_imm_not - Match an immediate that is a complement
61 def t2_so_imm_not : Operand<i32>,
63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
64 }], t2_so_imm_not_XFORM>;
66 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
67 def t2_so_imm_neg : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
70 }], t2_so_imm_neg_XFORM>;
72 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
73 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
74 // to get the first/second pieces.
75 def t2_so_imm2part : Operand<i32>,
77 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
81 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
82 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
83 return CurDAG->getTargetConstant(V, MVT::i32);
86 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
87 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
88 return CurDAG->getTargetConstant(V, MVT::i32);
91 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
92 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
96 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
97 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
98 return CurDAG->getTargetConstant(V, MVT::i32);
101 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
102 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
103 return CurDAG->getTargetConstant(V, MVT::i32);
106 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
107 def imm1_31 : PatLeaf<(i32 imm), [{
108 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
111 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
112 def imm0_4095 : Operand<i32>,
113 PatLeaf<(i32 imm), [{
114 return (uint32_t)N->getZExtValue() < 4096;
117 def imm0_4095_neg : PatLeaf<(i32 imm), [{
118 return (uint32_t)(-N->getZExtValue()) < 4096;
121 def imm0_255_neg : PatLeaf<(i32 imm), [{
122 return (uint32_t)(-N->getZExtValue()) < 255;
125 // Define Thumb2 specific addressing modes.
127 // t2addrmode_imm12 := reg + imm12
128 def t2addrmode_imm12 : Operand<i32>,
129 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
130 let PrintMethod = "printT2AddrModeImm12Operand";
131 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
134 // t2addrmode_imm8 := reg +/- imm8
135 def t2addrmode_imm8 : Operand<i32>,
136 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
137 let PrintMethod = "printT2AddrModeImm8Operand";
138 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
141 def t2am_imm8_offset : Operand<i32>,
142 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
143 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
146 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
147 def t2addrmode_imm8s4 : Operand<i32>,
148 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
149 let PrintMethod = "printT2AddrModeImm8s4Operand";
150 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
153 def t2am_imm8s4_offset : Operand<i32> {
154 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
157 // t2addrmode_so_reg := reg + (reg << imm2)
158 def t2addrmode_so_reg : Operand<i32>,
159 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
160 let PrintMethod = "printT2AddrModeSoRegOperand";
161 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
165 //===----------------------------------------------------------------------===//
166 // Multiclass helpers...
169 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
170 /// unary operation that produces a value. These are predicable and can be
171 /// changed to modify CPSR.
172 multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode,
173 bit Cheap = 0, bit ReMat = 0> {
175 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
177 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
178 let isAsCheapAsAMove = Cheap;
179 let isReMaterializable = ReMat;
180 let Inst{31-27} = 0b11110;
182 let Inst{24-21} = opcod;
183 let Inst{20} = ?; // The S bit.
184 let Inst{19-16} = 0b1111; // Rn
188 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
189 opc, ".w\t$dst, $src",
190 [(set GPR:$dst, (opnode GPR:$src))]> {
191 let Inst{31-27} = 0b11101;
192 let Inst{26-25} = 0b01;
193 let Inst{24-21} = opcod;
194 let Inst{20} = ?; // The S bit.
195 let Inst{19-16} = 0b1111; // Rn
196 let Inst{14-12} = 0b000; // imm3
197 let Inst{7-6} = 0b00; // imm2
198 let Inst{5-4} = 0b00; // type
201 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
202 opc, ".w\t$dst, $src",
203 [(set GPR:$dst, (opnode t2_so_reg:$src))]> {
204 let Inst{31-27} = 0b11101;
205 let Inst{26-25} = 0b01;
206 let Inst{24-21} = opcod;
207 let Inst{20} = ?; // The S bit.
208 let Inst{19-16} = 0b1111; // Rn
212 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
213 // binary operation that produces a value. These are predicable and can be
214 /// changed to modify CPSR.
215 multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
216 bit Commutable = 0, string wide =""> {
218 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
219 opc, "\t$dst, $lhs, $rhs",
220 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
221 let Inst{31-27} = 0b11110;
223 let Inst{24-21} = opcod;
224 let Inst{20} = ?; // The S bit.
228 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
229 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
230 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
231 let isCommutable = Commutable;
232 let Inst{31-27} = 0b11101;
233 let Inst{26-25} = 0b01;
234 let Inst{24-21} = opcod;
235 let Inst{20} = ?; // The S bit.
236 let Inst{14-12} = 0b000; // imm3
237 let Inst{7-6} = 0b00; // imm2
238 let Inst{5-4} = 0b00; // type
241 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
242 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
243 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
244 let Inst{31-27} = 0b11101;
245 let Inst{26-25} = 0b01;
246 let Inst{24-21} = opcod;
247 let Inst{20} = ?; // The S bit.
251 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
252 // the ".w" prefix to indicate that they are wide.
253 multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
254 bit Commutable = 0> :
255 T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
257 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
258 /// reversed. It doesn't define the 'rr' form since it's handled by its
259 /// T2I_bin_irs counterpart.
260 multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> {
262 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
263 opc, ".w\t$dst, $rhs, $lhs",
264 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
265 let Inst{31-27} = 0b11110;
267 let Inst{24-21} = opcod;
268 let Inst{20} = 0; // The S bit.
272 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
273 opc, "\t$dst, $rhs, $lhs",
274 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
275 let Inst{31-27} = 0b11101;
276 let Inst{26-25} = 0b01;
277 let Inst{24-21} = opcod;
278 let Inst{20} = 0; // The S bit.
282 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
283 /// instruction modifies the CPSR register.
284 let Defs = [CPSR] in {
285 multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
286 bit Commutable = 0> {
288 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
289 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
290 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
291 let Inst{31-27} = 0b11110;
293 let Inst{24-21} = opcod;
294 let Inst{20} = 1; // The S bit.
298 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
299 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
300 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
301 let isCommutable = Commutable;
302 let Inst{31-27} = 0b11101;
303 let Inst{26-25} = 0b01;
304 let Inst{24-21} = opcod;
305 let Inst{20} = 1; // The S bit.
306 let Inst{14-12} = 0b000; // imm3
307 let Inst{7-6} = 0b00; // imm2
308 let Inst{5-4} = 0b00; // type
311 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
312 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
313 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
314 let Inst{31-27} = 0b11101;
315 let Inst{26-25} = 0b01;
316 let Inst{24-21} = opcod;
317 let Inst{20} = 1; // The S bit.
322 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
323 /// patterns for a binary operation that produces a value.
324 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
325 bit Commutable = 0> {
327 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
328 opc, ".w\t$dst, $lhs, $rhs",
329 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
330 let Inst{31-27} = 0b11110;
333 let Inst{23-21} = op23_21;
334 let Inst{20} = 0; // The S bit.
338 def ri12 : T2I<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
339 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
340 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
341 let Inst{31-27} = 0b11110;
344 let Inst{23-21} = op23_21;
345 let Inst{20} = 0; // The S bit.
349 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
350 opc, ".w\t$dst, $lhs, $rhs",
351 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
352 let isCommutable = Commutable;
353 let Inst{31-27} = 0b11101;
354 let Inst{26-25} = 0b01;
356 let Inst{23-21} = op23_21;
357 let Inst{20} = 0; // The S bit.
358 let Inst{14-12} = 0b000; // imm3
359 let Inst{7-6} = 0b00; // imm2
360 let Inst{5-4} = 0b00; // type
363 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
364 opc, ".w\t$dst, $lhs, $rhs",
365 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
366 let Inst{31-27} = 0b11101;
367 let Inst{26-25} = 0b01;
369 let Inst{23-21} = op23_21;
370 let Inst{20} = 0; // The S bit.
374 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
375 /// for a binary operation that produces a value and use the carry
376 /// bit. It's not predicable.
377 let Uses = [CPSR] in {
378 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
379 bit Commutable = 0> {
381 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
382 opc, "\t$dst, $lhs, $rhs",
383 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
384 Requires<[IsThumb2]> {
385 let Inst{31-27} = 0b11110;
387 let Inst{24-21} = opcod;
388 let Inst{20} = 0; // The S bit.
392 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
393 opc, ".w\t$dst, $lhs, $rhs",
394 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
395 Requires<[IsThumb2]> {
396 let isCommutable = Commutable;
397 let Inst{31-27} = 0b11101;
398 let Inst{26-25} = 0b01;
399 let Inst{24-21} = opcod;
400 let Inst{20} = 0; // The S bit.
401 let Inst{14-12} = 0b000; // imm3
402 let Inst{7-6} = 0b00; // imm2
403 let Inst{5-4} = 0b00; // type
406 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
407 opc, ".w\t$dst, $lhs, $rhs",
408 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
409 Requires<[IsThumb2]> {
410 let Inst{31-27} = 0b11101;
411 let Inst{26-25} = 0b01;
412 let Inst{24-21} = opcod;
413 let Inst{20} = 0; // The S bit.
417 // Carry setting variants
418 let Defs = [CPSR] in {
419 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
420 bit Commutable = 0> {
422 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
423 opc, "\t$dst, $lhs, $rhs",
424 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
425 Requires<[IsThumb2]> {
426 let Inst{31-27} = 0b11110;
428 let Inst{24-21} = opcod;
429 let Inst{20} = 1; // The S bit.
433 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
434 opc, ".w\t$dst, $lhs, $rhs",
435 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
436 Requires<[IsThumb2]> {
437 let isCommutable = Commutable;
438 let Inst{31-27} = 0b11101;
439 let Inst{26-25} = 0b01;
440 let Inst{24-21} = opcod;
441 let Inst{20} = 1; // The S bit.
442 let Inst{14-12} = 0b000; // imm3
443 let Inst{7-6} = 0b00; // imm2
444 let Inst{5-4} = 0b00; // type
447 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
448 opc, ".w\t$dst, $lhs, $rhs",
449 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
450 Requires<[IsThumb2]> {
451 let Inst{31-27} = 0b11101;
452 let Inst{26-25} = 0b01;
453 let Inst{24-21} = opcod;
454 let Inst{20} = 1; // The S bit.
460 /// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
461 let Defs = [CPSR] in {
462 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
464 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
466 !strconcat(opc, "${s}.w\t$dst, $rhs, $lhs"),
467 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
468 let Inst{31-27} = 0b11110;
470 let Inst{24-21} = opcod;
471 let Inst{20} = 1; // The S bit.
475 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
477 !strconcat(opc, "${s}\t$dst, $rhs, $lhs"),
478 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
479 let Inst{31-27} = 0b11101;
480 let Inst{26-25} = 0b01;
481 let Inst{24-21} = opcod;
482 let Inst{20} = 1; // The S bit.
487 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
488 // rotate operation that produces a value.
489 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
491 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
492 opc, ".w\t$dst, $lhs, $rhs",
493 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]> {
494 let Inst{31-27} = 0b11101;
495 let Inst{26-21} = 0b010010;
496 let Inst{19-16} = 0b1111; // Rn
497 let Inst{5-4} = opcod;
500 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr,
501 opc, ".w\t$dst, $lhs, $rhs",
502 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
503 let Inst{31-27} = 0b11111;
504 let Inst{26-23} = 0b0100;
505 let Inst{22-21} = opcod;
506 let Inst{15-12} = 0b1111;
507 let Inst{7-4} = 0b0000;
511 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
512 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
513 /// a explicit result, only implicitly set CPSR.
514 let Defs = [CPSR] in {
515 multiclass T2I_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
517 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
518 opc, ".w\t$lhs, $rhs",
519 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> {
520 let Inst{31-27} = 0b11110;
522 let Inst{24-21} = opcod;
523 let Inst{20} = 1; // The S bit.
525 let Inst{11-8} = 0b1111; // Rd
528 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
529 opc, ".w\t$lhs, $rhs",
530 [(opnode GPR:$lhs, GPR:$rhs)]> {
531 let Inst{31-27} = 0b11101;
532 let Inst{26-25} = 0b01;
533 let Inst{24-21} = opcod;
534 let Inst{20} = 1; // The S bit.
535 let Inst{14-12} = 0b000; // imm3
536 let Inst{11-8} = 0b1111; // Rd
537 let Inst{7-6} = 0b00; // imm2
538 let Inst{5-4} = 0b00; // type
541 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
542 opc, ".w\t$lhs, $rhs",
543 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> {
544 let Inst{31-27} = 0b11101;
545 let Inst{26-25} = 0b01;
546 let Inst{24-21} = opcod;
547 let Inst{20} = 1; // The S bit.
548 let Inst{11-8} = 0b1111; // Rd
553 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
554 multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> {
555 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
556 opc, ".w\t$dst, $addr",
557 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
558 let Inst{31-27} = 0b11111;
559 let Inst{26-25} = 0b00;
560 let Inst{24} = signed;
562 let Inst{22-21} = opcod;
563 let Inst{20} = 1; // load
565 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
566 opc, "\t$dst, $addr",
567 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
568 let Inst{31-27} = 0b11111;
569 let Inst{26-25} = 0b00;
570 let Inst{24} = signed;
572 let Inst{22-21} = opcod;
573 let Inst{20} = 1; // load
575 // Offset: index==TRUE, wback==FALSE
576 let Inst{10} = 1; // The P bit.
577 let Inst{8} = 0; // The W bit.
579 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
580 opc, ".w\t$dst, $addr",
581 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
582 let Inst{31-27} = 0b11111;
583 let Inst{26-25} = 0b00;
584 let Inst{24} = signed;
586 let Inst{22-21} = opcod;
587 let Inst{20} = 1; // load
588 let Inst{11-6} = 0b000000;
590 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
591 opc, ".w\t$dst, $addr",
592 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
593 let isReMaterializable = 1;
594 let Inst{31-27} = 0b11111;
595 let Inst{26-25} = 0b00;
596 let Inst{24} = signed;
597 let Inst{23} = ?; // add = (U == '1')
598 let Inst{22-21} = opcod;
599 let Inst{20} = 1; // load
600 let Inst{19-16} = 0b1111; // Rn
604 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
605 multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> {
606 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
607 opc, ".w\t$src, $addr",
608 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
609 let Inst{31-27} = 0b11111;
610 let Inst{26-23} = 0b0001;
611 let Inst{22-21} = opcod;
612 let Inst{20} = 0; // !load
614 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
615 opc, "\t$src, $addr",
616 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
617 let Inst{31-27} = 0b11111;
618 let Inst{26-23} = 0b0000;
619 let Inst{22-21} = opcod;
620 let Inst{20} = 0; // !load
622 // Offset: index==TRUE, wback==FALSE
623 let Inst{10} = 1; // The P bit.
624 let Inst{8} = 0; // The W bit.
626 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
627 opc, ".w\t$src, $addr",
628 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
629 let Inst{31-27} = 0b11111;
630 let Inst{26-23} = 0b0000;
631 let Inst{22-21} = opcod;
632 let Inst{20} = 0; // !load
633 let Inst{11-6} = 0b000000;
637 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
638 /// register and one whose operand is a register rotated by 8/16/24.
639 multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
640 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
641 opc, ".w\t$dst, $src",
642 [(set GPR:$dst, (opnode GPR:$src))]> {
643 let Inst{31-27} = 0b11111;
644 let Inst{26-23} = 0b0100;
645 let Inst{22-20} = opcod;
646 let Inst{19-16} = 0b1111; // Rn
647 let Inst{15-12} = 0b1111;
649 let Inst{5-4} = 0b00; // rotate
651 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
652 opc, ".w\t$dst, $src, ror $rot",
653 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]> {
654 let Inst{31-27} = 0b11111;
655 let Inst{26-23} = 0b0100;
656 let Inst{22-20} = opcod;
657 let Inst{19-16} = 0b1111; // Rn
658 let Inst{15-12} = 0b1111;
660 let Inst{5-4} = {?,?}; // rotate
664 // SXTB16 and UXTB16 do not need the .w qualifier.
665 multiclass T2I_unary_rrot_nw<bits<3> opcod, string opc, PatFrag opnode> {
666 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
668 [(set GPR:$dst, (opnode GPR:$src))]> {
669 let Inst{31-27} = 0b11111;
670 let Inst{26-23} = 0b0100;
671 let Inst{22-20} = opcod;
672 let Inst{19-16} = 0b1111; // Rn
673 let Inst{15-12} = 0b1111;
675 let Inst{5-4} = 0b00; // rotate
677 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
678 opc, "\t$dst, $src, ror $rot",
679 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]> {
680 let Inst{31-27} = 0b11111;
681 let Inst{26-23} = 0b0100;
682 let Inst{22-20} = opcod;
683 let Inst{19-16} = 0b1111; // Rn
684 let Inst{15-12} = 0b1111;
686 let Inst{5-4} = {?,?}; // rotate
690 // DO variant - disassembly only, no pattern
692 multiclass T2I_unary_rrot_DO<bits<3> opcod, string opc> {
693 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
694 opc, "\t$dst, $src", []> {
695 let Inst{31-27} = 0b11111;
696 let Inst{26-23} = 0b0100;
697 let Inst{22-20} = opcod;
698 let Inst{19-16} = 0b1111; // Rn
699 let Inst{15-12} = 0b1111;
701 let Inst{5-4} = 0b00; // rotate
703 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
704 opc, "\t$dst, $src, ror $rot", []> {
705 let Inst{31-27} = 0b11111;
706 let Inst{26-23} = 0b0100;
707 let Inst{22-20} = opcod;
708 let Inst{19-16} = 0b1111; // Rn
709 let Inst{15-12} = 0b1111;
711 let Inst{5-4} = {?,?}; // rotate
715 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
716 /// register and one whose operand is a register rotated by 8/16/24.
717 multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
718 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
719 opc, "\t$dst, $LHS, $RHS",
720 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]> {
721 let Inst{31-27} = 0b11111;
722 let Inst{26-23} = 0b0100;
723 let Inst{22-20} = opcod;
724 let Inst{15-12} = 0b1111;
726 let Inst{5-4} = 0b00; // rotate
728 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
729 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
730 [(set GPR:$dst, (opnode GPR:$LHS,
731 (rotr GPR:$RHS, rot_imm:$rot)))]> {
732 let Inst{31-27} = 0b11111;
733 let Inst{26-23} = 0b0100;
734 let Inst{22-20} = opcod;
735 let Inst{15-12} = 0b1111;
737 let Inst{5-4} = {?,?}; // rotate
741 // DO variant - disassembly only, no pattern
743 multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> {
744 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
745 opc, "\t$dst, $LHS, $RHS", []> {
746 let Inst{31-27} = 0b11111;
747 let Inst{26-23} = 0b0100;
748 let Inst{22-20} = opcod;
749 let Inst{15-12} = 0b1111;
751 let Inst{5-4} = 0b00; // rotate
753 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
754 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> {
755 let Inst{31-27} = 0b11111;
756 let Inst{26-23} = 0b0100;
757 let Inst{22-20} = opcod;
758 let Inst{15-12} = 0b1111;
760 let Inst{5-4} = {?,?}; // rotate
764 //===----------------------------------------------------------------------===//
766 //===----------------------------------------------------------------------===//
768 //===----------------------------------------------------------------------===//
769 // Miscellaneous Instructions.
772 // LEApcrel - Load a pc-relative address into a register without offending the
774 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
775 "adr$p.w\t$dst, #$label", []> {
776 let Inst{31-27} = 0b11110;
777 let Inst{25-24} = 0b10;
778 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
781 let Inst{19-16} = 0b1111; // Rn
784 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
785 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
786 "adr$p.w\t$dst, #${label}_${id}", []> {
787 let Inst{31-27} = 0b11110;
788 let Inst{25-24} = 0b10;
789 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
792 let Inst{19-16} = 0b1111; // Rn
796 // ADD r, sp, {so_imm|i12}
797 def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
798 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> {
799 let Inst{31-27} = 0b11110;
801 let Inst{24-21} = 0b1000;
802 let Inst{20} = ?; // The S bit.
803 let Inst{19-16} = 0b1101; // Rn = sp
806 def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
807 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> {
808 let Inst{31-27} = 0b11110;
810 let Inst{24-21} = 0b0000;
811 let Inst{20} = 0; // The S bit.
812 let Inst{19-16} = 0b1101; // Rn = sp
817 def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
818 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> {
819 let Inst{31-27} = 0b11101;
820 let Inst{26-25} = 0b01;
821 let Inst{24-21} = 0b1000;
822 let Inst{20} = ?; // The S bit.
823 let Inst{19-16} = 0b1101; // Rn = sp
827 // SUB r, sp, {so_imm|i12}
828 def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
829 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> {
830 let Inst{31-27} = 0b11110;
832 let Inst{24-21} = 0b1101;
833 let Inst{20} = ?; // The S bit.
834 let Inst{19-16} = 0b1101; // Rn = sp
837 def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
838 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> {
839 let Inst{31-27} = 0b11110;
841 let Inst{24-21} = 0b0101;
842 let Inst{20} = 0; // The S bit.
843 let Inst{19-16} = 0b1101; // Rn = sp
848 def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
850 "sub", "\t$dst, $sp, $rhs", []> {
851 let Inst{31-27} = 0b11101;
852 let Inst{26-25} = 0b01;
853 let Inst{24-21} = 0b1101;
854 let Inst{20} = ?; // The S bit.
855 let Inst{19-16} = 0b1101; // Rn = sp
859 // Signed and unsigned division, for disassembly only
860 def t2SDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
861 "sdiv", "\t$dst, $a, $b", []> {
862 let Inst{31-27} = 0b11111;
863 let Inst{26-21} = 0b011100;
865 let Inst{15-12} = 0b1111;
866 let Inst{7-4} = 0b1111;
869 def t2UDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
870 "udiv", "\t$dst, $a, $b", []> {
871 let Inst{31-27} = 0b11111;
872 let Inst{26-21} = 0b011101;
874 let Inst{15-12} = 0b1111;
875 let Inst{7-4} = 0b1111;
878 // Pseudo instruction that will expand into a t2SUBrSPi + a copy.
879 let usesCustomInserter = 1 in { // Expanded after instruction selection.
880 def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
881 NoItinerary, "@ sub.w\t$dst, $sp, $imm", []>;
882 def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
883 NoItinerary, "@ subw\t$dst, $sp, $imm", []>;
884 def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
885 NoItinerary, "@ sub\t$dst, $sp, $rhs", []>;
886 } // usesCustomInserter
889 //===----------------------------------------------------------------------===//
890 // Load / store Instructions.
894 let canFoldAsLoad = 1, isReMaterializable = 1 in
895 defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>;
897 // Loads with zero extension
898 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
899 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
901 // Loads with sign extension
902 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
903 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
905 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
907 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
908 (ins t2addrmode_imm8s4:$addr),
909 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
910 def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
911 (ins i32imm:$addr), IIC_iLoadi,
912 "ldrd", "\t$dst1, $addr", []> {
913 let Inst{19-16} = 0b1111; // Rn
917 // zextload i1 -> zextload i8
918 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
919 (t2LDRBi12 t2addrmode_imm12:$addr)>;
920 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
921 (t2LDRBi8 t2addrmode_imm8:$addr)>;
922 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
923 (t2LDRBs t2addrmode_so_reg:$addr)>;
924 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
925 (t2LDRBpci tconstpool:$addr)>;
927 // extload -> zextload
928 // FIXME: Reduce the number of patterns by legalizing extload to zextload
930 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
931 (t2LDRBi12 t2addrmode_imm12:$addr)>;
932 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
933 (t2LDRBi8 t2addrmode_imm8:$addr)>;
934 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
935 (t2LDRBs t2addrmode_so_reg:$addr)>;
936 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
937 (t2LDRBpci tconstpool:$addr)>;
939 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
940 (t2LDRBi12 t2addrmode_imm12:$addr)>;
941 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
942 (t2LDRBi8 t2addrmode_imm8:$addr)>;
943 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
944 (t2LDRBs t2addrmode_so_reg:$addr)>;
945 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
946 (t2LDRBpci tconstpool:$addr)>;
948 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
949 (t2LDRHi12 t2addrmode_imm12:$addr)>;
950 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
951 (t2LDRHi8 t2addrmode_imm8:$addr)>;
952 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
953 (t2LDRHs t2addrmode_so_reg:$addr)>;
954 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
955 (t2LDRHpci tconstpool:$addr)>;
959 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
960 (ins t2addrmode_imm8:$addr),
961 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
962 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
965 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb),
966 (ins GPR:$base, t2am_imm8_offset:$offset),
967 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
968 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
971 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
972 (ins t2addrmode_imm8:$addr),
973 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
974 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
976 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
977 (ins GPR:$base, t2am_imm8_offset:$offset),
978 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
979 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
982 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
983 (ins t2addrmode_imm8:$addr),
984 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
985 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
987 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
988 (ins GPR:$base, t2am_imm8_offset:$offset),
989 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
990 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
993 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
994 (ins t2addrmode_imm8:$addr),
995 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
996 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
998 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
999 (ins GPR:$base, t2am_imm8_offset:$offset),
1000 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1001 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
1004 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1005 (ins t2addrmode_imm8:$addr),
1006 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1007 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
1009 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1010 (ins GPR:$base, t2am_imm8_offset:$offset),
1011 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1012 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
1016 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1017 // for disassembly only.
1018 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1019 class T2IldT<bit signed, bits<2> type, string opc>
1020 : T2Ii8<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, opc,
1021 "\t$dst, $addr", []> {
1022 let Inst{31-27} = 0b11111;
1023 let Inst{26-25} = 0b00;
1024 let Inst{24} = signed;
1026 let Inst{22-21} = type;
1027 let Inst{20} = 1; // load
1029 let Inst{10-8} = 0b110; // PUW.
1032 def t2LDRT : T2IldT<0, 0b10, "ldrt">;
1033 def t2LDRBT : T2IldT<0, 0b00, "ldrbt">;
1034 def t2LDRHT : T2IldT<0, 0b01, "ldrht">;
1035 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt">;
1036 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht">;
1039 defm t2STR :T2I_st<0b10,"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
1040 defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1041 defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1044 let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in
1045 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1046 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
1047 IIC_iStorer, "strd", "\t$src1, $addr", []>;
1050 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1051 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1052 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1053 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1055 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1057 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1058 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1059 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1060 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1062 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1064 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1065 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1066 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1067 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1069 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1071 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1072 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1073 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1074 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1076 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1078 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1079 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1080 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1081 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1083 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1085 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1086 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1087 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1088 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1090 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1092 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1094 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1095 class T2IstT<bits<2> type, string opc>
1096 : T2Ii8<(outs GPR:$src), (ins t2addrmode_imm8:$addr), IIC_iStorei, opc,
1097 "\t$src, $addr", []> {
1098 let Inst{31-27} = 0b11111;
1099 let Inst{26-25} = 0b00;
1100 let Inst{24} = 0; // not signed
1102 let Inst{22-21} = type;
1103 let Inst{20} = 0; // store
1105 let Inst{10-8} = 0b110; // PUW
1108 def t2STRT : T2IstT<0b10, "strt">;
1109 def t2STRBT : T2IstT<0b00, "strbt">;
1110 def t2STRHT : T2IstT<0b01, "strht">;
1112 // ldrd / strd pre / post variants
1113 // For disassembly only.
1115 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1116 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1117 "ldrd", "\t$dst1, $dst2, [$base, $imm]!", []>;
1119 def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1120 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1121 "ldrd", "\t$dst1, $dst2, [$base], $imm", []>;
1123 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
1124 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1125 NoItinerary, "strd", "\t$src1, $src2, [$base, $imm]!", []>;
1127 def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1128 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1129 NoItinerary, "strd", "\t$src1, $src2, [$base], $imm", []>;
1131 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1132 // data/instruction access. These are for disassembly only.
1134 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
1135 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
1136 multiclass T2Ipl<bit instr, bit write, string opc> {
1138 def i12 : T2I<(outs), (ins GPR:$base, i32imm:$imm), IIC_iLoadi, opc,
1139 "\t[$base, $imm]", []> {
1140 let Inst{31-25} = 0b1111100;
1141 let Inst{24} = instr;
1142 let Inst{23} = 1; // U = 1
1144 let Inst{21} = write;
1146 let Inst{15-12} = 0b1111;
1149 def i8 : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1150 "\t[$base, $imm]", []> {
1151 let Inst{31-25} = 0b1111100;
1152 let Inst{24} = instr;
1153 let Inst{23} = 0; // U = 0
1155 let Inst{21} = write;
1157 let Inst{15-12} = 0b1111;
1158 let Inst{11-8} = 0b1100;
1161 def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1162 "\t[pc, $imm]", []> {
1163 let Inst{31-25} = 0b1111100;
1164 let Inst{24} = instr;
1165 let Inst{23} = ?; // add = (U == 1)
1167 let Inst{21} = write;
1169 let Inst{19-16} = 0b1111; // Rn = 0b1111
1170 let Inst{15-12} = 0b1111;
1173 def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoadi, opc,
1174 "\t[$base, $a]", []> {
1175 let Inst{31-25} = 0b1111100;
1176 let Inst{24} = instr;
1177 let Inst{23} = 0; // add = TRUE for T1
1179 let Inst{21} = write;
1181 let Inst{15-12} = 0b1111;
1182 let Inst{11-6} = 0000000;
1183 let Inst{5-4} = 0b00; // no shift is applied
1186 def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoadi, opc,
1187 "\t[$base, $a, lsl $shamt]", []> {
1188 let Inst{31-25} = 0b1111100;
1189 let Inst{24} = instr;
1190 let Inst{23} = 0; // add = TRUE for T1
1192 let Inst{21} = write;
1194 let Inst{15-12} = 0b1111;
1195 let Inst{11-6} = 0000000;
1199 defm t2PLD : T2Ipl<0, 0, "pld">;
1200 defm t2PLDW : T2Ipl<0, 1, "pldw">;
1201 defm t2PLI : T2Ipl<1, 0, "pli">;
1203 //===----------------------------------------------------------------------===//
1204 // Load / store multiple Instructions.
1207 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1208 def t2LDM : T2XI<(outs),
1209 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
1210 IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb", []> {
1211 let Inst{31-27} = 0b11101;
1212 let Inst{26-25} = 0b00;
1213 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1215 let Inst{21} = ?; // The W bit.
1216 let Inst{20} = 1; // Load
1219 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1220 def t2STM : T2XI<(outs),
1221 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
1222 IIC_iStorem, "stm${addr:submode}${p}${addr:wide}\t$addr, $wb", []> {
1223 let Inst{31-27} = 0b11101;
1224 let Inst{26-25} = 0b00;
1225 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1227 let Inst{21} = ?; // The W bit.
1228 let Inst{20} = 0; // Store
1231 //===----------------------------------------------------------------------===//
1232 // Move Instructions.
1235 let neverHasSideEffects = 1 in
1236 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
1237 "mov", ".w\t$dst, $src", []> {
1238 let Inst{31-27} = 0b11101;
1239 let Inst{26-25} = 0b01;
1240 let Inst{24-21} = 0b0010;
1241 let Inst{20} = ?; // The S bit.
1242 let Inst{19-16} = 0b1111; // Rn
1243 let Inst{14-12} = 0b000;
1244 let Inst{7-4} = 0b0000;
1247 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1248 let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
1249 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
1250 "mov", ".w\t$dst, $src",
1251 [(set GPR:$dst, t2_so_imm:$src)]> {
1252 let Inst{31-27} = 0b11110;
1254 let Inst{24-21} = 0b0010;
1255 let Inst{20} = ?; // The S bit.
1256 let Inst{19-16} = 0b1111; // Rn
1260 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1261 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1262 "movw", "\t$dst, $src",
1263 [(set GPR:$dst, imm0_65535:$src)]> {
1264 let Inst{31-27} = 0b11110;
1266 let Inst{24-21} = 0b0010;
1267 let Inst{20} = 0; // The S bit.
1271 let Constraints = "$src = $dst" in
1272 def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi,
1273 "movt", "\t$dst, $imm",
1275 (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]> {
1276 let Inst{31-27} = 0b11110;
1278 let Inst{24-21} = 0b0110;
1279 let Inst{20} = 0; // The S bit.
1283 def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>;
1285 //===----------------------------------------------------------------------===//
1286 // Extend Instructions.
1291 defm t2SXTB : T2I_unary_rrot<0b100, "sxtb",
1292 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1293 defm t2SXTH : T2I_unary_rrot<0b000, "sxth",
1294 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1295 defm t2SXTB16 : T2I_unary_rrot_DO<0b010, "sxtb16">;
1297 defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab",
1298 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1299 defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah",
1300 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1301 defm t2SXTAB16 : T2I_bin_rrot_DO<0b010, "sxtab16">;
1303 // TODO: SXT(A){B|H}16 - done for disassembly only
1307 let AddedComplexity = 16 in {
1308 defm t2UXTB : T2I_unary_rrot<0b101, "uxtb",
1309 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1310 defm t2UXTH : T2I_unary_rrot<0b001, "uxth",
1311 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1312 defm t2UXTB16 : T2I_unary_rrot_nw<0b011, "uxtb16",
1313 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1315 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1316 (t2UXTB16r_rot GPR:$Src, 24)>;
1317 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1318 (t2UXTB16r_rot GPR:$Src, 8)>;
1320 defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
1321 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1322 defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah",
1323 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1324 defm t2UXTAB16 : T2I_bin_rrot_DO<0b011, "uxtab16">;
1327 //===----------------------------------------------------------------------===//
1328 // Arithmetic Instructions.
1331 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1332 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1333 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1334 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1336 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1337 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1338 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1339 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1340 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1342 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1343 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1344 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1345 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1346 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1347 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1348 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1349 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1352 defm t2RSB : T2I_rbin_is <0b1110, "rsb",
1353 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1354 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1355 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1357 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1358 let AddedComplexity = 1 in
1359 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1360 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1361 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1362 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1363 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1364 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1366 // Select Bytes -- for disassembly only
1368 def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel",
1369 "\t$dst, $a, $b", []> {
1370 let Inst{31-27} = 0b11111;
1371 let Inst{26-24} = 0b010;
1373 let Inst{22-20} = 0b010;
1374 let Inst{15-12} = 0b1111;
1376 let Inst{6-4} = 0b000;
1379 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1380 // And Miscellaneous operations -- for disassembly only
1381 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc>
1382 : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, opc,
1383 "\t$dst, $a, $b", [/* For disassembly only; pattern left blank */]> {
1384 let Inst{31-27} = 0b11111;
1385 let Inst{26-23} = 0b0101;
1386 let Inst{22-20} = op22_20;
1387 let Inst{15-12} = 0b1111;
1388 let Inst{7-4} = op7_4;
1391 // Saturating add/subtract -- for disassembly only
1393 def t2QADD : T2I_pam<0b000, 0b1000, "qadd">;
1394 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1395 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1396 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1397 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1398 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1399 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1400 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub">;
1401 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1402 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1403 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1404 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1405 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1406 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1407 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1408 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1410 // Signed/Unsigned add/subtract -- for disassembly only
1412 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1413 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1414 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1415 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1416 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1417 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1418 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1419 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1420 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1421 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1422 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1423 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1425 // Signed/Unsigned halving add/subtract -- for disassembly only
1427 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1428 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1429 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1430 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1431 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1432 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1433 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1434 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1435 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1436 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1437 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1438 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1440 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1442 def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1443 NoItinerary, "usad8", "\t$dst, $a, $b", []> {
1444 let Inst{15-12} = 0b1111;
1446 def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst),
1447 (ins GPR:$a, GPR:$b, GPR:$acc), NoItinerary, "usada8",
1448 "\t$dst, $a, $b, $acc", []>;
1450 // Signed/Unsigned saturate -- for disassembly only
1452 def t2SSATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1453 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
1454 [/* For disassembly only; pattern left blank */]> {
1455 let Inst{31-27} = 0b11110;
1456 let Inst{25-22} = 0b1100;
1459 let Inst{21} = 0; // sh = '0'
1462 def t2SSATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1463 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt",
1464 [/* For disassembly only; pattern left blank */]> {
1465 let Inst{31-27} = 0b11110;
1466 let Inst{25-22} = 0b1100;
1469 let Inst{21} = 1; // sh = '1'
1472 def t2SSAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
1473 "ssat16", "\t$dst, $bit_pos, $a",
1474 [/* For disassembly only; pattern left blank */]> {
1475 let Inst{31-27} = 0b11110;
1476 let Inst{25-22} = 0b1100;
1479 let Inst{21} = 1; // sh = '1'
1480 let Inst{14-12} = 0b000; // imm3 = '000'
1481 let Inst{7-6} = 0b00; // imm2 = '00'
1484 def t2USATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1485 NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt",
1486 [/* For disassembly only; pattern left blank */]> {
1487 let Inst{31-27} = 0b11110;
1488 let Inst{25-22} = 0b1110;
1491 let Inst{21} = 0; // sh = '0'
1494 def t2USATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1495 NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt",
1496 [/* For disassembly only; pattern left blank */]> {
1497 let Inst{31-27} = 0b11110;
1498 let Inst{25-22} = 0b1110;
1501 let Inst{21} = 1; // sh = '1'
1504 def t2USAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
1505 "usat16", "\t$dst, $bit_pos, $a",
1506 [/* For disassembly only; pattern left blank */]> {
1507 let Inst{31-27} = 0b11110;
1508 let Inst{25-22} = 0b1110;
1511 let Inst{21} = 1; // sh = '1'
1512 let Inst{14-12} = 0b000; // imm3 = '000'
1513 let Inst{7-6} = 0b00; // imm2 = '00'
1516 //===----------------------------------------------------------------------===//
1517 // Shift and rotate Instructions.
1520 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1521 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1522 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1523 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1525 let Uses = [CPSR] in {
1526 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1527 "rrx", "\t$dst, $src",
1528 [(set GPR:$dst, (ARMrrx GPR:$src))]> {
1529 let Inst{31-27} = 0b11101;
1530 let Inst{26-25} = 0b01;
1531 let Inst{24-21} = 0b0010;
1532 let Inst{20} = ?; // The S bit.
1533 let Inst{19-16} = 0b1111; // Rn
1534 let Inst{14-12} = 0b000;
1535 let Inst{7-4} = 0b0011;
1539 let Defs = [CPSR] in {
1540 def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1541 "lsrs.w\t$dst, $src, #1",
1542 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]> {
1543 let Inst{31-27} = 0b11101;
1544 let Inst{26-25} = 0b01;
1545 let Inst{24-21} = 0b0010;
1546 let Inst{20} = 1; // The S bit.
1547 let Inst{19-16} = 0b1111; // Rn
1548 let Inst{5-4} = 0b01; // Shift type.
1549 // Shift amount = Inst{14-12:7-6} = 1.
1550 let Inst{14-12} = 0b000;
1551 let Inst{7-6} = 0b01;
1553 def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1554 "asrs.w\t$dst, $src, #1",
1555 [(set GPR:$dst, (ARMsra_flag GPR:$src))]> {
1556 let Inst{31-27} = 0b11101;
1557 let Inst{26-25} = 0b01;
1558 let Inst{24-21} = 0b0010;
1559 let Inst{20} = 1; // The S bit.
1560 let Inst{19-16} = 0b1111; // Rn
1561 let Inst{5-4} = 0b10; // Shift type.
1562 // Shift amount = Inst{14-12:7-6} = 1.
1563 let Inst{14-12} = 0b000;
1564 let Inst{7-6} = 0b01;
1568 //===----------------------------------------------------------------------===//
1569 // Bitwise Instructions.
1572 defm t2AND : T2I_bin_w_irs<0b0000, "and",
1573 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1574 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1575 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1576 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1577 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1579 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1580 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1582 let Constraints = "$src = $dst" in
1583 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1584 IIC_iUNAsi, "bfc", "\t$dst, $imm",
1585 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]> {
1586 let Inst{31-27} = 0b11110;
1588 let Inst{24-20} = 0b10110;
1589 let Inst{19-16} = 0b1111; // Rn
1593 def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1594 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
1595 let Inst{31-27} = 0b11110;
1597 let Inst{24-20} = 0b10100;
1601 def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1602 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
1603 let Inst{31-27} = 0b11110;
1605 let Inst{24-20} = 0b11100;
1609 // A8.6.18 BFI - Bitfield insert (Encoding T1)
1610 // Added for disassembler with the pattern field purposely left blank.
1611 // FIXME: Utilize this instruction in codgen.
1612 def t2BFI : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1613 IIC_iALUi, "bfi", "\t$dst, $src, $lsb, $width", []> {
1614 let Inst{31-27} = 0b11110;
1616 let Inst{24-20} = 0b10110;
1620 defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS,
1623 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
1624 let AddedComplexity = 1 in
1625 defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
1628 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
1629 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
1631 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
1632 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
1633 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>,
1634 Requires<[IsThumb2]>;
1636 def : T2Pat<(t2_so_imm_not:$src),
1637 (t2MVNi t2_so_imm_not:$src)>;
1639 //===----------------------------------------------------------------------===//
1640 // Multiply Instructions.
1642 let isCommutable = 1 in
1643 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1644 "mul", "\t$dst, $a, $b",
1645 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]> {
1646 let Inst{31-27} = 0b11111;
1647 let Inst{26-23} = 0b0110;
1648 let Inst{22-20} = 0b000;
1649 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1650 let Inst{7-4} = 0b0000; // Multiply
1653 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1654 "mla", "\t$dst, $a, $b, $c",
1655 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]> {
1656 let Inst{31-27} = 0b11111;
1657 let Inst{26-23} = 0b0110;
1658 let Inst{22-20} = 0b000;
1659 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1660 let Inst{7-4} = 0b0000; // Multiply
1663 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1664 "mls", "\t$dst, $a, $b, $c",
1665 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]> {
1666 let Inst{31-27} = 0b11111;
1667 let Inst{26-23} = 0b0110;
1668 let Inst{22-20} = 0b000;
1669 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1670 let Inst{7-4} = 0b0001; // Multiply and Subtract
1673 // Extra precision multiplies with low / high results
1674 let neverHasSideEffects = 1 in {
1675 let isCommutable = 1 in {
1676 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1677 "smull", "\t$ldst, $hdst, $a, $b", []> {
1678 let Inst{31-27} = 0b11111;
1679 let Inst{26-23} = 0b0111;
1680 let Inst{22-20} = 0b000;
1681 let Inst{7-4} = 0b0000;
1684 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1685 "umull", "\t$ldst, $hdst, $a, $b", []> {
1686 let Inst{31-27} = 0b11111;
1687 let Inst{26-23} = 0b0111;
1688 let Inst{22-20} = 0b010;
1689 let Inst{7-4} = 0b0000;
1693 // Multiply + accumulate
1694 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1695 "smlal", "\t$ldst, $hdst, $a, $b", []>{
1696 let Inst{31-27} = 0b11111;
1697 let Inst{26-23} = 0b0111;
1698 let Inst{22-20} = 0b100;
1699 let Inst{7-4} = 0b0000;
1702 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1703 "umlal", "\t$ldst, $hdst, $a, $b", []>{
1704 let Inst{31-27} = 0b11111;
1705 let Inst{26-23} = 0b0111;
1706 let Inst{22-20} = 0b110;
1707 let Inst{7-4} = 0b0000;
1710 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1711 "umaal", "\t$ldst, $hdst, $a, $b", []>{
1712 let Inst{31-27} = 0b11111;
1713 let Inst{26-23} = 0b0111;
1714 let Inst{22-20} = 0b110;
1715 let Inst{7-4} = 0b0110;
1717 } // neverHasSideEffects
1719 // Rounding variants of the below included for disassembly only
1721 // Most significant word multiply
1722 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1723 "smmul", "\t$dst, $a, $b",
1724 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]> {
1725 let Inst{31-27} = 0b11111;
1726 let Inst{26-23} = 0b0110;
1727 let Inst{22-20} = 0b101;
1728 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1729 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1732 def t2SMMULR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1733 "smmulr", "\t$dst, $a, $b", []> {
1734 let Inst{31-27} = 0b11111;
1735 let Inst{26-23} = 0b0110;
1736 let Inst{22-20} = 0b101;
1737 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1738 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1741 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1742 "smmla", "\t$dst, $a, $b, $c",
1743 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]> {
1744 let Inst{31-27} = 0b11111;
1745 let Inst{26-23} = 0b0110;
1746 let Inst{22-20} = 0b101;
1747 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1748 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1751 def t2SMMLAR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1752 "smmlar", "\t$dst, $a, $b, $c", []> {
1753 let Inst{31-27} = 0b11111;
1754 let Inst{26-23} = 0b0110;
1755 let Inst{22-20} = 0b101;
1756 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1757 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1760 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1761 "smmls", "\t$dst, $a, $b, $c",
1762 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]> {
1763 let Inst{31-27} = 0b11111;
1764 let Inst{26-23} = 0b0110;
1765 let Inst{22-20} = 0b110;
1766 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1767 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1770 def t2SMMLSR : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1771 "smmlsr", "\t$dst, $a, $b, $c", []> {
1772 let Inst{31-27} = 0b11111;
1773 let Inst{26-23} = 0b0110;
1774 let Inst{22-20} = 0b110;
1775 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1776 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1779 multiclass T2I_smul<string opc, PatFrag opnode> {
1780 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1781 !strconcat(opc, "bb"), "\t$dst, $a, $b",
1782 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1783 (sext_inreg GPR:$b, i16)))]> {
1784 let Inst{31-27} = 0b11111;
1785 let Inst{26-23} = 0b0110;
1786 let Inst{22-20} = 0b001;
1787 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1788 let Inst{7-6} = 0b00;
1789 let Inst{5-4} = 0b00;
1792 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1793 !strconcat(opc, "bt"), "\t$dst, $a, $b",
1794 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1795 (sra GPR:$b, (i32 16))))]> {
1796 let Inst{31-27} = 0b11111;
1797 let Inst{26-23} = 0b0110;
1798 let Inst{22-20} = 0b001;
1799 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1800 let Inst{7-6} = 0b00;
1801 let Inst{5-4} = 0b01;
1804 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1805 !strconcat(opc, "tb"), "\t$dst, $a, $b",
1806 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1807 (sext_inreg GPR:$b, i16)))]> {
1808 let Inst{31-27} = 0b11111;
1809 let Inst{26-23} = 0b0110;
1810 let Inst{22-20} = 0b001;
1811 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1812 let Inst{7-6} = 0b00;
1813 let Inst{5-4} = 0b10;
1816 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1817 !strconcat(opc, "tt"), "\t$dst, $a, $b",
1818 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1819 (sra GPR:$b, (i32 16))))]> {
1820 let Inst{31-27} = 0b11111;
1821 let Inst{26-23} = 0b0110;
1822 let Inst{22-20} = 0b001;
1823 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1824 let Inst{7-6} = 0b00;
1825 let Inst{5-4} = 0b11;
1828 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1829 !strconcat(opc, "wb"), "\t$dst, $a, $b",
1830 [(set GPR:$dst, (sra (opnode GPR:$a,
1831 (sext_inreg GPR:$b, i16)), (i32 16)))]> {
1832 let Inst{31-27} = 0b11111;
1833 let Inst{26-23} = 0b0110;
1834 let Inst{22-20} = 0b011;
1835 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1836 let Inst{7-6} = 0b00;
1837 let Inst{5-4} = 0b00;
1840 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1841 !strconcat(opc, "wt"), "\t$dst, $a, $b",
1842 [(set GPR:$dst, (sra (opnode GPR:$a,
1843 (sra GPR:$b, (i32 16))), (i32 16)))]> {
1844 let Inst{31-27} = 0b11111;
1845 let Inst{26-23} = 0b0110;
1846 let Inst{22-20} = 0b011;
1847 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1848 let Inst{7-6} = 0b00;
1849 let Inst{5-4} = 0b01;
1854 multiclass T2I_smla<string opc, PatFrag opnode> {
1855 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1856 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1857 [(set GPR:$dst, (add GPR:$acc,
1858 (opnode (sext_inreg GPR:$a, i16),
1859 (sext_inreg GPR:$b, i16))))]> {
1860 let Inst{31-27} = 0b11111;
1861 let Inst{26-23} = 0b0110;
1862 let Inst{22-20} = 0b001;
1863 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1864 let Inst{7-6} = 0b00;
1865 let Inst{5-4} = 0b00;
1868 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1869 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1870 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1871 (sra GPR:$b, (i32 16)))))]> {
1872 let Inst{31-27} = 0b11111;
1873 let Inst{26-23} = 0b0110;
1874 let Inst{22-20} = 0b001;
1875 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1876 let Inst{7-6} = 0b00;
1877 let Inst{5-4} = 0b01;
1880 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1881 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1882 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1883 (sext_inreg GPR:$b, i16))))]> {
1884 let Inst{31-27} = 0b11111;
1885 let Inst{26-23} = 0b0110;
1886 let Inst{22-20} = 0b001;
1887 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1888 let Inst{7-6} = 0b00;
1889 let Inst{5-4} = 0b10;
1892 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1893 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1894 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1895 (sra GPR:$b, (i32 16)))))]> {
1896 let Inst{31-27} = 0b11111;
1897 let Inst{26-23} = 0b0110;
1898 let Inst{22-20} = 0b001;
1899 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1900 let Inst{7-6} = 0b00;
1901 let Inst{5-4} = 0b11;
1904 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1905 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1906 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1907 (sext_inreg GPR:$b, i16)), (i32 16))))]> {
1908 let Inst{31-27} = 0b11111;
1909 let Inst{26-23} = 0b0110;
1910 let Inst{22-20} = 0b011;
1911 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1912 let Inst{7-6} = 0b00;
1913 let Inst{5-4} = 0b00;
1916 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1917 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1918 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1919 (sra GPR:$b, (i32 16))), (i32 16))))]> {
1920 let Inst{31-27} = 0b11111;
1921 let Inst{26-23} = 0b0110;
1922 let Inst{22-20} = 0b011;
1923 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1924 let Inst{7-6} = 0b00;
1925 let Inst{5-4} = 0b01;
1929 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1930 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1932 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
1933 def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs GPR:$ldst,GPR:$hdst),
1934 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
1935 [/* For disassembly only; pattern left blank */]>;
1936 def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs GPR:$ldst,GPR:$hdst),
1937 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
1938 [/* For disassembly only; pattern left blank */]>;
1939 def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs GPR:$ldst,GPR:$hdst),
1940 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
1941 [/* For disassembly only; pattern left blank */]>;
1942 def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs GPR:$ldst,GPR:$hdst),
1943 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
1944 [/* For disassembly only; pattern left blank */]>;
1946 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1947 // These are for disassembly only.
1949 def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1950 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
1951 let Inst{15-12} = 0b1111;
1953 def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1954 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
1955 let Inst{15-12} = 0b1111;
1957 def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1958 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
1959 let Inst{15-12} = 0b1111;
1961 def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1962 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
1963 let Inst{15-12} = 0b1111;
1965 def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst),
1966 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlad",
1967 "\t$dst, $a, $b, $acc", []>;
1968 def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst),
1969 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smladx",
1970 "\t$dst, $a, $b, $acc", []>;
1971 def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst),
1972 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsd",
1973 "\t$dst, $a, $b, $acc", []>;
1974 def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst),
1975 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsdx",
1976 "\t$dst, $a, $b, $acc", []>;
1977 def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs GPR:$ldst,GPR:$hdst),
1978 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlald",
1979 "\t$ldst, $hdst, $a, $b", []>;
1980 def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs GPR:$ldst,GPR:$hdst),
1981 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaldx",
1982 "\t$ldst, $hdst, $a, $b", []>;
1983 def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs GPR:$ldst,GPR:$hdst),
1984 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsld",
1985 "\t$ldst, $hdst, $a, $b", []>;
1986 def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs GPR:$ldst,GPR:$hdst),
1987 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsldx",
1988 "\t$ldst, $hdst, $a, $b", []>;
1990 //===----------------------------------------------------------------------===//
1991 // Misc. Arithmetic Instructions.
1994 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
1995 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1996 : T2I<oops, iops, itin, opc, asm, pattern> {
1997 let Inst{31-27} = 0b11111;
1998 let Inst{26-22} = 0b01010;
1999 let Inst{21-20} = op1;
2000 let Inst{15-12} = 0b1111;
2001 let Inst{7-6} = 0b10;
2002 let Inst{5-4} = op2;
2005 def t2CLZ : T2I_misc<0b11, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2006 "clz", "\t$dst, $src", [(set GPR:$dst, (ctlz GPR:$src))]>;
2008 def t2RBIT : T2I_misc<0b01, 0b10, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2009 "rbit", "\t$dst, $src",
2010 [(set GPR:$dst, (ARMrbit GPR:$src))]>;
2012 def t2REV : T2I_misc<0b01, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2013 "rev", ".w\t$dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>;
2015 def t2REV16 : T2I_misc<0b01, 0b01, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2016 "rev16", ".w\t$dst, $src",
2018 (or (and (srl GPR:$src, (i32 8)), 0xFF),
2019 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
2020 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
2021 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
2023 def t2REVSH : T2I_misc<0b01, 0b11, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2024 "revsh", ".w\t$dst, $src",
2027 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
2028 (shl GPR:$src, (i32 8))), i16))]>;
2030 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
2031 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt",
2032 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
2033 (and (shl GPR:$src2, (i32 imm:$shamt)),
2035 let Inst{31-27} = 0b11101;
2036 let Inst{26-25} = 0b01;
2037 let Inst{24-20} = 0b01100;
2038 let Inst{5} = 0; // BT form
2042 // Alternate cases for PKHBT where identities eliminate some nodes.
2043 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
2044 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
2045 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
2046 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
2048 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
2049 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
2050 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
2051 (and (sra GPR:$src2, imm16_31:$shamt),
2053 let Inst{31-27} = 0b11101;
2054 let Inst{26-25} = 0b01;
2055 let Inst{24-20} = 0b01100;
2056 let Inst{5} = 1; // TB form
2060 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2061 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2062 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
2063 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
2064 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
2065 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
2066 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
2068 //===----------------------------------------------------------------------===//
2069 // Comparison Instructions...
2072 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2073 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2074 defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
2075 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2077 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2078 // Compare-to-zero still works out, just not the relationals
2079 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2080 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2081 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2082 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2084 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2085 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2087 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2088 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2090 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2091 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
2092 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2093 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
2095 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
2096 // Short range conditional branch. Looks awesome for loops. Need to figure
2097 // out how to use this one.
2100 // Conditional moves
2101 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2102 // a two-value operand where a dag node expects two operands. :(
2103 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr,
2104 "mov", ".w\t$dst, $true",
2105 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
2106 RegConstraint<"$false = $dst"> {
2107 let Inst{31-27} = 0b11101;
2108 let Inst{26-25} = 0b01;
2109 let Inst{24-21} = 0b0010;
2110 let Inst{20} = 0; // The S bit.
2111 let Inst{19-16} = 0b1111; // Rn
2112 let Inst{14-12} = 0b000;
2113 let Inst{7-4} = 0b0000;
2116 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
2117 IIC_iCMOVi, "mov", ".w\t$dst, $true",
2118 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
2119 RegConstraint<"$false = $dst"> {
2120 let Inst{31-27} = 0b11110;
2122 let Inst{24-21} = 0b0010;
2123 let Inst{20} = 0; // The S bit.
2124 let Inst{19-16} = 0b1111; // Rn
2128 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2129 string opc, string asm, list<dag> pattern>
2130 : T2I<oops, iops, itin, opc, asm, pattern> {
2131 let Inst{31-27} = 0b11101;
2132 let Inst{26-25} = 0b01;
2133 let Inst{24-21} = 0b0010;
2134 let Inst{20} = 0; // The S bit.
2135 let Inst{19-16} = 0b1111; // Rn
2136 let Inst{5-4} = opcod; // Shift type.
2138 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs GPR:$dst),
2139 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2140 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
2141 RegConstraint<"$false = $dst">;
2142 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs GPR:$dst),
2143 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2144 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
2145 RegConstraint<"$false = $dst">;
2146 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs GPR:$dst),
2147 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2148 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
2149 RegConstraint<"$false = $dst">;
2150 def t2MOVCCror : T2I_movcc_sh<0b11, (outs GPR:$dst),
2151 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2152 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
2153 RegConstraint<"$false = $dst">;
2155 //===----------------------------------------------------------------------===//
2156 // Atomic operations intrinsics
2159 // memory barriers protect the atomic sequences
2160 let hasSideEffects = 1 in {
2161 def t2Int_MemBarrierV7 : AInoP<(outs), (ins),
2162 Pseudo, NoItinerary,
2164 [(ARMMemBarrierV7)]>,
2165 Requires<[IsThumb2]> {
2166 let Inst{31-4} = 0xF3BF8F5;
2167 // FIXME: add support for options other than a full system DMB
2168 let Inst{3-0} = 0b1111;
2171 def t2Int_SyncBarrierV7 : AInoP<(outs), (ins),
2172 Pseudo, NoItinerary,
2174 [(ARMSyncBarrierV7)]>,
2175 Requires<[IsThumb2]> {
2176 let Inst{31-4} = 0xF3BF8F4;
2177 // FIXME: add support for options other than a full system DSB
2178 let Inst{3-0} = 0b1111;
2182 // Helper class for multiclass T2MemB -- for disassembly only
2183 class T2I_memb<string opc, string asm>
2184 : T2I<(outs), (ins), NoItinerary, opc, asm,
2185 [/* For disassembly only; pattern left blank */]>,
2186 Requires<[IsThumb2, HasV7]> {
2187 let Inst{31-20} = 0xf3b;
2188 let Inst{15-14} = 0b10;
2192 multiclass T2MemB<bits<4> op7_4, string opc> {
2194 def st : T2I_memb<opc, "\tst"> {
2195 let Inst{7-4} = op7_4;
2196 let Inst{3-0} = 0b1110;
2199 def ish : T2I_memb<opc, "\tish"> {
2200 let Inst{7-4} = op7_4;
2201 let Inst{3-0} = 0b1011;
2204 def ishst : T2I_memb<opc, "\tishst"> {
2205 let Inst{7-4} = op7_4;
2206 let Inst{3-0} = 0b1010;
2209 def nsh : T2I_memb<opc, "\tnsh"> {
2210 let Inst{7-4} = op7_4;
2211 let Inst{3-0} = 0b0111;
2214 def nshst : T2I_memb<opc, "\tnshst"> {
2215 let Inst{7-4} = op7_4;
2216 let Inst{3-0} = 0b0110;
2219 def osh : T2I_memb<opc, "\tosh"> {
2220 let Inst{7-4} = op7_4;
2221 let Inst{3-0} = 0b0011;
2224 def oshst : T2I_memb<opc, "\toshst"> {
2225 let Inst{7-4} = op7_4;
2226 let Inst{3-0} = 0b0010;
2230 // These DMB variants are for disassembly only.
2231 defm t2DMB : T2MemB<0b0101, "dmb">;
2233 // These DSB variants are for disassembly only.
2234 defm t2DSB : T2MemB<0b0100, "dsb">;
2236 // ISB has only full system option -- for disassembly only
2237 def t2ISBsy : T2I_memb<"isb", ""> {
2238 let Inst{7-4} = 0b0110;
2239 let Inst{3-0} = 0b1111;
2242 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2243 InstrItinClass itin, string opc, string asm, string cstr,
2244 list<dag> pattern, bits<4> rt2 = 0b1111>
2245 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2246 let Inst{31-27} = 0b11101;
2247 let Inst{26-20} = 0b0001101;
2248 let Inst{11-8} = rt2;
2249 let Inst{7-6} = 0b01;
2250 let Inst{5-4} = opcod;
2251 let Inst{3-0} = 0b1111;
2253 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2254 InstrItinClass itin, string opc, string asm, string cstr,
2255 list<dag> pattern, bits<4> rt2 = 0b1111>
2256 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2257 let Inst{31-27} = 0b11101;
2258 let Inst{26-20} = 0b0001100;
2259 let Inst{11-8} = rt2;
2260 let Inst{7-6} = 0b01;
2261 let Inst{5-4} = opcod;
2264 let mayLoad = 1 in {
2265 def t2LDREXB : T2I_ldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2266 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
2268 def t2LDREXH : T2I_ldrex<0b01, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2269 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
2271 def t2LDREX : Thumb2I<(outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2272 Size4Bytes, NoItinerary,
2273 "ldrex", "\t$dest, [$ptr]", "",
2275 let Inst{31-27} = 0b11101;
2276 let Inst{26-20} = 0b0000101;
2277 let Inst{11-8} = 0b1111;
2278 let Inst{7-0} = 0b00000000; // imm8 = 0
2280 def t2LDREXD : T2I_ldrex<0b11, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
2281 AddrModeNone, Size4Bytes, NoItinerary,
2282 "ldrexd", "\t$dest, $dest2, [$ptr]", "",
2286 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2287 def t2STREXB : T2I_strex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2288 AddrModeNone, Size4Bytes, NoItinerary,
2289 "strexb", "\t$success, $src, [$ptr]", "", []>;
2290 def t2STREXH : T2I_strex<0b01, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2291 AddrModeNone, Size4Bytes, NoItinerary,
2292 "strexh", "\t$success, $src, [$ptr]", "", []>;
2293 def t2STREX : Thumb2I<(outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2294 AddrModeNone, Size4Bytes, NoItinerary,
2295 "strex", "\t$success, $src, [$ptr]", "",
2297 let Inst{31-27} = 0b11101;
2298 let Inst{26-20} = 0b0000100;
2299 let Inst{7-0} = 0b00000000; // imm8 = 0
2301 def t2STREXD : T2I_strex<0b11, (outs GPR:$success),
2302 (ins GPR:$src, GPR:$src2, GPR:$ptr),
2303 AddrModeNone, Size4Bytes, NoItinerary,
2304 "strexd", "\t$success, $src, $src2, [$ptr]", "", [],
2308 // Clear-Exclusive is for disassembly only.
2309 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2310 [/* For disassembly only; pattern left blank */]>,
2311 Requires<[IsARM, HasV7]> {
2312 let Inst{31-20} = 0xf3b;
2313 let Inst{15-14} = 0b10;
2315 let Inst{7-4} = 0b0010;
2318 //===----------------------------------------------------------------------===//
2322 // __aeabi_read_tp preserves the registers r1-r3.
2324 Defs = [R0, R12, LR, CPSR] in {
2325 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2326 "bl\t__aeabi_read_tp",
2327 [(set R0, ARMthread_pointer)]> {
2328 let Inst{31-27} = 0b11110;
2329 let Inst{15-14} = 0b11;
2334 //===----------------------------------------------------------------------===//
2335 // SJLJ Exception handling intrinsics
2336 // eh_sjlj_setjmp() is an instruction sequence to store the return
2337 // address and save #0 in R0 for the non-longjmp case.
2338 // Since by its nature we may be coming from some other function to get
2339 // here, and we're using the stack frame for the containing function to
2340 // save/restore registers, we can't keep anything live in regs across
2341 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2342 // when we get here from a longjmp(). We force everthing out of registers
2343 // except for our own input by listing the relevant registers in Defs. By
2344 // doing so, we also cause the prologue/epilogue code to actively preserve
2345 // all of the callee-saved resgisters, which is exactly what we want.
2346 // The current SP is passed in $val, and we reuse the reg as a scratch.
2348 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2349 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2350 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2352 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
2353 AddrModeNone, SizeSpecial, NoItinerary,
2354 "str\t$val, [$src, #8]\t@ begin eh.setjmp\n"
2356 "\tadds\t$val, #9\n"
2357 "\tstr\t$val, [$src, #4]\n"
2360 "\tmovs\tr0, #1\t@ end eh.setjmp\n"
2362 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>;
2367 //===----------------------------------------------------------------------===//
2368 // Control-Flow Instructions
2371 // FIXME: remove when we have a way to marking a MI with these properties.
2372 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2374 // FIXME: Should pc be an implicit operand like PICADD, etc?
2375 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2376 hasExtraDefRegAllocReq = 1 in
2377 def t2LDM_RET : T2XI<(outs),
2378 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
2379 IIC_Br, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb",
2381 let Inst{31-27} = 0b11101;
2382 let Inst{26-25} = 0b00;
2383 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
2385 let Inst{21} = ?; // The W bit.
2386 let Inst{20} = 1; // Load
2389 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2390 let isPredicable = 1 in
2391 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2393 [(br bb:$target)]> {
2394 let Inst{31-27} = 0b11110;
2395 let Inst{15-14} = 0b10;
2399 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2402 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
2403 IIC_Br, "mov\tpc, $target\n$jt",
2404 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
2405 let Inst{31-27} = 0b11101;
2406 let Inst{26-20} = 0b0100100;
2407 let Inst{19-16} = 0b1111;
2408 let Inst{14-12} = 0b000;
2409 let Inst{11-8} = 0b1111; // Rd = pc
2410 let Inst{7-4} = 0b0000;
2413 // FIXME: Add a non-pc based case that can be predicated.
2416 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2417 IIC_Br, "tbb\t$index\n$jt", []> {
2418 let Inst{31-27} = 0b11101;
2419 let Inst{26-20} = 0b0001101;
2420 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2421 let Inst{15-8} = 0b11110000;
2422 let Inst{7-4} = 0b0000; // B form
2427 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2428 IIC_Br, "tbh\t$index\n$jt", []> {
2429 let Inst{31-27} = 0b11101;
2430 let Inst{26-20} = 0b0001101;
2431 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2432 let Inst{15-8} = 0b11110000;
2433 let Inst{7-4} = 0b0001; // H form
2436 // Generic versions of the above two instructions, for disassembly only
2438 def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2439 "tbb", "\t[$a, $b]", []>{
2440 let Inst{31-27} = 0b11101;
2441 let Inst{26-20} = 0b0001101;
2442 let Inst{15-8} = 0b11110000;
2443 let Inst{7-4} = 0b0000; // B form
2446 def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2447 "tbh", "\t[$a, $b, lsl #1]", []> {
2448 let Inst{31-27} = 0b11101;
2449 let Inst{26-20} = 0b0001101;
2450 let Inst{15-8} = 0b11110000;
2451 let Inst{7-4} = 0b0001; // H form
2453 } // isNotDuplicable, isIndirectBranch
2455 } // isBranch, isTerminator, isBarrier
2457 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2458 // a two-value operand where a dag node expects two operands. :(
2459 let isBranch = 1, isTerminator = 1 in
2460 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
2462 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
2463 let Inst{31-27} = 0b11110;
2464 let Inst{15-14} = 0b10;
2470 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
2471 AddrModeNone, Size2Bytes, IIC_iALUx,
2472 "it$mask\t$cc", "", []> {
2473 // 16-bit instruction.
2474 let Inst{31-16} = 0x0000;
2475 let Inst{15-8} = 0b10111111;
2478 // Branch and Exchange Jazelle -- for disassembly only
2480 def t2BXJ : T2I<(outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2481 [/* For disassembly only; pattern left blank */]> {
2482 let Inst{31-27} = 0b11110;
2484 let Inst{25-20} = 0b111100;
2485 let Inst{15-14} = 0b10;
2489 // Change Processor State is a system instruction -- for disassembly only.
2490 // The singleton $opt operand contains the following information:
2491 // opt{4-0} = mode from Inst{4-0}
2492 // opt{5} = changemode from Inst{17}
2493 // opt{8-6} = AIF from Inst{8-6}
2494 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
2495 def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
2496 [/* For disassembly only; pattern left blank */]> {
2497 let Inst{31-27} = 0b11110;
2499 let Inst{25-20} = 0b111010;
2500 let Inst{15-14} = 0b10;
2504 // A6.3.4 Branches and miscellaneous control
2505 // Table A6-14 Change Processor State, and hint instructions
2506 // Helper class for disassembly only.
2507 class T2I_hint<bits<8> op7_0, string opc, string asm>
2508 : T2I<(outs), (ins), NoItinerary, opc, asm,
2509 [/* For disassembly only; pattern left blank */]> {
2510 let Inst{31-20} = 0xf3a;
2511 let Inst{15-14} = 0b10;
2513 let Inst{10-8} = 0b000;
2514 let Inst{7-0} = op7_0;
2517 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
2518 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
2519 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
2520 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
2521 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
2523 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
2524 [/* For disassembly only; pattern left blank */]> {
2525 let Inst{31-20} = 0xf3a;
2526 let Inst{15-14} = 0b10;
2528 let Inst{10-8} = 0b000;
2529 let Inst{7-4} = 0b1111;
2532 // Secure Monitor Call is a system instruction -- for disassembly only
2533 // Option = Inst{19-16}
2534 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
2535 [/* For disassembly only; pattern left blank */]> {
2536 let Inst{31-27} = 0b11110;
2537 let Inst{26-20} = 0b1111111;
2538 let Inst{15-12} = 0b1000;
2541 // Store Return State is a system instruction -- for disassembly only
2542 def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
2543 [/* For disassembly only; pattern left blank */]> {
2544 let Inst{31-27} = 0b11101;
2545 let Inst{26-20} = 0b0000010; // W = 1
2548 def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
2549 [/* For disassembly only; pattern left blank */]> {
2550 let Inst{31-27} = 0b11101;
2551 let Inst{26-20} = 0b0000000; // W = 0
2554 def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
2555 [/* For disassembly only; pattern left blank */]> {
2556 let Inst{31-27} = 0b11101;
2557 let Inst{26-20} = 0b0011010; // W = 1
2560 def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
2561 [/* For disassembly only; pattern left blank */]> {
2562 let Inst{31-27} = 0b11101;
2563 let Inst{26-20} = 0b0011000; // W = 0
2566 // Return From Exception is a system instruction -- for disassembly only
2567 def t2RFEDBW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfedb", "\t$base!",
2568 [/* For disassembly only; pattern left blank */]> {
2569 let Inst{31-27} = 0b11101;
2570 let Inst{26-20} = 0b0000011; // W = 1
2573 def t2RFEDB : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeab", "\t$base",
2574 [/* For disassembly only; pattern left blank */]> {
2575 let Inst{31-27} = 0b11101;
2576 let Inst{26-20} = 0b0000001; // W = 0
2579 def t2RFEIAW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base!",
2580 [/* For disassembly only; pattern left blank */]> {
2581 let Inst{31-27} = 0b11101;
2582 let Inst{26-20} = 0b0011011; // W = 1
2585 def t2RFEIA : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base",
2586 [/* For disassembly only; pattern left blank */]> {
2587 let Inst{31-27} = 0b11101;
2588 let Inst{26-20} = 0b0011001; // W = 0
2591 //===----------------------------------------------------------------------===//
2592 // Non-Instruction Patterns
2595 // Two piece so_imms.
2596 def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS),
2597 (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2598 (t2_so_imm2part_2 imm:$RHS))>;
2599 def : T2Pat<(xor GPR:$LHS, t2_so_imm2part:$RHS),
2600 (t2EORri (t2EORri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2601 (t2_so_imm2part_2 imm:$RHS))>;
2602 def : T2Pat<(add GPR:$LHS, t2_so_imm2part:$RHS),
2603 (t2ADDri (t2ADDri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2604 (t2_so_imm2part_2 imm:$RHS))>;
2605 def : T2Pat<(add GPR:$LHS, t2_so_neg_imm2part:$RHS),
2606 (t2SUBri (t2SUBri GPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
2607 (t2_so_neg_imm2part_2 imm:$RHS))>;
2609 // 32-bit immediate using movw + movt.
2610 // This is a single pseudo instruction to make it re-materializable. Remove
2611 // when we can do generalized remat.
2612 let isReMaterializable = 1 in
2613 def t2MOVi32imm : T2Ix2<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
2614 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2615 [(set GPR:$dst, (i32 imm:$src))]>;
2617 // ConstantPool, GlobalAddress, and JumpTable
2618 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
2619 Requires<[IsThumb2, DontUseMovt]>;
2620 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
2621 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
2622 Requires<[IsThumb2, UseMovt]>;
2624 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2625 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
2627 // Pseudo instruction that combines ldr from constpool and add pc. This should
2628 // be expanded into two instructions late to allow if-conversion and
2630 let canFoldAsLoad = 1, isReMaterializable = 1 in
2631 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
2632 NoItinerary, "@ ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
2633 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
2635 Requires<[IsThumb2]>;
2637 //===----------------------------------------------------------------------===//
2638 // Move between special register and ARM core register -- for disassembly only
2642 def t2MRS : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
2643 [/* For disassembly only; pattern left blank */]> {
2644 let Inst{31-27} = 0b11110;
2646 let Inst{25-21} = 0b11111;
2647 let Inst{20} = 0; // The R bit.
2648 let Inst{15-14} = 0b10;
2653 def t2MRSsys : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
2654 [/* For disassembly only; pattern left blank */]> {
2655 let Inst{31-27} = 0b11110;
2657 let Inst{25-21} = 0b11111;
2658 let Inst{20} = 1; // The R bit.
2659 let Inst{15-14} = 0b10;
2664 def t2MSR : T2I<(outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, "msr",
2665 "\tcpsr$mask, $src",
2666 [/* For disassembly only; pattern left blank */]> {
2667 let Inst{31-27} = 0b11110;
2669 let Inst{25-21} = 0b11100;
2670 let Inst{20} = 0; // The R bit.
2671 let Inst{15-14} = 0b10;
2676 def t2MSRsys : T2I<(outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, "msr",
2677 "\tspsr$mask, $src",
2678 [/* For disassembly only; pattern left blank */]> {
2679 let Inst{31-27} = 0b11110;
2681 let Inst{25-21} = 0b11100;
2682 let Inst{20} = 1; // The R bit.
2683 let Inst{15-14} = 0b10;