1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Shifted operands. No register controlled shifts for Thumb2.
25 // Note: We do not support rrx shifted operands yet.
26 def t2_so_reg : Operand<i32>, // reg imm
27 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
29 let EncoderMethod = "getT2SORegOpValue";
30 let PrintMethod = "printT2SOOperand";
31 let MIOperandInfo = (ops rGPR, i32imm);
34 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
35 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
39 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
40 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
41 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
44 // t2_so_imm - Match a 32-bit immediate operand, which is an
45 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
46 // immediate splatted into multiple bytes of the word. t2_so_imm values are
47 // represented in the imm field in the same 12-bit form that they are encoded
48 // into t2_so_imm instructions: the 8-bit immediate is the least significant
49 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
50 def t2_so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_t2_so_imm(N); }]> {
51 let EncoderMethod = "getT2SOImmOpValue";
54 // t2_so_imm_not - Match an immediate that is a complement
56 def t2_so_imm_not : Operand<i32>,
58 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
59 }], t2_so_imm_not_XFORM>;
61 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
62 def t2_so_imm_neg : Operand<i32>,
64 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
65 }], t2_so_imm_neg_XFORM>;
67 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
68 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
69 // to get the first/second pieces.
70 def t2_so_imm2part : Operand<i32>,
72 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
76 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
77 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
78 return CurDAG->getTargetConstant(V, MVT::i32);
81 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
82 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
83 return CurDAG->getTargetConstant(V, MVT::i32);
86 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
87 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
91 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
92 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
93 return CurDAG->getTargetConstant(V, MVT::i32);
96 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
97 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
98 return CurDAG->getTargetConstant(V, MVT::i32);
101 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
102 def imm1_31 : PatLeaf<(i32 imm), [{
103 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
106 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
107 def imm0_4095 : Operand<i32>,
108 PatLeaf<(i32 imm), [{
109 return (uint32_t)N->getZExtValue() < 4096;
112 def imm0_4095_neg : PatLeaf<(i32 imm), [{
113 return (uint32_t)(-N->getZExtValue()) < 4096;
116 def imm0_255_neg : PatLeaf<(i32 imm), [{
117 return (uint32_t)(-N->getZExtValue()) < 255;
120 def imm0_255_not : PatLeaf<(i32 imm), [{
121 return (uint32_t)(~N->getZExtValue()) < 255;
124 // Define Thumb2 specific addressing modes.
126 // t2addrmode_imm12 := reg + imm12
127 def t2addrmode_imm12 : Operand<i32>,
128 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
129 let PrintMethod = "printAddrModeImm12Operand";
130 string EncoderMethod = "getAddrModeImm12OpValue";
131 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
134 // t2addrmode_imm8 := reg +/- imm8
135 def t2addrmode_imm8 : Operand<i32>,
136 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
137 let PrintMethod = "printT2AddrModeImm8Operand";
138 string EncoderMethod = "getT2AddrModeImm8OpValue";
139 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
142 def t2am_imm8_offset : Operand<i32>,
143 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
144 [], [SDNPWantRoot]> {
145 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
146 string EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
149 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
150 def t2addrmode_imm8s4 : Operand<i32> {
151 let PrintMethod = "printT2AddrModeImm8s4Operand";
152 string EncoderMethod = "getT2AddrModeImm8s4OpValue";
153 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
156 def t2am_imm8s4_offset : Operand<i32> {
157 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
160 // t2addrmode_so_reg := reg + (reg << imm2)
161 def t2addrmode_so_reg : Operand<i32>,
162 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
163 let PrintMethod = "printT2AddrModeSoRegOperand";
164 string EncoderMethod = "getT2AddrModeSORegOpValue";
165 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
169 //===----------------------------------------------------------------------===//
170 // Multiclass helpers...
174 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
175 string opc, string asm, list<dag> pattern>
176 : T2I<oops, iops, itin, opc, asm, pattern> {
180 let Inst{11-8} = Rd{3-0};
181 let Inst{26} = imm{11};
182 let Inst{14-12} = imm{10-8};
183 let Inst{7-0} = imm{7-0};
187 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
188 string opc, string asm, list<dag> pattern>
189 : T2sI<oops, iops, itin, opc, asm, pattern> {
194 let Inst{11-8} = Rd{3-0};
195 let Inst{26} = imm{11};
196 let Inst{14-12} = imm{10-8};
197 let Inst{7-0} = imm{7-0};
200 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
201 string opc, string asm, list<dag> pattern>
202 : T2I<oops, iops, itin, opc, asm, pattern> {
206 let Inst{19-16} = Rn{3-0};
207 let Inst{26} = imm{11};
208 let Inst{14-12} = imm{10-8};
209 let Inst{7-0} = imm{7-0};
213 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
214 string opc, string asm, list<dag> pattern>
215 : T2I<oops, iops, itin, opc, asm, pattern> {
219 let Inst{11-8} = Rd{3-0};
220 let Inst{3-0} = ShiftedRm{3-0};
221 let Inst{5-4} = ShiftedRm{6-5};
222 let Inst{14-12} = ShiftedRm{11-9};
223 let Inst{7-6} = ShiftedRm{8-7};
226 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
227 string opc, string asm, list<dag> pattern>
228 : T2I<oops, iops, itin, opc, asm, pattern> {
232 let Inst{11-8} = Rd{3-0};
233 let Inst{3-0} = ShiftedRm{3-0};
234 let Inst{5-4} = ShiftedRm{6-5};
235 let Inst{14-12} = ShiftedRm{11-9};
236 let Inst{7-6} = ShiftedRm{8-7};
239 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
240 string opc, string asm, list<dag> pattern>
241 : T2I<oops, iops, itin, opc, asm, pattern> {
245 let Inst{19-16} = Rn{3-0};
246 let Inst{3-0} = ShiftedRm{3-0};
247 let Inst{5-4} = ShiftedRm{6-5};
248 let Inst{14-12} = ShiftedRm{11-9};
249 let Inst{7-6} = ShiftedRm{8-7};
252 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
253 string opc, string asm, list<dag> pattern>
254 : T2I<oops, iops, itin, opc, asm, pattern> {
258 let Inst{11-8} = Rd{3-0};
259 let Inst{3-0} = Rm{3-0};
262 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
263 string opc, string asm, list<dag> pattern>
264 : T2sI<oops, iops, itin, opc, asm, pattern> {
268 let Inst{11-8} = Rd{3-0};
269 let Inst{3-0} = Rm{3-0};
272 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
273 string opc, string asm, list<dag> pattern>
274 : T2I<oops, iops, itin, opc, asm, pattern> {
278 let Inst{19-16} = Rn{3-0};
279 let Inst{3-0} = Rm{3-0};
283 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
284 string opc, string asm, list<dag> pattern>
285 : T2I<oops, iops, itin, opc, asm, pattern> {
289 let Inst{11-8} = Rd{3-0};
290 let Inst{3-0} = Rm{3-0};
293 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
294 string opc, string asm, list<dag> pattern>
295 : T2sI<oops, iops, itin, opc, asm, pattern> {
300 let Inst{11-8} = Rd{3-0};
301 let Inst{19-16} = Rn{3-0};
302 let Inst{26} = imm{11};
303 let Inst{14-12} = imm{10-8};
304 let Inst{7-0} = imm{7-0};
307 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
308 string opc, string asm, list<dag> pattern>
309 : T2I<oops, iops, itin, opc, asm, pattern> {
314 let Inst{11-8} = Rd{3-0};
315 let Inst{3-0} = Rm{3-0};
316 let Inst{14-12} = imm{4-2};
317 let Inst{7-6} = imm{1-0};
320 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
321 string opc, string asm, list<dag> pattern>
322 : T2sI<oops, iops, itin, opc, asm, pattern> {
327 let Inst{11-8} = Rd{3-0};
328 let Inst{3-0} = Rm{3-0};
329 let Inst{14-12} = imm{4-2};
330 let Inst{7-6} = imm{1-0};
333 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
334 string opc, string asm, list<dag> pattern>
335 : T2I<oops, iops, itin, opc, asm, pattern> {
340 let Inst{11-8} = Rd{3-0};
341 let Inst{19-16} = Rn{3-0};
342 let Inst{3-0} = Rm{3-0};
345 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
346 string opc, string asm, list<dag> pattern>
347 : T2sI<oops, iops, itin, opc, asm, pattern> {
352 let Inst{11-8} = Rd{3-0};
353 let Inst{19-16} = Rn{3-0};
354 let Inst{3-0} = Rm{3-0};
357 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
358 string opc, string asm, list<dag> pattern>
359 : T2I<oops, iops, itin, opc, asm, pattern> {
364 let Inst{11-8} = Rd{3-0};
365 let Inst{19-16} = Rn{3-0};
366 let Inst{3-0} = ShiftedRm{3-0};
367 let Inst{5-4} = ShiftedRm{6-5};
368 let Inst{14-12} = ShiftedRm{11-9};
369 let Inst{7-6} = ShiftedRm{8-7};
372 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
373 string opc, string asm, list<dag> pattern>
374 : T2sI<oops, iops, itin, opc, asm, pattern> {
379 let Inst{11-8} = Rd{3-0};
380 let Inst{19-16} = Rn{3-0};
381 let Inst{3-0} = ShiftedRm{3-0};
382 let Inst{5-4} = ShiftedRm{6-5};
383 let Inst{14-12} = ShiftedRm{11-9};
384 let Inst{7-6} = ShiftedRm{8-7};
387 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
388 string opc, string asm, list<dag> pattern>
389 : T2I<oops, iops, itin, opc, asm, pattern> {
395 let Inst{11-8} = Rd{3-0};
396 let Inst{19-16} = Rn{3-0};
397 let Inst{3-0} = Rm{3-0};
398 let Inst{15-12} = Ra{3-0};
402 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
403 /// unary operation that produces a value. These are predicable and can be
404 /// changed to modify CPSR.
405 multiclass T2I_un_irs<bits<4> opcod, string opc,
406 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
407 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
409 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
411 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
412 let isAsCheapAsAMove = Cheap;
413 let isReMaterializable = ReMat;
414 let Inst{31-27} = 0b11110;
416 let Inst{24-21} = opcod;
417 let Inst{20} = ?; // The S bit.
418 let Inst{19-16} = 0b1111; // Rn
422 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
424 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
425 let Inst{31-27} = 0b11101;
426 let Inst{26-25} = 0b01;
427 let Inst{24-21} = opcod;
428 let Inst{20} = ?; // The S bit.
429 let Inst{19-16} = 0b1111; // Rn
430 let Inst{14-12} = 0b000; // imm3
431 let Inst{7-6} = 0b00; // imm2
432 let Inst{5-4} = 0b00; // type
435 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
436 opc, ".w\t$Rd, $ShiftedRm",
437 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
438 let Inst{31-27} = 0b11101;
439 let Inst{26-25} = 0b01;
440 let Inst{24-21} = opcod;
441 let Inst{20} = ?; // The S bit.
442 let Inst{19-16} = 0b1111; // Rn
446 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
447 /// binary operation that produces a value. These are predicable and can be
448 /// changed to modify CPSR.
449 multiclass T2I_bin_irs<bits<4> opcod, string opc,
450 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
451 PatFrag opnode, bit Commutable = 0, string wide = ""> {
453 def ri : T2sTwoRegImm<
454 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
455 opc, "\t$Rd, $Rn, $imm",
456 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
457 let Inst{31-27} = 0b11110;
459 let Inst{24-21} = opcod;
460 let Inst{20} = ?; // The S bit.
464 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
465 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
466 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
467 let isCommutable = Commutable;
468 let Inst{31-27} = 0b11101;
469 let Inst{26-25} = 0b01;
470 let Inst{24-21} = opcod;
471 let Inst{20} = ?; // The S bit.
472 let Inst{14-12} = 0b000; // imm3
473 let Inst{7-6} = 0b00; // imm2
474 let Inst{5-4} = 0b00; // type
477 def rs : T2sTwoRegShiftedReg<
478 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
479 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
480 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
481 let Inst{31-27} = 0b11101;
482 let Inst{26-25} = 0b01;
483 let Inst{24-21} = opcod;
484 let Inst{20} = ?; // The S bit.
488 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
489 // the ".w" prefix to indicate that they are wide.
490 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
491 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
492 PatFrag opnode, bit Commutable = 0> :
493 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w">;
495 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
496 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
497 /// it is equivalent to the T2I_bin_irs counterpart.
498 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
500 def ri : T2sTwoRegImm<
501 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
502 opc, ".w\t$Rd, $Rn, $imm",
503 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
504 let Inst{31-27} = 0b11110;
506 let Inst{24-21} = opcod;
507 let Inst{20} = ?; // The S bit.
511 def rr : T2sThreeReg<
512 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
513 opc, "\t$Rd, $Rn, $Rm",
514 [/* For disassembly only; pattern left blank */]> {
515 let Inst{31-27} = 0b11101;
516 let Inst{26-25} = 0b01;
517 let Inst{24-21} = opcod;
518 let Inst{20} = ?; // The S bit.
519 let Inst{14-12} = 0b000; // imm3
520 let Inst{7-6} = 0b00; // imm2
521 let Inst{5-4} = 0b00; // type
524 def rs : T2sTwoRegShiftedReg<
525 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
526 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
527 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
528 let Inst{31-27} = 0b11101;
529 let Inst{26-25} = 0b01;
530 let Inst{24-21} = opcod;
531 let Inst{20} = ?; // The S bit.
535 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
536 /// instruction modifies the CPSR register.
537 let Defs = [CPSR] in {
538 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
539 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
540 PatFrag opnode, bit Commutable = 0> {
542 def ri : T2TwoRegImm<
543 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
544 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
545 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
546 let Inst{31-27} = 0b11110;
548 let Inst{24-21} = opcod;
549 let Inst{20} = 1; // The S bit.
554 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
555 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
556 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
557 let isCommutable = Commutable;
558 let Inst{31-27} = 0b11101;
559 let Inst{26-25} = 0b01;
560 let Inst{24-21} = opcod;
561 let Inst{20} = 1; // The S bit.
562 let Inst{14-12} = 0b000; // imm3
563 let Inst{7-6} = 0b00; // imm2
564 let Inst{5-4} = 0b00; // type
567 def rs : T2TwoRegShiftedReg<
568 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
569 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
570 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
571 let Inst{31-27} = 0b11101;
572 let Inst{26-25} = 0b01;
573 let Inst{24-21} = opcod;
574 let Inst{20} = 1; // The S bit.
579 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
580 /// patterns for a binary operation that produces a value.
581 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
582 bit Commutable = 0> {
584 // The register-immediate version is re-materializable. This is useful
585 // in particular for taking the address of a local.
586 let isReMaterializable = 1 in {
587 def ri : T2sTwoRegImm<
588 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
589 opc, ".w\t$Rd, $Rn, $imm",
590 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
591 let Inst{31-27} = 0b11110;
594 let Inst{23-21} = op23_21;
595 let Inst{20} = 0; // The S bit.
600 def ri12 : T2TwoRegImm<
601 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
602 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
603 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
604 let Inst{31-27} = 0b11110;
607 let Inst{23-21} = op23_21;
608 let Inst{20} = 0; // The S bit.
612 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
613 opc, ".w\t$Rd, $Rn, $Rm",
614 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
615 let isCommutable = Commutable;
616 let Inst{31-27} = 0b11101;
617 let Inst{26-25} = 0b01;
619 let Inst{23-21} = op23_21;
620 let Inst{20} = 0; // The S bit.
621 let Inst{14-12} = 0b000; // imm3
622 let Inst{7-6} = 0b00; // imm2
623 let Inst{5-4} = 0b00; // type
626 def rs : T2sTwoRegShiftedReg<
627 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
628 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
629 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
630 let Inst{31-27} = 0b11101;
631 let Inst{26-25} = 0b01;
633 let Inst{23-21} = op23_21;
634 let Inst{20} = 0; // The S bit.
638 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
639 /// for a binary operation that produces a value and use the carry
640 /// bit. It's not predicable.
641 let Uses = [CPSR] in {
642 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
643 bit Commutable = 0> {
645 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
646 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
647 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
648 Requires<[IsThumb2]> {
649 let Inst{31-27} = 0b11110;
651 let Inst{24-21} = opcod;
652 let Inst{20} = 0; // The S bit.
656 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
657 opc, ".w\t$Rd, $Rn, $Rm",
658 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
659 Requires<[IsThumb2]> {
660 let isCommutable = Commutable;
661 let Inst{31-27} = 0b11101;
662 let Inst{26-25} = 0b01;
663 let Inst{24-21} = opcod;
664 let Inst{20} = 0; // The S bit.
665 let Inst{14-12} = 0b000; // imm3
666 let Inst{7-6} = 0b00; // imm2
667 let Inst{5-4} = 0b00; // type
670 def rs : T2sTwoRegShiftedReg<
671 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
672 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
673 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
674 Requires<[IsThumb2]> {
675 let Inst{31-27} = 0b11101;
676 let Inst{26-25} = 0b01;
677 let Inst{24-21} = opcod;
678 let Inst{20} = 0; // The S bit.
682 // Carry setting variants
683 let Defs = [CPSR] in {
684 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
685 bit Commutable = 0> {
687 def ri : T2sTwoRegImm<
688 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
689 opc, "\t$Rd, $Rn, $imm",
690 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
691 Requires<[IsThumb2]> {
692 let Inst{31-27} = 0b11110;
694 let Inst{24-21} = opcod;
695 let Inst{20} = 1; // The S bit.
699 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
700 opc, ".w\t$Rd, $Rn, $Rm",
701 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
702 Requires<[IsThumb2]> {
703 let isCommutable = Commutable;
704 let Inst{31-27} = 0b11101;
705 let Inst{26-25} = 0b01;
706 let Inst{24-21} = opcod;
707 let Inst{20} = 1; // The S bit.
708 let Inst{14-12} = 0b000; // imm3
709 let Inst{7-6} = 0b00; // imm2
710 let Inst{5-4} = 0b00; // type
713 def rs : T2sTwoRegShiftedReg<
714 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
715 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
716 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
717 Requires<[IsThumb2]> {
718 let Inst{31-27} = 0b11101;
719 let Inst{26-25} = 0b01;
720 let Inst{24-21} = opcod;
721 let Inst{20} = 1; // The S bit.
727 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
728 /// version is not needed since this is only for codegen.
729 let Defs = [CPSR] in {
730 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
732 def ri : T2TwoRegImm<
733 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
734 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
735 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
736 let Inst{31-27} = 0b11110;
738 let Inst{24-21} = opcod;
739 let Inst{20} = 1; // The S bit.
743 def rs : T2TwoRegShiftedReg<
744 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
745 IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
746 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
747 let Inst{31-27} = 0b11101;
748 let Inst{26-25} = 0b01;
749 let Inst{24-21} = opcod;
750 let Inst{20} = 1; // The S bit.
755 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
756 // rotate operation that produces a value.
757 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
759 def ri : T2sTwoRegShiftImm<
760 (outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$imm), IIC_iMOVsi,
761 opc, ".w\t$Rd, $Rm, $imm",
762 [(set rGPR:$Rd, (opnode rGPR:$Rm, imm1_31:$imm))]> {
763 let Inst{31-27} = 0b11101;
764 let Inst{26-21} = 0b010010;
765 let Inst{19-16} = 0b1111; // Rn
766 let Inst{5-4} = opcod;
769 def rr : T2sThreeReg<
770 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
771 opc, ".w\t$Rd, $Rn, $Rm",
772 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
773 let Inst{31-27} = 0b11111;
774 let Inst{26-23} = 0b0100;
775 let Inst{22-21} = opcod;
776 let Inst{15-12} = 0b1111;
777 let Inst{7-4} = 0b0000;
781 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
782 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
783 /// a explicit result, only implicitly set CPSR.
784 let isCompare = 1, Defs = [CPSR] in {
785 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
786 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
789 def ri : T2OneRegCmpImm<
790 (outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
791 opc, ".w\t$Rn, $imm",
792 [(opnode GPR:$Rn, t2_so_imm:$imm)]> {
793 let Inst{31-27} = 0b11110;
795 let Inst{24-21} = opcod;
796 let Inst{20} = 1; // The S bit.
798 let Inst{11-8} = 0b1111; // Rd
801 def rr : T2TwoRegCmp<
802 (outs), (ins GPR:$lhs, rGPR:$rhs), iir,
803 opc, ".w\t$lhs, $rhs",
804 [(opnode GPR:$lhs, rGPR:$rhs)]> {
805 let Inst{31-27} = 0b11101;
806 let Inst{26-25} = 0b01;
807 let Inst{24-21} = opcod;
808 let Inst{20} = 1; // The S bit.
809 let Inst{14-12} = 0b000; // imm3
810 let Inst{11-8} = 0b1111; // Rd
811 let Inst{7-6} = 0b00; // imm2
812 let Inst{5-4} = 0b00; // type
815 def rs : T2OneRegCmpShiftedReg<
816 (outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
817 opc, ".w\t$Rn, $ShiftedRm",
818 [(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
819 let Inst{31-27} = 0b11101;
820 let Inst{26-25} = 0b01;
821 let Inst{24-21} = opcod;
822 let Inst{20} = 1; // The S bit.
823 let Inst{11-8} = 0b1111; // Rd
828 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
829 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
830 InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
831 def i12 : T2Ii12<(outs GPR:$Rt), (ins t2addrmode_imm12:$addr), iii,
832 opc, ".w\t$Rt, $addr",
833 [(set GPR:$Rt, (opnode t2addrmode_imm12:$addr))]> {
834 let Inst{31-27} = 0b11111;
835 let Inst{26-25} = 0b00;
836 let Inst{24} = signed;
838 let Inst{22-21} = opcod;
839 let Inst{20} = 1; // load
842 let Inst{15-12} = Rt{3-0};
845 let Inst{19-16} = addr{16-13}; // Rn
846 let Inst{23} = addr{12}; // U
847 let Inst{11-0} = addr{11-0}; // imm
849 def i8 : T2Ii8 <(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), iii,
851 [(set GPR:$Rt, (opnode t2addrmode_imm8:$addr))]> {
852 let Inst{31-27} = 0b11111;
853 let Inst{26-25} = 0b00;
854 let Inst{24} = signed;
856 let Inst{22-21} = opcod;
857 let Inst{20} = 1; // load
859 // Offset: index==TRUE, wback==FALSE
860 let Inst{10} = 1; // The P bit.
861 let Inst{8} = 0; // The W bit.
864 let Inst{15-12} = Rt{3-0};
867 let Inst{19-16} = addr{12-9}; // Rn
868 let Inst{9} = addr{8}; // U
869 let Inst{7-0} = addr{7-0}; // imm
871 def s : T2Iso <(outs GPR:$Rt), (ins t2addrmode_so_reg:$addr), iis,
872 opc, ".w\t$Rt, $addr",
873 [(set GPR:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
874 let Inst{31-27} = 0b11111;
875 let Inst{26-25} = 0b00;
876 let Inst{24} = signed;
878 let Inst{22-21} = opcod;
879 let Inst{20} = 1; // load
880 let Inst{11-6} = 0b000000;
883 let Inst{15-12} = Rt{3-0};
886 let Inst{19-16} = addr{9-6}; // Rn
887 let Inst{3-0} = addr{5-2}; // Rm
888 let Inst{5-4} = addr{1-0}; // imm
891 // FIXME: Is the pci variant actually needed?
892 def pci : T2Ipc <(outs GPR:$Rt), (ins i32imm:$addr), iii,
893 opc, ".w\t$Rt, $addr",
894 [(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
895 let isReMaterializable = 1;
896 let Inst{31-27} = 0b11111;
897 let Inst{26-25} = 0b00;
898 let Inst{24} = signed;
899 let Inst{23} = ?; // add = (U == '1')
900 let Inst{22-21} = opcod;
901 let Inst{20} = 1; // load
902 let Inst{19-16} = 0b1111; // Rn
906 let Inst{15-12} = Rt{3-0};
907 let Inst{11-0} = addr{11-0};
911 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
912 multiclass T2I_st<bits<2> opcod, string opc,
913 InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
914 def i12 : T2Ii12<(outs), (ins GPR:$Rt, t2addrmode_imm12:$addr), iii,
915 opc, ".w\t$Rt, $addr",
916 [(opnode GPR:$Rt, t2addrmode_imm12:$addr)]> {
917 let Inst{31-27} = 0b11111;
918 let Inst{26-23} = 0b0001;
919 let Inst{22-21} = opcod;
920 let Inst{20} = 0; // !load
923 let Inst{15-12} = Rt{3-0};
926 let Inst{19-16} = addr{16-13}; // Rn
927 let Inst{23} = addr{12}; // U
928 let Inst{11-0} = addr{11-0}; // imm
930 def i8 : T2Ii8 <(outs), (ins GPR:$Rt, t2addrmode_imm8:$addr), iii,
932 [(opnode GPR:$Rt, t2addrmode_imm8:$addr)]> {
933 let Inst{31-27} = 0b11111;
934 let Inst{26-23} = 0b0000;
935 let Inst{22-21} = opcod;
936 let Inst{20} = 0; // !load
938 // Offset: index==TRUE, wback==FALSE
939 let Inst{10} = 1; // The P bit.
940 let Inst{8} = 0; // The W bit.
943 let Inst{15-12} = Rt{3-0};
946 let Inst{19-16} = addr{12-9}; // Rn
947 let Inst{9} = addr{8}; // U
948 let Inst{7-0} = addr{7-0}; // imm
950 def s : T2Iso <(outs), (ins GPR:$Rt, t2addrmode_so_reg:$addr), iis,
951 opc, ".w\t$Rt, $addr",
952 [(opnode GPR:$Rt, t2addrmode_so_reg:$addr)]> {
953 let Inst{31-27} = 0b11111;
954 let Inst{26-23} = 0b0000;
955 let Inst{22-21} = opcod;
956 let Inst{20} = 0; // !load
957 let Inst{11-6} = 0b000000;
960 let Inst{15-12} = Rt{3-0};
963 let Inst{19-16} = addr{9-6}; // Rn
964 let Inst{3-0} = addr{5-2}; // Rm
965 let Inst{5-4} = addr{1-0}; // imm
969 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
970 /// register and one whose operand is a register rotated by 8/16/24.
971 multiclass T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> {
972 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
974 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
975 let Inst{31-27} = 0b11111;
976 let Inst{26-23} = 0b0100;
977 let Inst{22-20} = opcod;
978 let Inst{19-16} = 0b1111; // Rn
979 let Inst{15-12} = 0b1111;
981 let Inst{5-4} = 0b00; // rotate
983 def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
984 opc, ".w\t$Rd, $Rm, ror $rot",
985 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
986 let Inst{31-27} = 0b11111;
987 let Inst{26-23} = 0b0100;
988 let Inst{22-20} = opcod;
989 let Inst{19-16} = 0b1111; // Rn
990 let Inst{15-12} = 0b1111;
994 let Inst{5-4} = rot{1-0}; // rotate
998 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
999 multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
1000 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1002 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>,
1003 Requires<[HasT2ExtractPack, IsThumb2]> {
1004 let Inst{31-27} = 0b11111;
1005 let Inst{26-23} = 0b0100;
1006 let Inst{22-20} = opcod;
1007 let Inst{19-16} = 0b1111; // Rn
1008 let Inst{15-12} = 0b1111;
1010 let Inst{5-4} = 0b00; // rotate
1012 def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
1013 opc, "\t$dst, $Rm, ror $rot",
1014 [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1015 Requires<[HasT2ExtractPack, IsThumb2]> {
1016 let Inst{31-27} = 0b11111;
1017 let Inst{26-23} = 0b0100;
1018 let Inst{22-20} = opcod;
1019 let Inst{19-16} = 0b1111; // Rn
1020 let Inst{15-12} = 0b1111;
1024 let Inst{5-4} = rot{1-0}; // rotate
1028 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1030 multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
1031 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1032 opc, "\t$Rd, $Rm", []> {
1033 let Inst{31-27} = 0b11111;
1034 let Inst{26-23} = 0b0100;
1035 let Inst{22-20} = opcod;
1036 let Inst{19-16} = 0b1111; // Rn
1037 let Inst{15-12} = 0b1111;
1039 let Inst{5-4} = 0b00; // rotate
1041 def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
1042 opc, "\t$Rd, $Rm, ror $rot", []> {
1043 let Inst{31-27} = 0b11111;
1044 let Inst{26-23} = 0b0100;
1045 let Inst{22-20} = opcod;
1046 let Inst{19-16} = 0b1111; // Rn
1047 let Inst{15-12} = 0b1111;
1051 let Inst{5-4} = rot{1-0}; // rotate
1055 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1056 /// register and one whose operand is a register rotated by 8/16/24.
1057 multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> {
1058 def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1059 opc, "\t$Rd, $Rn, $Rm",
1060 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
1061 Requires<[HasT2ExtractPack, IsThumb2]> {
1062 let Inst{31-27} = 0b11111;
1063 let Inst{26-23} = 0b0100;
1064 let Inst{22-20} = opcod;
1065 let Inst{15-12} = 0b1111;
1067 let Inst{5-4} = 0b00; // rotate
1069 def rr_rot : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
1070 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
1071 [(set rGPR:$Rd, (opnode rGPR:$Rn,
1072 (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1073 Requires<[HasT2ExtractPack, IsThumb2]> {
1074 let Inst{31-27} = 0b11111;
1075 let Inst{26-23} = 0b0100;
1076 let Inst{22-20} = opcod;
1077 let Inst{15-12} = 0b1111;
1081 let Inst{5-4} = rot{1-0}; // rotate
1085 // DO variant - disassembly only, no pattern
1087 multiclass T2I_exta_rrot_DO<bits<3> opcod, string opc> {
1088 def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1089 opc, "\t$Rd, $Rn, $Rm", []> {
1090 let Inst{31-27} = 0b11111;
1091 let Inst{26-23} = 0b0100;
1092 let Inst{22-20} = opcod;
1093 let Inst{15-12} = 0b1111;
1095 let Inst{5-4} = 0b00; // rotate
1097 def rr_rot : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
1098 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot", []> {
1099 let Inst{31-27} = 0b11111;
1100 let Inst{26-23} = 0b0100;
1101 let Inst{22-20} = opcod;
1102 let Inst{15-12} = 0b1111;
1106 let Inst{5-4} = rot{1-0}; // rotate
1110 //===----------------------------------------------------------------------===//
1112 //===----------------------------------------------------------------------===//
1114 //===----------------------------------------------------------------------===//
1115 // Miscellaneous Instructions.
1118 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1119 string asm, list<dag> pattern>
1120 : T2XI<oops, iops, itin, asm, pattern> {
1124 let Inst{11-8} = Rd{3-0};
1125 let Inst{26} = label{11};
1126 let Inst{14-12} = label{10-8};
1127 let Inst{7-0} = label{7-0};
1130 // LEApcrel - Load a pc-relative address into a register without offending the
1132 let neverHasSideEffects = 1 in {
1133 let isReMaterializable = 1 in
1134 def t2LEApcrel : T2PCOneRegImm<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), IIC_iALUi,
1135 "adr${p}.w\t$Rd, #$label", []> {
1136 let Inst{31-27} = 0b11110;
1137 let Inst{25-24} = 0b10;
1138 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1141 let Inst{19-16} = 0b1111; // Rn
1146 } // neverHasSideEffects
1147 def t2LEApcrelJT : T2PCOneRegImm<(outs rGPR:$Rd),
1148 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
1149 "adr${p}.w\t$Rd, #${label}_${id}", []> {
1150 let Inst{31-27} = 0b11110;
1151 let Inst{25-24} = 0b10;
1152 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1155 let Inst{19-16} = 0b1111; // Rn
1159 // ADD r, sp, {so_imm|i12}
1160 def t2ADDrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_imm:$imm),
1161 IIC_iALUi, "add", ".w\t$Rd, $sp, $imm", []> {
1162 let Inst{31-27} = 0b11110;
1164 let Inst{24-21} = 0b1000;
1165 let Inst{20} = ?; // The S bit.
1166 let Inst{19-16} = 0b1101; // Rn = sp
1169 def t2ADDrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm),
1170 IIC_iALUi, "addw", "\t$Rd, $sp, $imm", []> {
1171 let Inst{31-27} = 0b11110;
1173 let Inst{24-21} = 0b0000;
1174 let Inst{20} = 0; // The S bit.
1175 let Inst{19-16} = 0b1101; // Rn = sp
1179 // ADD r, sp, so_reg
1180 def t2ADDrSPs : T2sTwoRegShiftedReg<
1181 (outs GPR:$Rd), (ins GPR:$sp, t2_so_reg:$ShiftedRm),
1182 IIC_iALUsi, "add", ".w\t$Rd, $sp, $ShiftedRm", []> {
1183 let Inst{31-27} = 0b11101;
1184 let Inst{26-25} = 0b01;
1185 let Inst{24-21} = 0b1000;
1186 let Inst{20} = ?; // The S bit.
1187 let Inst{19-16} = 0b1101; // Rn = sp
1191 // SUB r, sp, {so_imm|i12}
1192 def t2SUBrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_imm:$imm),
1193 IIC_iALUi, "sub", ".w\t$Rd, $sp, $imm", []> {
1194 let Inst{31-27} = 0b11110;
1196 let Inst{24-21} = 0b1101;
1197 let Inst{20} = ?; // The S bit.
1198 let Inst{19-16} = 0b1101; // Rn = sp
1201 def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm),
1202 IIC_iALUi, "subw", "\t$Rd, $sp, $imm", []> {
1203 let Inst{31-27} = 0b11110;
1205 let Inst{24-21} = 0b0101;
1206 let Inst{20} = 0; // The S bit.
1207 let Inst{19-16} = 0b1101; // Rn = sp
1211 // SUB r, sp, so_reg
1212 def t2SUBrSPs : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_reg:$imm),
1214 "sub", "\t$Rd, $sp, $imm", []> {
1215 let Inst{31-27} = 0b11101;
1216 let Inst{26-25} = 0b01;
1217 let Inst{24-21} = 0b1101;
1218 let Inst{20} = ?; // The S bit.
1219 let Inst{19-16} = 0b1101; // Rn = sp
1223 // Signed and unsigned division on v7-M
1224 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
1225 "sdiv", "\t$Rd, $Rn, $Rm",
1226 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
1227 Requires<[HasDivide, IsThumb2]> {
1228 let Inst{31-27} = 0b11111;
1229 let Inst{26-21} = 0b011100;
1231 let Inst{15-12} = 0b1111;
1232 let Inst{7-4} = 0b1111;
1235 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
1236 "udiv", "\t$Rd, $Rn, $Rm",
1237 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
1238 Requires<[HasDivide, IsThumb2]> {
1239 let Inst{31-27} = 0b11111;
1240 let Inst{26-21} = 0b011101;
1242 let Inst{15-12} = 0b1111;
1243 let Inst{7-4} = 0b1111;
1246 //===----------------------------------------------------------------------===//
1247 // Load / store Instructions.
1251 let canFoldAsLoad = 1, isReMaterializable = 1 in
1252 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si,
1253 UnOpFrag<(load node:$Src)>>;
1255 // Loads with zero extension
1256 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1257 UnOpFrag<(zextloadi16 node:$Src)>>;
1258 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1259 UnOpFrag<(zextloadi8 node:$Src)>>;
1261 // Loads with sign extension
1262 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1263 UnOpFrag<(sextloadi16 node:$Src)>>;
1264 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1265 UnOpFrag<(sextloadi8 node:$Src)>>;
1267 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1269 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1270 (ins t2addrmode_imm8s4:$addr),
1271 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
1272 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1274 // zextload i1 -> zextload i8
1275 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1276 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1277 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
1278 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1279 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1280 (t2LDRBs t2addrmode_so_reg:$addr)>;
1281 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1282 (t2LDRBpci tconstpool:$addr)>;
1284 // extload -> zextload
1285 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1287 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1288 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1289 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
1290 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1291 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1292 (t2LDRBs t2addrmode_so_reg:$addr)>;
1293 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1294 (t2LDRBpci tconstpool:$addr)>;
1296 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1297 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1298 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
1299 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1300 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1301 (t2LDRBs t2addrmode_so_reg:$addr)>;
1302 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1303 (t2LDRBpci tconstpool:$addr)>;
1305 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1306 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1307 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1308 (t2LDRHi8 t2addrmode_imm8:$addr)>;
1309 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1310 (t2LDRHs t2addrmode_so_reg:$addr)>;
1311 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1312 (t2LDRHpci tconstpool:$addr)>;
1314 // FIXME: The destination register of the loads and stores can't be PC, but
1315 // can be SP. We need another regclass (similar to rGPR) to represent
1316 // that. Not a pressing issue since these are selected manually,
1321 class T2Iidxld<bit signed, bits<2> opcod, bit pre,
1323 AddrMode am, IndexMode im, InstrItinClass itin,
1324 string opc, string asm, string cstr, list<dag> pattern>
1325 : T2Iidxldst<signed, opcod, 1, pre, oops,
1326 iops, am,im,itin, opc, asm, cstr, pattern>;
1327 class T2Iidxst<bit signed, bits<2> opcod, bit pre,
1329 AddrMode am, IndexMode im, InstrItinClass itin,
1330 string opc, string asm, string cstr, list<dag> pattern>
1331 : T2Iidxldst<signed, opcod, 0, pre, oops,
1332 iops, am,im,itin, opc, asm, cstr, pattern>;
1334 let mayLoad = 1, neverHasSideEffects = 1 in {
1335 def t2LDR_PRE : T2Iidxld<0, 0b10, 1, (outs GPR:$Rt, GPR:$Rn),
1336 (ins t2addrmode_imm8:$addr),
1337 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1338 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
1341 def t2LDR_POST : T2Iidxld<0, 0b10, 0, (outs GPR:$Rt, GPR:$Rn),
1342 (ins GPR:$base, t2am_imm8_offset:$offset),
1343 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1344 "ldr", "\t$Rt, [$Rn], $offset", "$base = $Rn",
1347 def t2LDRB_PRE : T2Iidxld<0, 0b00, 1, (outs GPR:$Rt, GPR:$Rn),
1348 (ins t2addrmode_imm8:$addr),
1349 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1350 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
1352 def t2LDRB_POST : T2Iidxld<0, 0b00, 0, (outs GPR:$Rt, GPR:$Rn),
1353 (ins GPR:$base, t2am_imm8_offset:$offset),
1354 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1355 "ldrb", "\t$Rt, [$Rn], $offset", "$base = $Rn",
1358 def t2LDRH_PRE : T2Iidxld<0, 0b01, 1, (outs GPR:$Rt, GPR:$Rn),
1359 (ins t2addrmode_imm8:$addr),
1360 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1361 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
1363 def t2LDRH_POST : T2Iidxld<0, 0b01, 0, (outs GPR:$Rt, GPR:$Rn),
1364 (ins GPR:$base, t2am_imm8_offset:$offset),
1365 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1366 "ldrh", "\t$Rt, [$Rn], $offset", "$base = $Rn",
1369 def t2LDRSB_PRE : T2Iidxld<1, 0b00, 1, (outs GPR:$Rt, GPR:$Rn),
1370 (ins t2addrmode_imm8:$addr),
1371 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1372 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
1374 def t2LDRSB_POST : T2Iidxld<1, 0b00, 0, (outs GPR:$Rt, GPR:$Rn),
1375 (ins GPR:$base, t2am_imm8_offset:$offset),
1376 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1377 "ldrsb", "\t$Rt, [$Rn], $offset", "$base = $Rn",
1380 def t2LDRSH_PRE : T2Iidxld<1, 0b01, 1, (outs GPR:$Rt, GPR:$Rn),
1381 (ins t2addrmode_imm8:$addr),
1382 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1383 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
1385 def t2LDRSH_POST : T2Iidxld<1, 0b01, 0, (outs GPR:$dst, GPR:$Rn),
1386 (ins GPR:$base, t2am_imm8_offset:$offset),
1387 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1388 "ldrsh", "\t$dst, [$Rn], $offset", "$base = $Rn",
1390 } // mayLoad = 1, neverHasSideEffects = 1
1392 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1393 // for disassembly only.
1394 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1395 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1396 : T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1397 "\t$Rt, $addr", []> {
1398 let Inst{31-27} = 0b11111;
1399 let Inst{26-25} = 0b00;
1400 let Inst{24} = signed;
1402 let Inst{22-21} = type;
1403 let Inst{20} = 1; // load
1405 let Inst{10-8} = 0b110; // PUW.
1409 let Inst{15-12} = Rt{3-0};
1410 let Inst{19-16} = addr{12-9};
1411 let Inst{7-0} = addr{7-0};
1414 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1415 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1416 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1417 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1418 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1421 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si,
1422 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1423 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1424 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1425 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1426 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1429 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1430 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1431 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1432 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
1435 def t2STR_PRE : T2Iidxst<0, 0b10, 1, (outs GPR:$base_wb),
1436 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1437 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1438 "str", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
1440 (pre_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1442 def t2STR_POST : T2Iidxst<0, 0b10, 0, (outs GPR:$base_wb),
1443 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1444 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1445 "str", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
1447 (post_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1449 def t2STRH_PRE : T2Iidxst<0, 0b01, 1, (outs GPR:$base_wb),
1450 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1451 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1452 "strh", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
1454 (pre_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1456 def t2STRH_POST : T2Iidxst<0, 0b01, 0, (outs GPR:$base_wb),
1457 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1458 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1459 "strh", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
1461 (post_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1463 def t2STRB_PRE : T2Iidxst<0, 0b00, 1, (outs GPR:$base_wb),
1464 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1465 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1466 "strb", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
1468 (pre_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1470 def t2STRB_POST : T2Iidxst<0, 0b00, 0, (outs GPR:$base_wb),
1471 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1472 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1473 "strb", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
1475 (post_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1477 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1479 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1480 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1481 : T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1482 "\t$Rt, $addr", []> {
1483 let Inst{31-27} = 0b11111;
1484 let Inst{26-25} = 0b00;
1485 let Inst{24} = 0; // not signed
1487 let Inst{22-21} = type;
1488 let Inst{20} = 0; // store
1490 let Inst{10-8} = 0b110; // PUW
1494 let Inst{15-12} = Rt{3-0};
1495 let Inst{19-16} = addr{12-9};
1496 let Inst{7-0} = addr{7-0};
1499 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1500 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1501 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1503 // ldrd / strd pre / post variants
1504 // For disassembly only.
1506 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$Rt, GPR:$Rt2),
1507 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1508 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1510 def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$Rt, GPR:$Rt2),
1511 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1512 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
1514 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
1515 (ins GPR:$Rt, GPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1516 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1518 def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1519 (ins GPR:$Rt, GPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1520 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
1522 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1523 // data/instruction access. These are for disassembly only.
1524 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1525 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1526 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1528 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1530 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1531 let Inst{31-25} = 0b1111100;
1532 let Inst{24} = instr;
1534 let Inst{21} = write;
1536 let Inst{15-12} = 0b1111;
1539 let Inst{19-16} = addr{16-13}; // Rn
1540 let Inst{23} = addr{12}; // U
1541 let Inst{11-0} = addr{11-0}; // imm12
1544 def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
1546 [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
1547 let Inst{31-25} = 0b1111100;
1548 let Inst{24} = instr;
1549 let Inst{23} = 0; // U = 0
1551 let Inst{21} = write;
1553 let Inst{15-12} = 0b1111;
1554 let Inst{11-8} = 0b1100;
1557 let Inst{19-16} = addr{12-9}; // Rn
1558 let Inst{7-0} = addr{7-0}; // imm8
1561 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1563 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1564 let Inst{31-25} = 0b1111100;
1565 let Inst{24} = instr;
1566 let Inst{23} = 0; // add = TRUE for T1
1568 let Inst{21} = write;
1570 let Inst{15-12} = 0b1111;
1571 let Inst{11-6} = 0000000;
1574 let Inst{19-16} = addr{9-6}; // Rn
1575 let Inst{3-0} = addr{5-2}; // Rm
1576 let Inst{5-4} = addr{1-0}; // imm2
1580 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1581 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1582 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1584 //===----------------------------------------------------------------------===//
1585 // Load / store multiple Instructions.
1588 multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1589 InstrItinClass itin_upd, bit L_bit> {
1591 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1592 itin, !strconcat(asm, "ia${p}.w\t$Rn, $regs"), []> {
1596 let Inst{31-27} = 0b11101;
1597 let Inst{26-25} = 0b00;
1598 let Inst{24-23} = 0b01; // Increment After
1600 let Inst{21} = 0; // No writeback
1601 let Inst{20} = L_bit;
1602 let Inst{19-16} = Rn;
1603 let Inst{15-0} = regs;
1606 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1607 itin_upd, !strconcat(asm, "ia${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1611 let Inst{31-27} = 0b11101;
1612 let Inst{26-25} = 0b00;
1613 let Inst{24-23} = 0b01; // Increment After
1615 let Inst{21} = 1; // Writeback
1616 let Inst{20} = L_bit;
1617 let Inst{19-16} = Rn;
1618 let Inst{15-0} = regs;
1621 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1622 itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
1626 let Inst{31-27} = 0b11101;
1627 let Inst{26-25} = 0b00;
1628 let Inst{24-23} = 0b10; // Decrement Before
1630 let Inst{21} = 0; // No writeback
1631 let Inst{20} = L_bit;
1632 let Inst{19-16} = Rn;
1633 let Inst{15-0} = regs;
1636 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1637 itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
1641 let Inst{31-27} = 0b11101;
1642 let Inst{26-25} = 0b00;
1643 let Inst{24-23} = 0b10; // Decrement Before
1645 let Inst{21} = 1; // Writeback
1646 let Inst{20} = L_bit;
1647 let Inst{19-16} = Rn;
1648 let Inst{15-0} = regs;
1652 let neverHasSideEffects = 1 in {
1654 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1655 defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1657 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1658 defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1660 } // neverHasSideEffects
1663 //===----------------------------------------------------------------------===//
1664 // Move Instructions.
1667 let neverHasSideEffects = 1 in
1668 def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1669 "mov", ".w\t$Rd, $Rm", []> {
1670 let Inst{31-27} = 0b11101;
1671 let Inst{26-25} = 0b01;
1672 let Inst{24-21} = 0b0010;
1673 let Inst{20} = ?; // The S bit.
1674 let Inst{19-16} = 0b1111; // Rn
1675 let Inst{14-12} = 0b000;
1676 let Inst{7-4} = 0b0000;
1679 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1680 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1681 AddedComplexity = 1 in
1682 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1683 "mov", ".w\t$Rd, $imm",
1684 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1685 let Inst{31-27} = 0b11110;
1687 let Inst{24-21} = 0b0010;
1688 let Inst{20} = ?; // The S bit.
1689 let Inst{19-16} = 0b1111; // Rn
1693 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1694 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm:$imm), IIC_iMOVi,
1695 "movw", "\t$Rd, $imm",
1696 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1697 let Inst{31-27} = 0b11110;
1699 let Inst{24-21} = 0b0010;
1700 let Inst{20} = 0; // The S bit.
1706 let Inst{11-8} = Rd{3-0};
1707 let Inst{19-16} = imm{15-12};
1708 let Inst{26} = imm{11};
1709 let Inst{14-12} = imm{10-8};
1710 let Inst{7-0} = imm{7-0};
1713 let Constraints = "$src = $Rd" in
1714 def t2MOVTi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$src, i32imm:$imm), IIC_iMOVi,
1715 "movt", "\t$Rd, $imm",
1717 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1718 let Inst{31-27} = 0b11110;
1720 let Inst{24-21} = 0b0110;
1721 let Inst{20} = 0; // The S bit.
1727 let Inst{11-8} = Rd{3-0};
1728 let Inst{19-16} = imm{15-12};
1729 let Inst{26} = imm{11};
1730 let Inst{14-12} = imm{10-8};
1731 let Inst{7-0} = imm{7-0};
1734 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1736 //===----------------------------------------------------------------------===//
1737 // Extend Instructions.
1742 defm t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1743 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1744 defm t2SXTH : T2I_ext_rrot<0b000, "sxth",
1745 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1746 defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1748 defm t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1749 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1750 defm t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1751 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1752 defm t2SXTAB16 : T2I_exta_rrot_DO<0b010, "sxtab16">;
1754 // TODO: SXT(A){B|H}16 - done for disassembly only
1758 let AddedComplexity = 16 in {
1759 defm t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1760 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1761 defm t2UXTH : T2I_ext_rrot<0b001, "uxth",
1762 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1763 defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1764 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1766 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1767 // The transformation should probably be done as a combiner action
1768 // instead so we can include a check for masking back in the upper
1769 // eight bits of the source into the lower eight bits of the result.
1770 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1771 // (t2UXTB16r_rot rGPR:$Src, 24)>,
1772 // Requires<[HasT2ExtractPack, IsThumb2]>;
1773 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1774 (t2UXTB16r_rot rGPR:$Src, 8)>,
1775 Requires<[HasT2ExtractPack, IsThumb2]>;
1777 defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1778 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1779 defm t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1780 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1781 defm t2UXTAB16 : T2I_exta_rrot_DO<0b011, "uxtab16">;
1784 //===----------------------------------------------------------------------===//
1785 // Arithmetic Instructions.
1788 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1789 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1790 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1791 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1793 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1794 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1795 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1796 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1797 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1798 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1799 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1801 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1802 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1803 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1804 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1805 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1806 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1807 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1808 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1811 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1812 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1813 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1814 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1816 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1817 // The assume-no-carry-in form uses the negation of the input since add/sub
1818 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1819 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1821 // The AddedComplexity preferences the first variant over the others since
1822 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1823 let AddedComplexity = 1 in
1824 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1825 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1826 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1827 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1828 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1829 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1830 let AddedComplexity = 1 in
1831 def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm),
1832 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1833 def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm),
1834 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1835 // The with-carry-in form matches bitwise not instead of the negation.
1836 // Effectively, the inverse interpretation of the carry flag already accounts
1837 // for part of the negation.
1838 let AddedComplexity = 1 in
1839 def : T2Pat<(adde rGPR:$src, imm0_255_not:$imm),
1840 (t2SBCSri rGPR:$src, imm0_255_not:$imm)>;
1841 def : T2Pat<(adde rGPR:$src, t2_so_imm_not:$imm),
1842 (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>;
1844 // Select Bytes -- for disassembly only
1846 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1847 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []> {
1848 let Inst{31-27} = 0b11111;
1849 let Inst{26-24} = 0b010;
1851 let Inst{22-20} = 0b010;
1852 let Inst{15-12} = 0b1111;
1854 let Inst{6-4} = 0b000;
1857 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1858 // And Miscellaneous operations -- for disassembly only
1859 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1860 list<dag> pat = [/* For disassembly only; pattern left blank */]>
1861 : T2I<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary, opc,
1862 "\t$Rd, $Rn, $Rm", pat> {
1863 let Inst{31-27} = 0b11111;
1864 let Inst{26-23} = 0b0101;
1865 let Inst{22-20} = op22_20;
1866 let Inst{15-12} = 0b1111;
1867 let Inst{7-4} = op7_4;
1873 let Inst{11-8} = Rd{3-0};
1874 let Inst{19-16} = Rn{3-0};
1875 let Inst{3-0} = Rm{3-0};
1878 // Saturating add/subtract -- for disassembly only
1880 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1881 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))]>;
1882 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1883 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1884 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1885 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1886 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1887 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1888 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1889 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))]>;
1890 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1891 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1892 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1893 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1894 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1895 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1896 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1897 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1899 // Signed/Unsigned add/subtract -- for disassembly only
1901 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1902 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1903 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1904 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1905 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1906 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1907 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1908 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1909 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1910 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1911 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1912 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1914 // Signed/Unsigned halving add/subtract -- for disassembly only
1916 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1917 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1918 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1919 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1920 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1921 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1922 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1923 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1924 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1925 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1926 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1927 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1929 // Helper class for disassembly only
1930 // A6.3.16 & A6.3.17
1931 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1932 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1933 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1934 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1935 let Inst{31-27} = 0b11111;
1936 let Inst{26-24} = 0b011;
1937 let Inst{23} = long;
1938 let Inst{22-20} = op22_20;
1939 let Inst{7-4} = op7_4;
1942 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1943 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1944 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1945 let Inst{31-27} = 0b11111;
1946 let Inst{26-24} = 0b011;
1947 let Inst{23} = long;
1948 let Inst{22-20} = op22_20;
1949 let Inst{7-4} = op7_4;
1952 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1954 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1955 (ins rGPR:$Rn, rGPR:$Rm),
1956 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []> {
1957 let Inst{15-12} = 0b1111;
1959 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1960 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1961 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>;
1963 // Signed/Unsigned saturate -- for disassembly only
1965 class T2SatI<dag oops, dag iops, InstrItinClass itin,
1966 string opc, string asm, list<dag> pattern>
1967 : T2I<oops, iops, itin, opc, asm, pattern> {
1973 let Inst{11-8} = Rd{3-0};
1974 let Inst{19-16} = Rn{3-0};
1975 let Inst{4-0} = sat_imm{4-0};
1976 let Inst{21} = sh{6};
1977 let Inst{14-12} = sh{4-2};
1978 let Inst{7-6} = sh{1-0};
1982 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1983 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1984 [/* For disassembly only; pattern left blank */]> {
1985 let Inst{31-27} = 0b11110;
1986 let Inst{25-22} = 0b1100;
1991 def t2SSAT16: T2SatI<
1992 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn), NoItinerary,
1993 "ssat16", "\t$Rd, $sat_imm, $Rn",
1994 [/* For disassembly only; pattern left blank */]> {
1995 let Inst{31-27} = 0b11110;
1996 let Inst{25-22} = 0b1100;
1999 let Inst{21} = 1; // sh = '1'
2000 let Inst{14-12} = 0b000; // imm3 = '000'
2001 let Inst{7-6} = 0b00; // imm2 = '00'
2005 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
2006 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
2007 [/* For disassembly only; pattern left blank */]> {
2008 let Inst{31-27} = 0b11110;
2009 let Inst{25-22} = 0b1110;
2014 def t2USAT16: T2SatI<
2015 (outs rGPR:$dst), (ins i32imm:$sat_imm, rGPR:$Rn), NoItinerary,
2016 "usat16", "\t$dst, $sat_imm, $Rn",
2017 [/* For disassembly only; pattern left blank */]> {
2018 let Inst{31-27} = 0b11110;
2019 let Inst{25-22} = 0b1110;
2022 let Inst{21} = 1; // sh = '1'
2023 let Inst{14-12} = 0b000; // imm3 = '000'
2024 let Inst{7-6} = 0b00; // imm2 = '00'
2027 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2028 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2030 //===----------------------------------------------------------------------===//
2031 // Shift and rotate Instructions.
2034 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
2035 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
2036 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
2037 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
2039 let Uses = [CPSR] in {
2040 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2041 "rrx", "\t$Rd, $Rm",
2042 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2043 let Inst{31-27} = 0b11101;
2044 let Inst{26-25} = 0b01;
2045 let Inst{24-21} = 0b0010;
2046 let Inst{20} = ?; // The S bit.
2047 let Inst{19-16} = 0b1111; // Rn
2048 let Inst{14-12} = 0b000;
2049 let Inst{7-4} = 0b0011;
2053 let Defs = [CPSR] in {
2054 def t2MOVsrl_flag : T2TwoRegShiftImm<
2055 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2056 "lsrs", ".w\t$Rd, $Rm, #1",
2057 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2058 let Inst{31-27} = 0b11101;
2059 let Inst{26-25} = 0b01;
2060 let Inst{24-21} = 0b0010;
2061 let Inst{20} = 1; // The S bit.
2062 let Inst{19-16} = 0b1111; // Rn
2063 let Inst{5-4} = 0b01; // Shift type.
2064 // Shift amount = Inst{14-12:7-6} = 1.
2065 let Inst{14-12} = 0b000;
2066 let Inst{7-6} = 0b01;
2068 def t2MOVsra_flag : T2TwoRegShiftImm<
2069 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2070 "asrs", ".w\t$Rd, $Rm, #1",
2071 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2072 let Inst{31-27} = 0b11101;
2073 let Inst{26-25} = 0b01;
2074 let Inst{24-21} = 0b0010;
2075 let Inst{20} = 1; // The S bit.
2076 let Inst{19-16} = 0b1111; // Rn
2077 let Inst{5-4} = 0b10; // Shift type.
2078 // Shift amount = Inst{14-12:7-6} = 1.
2079 let Inst{14-12} = 0b000;
2080 let Inst{7-6} = 0b01;
2084 //===----------------------------------------------------------------------===//
2085 // Bitwise Instructions.
2088 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2089 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2090 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2091 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2092 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2093 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2094 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2095 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2096 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2098 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2099 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2100 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2102 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2103 string opc, string asm, list<dag> pattern>
2104 : T2I<oops, iops, itin, opc, asm, pattern> {
2109 let Inst{11-8} = Rd{3-0};
2110 let Inst{4-0} = msb{4-0};
2111 let Inst{14-12} = lsb{4-2};
2112 let Inst{7-6} = lsb{1-0};
2115 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2116 string opc, string asm, list<dag> pattern>
2117 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2120 let Inst{19-16} = Rn{3-0};
2123 let Constraints = "$src = $Rd" in
2124 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2125 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2126 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2127 let Inst{31-27} = 0b11110;
2129 let Inst{24-20} = 0b10110;
2130 let Inst{19-16} = 0b1111; // Rn
2134 let msb{4-0} = imm{9-5};
2135 let lsb{4-0} = imm{4-0};
2138 def t2SBFX: T2TwoRegBitFI<
2139 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2140 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2141 let Inst{31-27} = 0b11110;
2143 let Inst{24-20} = 0b10100;
2147 def t2UBFX: T2TwoRegBitFI<
2148 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2149 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2150 let Inst{31-27} = 0b11110;
2152 let Inst{24-20} = 0b11100;
2156 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2157 let Constraints = "$src = $Rd" in
2158 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2159 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2160 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2161 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2162 bf_inv_mask_imm:$imm))]> {
2163 let Inst{31-27} = 0b11110;
2165 let Inst{24-20} = 0b10110;
2169 let msb{4-0} = imm{9-5};
2170 let lsb{4-0} = imm{4-0};
2173 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2174 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2175 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2177 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2178 let AddedComplexity = 1 in
2179 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2180 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2181 UnOpFrag<(not node:$Src)>, 1, 1>;
2184 let AddedComplexity = 1 in
2185 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2186 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2188 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2189 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2190 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2191 Requires<[IsThumb2]>;
2193 def : T2Pat<(t2_so_imm_not:$src),
2194 (t2MVNi t2_so_imm_not:$src)>;
2196 //===----------------------------------------------------------------------===//
2197 // Multiply Instructions.
2199 let isCommutable = 1 in
2200 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2201 "mul", "\t$Rd, $Rn, $Rm",
2202 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2203 let Inst{31-27} = 0b11111;
2204 let Inst{26-23} = 0b0110;
2205 let Inst{22-20} = 0b000;
2206 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2207 let Inst{7-4} = 0b0000; // Multiply
2210 def t2MLA: T2FourReg<
2211 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2212 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2213 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2214 let Inst{31-27} = 0b11111;
2215 let Inst{26-23} = 0b0110;
2216 let Inst{22-20} = 0b000;
2217 let Inst{7-4} = 0b0000; // Multiply
2220 def t2MLS: T2FourReg<
2221 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2222 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2223 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2224 let Inst{31-27} = 0b11111;
2225 let Inst{26-23} = 0b0110;
2226 let Inst{22-20} = 0b000;
2227 let Inst{7-4} = 0b0001; // Multiply and Subtract
2230 // Extra precision multiplies with low / high results
2231 let neverHasSideEffects = 1 in {
2232 let isCommutable = 1 in {
2233 def t2SMULL : T2FourReg<
2234 (outs rGPR:$Rd, rGPR:$Ra),
2235 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2236 "smull", "\t$Rd, $Ra, $Rn, $Rm", []> {
2237 let Inst{31-27} = 0b11111;
2238 let Inst{26-23} = 0b0111;
2239 let Inst{22-20} = 0b000;
2240 let Inst{7-4} = 0b0000;
2243 def t2UMULL : T2FourReg<
2244 (outs rGPR:$Rd, rGPR:$Ra),
2245 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2246 "umull", "\t$Rd, $Ra, $Rn, $Rm", []> {
2247 let Inst{31-27} = 0b11111;
2248 let Inst{26-23} = 0b0111;
2249 let Inst{22-20} = 0b010;
2250 let Inst{7-4} = 0b0000;
2254 // Multiply + accumulate
2255 def t2SMLAL : T2FourReg<(outs rGPR:$Ra, rGPR:$Rd),
2256 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2257 "smlal", "\t$Ra, $Rd, $Rn, $Rm", []>{
2258 let Inst{31-27} = 0b11111;
2259 let Inst{26-23} = 0b0111;
2260 let Inst{22-20} = 0b100;
2261 let Inst{7-4} = 0b0000;
2264 def t2UMLAL : T2FourReg<(outs rGPR:$Ra, rGPR:$Rd),
2265 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2266 "umlal", "\t$Ra, $Rd, $Rn, $Rm", []>{
2267 let Inst{31-27} = 0b11111;
2268 let Inst{26-23} = 0b0111;
2269 let Inst{22-20} = 0b110;
2270 let Inst{7-4} = 0b0000;
2273 def t2UMAAL : T2FourReg<(outs rGPR:$Ra, rGPR:$Rd),
2274 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2275 "umaal", "\t$Ra, $Rd, $Rn, $Rm", []>{
2276 let Inst{31-27} = 0b11111;
2277 let Inst{26-23} = 0b0111;
2278 let Inst{22-20} = 0b110;
2279 let Inst{7-4} = 0b0110;
2281 } // neverHasSideEffects
2283 // Rounding variants of the below included for disassembly only
2285 // Most significant word multiply
2286 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2287 "smmul", "\t$Rd, $Rn, $Rm",
2288 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]> {
2289 let Inst{31-27} = 0b11111;
2290 let Inst{26-23} = 0b0110;
2291 let Inst{22-20} = 0b101;
2292 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2293 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2296 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2297 "smmulr", "\t$Rd, $Rn, $Rm", []> {
2298 let Inst{31-27} = 0b11111;
2299 let Inst{26-23} = 0b0110;
2300 let Inst{22-20} = 0b101;
2301 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2302 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2305 def t2SMMLA : T2FourReg<
2306 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2307 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2308 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]> {
2309 let Inst{31-27} = 0b11111;
2310 let Inst{26-23} = 0b0110;
2311 let Inst{22-20} = 0b101;
2312 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2315 def t2SMMLAR: T2FourReg<
2316 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2317 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []> {
2318 let Inst{31-27} = 0b11111;
2319 let Inst{26-23} = 0b0110;
2320 let Inst{22-20} = 0b101;
2321 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2324 def t2SMMLS: T2FourReg<
2325 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2326 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2327 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]> {
2328 let Inst{31-27} = 0b11111;
2329 let Inst{26-23} = 0b0110;
2330 let Inst{22-20} = 0b110;
2331 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2334 def t2SMMLSR:T2FourReg<
2335 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2336 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []> {
2337 let Inst{31-27} = 0b11111;
2338 let Inst{26-23} = 0b0110;
2339 let Inst{22-20} = 0b110;
2340 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2343 multiclass T2I_smul<string opc, PatFrag opnode> {
2344 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2345 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2346 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2347 (sext_inreg rGPR:$Rm, i16)))]> {
2348 let Inst{31-27} = 0b11111;
2349 let Inst{26-23} = 0b0110;
2350 let Inst{22-20} = 0b001;
2351 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2352 let Inst{7-6} = 0b00;
2353 let Inst{5-4} = 0b00;
2356 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2357 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2358 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2359 (sra rGPR:$Rm, (i32 16))))]> {
2360 let Inst{31-27} = 0b11111;
2361 let Inst{26-23} = 0b0110;
2362 let Inst{22-20} = 0b001;
2363 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2364 let Inst{7-6} = 0b00;
2365 let Inst{5-4} = 0b01;
2368 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2369 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2370 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2371 (sext_inreg rGPR:$Rm, i16)))]> {
2372 let Inst{31-27} = 0b11111;
2373 let Inst{26-23} = 0b0110;
2374 let Inst{22-20} = 0b001;
2375 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2376 let Inst{7-6} = 0b00;
2377 let Inst{5-4} = 0b10;
2380 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2381 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2382 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2383 (sra rGPR:$Rm, (i32 16))))]> {
2384 let Inst{31-27} = 0b11111;
2385 let Inst{26-23} = 0b0110;
2386 let Inst{22-20} = 0b001;
2387 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2388 let Inst{7-6} = 0b00;
2389 let Inst{5-4} = 0b11;
2392 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2393 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2394 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2395 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]> {
2396 let Inst{31-27} = 0b11111;
2397 let Inst{26-23} = 0b0110;
2398 let Inst{22-20} = 0b011;
2399 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2400 let Inst{7-6} = 0b00;
2401 let Inst{5-4} = 0b00;
2404 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2405 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2406 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2407 (sra rGPR:$Rm, (i32 16))), (i32 16)))]> {
2408 let Inst{31-27} = 0b11111;
2409 let Inst{26-23} = 0b0110;
2410 let Inst{22-20} = 0b011;
2411 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2412 let Inst{7-6} = 0b00;
2413 let Inst{5-4} = 0b01;
2418 multiclass T2I_smla<string opc, PatFrag opnode> {
2420 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2421 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2422 [(set rGPR:$Rd, (add rGPR:$Ra,
2423 (opnode (sext_inreg rGPR:$Rn, i16),
2424 (sext_inreg rGPR:$Rm, i16))))]> {
2425 let Inst{31-27} = 0b11111;
2426 let Inst{26-23} = 0b0110;
2427 let Inst{22-20} = 0b001;
2428 let Inst{7-6} = 0b00;
2429 let Inst{5-4} = 0b00;
2433 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2434 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2435 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2436 (sra rGPR:$Rm, (i32 16)))))]> {
2437 let Inst{31-27} = 0b11111;
2438 let Inst{26-23} = 0b0110;
2439 let Inst{22-20} = 0b001;
2440 let Inst{7-6} = 0b00;
2441 let Inst{5-4} = 0b01;
2445 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2446 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2447 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2448 (sext_inreg rGPR:$Rm, i16))))]> {
2449 let Inst{31-27} = 0b11111;
2450 let Inst{26-23} = 0b0110;
2451 let Inst{22-20} = 0b001;
2452 let Inst{7-6} = 0b00;
2453 let Inst{5-4} = 0b10;
2457 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2458 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2459 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2460 (sra rGPR:$Rm, (i32 16)))))]> {
2461 let Inst{31-27} = 0b11111;
2462 let Inst{26-23} = 0b0110;
2463 let Inst{22-20} = 0b001;
2464 let Inst{7-6} = 0b00;
2465 let Inst{5-4} = 0b11;
2469 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2470 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2471 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2472 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]> {
2473 let Inst{31-27} = 0b11111;
2474 let Inst{26-23} = 0b0110;
2475 let Inst{22-20} = 0b011;
2476 let Inst{7-6} = 0b00;
2477 let Inst{5-4} = 0b00;
2481 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2482 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2483 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2484 (sra rGPR:$Rm, (i32 16))), (i32 16))))]> {
2485 let Inst{31-27} = 0b11111;
2486 let Inst{26-23} = 0b0110;
2487 let Inst{22-20} = 0b011;
2488 let Inst{7-6} = 0b00;
2489 let Inst{5-4} = 0b01;
2493 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2494 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2496 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2497 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2498 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2499 [/* For disassembly only; pattern left blank */]>;
2500 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2501 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2502 [/* For disassembly only; pattern left blank */]>;
2503 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2504 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2505 [/* For disassembly only; pattern left blank */]>;
2506 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2507 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2508 [/* For disassembly only; pattern left blank */]>;
2510 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2511 // These are for disassembly only.
2513 def t2SMUAD: T2ThreeReg_mac<
2514 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2515 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []> {
2516 let Inst{15-12} = 0b1111;
2518 def t2SMUADX:T2ThreeReg_mac<
2519 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2520 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []> {
2521 let Inst{15-12} = 0b1111;
2523 def t2SMUSD: T2ThreeReg_mac<
2524 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2525 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []> {
2526 let Inst{15-12} = 0b1111;
2528 def t2SMUSDX:T2ThreeReg_mac<
2529 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2530 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []> {
2531 let Inst{15-12} = 0b1111;
2533 def t2SMLAD : T2ThreeReg_mac<
2534 0, 0b010, 0b0000, (outs rGPR:$Rd),
2535 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2536 "\t$Rd, $Rn, $Rm, $Ra", []>;
2537 def t2SMLADX : T2FourReg_mac<
2538 0, 0b010, 0b0001, (outs rGPR:$Rd),
2539 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2540 "\t$Rd, $Rn, $Rm, $Ra", []>;
2541 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2542 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2543 "\t$Rd, $Rn, $Rm, $Ra", []>;
2544 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2545 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2546 "\t$Rd, $Rn, $Rm, $Ra", []>;
2547 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2548 (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2549 "\t$Ra, $Rd, $Rm, $Rn", []>;
2550 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2551 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2552 "\t$Ra, $Rd, $Rm, $Rn", []>;
2553 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2554 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2555 "\t$Ra, $Rd, $Rm, $Rn", []>;
2556 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2557 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2558 "\t$Ra, $Rd, $Rm, $Rn", []>;
2560 //===----------------------------------------------------------------------===//
2561 // Misc. Arithmetic Instructions.
2564 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2565 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2566 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2567 let Inst{31-27} = 0b11111;
2568 let Inst{26-22} = 0b01010;
2569 let Inst{21-20} = op1;
2570 let Inst{15-12} = 0b1111;
2571 let Inst{7-6} = 0b10;
2572 let Inst{5-4} = op2;
2573 let Rn{3-0} = Rm{3-0};
2576 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2577 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2579 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2580 "rbit", "\t$Rd, $Rm",
2581 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2583 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2584 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2586 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2587 "rev16", ".w\t$Rd, $Rm",
2589 (or (and (srl rGPR:$Rm, (i32 8)), 0xFF),
2590 (or (and (shl rGPR:$Rm, (i32 8)), 0xFF00),
2591 (or (and (srl rGPR:$Rm, (i32 8)), 0xFF0000),
2592 (and (shl rGPR:$Rm, (i32 8)), 0xFF000000)))))]>;
2594 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2595 "revsh", ".w\t$Rd, $Rm",
2598 (or (srl (and rGPR:$Rm, 0xFF00), (i32 8)),
2599 (shl rGPR:$Rm, (i32 8))), i16))]>;
2601 def t2PKHBT : T2ThreeReg<
2602 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2603 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2604 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2605 (and (shl rGPR:$Rm, lsl_amt:$sh),
2607 Requires<[HasT2ExtractPack, IsThumb2]> {
2608 let Inst{31-27} = 0b11101;
2609 let Inst{26-25} = 0b01;
2610 let Inst{24-20} = 0b01100;
2611 let Inst{5} = 0; // BT form
2615 let Inst{14-12} = sh{7-5};
2616 let Inst{7-6} = sh{4-3};
2619 // Alternate cases for PKHBT where identities eliminate some nodes.
2620 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2621 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2622 Requires<[HasT2ExtractPack, IsThumb2]>;
2623 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2624 (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>,
2625 Requires<[HasT2ExtractPack, IsThumb2]>;
2627 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2628 // will match the pattern below.
2629 def t2PKHTB : T2ThreeReg<
2630 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2631 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2632 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2633 (and (sra rGPR:$Rm, asr_amt:$sh),
2635 Requires<[HasT2ExtractPack, IsThumb2]> {
2636 let Inst{31-27} = 0b11101;
2637 let Inst{26-25} = 0b01;
2638 let Inst{24-20} = 0b01100;
2639 let Inst{5} = 1; // TB form
2643 let Inst{14-12} = sh{7-5};
2644 let Inst{7-6} = sh{4-3};
2647 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2648 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2649 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2650 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>,
2651 Requires<[HasT2ExtractPack, IsThumb2]>;
2652 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2653 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2654 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>,
2655 Requires<[HasT2ExtractPack, IsThumb2]>;
2657 //===----------------------------------------------------------------------===//
2658 // Comparison Instructions...
2660 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2661 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2662 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2663 defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
2664 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2665 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2667 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2668 // Compare-to-zero still works out, just not the relationals
2669 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2670 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2671 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2672 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2673 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2675 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2676 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2678 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2679 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2681 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2682 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2683 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2684 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2685 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2686 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2688 // Conditional moves
2689 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2690 // a two-value operand where a dag node expects two operands. :(
2691 let neverHasSideEffects = 1 in {
2692 def t2MOVCCr : T2TwoReg<
2693 (outs rGPR:$Rd), (ins rGPR:$false, rGPR:$Rm), IIC_iCMOVr,
2694 "mov", ".w\t$Rd, $Rm",
2695 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2696 RegConstraint<"$false = $Rd"> {
2697 let Inst{31-27} = 0b11101;
2698 let Inst{26-25} = 0b01;
2699 let Inst{24-21} = 0b0010;
2700 let Inst{20} = 0; // The S bit.
2701 let Inst{19-16} = 0b1111; // Rn
2702 let Inst{14-12} = 0b000;
2703 let Inst{7-4} = 0b0000;
2706 let isMoveImm = 1 in
2707 def t2MOVCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2708 IIC_iCMOVi, "mov", ".w\t$Rd, $imm",
2709 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2710 RegConstraint<"$false = $Rd"> {
2711 let Inst{31-27} = 0b11110;
2713 let Inst{24-21} = 0b0010;
2714 let Inst{20} = 0; // The S bit.
2715 let Inst{19-16} = 0b1111; // Rn
2719 let isMoveImm = 1 in
2720 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, i32imm:$imm),
2722 "movw", "\t$Rd, $imm", []>,
2723 RegConstraint<"$false = $Rd"> {
2724 let Inst{31-27} = 0b11110;
2726 let Inst{24-21} = 0b0010;
2727 let Inst{20} = 0; // The S bit.
2733 let Inst{11-8} = Rd{3-0};
2734 let Inst{19-16} = imm{15-12};
2735 let Inst{26} = imm{11};
2736 let Inst{14-12} = imm{10-8};
2737 let Inst{7-0} = imm{7-0};
2740 let isMoveImm = 1 in
2741 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2742 (ins rGPR:$false, i32imm:$src, pred:$p),
2743 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2745 let isMoveImm = 1 in
2746 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2747 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2748 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2749 imm:$cc, CCR:$ccr))*/]>,
2750 RegConstraint<"$false = $Rd"> {
2751 let Inst{31-27} = 0b11110;
2753 let Inst{24-21} = 0b0011;
2754 let Inst{20} = 0; // The S bit.
2755 let Inst{19-16} = 0b1111; // Rn
2759 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2760 string opc, string asm, list<dag> pattern>
2761 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2762 let Inst{31-27} = 0b11101;
2763 let Inst{26-25} = 0b01;
2764 let Inst{24-21} = 0b0010;
2765 let Inst{20} = 0; // The S bit.
2766 let Inst{19-16} = 0b1111; // Rn
2767 let Inst{5-4} = opcod; // Shift type.
2769 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2770 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2771 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2772 RegConstraint<"$false = $Rd">;
2773 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2774 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2775 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2776 RegConstraint<"$false = $Rd">;
2777 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2778 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2779 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2780 RegConstraint<"$false = $Rd">;
2781 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2782 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2783 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2784 RegConstraint<"$false = $Rd">;
2785 } // neverHasSideEffects
2787 //===----------------------------------------------------------------------===//
2788 // Atomic operations intrinsics
2791 // memory barriers protect the atomic sequences
2792 let hasSideEffects = 1 in {
2793 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2794 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2795 Requires<[IsThumb, HasDB]> {
2797 let Inst{31-4} = 0xf3bf8f5;
2798 let Inst{3-0} = opt;
2802 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2804 [/* For disassembly only; pattern left blank */]>,
2805 Requires<[IsThumb, HasDB]> {
2807 let Inst{31-4} = 0xf3bf8f4;
2808 let Inst{3-0} = opt;
2811 // ISB has only full system option -- for disassembly only
2812 def t2ISB : T2I<(outs), (ins), NoItinerary, "isb", "",
2813 [/* For disassembly only; pattern left blank */]>,
2814 Requires<[IsThumb2, HasV7]> {
2815 let Inst{31-4} = 0xf3bf8f6;
2816 let Inst{3-0} = 0b1111;
2819 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2820 InstrItinClass itin, string opc, string asm, string cstr,
2821 list<dag> pattern, bits<4> rt2 = 0b1111>
2822 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2823 let Inst{31-27} = 0b11101;
2824 let Inst{26-20} = 0b0001101;
2825 let Inst{11-8} = rt2;
2826 let Inst{7-6} = 0b01;
2827 let Inst{5-4} = opcod;
2828 let Inst{3-0} = 0b1111;
2832 let Inst{19-16} = Rn{3-0};
2833 let Inst{15-12} = Rt{3-0};
2835 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2836 InstrItinClass itin, string opc, string asm, string cstr,
2837 list<dag> pattern, bits<4> rt2 = 0b1111>
2838 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2839 let Inst{31-27} = 0b11101;
2840 let Inst{26-20} = 0b0001100;
2841 let Inst{11-8} = rt2;
2842 let Inst{7-6} = 0b01;
2843 let Inst{5-4} = opcod;
2848 let Inst{11-8} = Rd{3-0};
2849 let Inst{19-16} = Rn{3-0};
2850 let Inst{15-12} = Rt{3-0};
2853 let mayLoad = 1 in {
2854 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins rGPR:$Rn), AddrModeNone,
2855 Size4Bytes, NoItinerary, "ldrexb", "\t$Rt, [$Rn]",
2857 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins rGPR:$Rn), AddrModeNone,
2858 Size4Bytes, NoItinerary, "ldrexh", "\t$Rt, [$Rn]",
2860 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins rGPR:$Rn), AddrModeNone,
2861 Size4Bytes, NoItinerary,
2862 "ldrex", "\t$Rt, [$Rn]", "",
2864 let Inst{31-27} = 0b11101;
2865 let Inst{26-20} = 0b0000101;
2866 let Inst{11-8} = 0b1111;
2867 let Inst{7-0} = 0b00000000; // imm8 = 0
2869 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2), (ins rGPR:$Rn),
2870 AddrModeNone, Size4Bytes, NoItinerary,
2871 "ldrexd", "\t$Rt, $Rt2, [$Rn]", "",
2874 let Inst{11-8} = Rt2{3-0};
2878 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2879 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rn),
2880 AddrModeNone, Size4Bytes, NoItinerary,
2881 "strexb", "\t$Rd, $Rt, [$Rn]", "", []>;
2882 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rn),
2883 AddrModeNone, Size4Bytes, NoItinerary,
2884 "strexh", "\t$Rd, $Rt, [$Rn]", "", []>;
2885 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rn),
2886 AddrModeNone, Size4Bytes, NoItinerary,
2887 "strex", "\t$Rd, $Rt, [$Rn]", "",
2889 let Inst{31-27} = 0b11101;
2890 let Inst{26-20} = 0b0000100;
2891 let Inst{7-0} = 0b00000000; // imm8 = 0
2893 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2894 (ins rGPR:$Rt, rGPR:$Rt2, rGPR:$Rn),
2895 AddrModeNone, Size4Bytes, NoItinerary,
2896 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]", "", [],
2899 let Inst{11-8} = Rt2{3-0};
2903 // Clear-Exclusive is for disassembly only.
2904 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2905 [/* For disassembly only; pattern left blank */]>,
2906 Requires<[IsARM, HasV7]> {
2907 let Inst{31-20} = 0xf3b;
2908 let Inst{15-14} = 0b10;
2910 let Inst{7-4} = 0b0010;
2913 //===----------------------------------------------------------------------===//
2917 // __aeabi_read_tp preserves the registers r1-r3.
2919 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
2920 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2921 "bl\t__aeabi_read_tp",
2922 [(set R0, ARMthread_pointer)]> {
2923 let Inst{31-27} = 0b11110;
2924 let Inst{15-14} = 0b11;
2929 //===----------------------------------------------------------------------===//
2930 // SJLJ Exception handling intrinsics
2931 // eh_sjlj_setjmp() is an instruction sequence to store the return
2932 // address and save #0 in R0 for the non-longjmp case.
2933 // Since by its nature we may be coming from some other function to get
2934 // here, and we're using the stack frame for the containing function to
2935 // save/restore registers, we can't keep anything live in regs across
2936 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2937 // when we get here from a longjmp(). We force everthing out of registers
2938 // except for our own input by listing the relevant registers in Defs. By
2939 // doing so, we also cause the prologue/epilogue code to actively preserve
2940 // all of the callee-saved resgisters, which is exactly what we want.
2941 // $val is a scratch register for our use.
2943 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2944 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2945 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2946 D31 ], hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2947 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2948 AddrModeNone, SizeSpecial, NoItinerary, "", "",
2949 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2950 Requires<[IsThumb2, HasVFP2]>;
2954 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2955 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2956 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2957 AddrModeNone, SizeSpecial, NoItinerary, "", "",
2958 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2959 Requires<[IsThumb2, NoVFP]>;
2963 //===----------------------------------------------------------------------===//
2964 // Control-Flow Instructions
2967 // FIXME: remove when we have a way to marking a MI with these properties.
2968 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2970 // FIXME: Should pc be an implicit operand like PICADD, etc?
2971 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2972 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2973 def t2LDMIA_RET: T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2974 reglist:$regs, variable_ops),
2976 "ldmia${p}.w\t$Rn!, $regs",
2981 let Inst{31-27} = 0b11101;
2982 let Inst{26-25} = 0b00;
2983 let Inst{24-23} = 0b01; // Increment After
2985 let Inst{21} = 1; // Writeback
2987 let Inst{19-16} = Rn;
2988 let Inst{15-0} = regs;
2991 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2992 let isPredicable = 1 in
2993 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2995 [(br bb:$target)]> {
2996 let Inst{31-27} = 0b11110;
2997 let Inst{15-14} = 0b10;
3001 let Inst{26} = target{19};
3002 let Inst{11} = target{18};
3003 let Inst{13} = target{17};
3004 let Inst{21-16} = target{16-11};
3005 let Inst{10-0} = target{10-0};
3008 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3009 def t2BR_JT : tPseudoInst<(outs),
3010 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3011 SizeSpecial, IIC_Br,
3012 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3014 // FIXME: Add a non-pc based case that can be predicated.
3015 def t2TBB_JT : tPseudoInst<(outs),
3016 (ins GPR:$index, i32imm:$jt, i32imm:$id),
3017 SizeSpecial, IIC_Br, []>;
3019 def t2TBH_JT : tPseudoInst<(outs),
3020 (ins GPR:$index, i32imm:$jt, i32imm:$id),
3021 SizeSpecial, IIC_Br, []>;
3023 def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3024 "tbb", "\t[$Rn, $Rm]", []> {
3027 let Inst{27-20} = 0b10001101;
3028 let Inst{19-16} = Rn;
3029 let Inst{15-5} = 0b11110000000;
3030 let Inst{4} = 0; // B form
3034 def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3035 "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
3038 let Inst{27-20} = 0b10001101;
3039 let Inst{19-16} = Rn;
3040 let Inst{15-5} = 0b11110000000;
3041 let Inst{4} = 1; // H form
3044 } // isNotDuplicable, isIndirectBranch
3046 } // isBranch, isTerminator, isBarrier
3048 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3049 // a two-value operand where a dag node expects two operands. :(
3050 let isBranch = 1, isTerminator = 1 in
3051 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3053 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3054 let Inst{31-27} = 0b11110;
3055 let Inst{15-14} = 0b10;
3059 let Inst{26} = target{19};
3060 let Inst{11} = target{18};
3061 let Inst{13} = target{17};
3062 let Inst{21-16} = target{16-11};
3063 let Inst{10-0} = target{10-0};
3068 let Defs = [ITSTATE] in
3069 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3070 AddrModeNone, Size2Bytes, IIC_iALUx,
3071 "it$mask\t$cc", "", []> {
3072 // 16-bit instruction.
3073 let Inst{31-16} = 0x0000;
3074 let Inst{15-8} = 0b10111111;
3078 let Inst{7-4} = cc{3-0};
3079 let Inst{3-0} = mask{3-0};
3082 // Branch and Exchange Jazelle -- for disassembly only
3084 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
3085 [/* For disassembly only; pattern left blank */]> {
3086 let Inst{31-27} = 0b11110;
3088 let Inst{25-20} = 0b111100;
3089 let Inst{15-14} = 0b10;
3093 let Inst{19-16} = func{3-0};
3096 // Change Processor State is a system instruction -- for disassembly only.
3097 // The singleton $opt operand contains the following information:
3098 // opt{4-0} = mode from Inst{4-0}
3099 // opt{5} = changemode from Inst{17}
3100 // opt{8-6} = AIF from Inst{8-6}
3101 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
3102 def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
3103 [/* For disassembly only; pattern left blank */]> {
3104 let Inst{31-27} = 0b11110;
3106 let Inst{25-20} = 0b111010;
3107 let Inst{15-14} = 0b10;
3113 let Inst{4-0} = opt{4-0};
3116 let Inst{8} = opt{5};
3119 let Inst{5} = opt{6};
3122 let Inst{6} = opt{7};
3125 let Inst{7} = opt{8};
3128 let Inst{10-9} = opt{10-9};
3131 // A6.3.4 Branches and miscellaneous control
3132 // Table A6-14 Change Processor State, and hint instructions
3133 // Helper class for disassembly only.
3134 class T2I_hint<bits<8> op7_0, string opc, string asm>
3135 : T2I<(outs), (ins), NoItinerary, opc, asm,
3136 [/* For disassembly only; pattern left blank */]> {
3137 let Inst{31-20} = 0xf3a;
3138 let Inst{15-14} = 0b10;
3140 let Inst{10-8} = 0b000;
3141 let Inst{7-0} = op7_0;
3144 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3145 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3146 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3147 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3148 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3150 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
3151 [/* For disassembly only; pattern left blank */]> {
3152 let Inst{31-20} = 0xf3a;
3153 let Inst{15-14} = 0b10;
3155 let Inst{10-8} = 0b000;
3156 let Inst{7-4} = 0b1111;
3159 let Inst{3-0} = opt{3-0};
3162 // Secure Monitor Call is a system instruction -- for disassembly only
3163 // Option = Inst{19-16}
3164 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
3165 [/* For disassembly only; pattern left blank */]> {
3166 let Inst{31-27} = 0b11110;
3167 let Inst{26-20} = 0b1111111;
3168 let Inst{15-12} = 0b1000;
3171 let Inst{19-16} = opt{3-0};
3174 class T2SRS<bits<12> op31_20,
3175 dag oops, dag iops, InstrItinClass itin,
3176 string opc, string asm, list<dag> pattern>
3177 : T2I<oops, iops, itin, opc, asm, pattern> {
3178 let Inst{31-20} = op31_20{11-0};
3181 let Inst{4-0} = mode{4-0};
3184 // Store Return State is a system instruction -- for disassembly only
3185 def t2SRSDBW : T2SRS<0b111010000010,
3186 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3187 [/* For disassembly only; pattern left blank */]>;
3188 def t2SRSDB : T2SRS<0b111010000000,
3189 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3190 [/* For disassembly only; pattern left blank */]>;
3191 def t2SRSIAW : T2SRS<0b111010011010,
3192 (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3193 [/* For disassembly only; pattern left blank */]>;
3194 def t2SRSIA : T2SRS<0b111010011000,
3195 (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3196 [/* For disassembly only; pattern left blank */]>;
3198 // Return From Exception is a system instruction -- for disassembly only
3200 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3201 string opc, string asm, list<dag> pattern>
3202 : T2I<oops, iops, itin, opc, asm, pattern> {
3203 let Inst{31-20} = op31_20{11-0};
3206 let Inst{19-16} = Rn{3-0};
3209 def t2RFEDBW : T2RFE<0b111010000011,
3210 (outs), (ins rGPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3211 [/* For disassembly only; pattern left blank */]>;
3212 def t2RFEDB : T2RFE<0b111010000001,
3213 (outs), (ins rGPR:$Rn), NoItinerary, "rfeab", "\t$Rn",
3214 [/* For disassembly only; pattern left blank */]>;
3215 def t2RFEIAW : T2RFE<0b111010011011,
3216 (outs), (ins rGPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3217 [/* For disassembly only; pattern left blank */]>;
3218 def t2RFEIA : T2RFE<0b111010011001,
3219 (outs), (ins rGPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3220 [/* For disassembly only; pattern left blank */]>;
3222 //===----------------------------------------------------------------------===//
3223 // Non-Instruction Patterns
3226 // 32-bit immediate using movw + movt.
3227 // This is a single pseudo instruction to make it re-materializable.
3228 // FIXME: Remove this when we can do generalized remat.
3229 let isReMaterializable = 1, isMoveImm = 1 in
3230 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3231 [(set rGPR:$dst, (i32 imm:$src))]>,
3232 Requires<[IsThumb, HasV6T2]>;
3234 // ConstantPool, GlobalAddress, and JumpTable
3235 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3236 Requires<[IsThumb2, DontUseMovt]>;
3237 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3238 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3239 Requires<[IsThumb2, UseMovt]>;
3241 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3242 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3244 // Pseudo instruction that combines ldr from constpool and add pc. This should
3245 // be expanded into two instructions late to allow if-conversion and
3247 let canFoldAsLoad = 1, isReMaterializable = 1 in
3248 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3250 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3252 Requires<[IsThumb2]>;
3254 //===----------------------------------------------------------------------===//
3255 // Move between special register and ARM core register -- for disassembly only
3258 class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3259 dag oops, dag iops, InstrItinClass itin,
3260 string opc, string asm, list<dag> pattern>
3261 : T2I<oops, iops, itin, opc, asm, pattern> {
3262 let Inst{31-20} = op31_20{11-0};
3263 let Inst{15-14} = op15_14{1-0};
3264 let Inst{12} = op12{0};
3267 class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3268 dag oops, dag iops, InstrItinClass itin,
3269 string opc, string asm, list<dag> pattern>
3270 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3272 let Inst{11-8} = Rd{3-0};
3275 def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3276 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3277 [/* For disassembly only; pattern left blank */]>;
3278 def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3279 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3280 [/* For disassembly only; pattern left blank */]>;
3282 class T2MSR<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3283 dag oops, dag iops, InstrItinClass itin,
3284 string opc, string asm, list<dag> pattern>
3285 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3288 let Inst{19-16} = Rn{3-0};
3289 let Inst{11-8} = mask{3-0};
3292 def t2MSR : T2MSR<0b111100111000, 0b10, 0,
3293 (outs), (ins rGPR:$Rn, msr_mask:$mask), NoItinerary, "msr",
3295 [/* For disassembly only; pattern left blank */]>;
3296 def t2MSRsys : T2MSR<0b111100111001, 0b10, 0,
3297 (outs), (ins rGPR:$Rn, msr_mask:$mask), NoItinerary, "msr",
3299 [/* For disassembly only; pattern left blank */]>;