1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops GPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant
53 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>,
56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
59 // t2_so_imm_not - Match an immediate that is a complement
61 def t2_so_imm_not : Operand<i32>,
63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
64 }], t2_so_imm_not_XFORM>;
66 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
67 def t2_so_imm_neg : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
70 }], t2_so_imm_neg_XFORM>;
72 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
73 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
74 // to get the first/second pieces.
75 def t2_so_imm2part : Operand<i32>,
77 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
81 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
82 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
83 return CurDAG->getTargetConstant(V, MVT::i32);
86 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
87 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
88 return CurDAG->getTargetConstant(V, MVT::i32);
91 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
92 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
96 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
97 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
98 return CurDAG->getTargetConstant(V, MVT::i32);
101 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
102 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
103 return CurDAG->getTargetConstant(V, MVT::i32);
106 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
107 def imm1_31 : PatLeaf<(i32 imm), [{
108 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
111 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
112 def imm0_4095 : Operand<i32>,
113 PatLeaf<(i32 imm), [{
114 return (uint32_t)N->getZExtValue() < 4096;
117 def imm0_4095_neg : PatLeaf<(i32 imm), [{
118 return (uint32_t)(-N->getZExtValue()) < 4096;
121 def imm0_255_neg : PatLeaf<(i32 imm), [{
122 return (uint32_t)(-N->getZExtValue()) < 255;
125 def imm0_255_not : PatLeaf<(i32 imm), [{
126 return (uint32_t)(~N->getZExtValue()) < 255;
129 // Define Thumb2 specific addressing modes.
131 // t2addrmode_imm12 := reg + imm12
132 def t2addrmode_imm12 : Operand<i32>,
133 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
134 let PrintMethod = "printT2AddrModeImm12Operand";
135 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
138 // t2addrmode_imm8 := reg +/- imm8
139 def t2addrmode_imm8 : Operand<i32>,
140 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
141 let PrintMethod = "printT2AddrModeImm8Operand";
142 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
145 def t2am_imm8_offset : Operand<i32>,
146 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
147 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
150 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
151 def t2addrmode_imm8s4 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
153 let PrintMethod = "printT2AddrModeImm8s4Operand";
154 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
157 def t2am_imm8s4_offset : Operand<i32> {
158 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
161 // t2addrmode_so_reg := reg + (reg << imm2)
162 def t2addrmode_so_reg : Operand<i32>,
163 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
164 let PrintMethod = "printT2AddrModeSoRegOperand";
165 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
169 //===----------------------------------------------------------------------===//
170 // Multiclass helpers...
173 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
174 /// unary operation that produces a value. These are predicable and can be
175 /// changed to modify CPSR.
176 multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode,
177 bit Cheap = 0, bit ReMat = 0> {
179 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
181 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
182 let isAsCheapAsAMove = Cheap;
183 let isReMaterializable = ReMat;
184 let Inst{31-27} = 0b11110;
186 let Inst{24-21} = opcod;
187 let Inst{20} = ?; // The S bit.
188 let Inst{19-16} = 0b1111; // Rn
192 def r : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
193 opc, ".w\t$dst, $src",
194 [(set GPR:$dst, (opnode GPR:$src))]> {
195 let Inst{31-27} = 0b11101;
196 let Inst{26-25} = 0b01;
197 let Inst{24-21} = opcod;
198 let Inst{20} = ?; // The S bit.
199 let Inst{19-16} = 0b1111; // Rn
200 let Inst{14-12} = 0b000; // imm3
201 let Inst{7-6} = 0b00; // imm2
202 let Inst{5-4} = 0b00; // type
205 def s : T2sI<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
206 opc, ".w\t$dst, $src",
207 [(set GPR:$dst, (opnode t2_so_reg:$src))]> {
208 let Inst{31-27} = 0b11101;
209 let Inst{26-25} = 0b01;
210 let Inst{24-21} = opcod;
211 let Inst{20} = ?; // The S bit.
212 let Inst{19-16} = 0b1111; // Rn
216 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
217 /// binary operation that produces a value. These are predicable and can be
218 /// changed to modify CPSR.
219 multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
220 bit Commutable = 0, string wide =""> {
222 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
223 opc, "\t$dst, $lhs, $rhs",
224 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
225 let Inst{31-27} = 0b11110;
227 let Inst{24-21} = opcod;
228 let Inst{20} = ?; // The S bit.
232 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
233 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
234 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
235 let isCommutable = Commutable;
236 let Inst{31-27} = 0b11101;
237 let Inst{26-25} = 0b01;
238 let Inst{24-21} = opcod;
239 let Inst{20} = ?; // The S bit.
240 let Inst{14-12} = 0b000; // imm3
241 let Inst{7-6} = 0b00; // imm2
242 let Inst{5-4} = 0b00; // type
245 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
246 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
247 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
248 let Inst{31-27} = 0b11101;
249 let Inst{26-25} = 0b01;
250 let Inst{24-21} = opcod;
251 let Inst{20} = ?; // The S bit.
255 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
256 // the ".w" prefix to indicate that they are wide.
257 multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
258 bit Commutable = 0> :
259 T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
261 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
262 /// reversed. It doesn't define the 'rr' form since it's handled by its
263 /// T2I_bin_irs counterpart.
264 multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> {
266 def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
267 opc, ".w\t$dst, $rhs, $lhs",
268 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
269 let Inst{31-27} = 0b11110;
271 let Inst{24-21} = opcod;
272 let Inst{20} = ?; // The S bit.
276 def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
277 opc, "\t$dst, $rhs, $lhs",
278 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
279 let Inst{31-27} = 0b11101;
280 let Inst{26-25} = 0b01;
281 let Inst{24-21} = opcod;
282 let Inst{20} = ?; // The S bit.
286 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
287 /// instruction modifies the CPSR register.
288 let Defs = [CPSR] in {
289 multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
290 bit Commutable = 0> {
292 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
293 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
294 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
295 let Inst{31-27} = 0b11110;
297 let Inst{24-21} = opcod;
298 let Inst{20} = 1; // The S bit.
302 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
303 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
304 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
305 let isCommutable = Commutable;
306 let Inst{31-27} = 0b11101;
307 let Inst{26-25} = 0b01;
308 let Inst{24-21} = opcod;
309 let Inst{20} = 1; // The S bit.
310 let Inst{14-12} = 0b000; // imm3
311 let Inst{7-6} = 0b00; // imm2
312 let Inst{5-4} = 0b00; // type
315 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
316 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
317 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
318 let Inst{31-27} = 0b11101;
319 let Inst{26-25} = 0b01;
320 let Inst{24-21} = opcod;
321 let Inst{20} = 1; // The S bit.
326 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
327 /// patterns for a binary operation that produces a value.
328 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
329 bit Commutable = 0> {
331 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
332 opc, ".w\t$dst, $lhs, $rhs",
333 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
334 let Inst{31-27} = 0b11110;
337 let Inst{23-21} = op23_21;
338 let Inst{20} = 0; // The S bit.
342 def ri12 : T2I<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
343 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
344 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
345 let Inst{31-27} = 0b11110;
348 let Inst{23-21} = op23_21;
349 let Inst{20} = 0; // The S bit.
353 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
354 opc, ".w\t$dst, $lhs, $rhs",
355 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
356 let isCommutable = Commutable;
357 let Inst{31-27} = 0b11101;
358 let Inst{26-25} = 0b01;
360 let Inst{23-21} = op23_21;
361 let Inst{20} = 0; // The S bit.
362 let Inst{14-12} = 0b000; // imm3
363 let Inst{7-6} = 0b00; // imm2
364 let Inst{5-4} = 0b00; // type
367 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
368 opc, ".w\t$dst, $lhs, $rhs",
369 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
370 let Inst{31-27} = 0b11101;
371 let Inst{26-25} = 0b01;
373 let Inst{23-21} = op23_21;
374 let Inst{20} = 0; // The S bit.
378 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
379 /// for a binary operation that produces a value and use the carry
380 /// bit. It's not predicable.
381 let Uses = [CPSR] in {
382 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
383 bit Commutable = 0> {
385 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
386 opc, "\t$dst, $lhs, $rhs",
387 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
388 Requires<[IsThumb2]> {
389 let Inst{31-27} = 0b11110;
391 let Inst{24-21} = opcod;
392 let Inst{20} = 0; // The S bit.
396 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
397 opc, ".w\t$dst, $lhs, $rhs",
398 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
399 Requires<[IsThumb2]> {
400 let isCommutable = Commutable;
401 let Inst{31-27} = 0b11101;
402 let Inst{26-25} = 0b01;
403 let Inst{24-21} = opcod;
404 let Inst{20} = 0; // The S bit.
405 let Inst{14-12} = 0b000; // imm3
406 let Inst{7-6} = 0b00; // imm2
407 let Inst{5-4} = 0b00; // type
410 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
411 opc, ".w\t$dst, $lhs, $rhs",
412 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
413 Requires<[IsThumb2]> {
414 let Inst{31-27} = 0b11101;
415 let Inst{26-25} = 0b01;
416 let Inst{24-21} = opcod;
417 let Inst{20} = 0; // The S bit.
421 // Carry setting variants
422 let Defs = [CPSR] in {
423 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
424 bit Commutable = 0> {
426 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
427 opc, "\t$dst, $lhs, $rhs",
428 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
429 Requires<[IsThumb2]> {
430 let Inst{31-27} = 0b11110;
432 let Inst{24-21} = opcod;
433 let Inst{20} = 1; // The S bit.
437 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
438 opc, ".w\t$dst, $lhs, $rhs",
439 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
440 Requires<[IsThumb2]> {
441 let isCommutable = Commutable;
442 let Inst{31-27} = 0b11101;
443 let Inst{26-25} = 0b01;
444 let Inst{24-21} = opcod;
445 let Inst{20} = 1; // The S bit.
446 let Inst{14-12} = 0b000; // imm3
447 let Inst{7-6} = 0b00; // imm2
448 let Inst{5-4} = 0b00; // type
451 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
452 opc, ".w\t$dst, $lhs, $rhs",
453 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
454 Requires<[IsThumb2]> {
455 let Inst{31-27} = 0b11101;
456 let Inst{26-25} = 0b01;
457 let Inst{24-21} = opcod;
458 let Inst{20} = 1; // The S bit.
464 /// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
465 let Defs = [CPSR] in {
466 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
468 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
469 !strconcat(opc, "s"), ".w\t$dst, $rhs, $lhs",
470 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
471 let Inst{31-27} = 0b11110;
473 let Inst{24-21} = opcod;
474 let Inst{20} = 1; // The S bit.
478 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
479 !strconcat(opc, "s"), "\t$dst, $rhs, $lhs",
480 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
481 let Inst{31-27} = 0b11101;
482 let Inst{26-25} = 0b01;
483 let Inst{24-21} = opcod;
484 let Inst{20} = 1; // The S bit.
489 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
490 // rotate operation that produces a value.
491 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
493 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
494 opc, ".w\t$dst, $lhs, $rhs",
495 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]> {
496 let Inst{31-27} = 0b11101;
497 let Inst{26-21} = 0b010010;
498 let Inst{19-16} = 0b1111; // Rn
499 let Inst{5-4} = opcod;
502 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr,
503 opc, ".w\t$dst, $lhs, $rhs",
504 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
505 let Inst{31-27} = 0b11111;
506 let Inst{26-23} = 0b0100;
507 let Inst{22-21} = opcod;
508 let Inst{15-12} = 0b1111;
509 let Inst{7-4} = 0b0000;
513 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
514 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
515 /// a explicit result, only implicitly set CPSR.
516 let Defs = [CPSR] in {
517 multiclass T2I_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
519 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
520 opc, ".w\t$lhs, $rhs",
521 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> {
522 let Inst{31-27} = 0b11110;
524 let Inst{24-21} = opcod;
525 let Inst{20} = 1; // The S bit.
527 let Inst{11-8} = 0b1111; // Rd
530 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
531 opc, ".w\t$lhs, $rhs",
532 [(opnode GPR:$lhs, GPR:$rhs)]> {
533 let Inst{31-27} = 0b11101;
534 let Inst{26-25} = 0b01;
535 let Inst{24-21} = opcod;
536 let Inst{20} = 1; // The S bit.
537 let Inst{14-12} = 0b000; // imm3
538 let Inst{11-8} = 0b1111; // Rd
539 let Inst{7-6} = 0b00; // imm2
540 let Inst{5-4} = 0b00; // type
543 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
544 opc, ".w\t$lhs, $rhs",
545 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> {
546 let Inst{31-27} = 0b11101;
547 let Inst{26-25} = 0b01;
548 let Inst{24-21} = opcod;
549 let Inst{20} = 1; // The S bit.
550 let Inst{11-8} = 0b1111; // Rd
555 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
556 multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> {
557 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
558 opc, ".w\t$dst, $addr",
559 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
560 let Inst{31-27} = 0b11111;
561 let Inst{26-25} = 0b00;
562 let Inst{24} = signed;
564 let Inst{22-21} = opcod;
565 let Inst{20} = 1; // load
567 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
568 opc, "\t$dst, $addr",
569 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
570 let Inst{31-27} = 0b11111;
571 let Inst{26-25} = 0b00;
572 let Inst{24} = signed;
574 let Inst{22-21} = opcod;
575 let Inst{20} = 1; // load
577 // Offset: index==TRUE, wback==FALSE
578 let Inst{10} = 1; // The P bit.
579 let Inst{8} = 0; // The W bit.
581 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
582 opc, ".w\t$dst, $addr",
583 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
584 let Inst{31-27} = 0b11111;
585 let Inst{26-25} = 0b00;
586 let Inst{24} = signed;
588 let Inst{22-21} = opcod;
589 let Inst{20} = 1; // load
590 let Inst{11-6} = 0b000000;
592 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
593 opc, ".w\t$dst, $addr",
594 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
595 let isReMaterializable = 1;
596 let Inst{31-27} = 0b11111;
597 let Inst{26-25} = 0b00;
598 let Inst{24} = signed;
599 let Inst{23} = ?; // add = (U == '1')
600 let Inst{22-21} = opcod;
601 let Inst{20} = 1; // load
602 let Inst{19-16} = 0b1111; // Rn
606 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
607 multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> {
608 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
609 opc, ".w\t$src, $addr",
610 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
611 let Inst{31-27} = 0b11111;
612 let Inst{26-23} = 0b0001;
613 let Inst{22-21} = opcod;
614 let Inst{20} = 0; // !load
616 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
617 opc, "\t$src, $addr",
618 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
619 let Inst{31-27} = 0b11111;
620 let Inst{26-23} = 0b0000;
621 let Inst{22-21} = opcod;
622 let Inst{20} = 0; // !load
624 // Offset: index==TRUE, wback==FALSE
625 let Inst{10} = 1; // The P bit.
626 let Inst{8} = 0; // The W bit.
628 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
629 opc, ".w\t$src, $addr",
630 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
631 let Inst{31-27} = 0b11111;
632 let Inst{26-23} = 0b0000;
633 let Inst{22-21} = opcod;
634 let Inst{20} = 0; // !load
635 let Inst{11-6} = 0b000000;
639 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
640 /// register and one whose operand is a register rotated by 8/16/24.
641 multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
642 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
643 opc, ".w\t$dst, $src",
644 [(set GPR:$dst, (opnode GPR:$src))]> {
645 let Inst{31-27} = 0b11111;
646 let Inst{26-23} = 0b0100;
647 let Inst{22-20} = opcod;
648 let Inst{19-16} = 0b1111; // Rn
649 let Inst{15-12} = 0b1111;
651 let Inst{5-4} = 0b00; // rotate
653 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
654 opc, ".w\t$dst, $src, ror $rot",
655 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]> {
656 let Inst{31-27} = 0b11111;
657 let Inst{26-23} = 0b0100;
658 let Inst{22-20} = opcod;
659 let Inst{19-16} = 0b1111; // Rn
660 let Inst{15-12} = 0b1111;
662 let Inst{5-4} = {?,?}; // rotate
666 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
667 multiclass T2I_unary_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
668 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
670 [(set GPR:$dst, (opnode GPR:$src))]>,
671 Requires<[HasT2ExtractPack]> {
672 let Inst{31-27} = 0b11111;
673 let Inst{26-23} = 0b0100;
674 let Inst{22-20} = opcod;
675 let Inst{19-16} = 0b1111; // Rn
676 let Inst{15-12} = 0b1111;
678 let Inst{5-4} = 0b00; // rotate
680 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
681 opc, "\t$dst, $src, ror $rot",
682 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
683 Requires<[HasT2ExtractPack]> {
684 let Inst{31-27} = 0b11111;
685 let Inst{26-23} = 0b0100;
686 let Inst{22-20} = opcod;
687 let Inst{19-16} = 0b1111; // Rn
688 let Inst{15-12} = 0b1111;
690 let Inst{5-4} = {?,?}; // rotate
694 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
696 multiclass T2I_unary_rrot_sxtb16<bits<3> opcod, string opc> {
697 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
698 opc, "\t$dst, $src", []> {
699 let Inst{31-27} = 0b11111;
700 let Inst{26-23} = 0b0100;
701 let Inst{22-20} = opcod;
702 let Inst{19-16} = 0b1111; // Rn
703 let Inst{15-12} = 0b1111;
705 let Inst{5-4} = 0b00; // rotate
707 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
708 opc, "\t$dst, $src, ror $rot", []> {
709 let Inst{31-27} = 0b11111;
710 let Inst{26-23} = 0b0100;
711 let Inst{22-20} = opcod;
712 let Inst{19-16} = 0b1111; // Rn
713 let Inst{15-12} = 0b1111;
715 let Inst{5-4} = {?,?}; // rotate
719 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
720 /// register and one whose operand is a register rotated by 8/16/24.
721 multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
722 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
723 opc, "\t$dst, $LHS, $RHS",
724 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
725 Requires<[HasT2ExtractPack]> {
726 let Inst{31-27} = 0b11111;
727 let Inst{26-23} = 0b0100;
728 let Inst{22-20} = opcod;
729 let Inst{15-12} = 0b1111;
731 let Inst{5-4} = 0b00; // rotate
733 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
734 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
735 [(set GPR:$dst, (opnode GPR:$LHS,
736 (rotr GPR:$RHS, rot_imm:$rot)))]>,
737 Requires<[HasT2ExtractPack]> {
738 let Inst{31-27} = 0b11111;
739 let Inst{26-23} = 0b0100;
740 let Inst{22-20} = opcod;
741 let Inst{15-12} = 0b1111;
743 let Inst{5-4} = {?,?}; // rotate
747 // DO variant - disassembly only, no pattern
749 multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> {
750 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
751 opc, "\t$dst, $LHS, $RHS", []> {
752 let Inst{31-27} = 0b11111;
753 let Inst{26-23} = 0b0100;
754 let Inst{22-20} = opcod;
755 let Inst{15-12} = 0b1111;
757 let Inst{5-4} = 0b00; // rotate
759 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
760 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> {
761 let Inst{31-27} = 0b11111;
762 let Inst{26-23} = 0b0100;
763 let Inst{22-20} = opcod;
764 let Inst{15-12} = 0b1111;
766 let Inst{5-4} = {?,?}; // rotate
770 //===----------------------------------------------------------------------===//
772 //===----------------------------------------------------------------------===//
774 //===----------------------------------------------------------------------===//
775 // Miscellaneous Instructions.
778 // LEApcrel - Load a pc-relative address into a register without offending the
780 let neverHasSideEffects = 1 in {
781 let isReMaterializable = 1 in
782 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
783 "adr$p.w\t$dst, #$label", []> {
784 let Inst{31-27} = 0b11110;
785 let Inst{25-24} = 0b10;
786 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
789 let Inst{19-16} = 0b1111; // Rn
792 } // neverHasSideEffects
793 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
794 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
795 "adr$p.w\t$dst, #${label}_${id}", []> {
796 let Inst{31-27} = 0b11110;
797 let Inst{25-24} = 0b10;
798 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
801 let Inst{19-16} = 0b1111; // Rn
805 // ADD r, sp, {so_imm|i12}
806 def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
807 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> {
808 let Inst{31-27} = 0b11110;
810 let Inst{24-21} = 0b1000;
811 let Inst{20} = ?; // The S bit.
812 let Inst{19-16} = 0b1101; // Rn = sp
815 def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
816 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> {
817 let Inst{31-27} = 0b11110;
819 let Inst{24-21} = 0b0000;
820 let Inst{20} = 0; // The S bit.
821 let Inst{19-16} = 0b1101; // Rn = sp
826 def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
827 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> {
828 let Inst{31-27} = 0b11101;
829 let Inst{26-25} = 0b01;
830 let Inst{24-21} = 0b1000;
831 let Inst{20} = ?; // The S bit.
832 let Inst{19-16} = 0b1101; // Rn = sp
836 // SUB r, sp, {so_imm|i12}
837 def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
838 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> {
839 let Inst{31-27} = 0b11110;
841 let Inst{24-21} = 0b1101;
842 let Inst{20} = ?; // The S bit.
843 let Inst{19-16} = 0b1101; // Rn = sp
846 def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
847 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> {
848 let Inst{31-27} = 0b11110;
850 let Inst{24-21} = 0b0101;
851 let Inst{20} = 0; // The S bit.
852 let Inst{19-16} = 0b1101; // Rn = sp
857 def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
859 "sub", "\t$dst, $sp, $rhs", []> {
860 let Inst{31-27} = 0b11101;
861 let Inst{26-25} = 0b01;
862 let Inst{24-21} = 0b1101;
863 let Inst{20} = ?; // The S bit.
864 let Inst{19-16} = 0b1101; // Rn = sp
868 // Signed and unsigned division on v7-M
869 def t2SDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
870 "sdiv", "\t$dst, $a, $b",
871 [(set GPR:$dst, (sdiv GPR:$a, GPR:$b))]>,
872 Requires<[HasDivide]> {
873 let Inst{31-27} = 0b11111;
874 let Inst{26-21} = 0b011100;
876 let Inst{15-12} = 0b1111;
877 let Inst{7-4} = 0b1111;
880 def t2UDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
881 "udiv", "\t$dst, $a, $b",
882 [(set GPR:$dst, (udiv GPR:$a, GPR:$b))]>,
883 Requires<[HasDivide]> {
884 let Inst{31-27} = 0b11111;
885 let Inst{26-21} = 0b011101;
887 let Inst{15-12} = 0b1111;
888 let Inst{7-4} = 0b1111;
891 // Pseudo instruction that will expand into a t2SUBrSPi + a copy.
892 let usesCustomInserter = 1 in { // Expanded after instruction selection.
893 def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
894 NoItinerary, "${:comment} sub.w\t$dst, $sp, $imm", []>;
895 def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
896 NoItinerary, "${:comment} subw\t$dst, $sp, $imm", []>;
897 def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
898 NoItinerary, "${:comment} sub\t$dst, $sp, $rhs", []>;
899 } // usesCustomInserter
902 //===----------------------------------------------------------------------===//
903 // Load / store Instructions.
907 let canFoldAsLoad = 1, isReMaterializable = 1 in
908 defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>;
910 // Loads with zero extension
911 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
912 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
914 // Loads with sign extension
915 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
916 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
918 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
920 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
921 (ins t2addrmode_imm8s4:$addr),
922 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
923 def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
924 (ins i32imm:$addr), IIC_iLoadi,
925 "ldrd", "\t$dst1, $addr", []> {
926 let Inst{19-16} = 0b1111; // Rn
928 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
930 // zextload i1 -> zextload i8
931 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
932 (t2LDRBi12 t2addrmode_imm12:$addr)>;
933 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
934 (t2LDRBi8 t2addrmode_imm8:$addr)>;
935 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
936 (t2LDRBs t2addrmode_so_reg:$addr)>;
937 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
938 (t2LDRBpci tconstpool:$addr)>;
940 // extload -> zextload
941 // FIXME: Reduce the number of patterns by legalizing extload to zextload
943 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
944 (t2LDRBi12 t2addrmode_imm12:$addr)>;
945 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
946 (t2LDRBi8 t2addrmode_imm8:$addr)>;
947 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
948 (t2LDRBs t2addrmode_so_reg:$addr)>;
949 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
950 (t2LDRBpci tconstpool:$addr)>;
952 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
953 (t2LDRBi12 t2addrmode_imm12:$addr)>;
954 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
955 (t2LDRBi8 t2addrmode_imm8:$addr)>;
956 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
957 (t2LDRBs t2addrmode_so_reg:$addr)>;
958 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
959 (t2LDRBpci tconstpool:$addr)>;
961 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
962 (t2LDRHi12 t2addrmode_imm12:$addr)>;
963 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
964 (t2LDRHi8 t2addrmode_imm8:$addr)>;
965 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
966 (t2LDRHs t2addrmode_so_reg:$addr)>;
967 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
968 (t2LDRHpci tconstpool:$addr)>;
971 let mayLoad = 1, neverHasSideEffects = 1 in {
972 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
973 (ins t2addrmode_imm8:$addr),
974 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
975 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
978 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb),
979 (ins GPR:$base, t2am_imm8_offset:$offset),
980 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
981 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
984 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
985 (ins t2addrmode_imm8:$addr),
986 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
987 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
989 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
990 (ins GPR:$base, t2am_imm8_offset:$offset),
991 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
992 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
995 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
996 (ins t2addrmode_imm8:$addr),
997 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
998 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
1000 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1001 (ins GPR:$base, t2am_imm8_offset:$offset),
1002 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1003 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
1006 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1007 (ins t2addrmode_imm8:$addr),
1008 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1009 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
1011 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1012 (ins GPR:$base, t2am_imm8_offset:$offset),
1013 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1014 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
1017 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1018 (ins t2addrmode_imm8:$addr),
1019 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1020 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
1022 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1023 (ins GPR:$base, t2am_imm8_offset:$offset),
1024 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1025 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
1027 } // mayLoad = 1, neverHasSideEffects = 1
1029 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1030 // for disassembly only.
1031 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1032 class T2IldT<bit signed, bits<2> type, string opc>
1033 : T2Ii8<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, opc,
1034 "\t$dst, $addr", []> {
1035 let Inst{31-27} = 0b11111;
1036 let Inst{26-25} = 0b00;
1037 let Inst{24} = signed;
1039 let Inst{22-21} = type;
1040 let Inst{20} = 1; // load
1042 let Inst{10-8} = 0b110; // PUW.
1045 def t2LDRT : T2IldT<0, 0b10, "ldrt">;
1046 def t2LDRBT : T2IldT<0, 0b00, "ldrbt">;
1047 def t2LDRHT : T2IldT<0, 0b01, "ldrht">;
1048 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt">;
1049 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht">;
1052 defm t2STR :T2I_st<0b10,"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
1053 defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1054 defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1057 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1058 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1059 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
1060 IIC_iStorer, "strd", "\t$src1, $addr", []>;
1063 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1064 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1065 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1066 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1068 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1070 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1071 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1072 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1073 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1075 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1077 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1078 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1079 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1080 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1082 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1084 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1085 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1086 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1087 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1089 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1091 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1092 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1093 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1094 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1096 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1098 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1099 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1100 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1101 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1103 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1105 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1107 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1108 class T2IstT<bits<2> type, string opc>
1109 : T2Ii8<(outs GPR:$src), (ins t2addrmode_imm8:$addr), IIC_iStorei, opc,
1110 "\t$src, $addr", []> {
1111 let Inst{31-27} = 0b11111;
1112 let Inst{26-25} = 0b00;
1113 let Inst{24} = 0; // not signed
1115 let Inst{22-21} = type;
1116 let Inst{20} = 0; // store
1118 let Inst{10-8} = 0b110; // PUW
1121 def t2STRT : T2IstT<0b10, "strt">;
1122 def t2STRBT : T2IstT<0b00, "strbt">;
1123 def t2STRHT : T2IstT<0b01, "strht">;
1125 // ldrd / strd pre / post variants
1126 // For disassembly only.
1128 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1129 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1130 "ldrd", "\t$dst1, $dst2, [$base, $imm]!", []>;
1132 def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1133 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1134 "ldrd", "\t$dst1, $dst2, [$base], $imm", []>;
1136 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
1137 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1138 NoItinerary, "strd", "\t$src1, $src2, [$base, $imm]!", []>;
1140 def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1141 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1142 NoItinerary, "strd", "\t$src1, $src2, [$base], $imm", []>;
1144 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1145 // data/instruction access. These are for disassembly only.
1147 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
1148 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
1149 multiclass T2Ipl<bit instr, bit write, string opc> {
1151 def i12 : T2I<(outs), (ins GPR:$base, i32imm:$imm), IIC_iLoadi, opc,
1152 "\t[$base, $imm]", []> {
1153 let Inst{31-25} = 0b1111100;
1154 let Inst{24} = instr;
1155 let Inst{23} = 1; // U = 1
1157 let Inst{21} = write;
1159 let Inst{15-12} = 0b1111;
1162 def i8 : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1163 "\t[$base, $imm]", []> {
1164 let Inst{31-25} = 0b1111100;
1165 let Inst{24} = instr;
1166 let Inst{23} = 0; // U = 0
1168 let Inst{21} = write;
1170 let Inst{15-12} = 0b1111;
1171 let Inst{11-8} = 0b1100;
1174 def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1175 "\t[pc, $imm]", []> {
1176 let Inst{31-25} = 0b1111100;
1177 let Inst{24} = instr;
1178 let Inst{23} = ?; // add = (U == 1)
1180 let Inst{21} = write;
1182 let Inst{19-16} = 0b1111; // Rn = 0b1111
1183 let Inst{15-12} = 0b1111;
1186 def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoadi, opc,
1187 "\t[$base, $a]", []> {
1188 let Inst{31-25} = 0b1111100;
1189 let Inst{24} = instr;
1190 let Inst{23} = 0; // add = TRUE for T1
1192 let Inst{21} = write;
1194 let Inst{15-12} = 0b1111;
1195 let Inst{11-6} = 0000000;
1196 let Inst{5-4} = 0b00; // no shift is applied
1199 def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoadi, opc,
1200 "\t[$base, $a, lsl $shamt]", []> {
1201 let Inst{31-25} = 0b1111100;
1202 let Inst{24} = instr;
1203 let Inst{23} = 0; // add = TRUE for T1
1205 let Inst{21} = write;
1207 let Inst{15-12} = 0b1111;
1208 let Inst{11-6} = 0000000;
1212 defm t2PLD : T2Ipl<0, 0, "pld">;
1213 defm t2PLDW : T2Ipl<0, 1, "pldw">;
1214 defm t2PLI : T2Ipl<1, 0, "pli">;
1216 //===----------------------------------------------------------------------===//
1217 // Load / store multiple Instructions.
1220 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1221 def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1222 reglist:$dsts, variable_ops), IIC_iLoadm,
1223 "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> {
1224 let Inst{31-27} = 0b11101;
1225 let Inst{26-25} = 0b00;
1226 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1228 let Inst{21} = 0; // The W bit.
1229 let Inst{20} = 1; // Load
1232 def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1233 reglist:$dsts, variable_ops), IIC_iLoadm,
1234 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
1235 "$addr.addr = $wb", []> {
1236 let Inst{31-27} = 0b11101;
1237 let Inst{26-25} = 0b00;
1238 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1240 let Inst{21} = 1; // The W bit.
1241 let Inst{20} = 1; // Load
1243 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1245 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1246 def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1247 reglist:$srcs, variable_ops), IIC_iStorem,
1248 "stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> {
1249 let Inst{31-27} = 0b11101;
1250 let Inst{26-25} = 0b00;
1251 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1253 let Inst{21} = 0; // The W bit.
1254 let Inst{20} = 0; // Store
1257 def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1258 reglist:$srcs, variable_ops),
1260 "stm${addr:submode}${p}${addr:wide}\t$addr!, $srcs",
1261 "$addr.addr = $wb", []> {
1262 let Inst{31-27} = 0b11101;
1263 let Inst{26-25} = 0b00;
1264 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1266 let Inst{21} = 1; // The W bit.
1267 let Inst{20} = 0; // Store
1269 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1271 //===----------------------------------------------------------------------===//
1272 // Move Instructions.
1275 let neverHasSideEffects = 1 in
1276 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
1277 "mov", ".w\t$dst, $src", []> {
1278 let Inst{31-27} = 0b11101;
1279 let Inst{26-25} = 0b01;
1280 let Inst{24-21} = 0b0010;
1281 let Inst{20} = ?; // The S bit.
1282 let Inst{19-16} = 0b1111; // Rn
1283 let Inst{14-12} = 0b000;
1284 let Inst{7-4} = 0b0000;
1287 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1288 let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
1289 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
1290 "mov", ".w\t$dst, $src",
1291 [(set GPR:$dst, t2_so_imm:$src)]> {
1292 let Inst{31-27} = 0b11110;
1294 let Inst{24-21} = 0b0010;
1295 let Inst{20} = ?; // The S bit.
1296 let Inst{19-16} = 0b1111; // Rn
1300 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1301 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1302 "movw", "\t$dst, $src",
1303 [(set GPR:$dst, imm0_65535:$src)]> {
1304 let Inst{31-27} = 0b11110;
1306 let Inst{24-21} = 0b0010;
1307 let Inst{20} = 0; // The S bit.
1311 let Constraints = "$src = $dst" in
1312 def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi,
1313 "movt", "\t$dst, $imm",
1315 (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]> {
1316 let Inst{31-27} = 0b11110;
1318 let Inst{24-21} = 0b0110;
1319 let Inst{20} = 0; // The S bit.
1323 def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>;
1325 //===----------------------------------------------------------------------===//
1326 // Extend Instructions.
1331 defm t2SXTB : T2I_unary_rrot<0b100, "sxtb",
1332 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1333 defm t2SXTH : T2I_unary_rrot<0b000, "sxth",
1334 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1335 defm t2SXTB16 : T2I_unary_rrot_sxtb16<0b010, "sxtb16">;
1337 defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab",
1338 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1339 defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah",
1340 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1341 defm t2SXTAB16 : T2I_bin_rrot_DO<0b010, "sxtab16">;
1343 // TODO: SXT(A){B|H}16 - done for disassembly only
1347 let AddedComplexity = 16 in {
1348 defm t2UXTB : T2I_unary_rrot<0b101, "uxtb",
1349 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1350 defm t2UXTH : T2I_unary_rrot<0b001, "uxth",
1351 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1352 defm t2UXTB16 : T2I_unary_rrot_uxtb16<0b011, "uxtb16",
1353 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1355 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1356 (t2UXTB16r_rot GPR:$Src, 24)>, Requires<[HasT2ExtractPack]>;
1357 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1358 (t2UXTB16r_rot GPR:$Src, 8)>, Requires<[HasT2ExtractPack]>;
1360 defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
1361 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1362 defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah",
1363 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1364 defm t2UXTAB16 : T2I_bin_rrot_DO<0b011, "uxtab16">;
1367 //===----------------------------------------------------------------------===//
1368 // Arithmetic Instructions.
1371 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1372 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1373 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1374 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1376 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1377 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1378 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1379 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1380 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1382 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1383 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1384 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1385 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1386 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1387 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1388 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1389 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1392 defm t2RSB : T2I_rbin_is <0b1110, "rsb",
1393 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1394 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1395 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1397 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1398 // The assume-no-carry-in form uses the negation of the input since add/sub
1399 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1400 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1402 // The AddedComplexity preferences the first variant over the others since
1403 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1404 let AddedComplexity = 1 in
1405 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1406 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1407 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1408 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1409 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1410 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1411 let AddedComplexity = 1 in
1412 def : T2Pat<(addc GPR:$src, imm0_255_neg:$imm),
1413 (t2SUBSri GPR:$src, imm0_255_neg:$imm)>;
1414 def : T2Pat<(addc GPR:$src, t2_so_imm_neg:$imm),
1415 (t2SUBSri GPR:$src, t2_so_imm_neg:$imm)>;
1416 // The with-carry-in form matches bitwise not instead of the negation.
1417 // Effectively, the inverse interpretation of the carry flag already accounts
1418 // for part of the negation.
1419 let AddedComplexity = 1 in
1420 def : T2Pat<(adde GPR:$src, imm0_255_not:$imm),
1421 (t2SBCSri GPR:$src, imm0_255_not:$imm)>;
1422 def : T2Pat<(adde GPR:$src, t2_so_imm_not:$imm),
1423 (t2SBCSri GPR:$src, t2_so_imm_not:$imm)>;
1425 // Select Bytes -- for disassembly only
1427 def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel",
1428 "\t$dst, $a, $b", []> {
1429 let Inst{31-27} = 0b11111;
1430 let Inst{26-24} = 0b010;
1432 let Inst{22-20} = 0b010;
1433 let Inst{15-12} = 0b1111;
1435 let Inst{6-4} = 0b000;
1438 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1439 // And Miscellaneous operations -- for disassembly only
1440 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc>
1441 : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, opc,
1442 "\t$dst, $a, $b", [/* For disassembly only; pattern left blank */]> {
1443 let Inst{31-27} = 0b11111;
1444 let Inst{26-23} = 0b0101;
1445 let Inst{22-20} = op22_20;
1446 let Inst{15-12} = 0b1111;
1447 let Inst{7-4} = op7_4;
1450 // Saturating add/subtract -- for disassembly only
1452 def t2QADD : T2I_pam<0b000, 0b1000, "qadd">;
1453 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1454 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1455 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1456 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1457 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1458 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1459 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub">;
1460 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1461 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1462 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1463 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1464 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1465 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1466 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1467 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1469 // Signed/Unsigned add/subtract -- for disassembly only
1471 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1472 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1473 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1474 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1475 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1476 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1477 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1478 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1479 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1480 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1481 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1482 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1484 // Signed/Unsigned halving add/subtract -- for disassembly only
1486 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1487 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1488 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1489 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1490 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1491 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1492 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1493 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1494 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1495 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1496 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1497 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1499 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1501 def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1502 NoItinerary, "usad8", "\t$dst, $a, $b", []> {
1503 let Inst{15-12} = 0b1111;
1505 def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst),
1506 (ins GPR:$a, GPR:$b, GPR:$acc), NoItinerary, "usada8",
1507 "\t$dst, $a, $b, $acc", []>;
1509 // Signed/Unsigned saturate -- for disassembly only
1511 def t2SSATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1512 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
1513 [/* For disassembly only; pattern left blank */]> {
1514 let Inst{31-27} = 0b11110;
1515 let Inst{25-22} = 0b1100;
1518 let Inst{21} = 0; // sh = '0'
1521 def t2SSATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1522 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt",
1523 [/* For disassembly only; pattern left blank */]> {
1524 let Inst{31-27} = 0b11110;
1525 let Inst{25-22} = 0b1100;
1528 let Inst{21} = 1; // sh = '1'
1531 def t2SSAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
1532 "ssat16", "\t$dst, $bit_pos, $a",
1533 [/* For disassembly only; pattern left blank */]> {
1534 let Inst{31-27} = 0b11110;
1535 let Inst{25-22} = 0b1100;
1538 let Inst{21} = 1; // sh = '1'
1539 let Inst{14-12} = 0b000; // imm3 = '000'
1540 let Inst{7-6} = 0b00; // imm2 = '00'
1543 def t2USATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1544 NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt",
1545 [/* For disassembly only; pattern left blank */]> {
1546 let Inst{31-27} = 0b11110;
1547 let Inst{25-22} = 0b1110;
1550 let Inst{21} = 0; // sh = '0'
1553 def t2USATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1554 NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt",
1555 [/* For disassembly only; pattern left blank */]> {
1556 let Inst{31-27} = 0b11110;
1557 let Inst{25-22} = 0b1110;
1560 let Inst{21} = 1; // sh = '1'
1563 def t2USAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
1564 "usat16", "\t$dst, $bit_pos, $a",
1565 [/* For disassembly only; pattern left blank */]> {
1566 let Inst{31-27} = 0b11110;
1567 let Inst{25-22} = 0b1110;
1570 let Inst{21} = 1; // sh = '1'
1571 let Inst{14-12} = 0b000; // imm3 = '000'
1572 let Inst{7-6} = 0b00; // imm2 = '00'
1575 //===----------------------------------------------------------------------===//
1576 // Shift and rotate Instructions.
1579 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1580 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1581 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1582 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1584 let Uses = [CPSR] in {
1585 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1586 "rrx", "\t$dst, $src",
1587 [(set GPR:$dst, (ARMrrx GPR:$src))]> {
1588 let Inst{31-27} = 0b11101;
1589 let Inst{26-25} = 0b01;
1590 let Inst{24-21} = 0b0010;
1591 let Inst{20} = ?; // The S bit.
1592 let Inst{19-16} = 0b1111; // Rn
1593 let Inst{14-12} = 0b000;
1594 let Inst{7-4} = 0b0011;
1598 let Defs = [CPSR] in {
1599 def t2MOVsrl_flag : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1600 "lsrs", ".w\t$dst, $src, #1",
1601 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]> {
1602 let Inst{31-27} = 0b11101;
1603 let Inst{26-25} = 0b01;
1604 let Inst{24-21} = 0b0010;
1605 let Inst{20} = 1; // The S bit.
1606 let Inst{19-16} = 0b1111; // Rn
1607 let Inst{5-4} = 0b01; // Shift type.
1608 // Shift amount = Inst{14-12:7-6} = 1.
1609 let Inst{14-12} = 0b000;
1610 let Inst{7-6} = 0b01;
1612 def t2MOVsra_flag : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1613 "asrs", ".w\t$dst, $src, #1",
1614 [(set GPR:$dst, (ARMsra_flag GPR:$src))]> {
1615 let Inst{31-27} = 0b11101;
1616 let Inst{26-25} = 0b01;
1617 let Inst{24-21} = 0b0010;
1618 let Inst{20} = 1; // The S bit.
1619 let Inst{19-16} = 0b1111; // Rn
1620 let Inst{5-4} = 0b10; // Shift type.
1621 // Shift amount = Inst{14-12:7-6} = 1.
1622 let Inst{14-12} = 0b000;
1623 let Inst{7-6} = 0b01;
1627 //===----------------------------------------------------------------------===//
1628 // Bitwise Instructions.
1631 defm t2AND : T2I_bin_w_irs<0b0000, "and",
1632 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1633 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1634 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1635 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1636 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1638 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1639 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1641 let Constraints = "$src = $dst" in
1642 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1643 IIC_iUNAsi, "bfc", "\t$dst, $imm",
1644 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]> {
1645 let Inst{31-27} = 0b11110;
1647 let Inst{24-20} = 0b10110;
1648 let Inst{19-16} = 0b1111; // Rn
1652 def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1653 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
1654 let Inst{31-27} = 0b11110;
1656 let Inst{24-20} = 0b10100;
1660 def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1661 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
1662 let Inst{31-27} = 0b11110;
1664 let Inst{24-20} = 0b11100;
1668 // A8.6.18 BFI - Bitfield insert (Encoding T1)
1669 // Added for disassembler with the pattern field purposely left blank.
1670 // FIXME: Utilize this instruction in codgen.
1671 def t2BFI : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1672 IIC_iALUi, "bfi", "\t$dst, $src, $lsb, $width", []> {
1673 let Inst{31-27} = 0b11110;
1675 let Inst{24-20} = 0b10110;
1679 defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS,
1682 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
1683 let AddedComplexity = 1 in
1684 defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
1687 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
1688 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
1690 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
1691 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
1692 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>,
1693 Requires<[IsThumb2]>;
1695 def : T2Pat<(t2_so_imm_not:$src),
1696 (t2MVNi t2_so_imm_not:$src)>;
1698 //===----------------------------------------------------------------------===//
1699 // Multiply Instructions.
1701 let isCommutable = 1 in
1702 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1703 "mul", "\t$dst, $a, $b",
1704 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]> {
1705 let Inst{31-27} = 0b11111;
1706 let Inst{26-23} = 0b0110;
1707 let Inst{22-20} = 0b000;
1708 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1709 let Inst{7-4} = 0b0000; // Multiply
1712 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1713 "mla", "\t$dst, $a, $b, $c",
1714 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]> {
1715 let Inst{31-27} = 0b11111;
1716 let Inst{26-23} = 0b0110;
1717 let Inst{22-20} = 0b000;
1718 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1719 let Inst{7-4} = 0b0000; // Multiply
1722 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1723 "mls", "\t$dst, $a, $b, $c",
1724 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]> {
1725 let Inst{31-27} = 0b11111;
1726 let Inst{26-23} = 0b0110;
1727 let Inst{22-20} = 0b000;
1728 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1729 let Inst{7-4} = 0b0001; // Multiply and Subtract
1732 // Extra precision multiplies with low / high results
1733 let neverHasSideEffects = 1 in {
1734 let isCommutable = 1 in {
1735 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1736 "smull", "\t$ldst, $hdst, $a, $b", []> {
1737 let Inst{31-27} = 0b11111;
1738 let Inst{26-23} = 0b0111;
1739 let Inst{22-20} = 0b000;
1740 let Inst{7-4} = 0b0000;
1743 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1744 "umull", "\t$ldst, $hdst, $a, $b", []> {
1745 let Inst{31-27} = 0b11111;
1746 let Inst{26-23} = 0b0111;
1747 let Inst{22-20} = 0b010;
1748 let Inst{7-4} = 0b0000;
1752 // Multiply + accumulate
1753 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1754 "smlal", "\t$ldst, $hdst, $a, $b", []>{
1755 let Inst{31-27} = 0b11111;
1756 let Inst{26-23} = 0b0111;
1757 let Inst{22-20} = 0b100;
1758 let Inst{7-4} = 0b0000;
1761 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1762 "umlal", "\t$ldst, $hdst, $a, $b", []>{
1763 let Inst{31-27} = 0b11111;
1764 let Inst{26-23} = 0b0111;
1765 let Inst{22-20} = 0b110;
1766 let Inst{7-4} = 0b0000;
1769 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1770 "umaal", "\t$ldst, $hdst, $a, $b", []>{
1771 let Inst{31-27} = 0b11111;
1772 let Inst{26-23} = 0b0111;
1773 let Inst{22-20} = 0b110;
1774 let Inst{7-4} = 0b0110;
1776 } // neverHasSideEffects
1778 // Rounding variants of the below included for disassembly only
1780 // Most significant word multiply
1781 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1782 "smmul", "\t$dst, $a, $b",
1783 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]> {
1784 let Inst{31-27} = 0b11111;
1785 let Inst{26-23} = 0b0110;
1786 let Inst{22-20} = 0b101;
1787 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1788 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1791 def t2SMMULR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1792 "smmulr", "\t$dst, $a, $b", []> {
1793 let Inst{31-27} = 0b11111;
1794 let Inst{26-23} = 0b0110;
1795 let Inst{22-20} = 0b101;
1796 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1797 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1800 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1801 "smmla", "\t$dst, $a, $b, $c",
1802 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]> {
1803 let Inst{31-27} = 0b11111;
1804 let Inst{26-23} = 0b0110;
1805 let Inst{22-20} = 0b101;
1806 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1807 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1810 def t2SMMLAR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1811 "smmlar", "\t$dst, $a, $b, $c", []> {
1812 let Inst{31-27} = 0b11111;
1813 let Inst{26-23} = 0b0110;
1814 let Inst{22-20} = 0b101;
1815 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1816 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1819 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1820 "smmls", "\t$dst, $a, $b, $c",
1821 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]> {
1822 let Inst{31-27} = 0b11111;
1823 let Inst{26-23} = 0b0110;
1824 let Inst{22-20} = 0b110;
1825 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1826 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1829 def t2SMMLSR : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1830 "smmlsr", "\t$dst, $a, $b, $c", []> {
1831 let Inst{31-27} = 0b11111;
1832 let Inst{26-23} = 0b0110;
1833 let Inst{22-20} = 0b110;
1834 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1835 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1838 multiclass T2I_smul<string opc, PatFrag opnode> {
1839 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1840 !strconcat(opc, "bb"), "\t$dst, $a, $b",
1841 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1842 (sext_inreg GPR:$b, i16)))]> {
1843 let Inst{31-27} = 0b11111;
1844 let Inst{26-23} = 0b0110;
1845 let Inst{22-20} = 0b001;
1846 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1847 let Inst{7-6} = 0b00;
1848 let Inst{5-4} = 0b00;
1851 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1852 !strconcat(opc, "bt"), "\t$dst, $a, $b",
1853 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1854 (sra GPR:$b, (i32 16))))]> {
1855 let Inst{31-27} = 0b11111;
1856 let Inst{26-23} = 0b0110;
1857 let Inst{22-20} = 0b001;
1858 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1859 let Inst{7-6} = 0b00;
1860 let Inst{5-4} = 0b01;
1863 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1864 !strconcat(opc, "tb"), "\t$dst, $a, $b",
1865 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1866 (sext_inreg GPR:$b, i16)))]> {
1867 let Inst{31-27} = 0b11111;
1868 let Inst{26-23} = 0b0110;
1869 let Inst{22-20} = 0b001;
1870 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1871 let Inst{7-6} = 0b00;
1872 let Inst{5-4} = 0b10;
1875 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1876 !strconcat(opc, "tt"), "\t$dst, $a, $b",
1877 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1878 (sra GPR:$b, (i32 16))))]> {
1879 let Inst{31-27} = 0b11111;
1880 let Inst{26-23} = 0b0110;
1881 let Inst{22-20} = 0b001;
1882 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1883 let Inst{7-6} = 0b00;
1884 let Inst{5-4} = 0b11;
1887 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1888 !strconcat(opc, "wb"), "\t$dst, $a, $b",
1889 [(set GPR:$dst, (sra (opnode GPR:$a,
1890 (sext_inreg GPR:$b, i16)), (i32 16)))]> {
1891 let Inst{31-27} = 0b11111;
1892 let Inst{26-23} = 0b0110;
1893 let Inst{22-20} = 0b011;
1894 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1895 let Inst{7-6} = 0b00;
1896 let Inst{5-4} = 0b00;
1899 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1900 !strconcat(opc, "wt"), "\t$dst, $a, $b",
1901 [(set GPR:$dst, (sra (opnode GPR:$a,
1902 (sra GPR:$b, (i32 16))), (i32 16)))]> {
1903 let Inst{31-27} = 0b11111;
1904 let Inst{26-23} = 0b0110;
1905 let Inst{22-20} = 0b011;
1906 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1907 let Inst{7-6} = 0b00;
1908 let Inst{5-4} = 0b01;
1913 multiclass T2I_smla<string opc, PatFrag opnode> {
1914 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1915 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1916 [(set GPR:$dst, (add GPR:$acc,
1917 (opnode (sext_inreg GPR:$a, i16),
1918 (sext_inreg GPR:$b, i16))))]> {
1919 let Inst{31-27} = 0b11111;
1920 let Inst{26-23} = 0b0110;
1921 let Inst{22-20} = 0b001;
1922 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1923 let Inst{7-6} = 0b00;
1924 let Inst{5-4} = 0b00;
1927 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1928 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1929 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1930 (sra GPR:$b, (i32 16)))))]> {
1931 let Inst{31-27} = 0b11111;
1932 let Inst{26-23} = 0b0110;
1933 let Inst{22-20} = 0b001;
1934 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1935 let Inst{7-6} = 0b00;
1936 let Inst{5-4} = 0b01;
1939 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1940 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1941 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1942 (sext_inreg GPR:$b, i16))))]> {
1943 let Inst{31-27} = 0b11111;
1944 let Inst{26-23} = 0b0110;
1945 let Inst{22-20} = 0b001;
1946 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1947 let Inst{7-6} = 0b00;
1948 let Inst{5-4} = 0b10;
1951 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1952 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1953 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1954 (sra GPR:$b, (i32 16)))))]> {
1955 let Inst{31-27} = 0b11111;
1956 let Inst{26-23} = 0b0110;
1957 let Inst{22-20} = 0b001;
1958 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1959 let Inst{7-6} = 0b00;
1960 let Inst{5-4} = 0b11;
1963 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1964 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1965 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1966 (sext_inreg GPR:$b, i16)), (i32 16))))]> {
1967 let Inst{31-27} = 0b11111;
1968 let Inst{26-23} = 0b0110;
1969 let Inst{22-20} = 0b011;
1970 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1971 let Inst{7-6} = 0b00;
1972 let Inst{5-4} = 0b00;
1975 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1976 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1977 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1978 (sra GPR:$b, (i32 16))), (i32 16))))]> {
1979 let Inst{31-27} = 0b11111;
1980 let Inst{26-23} = 0b0110;
1981 let Inst{22-20} = 0b011;
1982 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1983 let Inst{7-6} = 0b00;
1984 let Inst{5-4} = 0b01;
1988 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1989 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1991 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
1992 def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs GPR:$ldst,GPR:$hdst),
1993 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
1994 [/* For disassembly only; pattern left blank */]>;
1995 def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs GPR:$ldst,GPR:$hdst),
1996 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
1997 [/* For disassembly only; pattern left blank */]>;
1998 def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs GPR:$ldst,GPR:$hdst),
1999 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
2000 [/* For disassembly only; pattern left blank */]>;
2001 def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs GPR:$ldst,GPR:$hdst),
2002 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
2003 [/* For disassembly only; pattern left blank */]>;
2005 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2006 // These are for disassembly only.
2008 def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2009 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
2010 let Inst{15-12} = 0b1111;
2012 def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2013 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
2014 let Inst{15-12} = 0b1111;
2016 def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2017 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
2018 let Inst{15-12} = 0b1111;
2020 def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2021 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
2022 let Inst{15-12} = 0b1111;
2024 def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst),
2025 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlad",
2026 "\t$dst, $a, $b, $acc", []>;
2027 def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst),
2028 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smladx",
2029 "\t$dst, $a, $b, $acc", []>;
2030 def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst),
2031 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsd",
2032 "\t$dst, $a, $b, $acc", []>;
2033 def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst),
2034 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsdx",
2035 "\t$dst, $a, $b, $acc", []>;
2036 def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs GPR:$ldst,GPR:$hdst),
2037 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlald",
2038 "\t$ldst, $hdst, $a, $b", []>;
2039 def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs GPR:$ldst,GPR:$hdst),
2040 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaldx",
2041 "\t$ldst, $hdst, $a, $b", []>;
2042 def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs GPR:$ldst,GPR:$hdst),
2043 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsld",
2044 "\t$ldst, $hdst, $a, $b", []>;
2045 def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs GPR:$ldst,GPR:$hdst),
2046 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsldx",
2047 "\t$ldst, $hdst, $a, $b", []>;
2049 //===----------------------------------------------------------------------===//
2050 // Misc. Arithmetic Instructions.
2053 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2054 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2055 : T2I<oops, iops, itin, opc, asm, pattern> {
2056 let Inst{31-27} = 0b11111;
2057 let Inst{26-22} = 0b01010;
2058 let Inst{21-20} = op1;
2059 let Inst{15-12} = 0b1111;
2060 let Inst{7-6} = 0b10;
2061 let Inst{5-4} = op2;
2064 def t2CLZ : T2I_misc<0b11, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2065 "clz", "\t$dst, $src", [(set GPR:$dst, (ctlz GPR:$src))]>;
2067 def t2RBIT : T2I_misc<0b01, 0b10, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2068 "rbit", "\t$dst, $src",
2069 [(set GPR:$dst, (ARMrbit GPR:$src))]>;
2071 def t2REV : T2I_misc<0b01, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2072 "rev", ".w\t$dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>;
2074 def t2REV16 : T2I_misc<0b01, 0b01, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2075 "rev16", ".w\t$dst, $src",
2077 (or (and (srl GPR:$src, (i32 8)), 0xFF),
2078 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
2079 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
2080 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
2082 def t2REVSH : T2I_misc<0b01, 0b11, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2083 "revsh", ".w\t$dst, $src",
2086 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
2087 (shl GPR:$src, (i32 8))), i16))]>;
2089 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
2090 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt",
2091 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
2092 (and (shl GPR:$src2, (i32 imm:$shamt)),
2094 Requires<[HasT2ExtractPack]> {
2095 let Inst{31-27} = 0b11101;
2096 let Inst{26-25} = 0b01;
2097 let Inst{24-20} = 0b01100;
2098 let Inst{5} = 0; // BT form
2102 // Alternate cases for PKHBT where identities eliminate some nodes.
2103 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
2104 (t2PKHBT GPR:$src1, GPR:$src2, 0)>,
2105 Requires<[HasT2ExtractPack]>;
2106 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
2107 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>,
2108 Requires<[HasT2ExtractPack]>;
2110 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
2111 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
2112 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
2113 (and (sra GPR:$src2, imm16_31:$shamt),
2115 Requires<[HasT2ExtractPack]> {
2116 let Inst{31-27} = 0b11101;
2117 let Inst{26-25} = 0b01;
2118 let Inst{24-20} = 0b01100;
2119 let Inst{5} = 1; // TB form
2123 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2124 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2125 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
2126 (t2PKHTB GPR:$src1, GPR:$src2, 16)>,
2127 Requires<[HasT2ExtractPack]>;
2128 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
2129 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
2130 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>,
2131 Requires<[HasT2ExtractPack]>;
2133 //===----------------------------------------------------------------------===//
2134 // Comparison Instructions...
2137 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2138 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2139 defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
2140 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2142 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2143 // Compare-to-zero still works out, just not the relationals
2144 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2145 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2146 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2147 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2149 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2150 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2152 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2153 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2155 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2156 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
2157 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2158 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
2160 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
2161 // Short range conditional branch. Looks awesome for loops. Need to figure
2162 // out how to use this one.
2165 // Conditional moves
2166 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2167 // a two-value operand where a dag node expects two operands. :(
2168 let neverHasSideEffects = 1 in {
2169 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr,
2170 "mov", ".w\t$dst, $true",
2171 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
2172 RegConstraint<"$false = $dst"> {
2173 let Inst{31-27} = 0b11101;
2174 let Inst{26-25} = 0b01;
2175 let Inst{24-21} = 0b0010;
2176 let Inst{20} = 0; // The S bit.
2177 let Inst{19-16} = 0b1111; // Rn
2178 let Inst{14-12} = 0b000;
2179 let Inst{7-4} = 0b0000;
2182 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
2183 IIC_iCMOVi, "mov", ".w\t$dst, $true",
2184 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
2185 RegConstraint<"$false = $dst"> {
2186 let Inst{31-27} = 0b11110;
2188 let Inst{24-21} = 0b0010;
2189 let Inst{20} = 0; // The S bit.
2190 let Inst{19-16} = 0b1111; // Rn
2194 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2195 string opc, string asm, list<dag> pattern>
2196 : T2I<oops, iops, itin, opc, asm, pattern> {
2197 let Inst{31-27} = 0b11101;
2198 let Inst{26-25} = 0b01;
2199 let Inst{24-21} = 0b0010;
2200 let Inst{20} = 0; // The S bit.
2201 let Inst{19-16} = 0b1111; // Rn
2202 let Inst{5-4} = opcod; // Shift type.
2204 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs GPR:$dst),
2205 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2206 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
2207 RegConstraint<"$false = $dst">;
2208 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs GPR:$dst),
2209 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2210 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
2211 RegConstraint<"$false = $dst">;
2212 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs GPR:$dst),
2213 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2214 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
2215 RegConstraint<"$false = $dst">;
2216 def t2MOVCCror : T2I_movcc_sh<0b11, (outs GPR:$dst),
2217 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2218 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
2219 RegConstraint<"$false = $dst">;
2220 } // neverHasSideEffects
2222 //===----------------------------------------------------------------------===//
2223 // Atomic operations intrinsics
2226 // memory barriers protect the atomic sequences
2227 let hasSideEffects = 1 in {
2228 def t2Int_MemBarrierV7 : AInoP<(outs), (ins),
2229 ThumbFrm, NoItinerary,
2231 [(ARMMemBarrierV7)]>,
2232 Requires<[IsThumb2]> {
2233 let Inst{31-4} = 0xF3BF8F5;
2234 // FIXME: add support for options other than a full system DMB
2235 let Inst{3-0} = 0b1111;
2238 def t2Int_SyncBarrierV7 : AInoP<(outs), (ins),
2239 ThumbFrm, NoItinerary,
2241 [(ARMSyncBarrierV7)]>,
2242 Requires<[IsThumb2]> {
2243 let Inst{31-4} = 0xF3BF8F4;
2244 // FIXME: add support for options other than a full system DSB
2245 let Inst{3-0} = 0b1111;
2249 // Helper class for multiclass T2MemB -- for disassembly only
2250 class T2I_memb<string opc, string asm>
2251 : T2I<(outs), (ins), NoItinerary, opc, asm,
2252 [/* For disassembly only; pattern left blank */]>,
2253 Requires<[IsThumb2, HasV7]> {
2254 let Inst{31-20} = 0xf3b;
2255 let Inst{15-14} = 0b10;
2259 multiclass T2MemB<bits<4> op7_4, string opc> {
2261 def st : T2I_memb<opc, "\tst"> {
2262 let Inst{7-4} = op7_4;
2263 let Inst{3-0} = 0b1110;
2266 def ish : T2I_memb<opc, "\tish"> {
2267 let Inst{7-4} = op7_4;
2268 let Inst{3-0} = 0b1011;
2271 def ishst : T2I_memb<opc, "\tishst"> {
2272 let Inst{7-4} = op7_4;
2273 let Inst{3-0} = 0b1010;
2276 def nsh : T2I_memb<opc, "\tnsh"> {
2277 let Inst{7-4} = op7_4;
2278 let Inst{3-0} = 0b0111;
2281 def nshst : T2I_memb<opc, "\tnshst"> {
2282 let Inst{7-4} = op7_4;
2283 let Inst{3-0} = 0b0110;
2286 def osh : T2I_memb<opc, "\tosh"> {
2287 let Inst{7-4} = op7_4;
2288 let Inst{3-0} = 0b0011;
2291 def oshst : T2I_memb<opc, "\toshst"> {
2292 let Inst{7-4} = op7_4;
2293 let Inst{3-0} = 0b0010;
2297 // These DMB variants are for disassembly only.
2298 defm t2DMB : T2MemB<0b0101, "dmb">;
2300 // These DSB variants are for disassembly only.
2301 defm t2DSB : T2MemB<0b0100, "dsb">;
2303 // ISB has only full system option -- for disassembly only
2304 def t2ISBsy : T2I_memb<"isb", ""> {
2305 let Inst{7-4} = 0b0110;
2306 let Inst{3-0} = 0b1111;
2309 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2310 InstrItinClass itin, string opc, string asm, string cstr,
2311 list<dag> pattern, bits<4> rt2 = 0b1111>
2312 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2313 let Inst{31-27} = 0b11101;
2314 let Inst{26-20} = 0b0001101;
2315 let Inst{11-8} = rt2;
2316 let Inst{7-6} = 0b01;
2317 let Inst{5-4} = opcod;
2318 let Inst{3-0} = 0b1111;
2320 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2321 InstrItinClass itin, string opc, string asm, string cstr,
2322 list<dag> pattern, bits<4> rt2 = 0b1111>
2323 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2324 let Inst{31-27} = 0b11101;
2325 let Inst{26-20} = 0b0001100;
2326 let Inst{11-8} = rt2;
2327 let Inst{7-6} = 0b01;
2328 let Inst{5-4} = opcod;
2331 let mayLoad = 1 in {
2332 def t2LDREXB : T2I_ldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2333 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
2335 def t2LDREXH : T2I_ldrex<0b01, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2336 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
2338 def t2LDREX : Thumb2I<(outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2339 Size4Bytes, NoItinerary,
2340 "ldrex", "\t$dest, [$ptr]", "",
2342 let Inst{31-27} = 0b11101;
2343 let Inst{26-20} = 0b0000101;
2344 let Inst{11-8} = 0b1111;
2345 let Inst{7-0} = 0b00000000; // imm8 = 0
2347 def t2LDREXD : T2I_ldrex<0b11, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
2348 AddrModeNone, Size4Bytes, NoItinerary,
2349 "ldrexd", "\t$dest, $dest2, [$ptr]", "",
2353 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2354 def t2STREXB : T2I_strex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2355 AddrModeNone, Size4Bytes, NoItinerary,
2356 "strexb", "\t$success, $src, [$ptr]", "", []>;
2357 def t2STREXH : T2I_strex<0b01, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2358 AddrModeNone, Size4Bytes, NoItinerary,
2359 "strexh", "\t$success, $src, [$ptr]", "", []>;
2360 def t2STREX : Thumb2I<(outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2361 AddrModeNone, Size4Bytes, NoItinerary,
2362 "strex", "\t$success, $src, [$ptr]", "",
2364 let Inst{31-27} = 0b11101;
2365 let Inst{26-20} = 0b0000100;
2366 let Inst{7-0} = 0b00000000; // imm8 = 0
2368 def t2STREXD : T2I_strex<0b11, (outs GPR:$success),
2369 (ins GPR:$src, GPR:$src2, GPR:$ptr),
2370 AddrModeNone, Size4Bytes, NoItinerary,
2371 "strexd", "\t$success, $src, $src2, [$ptr]", "", [],
2375 // Clear-Exclusive is for disassembly only.
2376 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2377 [/* For disassembly only; pattern left blank */]>,
2378 Requires<[IsARM, HasV7]> {
2379 let Inst{31-20} = 0xf3b;
2380 let Inst{15-14} = 0b10;
2382 let Inst{7-4} = 0b0010;
2385 //===----------------------------------------------------------------------===//
2389 // __aeabi_read_tp preserves the registers r1-r3.
2391 Defs = [R0, R12, LR, CPSR] in {
2392 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2393 "bl\t__aeabi_read_tp",
2394 [(set R0, ARMthread_pointer)]> {
2395 let Inst{31-27} = 0b11110;
2396 let Inst{15-14} = 0b11;
2401 //===----------------------------------------------------------------------===//
2402 // SJLJ Exception handling intrinsics
2403 // eh_sjlj_setjmp() is an instruction sequence to store the return
2404 // address and save #0 in R0 for the non-longjmp case.
2405 // Since by its nature we may be coming from some other function to get
2406 // here, and we're using the stack frame for the containing function to
2407 // save/restore registers, we can't keep anything live in regs across
2408 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2409 // when we get here from a longjmp(). We force everthing out of registers
2410 // except for our own input by listing the relevant registers in Defs. By
2411 // doing so, we also cause the prologue/epilogue code to actively preserve
2412 // all of the callee-saved resgisters, which is exactly what we want.
2413 // $val is a scratch register for our use.
2415 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2416 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2417 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2418 D31 ], hasSideEffects = 1, isBarrier = 1 in {
2419 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
2420 AddrModeNone, SizeSpecial, NoItinerary,
2421 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
2422 "adds\t$val, #7\n\t"
2423 "str\t$val, [$src, #4]\n\t"
2426 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
2428 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>,
2429 Requires<[IsThumb2, HasVFP2]>;
2433 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2434 hasSideEffects = 1, isBarrier = 1 in {
2435 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
2436 AddrModeNone, SizeSpecial, NoItinerary,
2437 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
2438 "adds\t$val, #7\n\t"
2439 "str\t$val, [$src, #4]\n\t"
2442 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
2444 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>,
2445 Requires<[IsThumb2, NoVFP]>;
2449 //===----------------------------------------------------------------------===//
2450 // Control-Flow Instructions
2453 // FIXME: remove when we have a way to marking a MI with these properties.
2454 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2456 // FIXME: Should pc be an implicit operand like PICADD, etc?
2457 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2458 hasExtraDefRegAllocReq = 1 in
2459 def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
2460 reglist:$dsts, variable_ops), IIC_Br,
2461 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
2462 "$addr.addr = $wb", []> {
2463 let Inst{31-27} = 0b11101;
2464 let Inst{26-25} = 0b00;
2465 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
2467 let Inst{21} = 1; // The W bit.
2468 let Inst{20} = 1; // Load
2471 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2472 let isPredicable = 1 in
2473 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2475 [(br bb:$target)]> {
2476 let Inst{31-27} = 0b11110;
2477 let Inst{15-14} = 0b10;
2481 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2484 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
2485 IIC_Br, "mov\tpc, $target\n$jt",
2486 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
2487 let Inst{31-27} = 0b11101;
2488 let Inst{26-20} = 0b0100100;
2489 let Inst{19-16} = 0b1111;
2490 let Inst{14-12} = 0b000;
2491 let Inst{11-8} = 0b1111; // Rd = pc
2492 let Inst{7-4} = 0b0000;
2495 // FIXME: Add a non-pc based case that can be predicated.
2498 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2499 IIC_Br, "tbb\t$index\n$jt", []> {
2500 let Inst{31-27} = 0b11101;
2501 let Inst{26-20} = 0b0001101;
2502 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2503 let Inst{15-8} = 0b11110000;
2504 let Inst{7-4} = 0b0000; // B form
2509 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2510 IIC_Br, "tbh\t$index\n$jt", []> {
2511 let Inst{31-27} = 0b11101;
2512 let Inst{26-20} = 0b0001101;
2513 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2514 let Inst{15-8} = 0b11110000;
2515 let Inst{7-4} = 0b0001; // H form
2518 // Generic versions of the above two instructions, for disassembly only
2520 def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2521 "tbb", "\t[$a, $b]", []>{
2522 let Inst{31-27} = 0b11101;
2523 let Inst{26-20} = 0b0001101;
2524 let Inst{15-8} = 0b11110000;
2525 let Inst{7-4} = 0b0000; // B form
2528 def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2529 "tbh", "\t[$a, $b, lsl #1]", []> {
2530 let Inst{31-27} = 0b11101;
2531 let Inst{26-20} = 0b0001101;
2532 let Inst{15-8} = 0b11110000;
2533 let Inst{7-4} = 0b0001; // H form
2535 } // isNotDuplicable, isIndirectBranch
2537 } // isBranch, isTerminator, isBarrier
2539 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2540 // a two-value operand where a dag node expects two operands. :(
2541 let isBranch = 1, isTerminator = 1 in
2542 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
2544 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
2545 let Inst{31-27} = 0b11110;
2546 let Inst{15-14} = 0b10;
2552 let Defs = [ITSTATE] in
2553 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
2554 AddrModeNone, Size2Bytes, IIC_iALUx,
2555 "it$mask\t$cc", "", []> {
2556 // 16-bit instruction.
2557 let Inst{31-16} = 0x0000;
2558 let Inst{15-8} = 0b10111111;
2561 // Branch and Exchange Jazelle -- for disassembly only
2563 def t2BXJ : T2I<(outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2564 [/* For disassembly only; pattern left blank */]> {
2565 let Inst{31-27} = 0b11110;
2567 let Inst{25-20} = 0b111100;
2568 let Inst{15-14} = 0b10;
2572 // Change Processor State is a system instruction -- for disassembly only.
2573 // The singleton $opt operand contains the following information:
2574 // opt{4-0} = mode from Inst{4-0}
2575 // opt{5} = changemode from Inst{17}
2576 // opt{8-6} = AIF from Inst{8-6}
2577 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
2578 def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
2579 [/* For disassembly only; pattern left blank */]> {
2580 let Inst{31-27} = 0b11110;
2582 let Inst{25-20} = 0b111010;
2583 let Inst{15-14} = 0b10;
2587 // A6.3.4 Branches and miscellaneous control
2588 // Table A6-14 Change Processor State, and hint instructions
2589 // Helper class for disassembly only.
2590 class T2I_hint<bits<8> op7_0, string opc, string asm>
2591 : T2I<(outs), (ins), NoItinerary, opc, asm,
2592 [/* For disassembly only; pattern left blank */]> {
2593 let Inst{31-20} = 0xf3a;
2594 let Inst{15-14} = 0b10;
2596 let Inst{10-8} = 0b000;
2597 let Inst{7-0} = op7_0;
2600 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
2601 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
2602 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
2603 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
2604 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
2606 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
2607 [/* For disassembly only; pattern left blank */]> {
2608 let Inst{31-20} = 0xf3a;
2609 let Inst{15-14} = 0b10;
2611 let Inst{10-8} = 0b000;
2612 let Inst{7-4} = 0b1111;
2615 // Secure Monitor Call is a system instruction -- for disassembly only
2616 // Option = Inst{19-16}
2617 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
2618 [/* For disassembly only; pattern left blank */]> {
2619 let Inst{31-27} = 0b11110;
2620 let Inst{26-20} = 0b1111111;
2621 let Inst{15-12} = 0b1000;
2624 // Store Return State is a system instruction -- for disassembly only
2625 def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
2626 [/* For disassembly only; pattern left blank */]> {
2627 let Inst{31-27} = 0b11101;
2628 let Inst{26-20} = 0b0000010; // W = 1
2631 def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
2632 [/* For disassembly only; pattern left blank */]> {
2633 let Inst{31-27} = 0b11101;
2634 let Inst{26-20} = 0b0000000; // W = 0
2637 def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
2638 [/* For disassembly only; pattern left blank */]> {
2639 let Inst{31-27} = 0b11101;
2640 let Inst{26-20} = 0b0011010; // W = 1
2643 def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
2644 [/* For disassembly only; pattern left blank */]> {
2645 let Inst{31-27} = 0b11101;
2646 let Inst{26-20} = 0b0011000; // W = 0
2649 // Return From Exception is a system instruction -- for disassembly only
2650 def t2RFEDBW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfedb", "\t$base!",
2651 [/* For disassembly only; pattern left blank */]> {
2652 let Inst{31-27} = 0b11101;
2653 let Inst{26-20} = 0b0000011; // W = 1
2656 def t2RFEDB : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeab", "\t$base",
2657 [/* For disassembly only; pattern left blank */]> {
2658 let Inst{31-27} = 0b11101;
2659 let Inst{26-20} = 0b0000001; // W = 0
2662 def t2RFEIAW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base!",
2663 [/* For disassembly only; pattern left blank */]> {
2664 let Inst{31-27} = 0b11101;
2665 let Inst{26-20} = 0b0011011; // W = 1
2668 def t2RFEIA : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base",
2669 [/* For disassembly only; pattern left blank */]> {
2670 let Inst{31-27} = 0b11101;
2671 let Inst{26-20} = 0b0011001; // W = 0
2674 //===----------------------------------------------------------------------===//
2675 // Non-Instruction Patterns
2678 // Two piece so_imms.
2679 def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS),
2680 (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2681 (t2_so_imm2part_2 imm:$RHS))>;
2682 def : T2Pat<(xor GPR:$LHS, t2_so_imm2part:$RHS),
2683 (t2EORri (t2EORri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2684 (t2_so_imm2part_2 imm:$RHS))>;
2685 def : T2Pat<(add GPR:$LHS, t2_so_imm2part:$RHS),
2686 (t2ADDri (t2ADDri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2687 (t2_so_imm2part_2 imm:$RHS))>;
2688 def : T2Pat<(add GPR:$LHS, t2_so_neg_imm2part:$RHS),
2689 (t2SUBri (t2SUBri GPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
2690 (t2_so_neg_imm2part_2 imm:$RHS))>;
2692 // 32-bit immediate using movw + movt.
2693 // This is a single pseudo instruction to make it re-materializable. Remove
2694 // when we can do generalized remat.
2695 let isReMaterializable = 1 in
2696 def t2MOVi32imm : T2Ix2<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
2697 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2698 [(set GPR:$dst, (i32 imm:$src))]>;
2700 // ConstantPool, GlobalAddress, and JumpTable
2701 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
2702 Requires<[IsThumb2, DontUseMovt]>;
2703 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
2704 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
2705 Requires<[IsThumb2, UseMovt]>;
2707 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2708 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
2710 // Pseudo instruction that combines ldr from constpool and add pc. This should
2711 // be expanded into two instructions late to allow if-conversion and
2713 let canFoldAsLoad = 1, isReMaterializable = 1 in
2714 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
2716 "${:comment} ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
2717 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
2719 Requires<[IsThumb2]>;
2721 //===----------------------------------------------------------------------===//
2722 // Move between special register and ARM core register -- for disassembly only
2726 def t2MRS : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
2727 [/* For disassembly only; pattern left blank */]> {
2728 let Inst{31-27} = 0b11110;
2730 let Inst{25-21} = 0b11111;
2731 let Inst{20} = 0; // The R bit.
2732 let Inst{15-14} = 0b10;
2737 def t2MRSsys : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
2738 [/* For disassembly only; pattern left blank */]> {
2739 let Inst{31-27} = 0b11110;
2741 let Inst{25-21} = 0b11111;
2742 let Inst{20} = 1; // The R bit.
2743 let Inst{15-14} = 0b10;
2748 def t2MSR : T2I<(outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, "msr",
2749 "\tcpsr$mask, $src",
2750 [/* For disassembly only; pattern left blank */]> {
2751 let Inst{31-27} = 0b11110;
2753 let Inst{25-21} = 0b11100;
2754 let Inst{20} = 0; // The R bit.
2755 let Inst{15-14} = 0b10;
2760 def t2MSRsys : T2I<(outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, "msr",
2761 "\tspsr$mask, $src",
2762 [/* For disassembly only; pattern left blank */]> {
2763 let Inst{31-27} = 0b11110;
2765 let Inst{25-21} = 0b11100;
2766 let Inst{20} = 1; // The R bit.
2767 let Inst{15-14} = 0b10;