1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops rGPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant
53 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>,
56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
59 // t2_so_imm_not - Match an immediate that is a complement
61 def t2_so_imm_not : Operand<i32>,
63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
64 }], t2_so_imm_not_XFORM>;
66 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
67 def t2_so_imm_neg : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
70 }], t2_so_imm_neg_XFORM>;
72 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
73 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
74 // to get the first/second pieces.
75 def t2_so_imm2part : Operand<i32>,
77 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
81 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
82 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
83 return CurDAG->getTargetConstant(V, MVT::i32);
86 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
87 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
88 return CurDAG->getTargetConstant(V, MVT::i32);
91 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
92 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
96 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
97 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
98 return CurDAG->getTargetConstant(V, MVT::i32);
101 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
102 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
103 return CurDAG->getTargetConstant(V, MVT::i32);
106 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
107 def imm1_31 : PatLeaf<(i32 imm), [{
108 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
111 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
112 def imm0_4095 : Operand<i32>,
113 PatLeaf<(i32 imm), [{
114 return (uint32_t)N->getZExtValue() < 4096;
117 def imm0_4095_neg : PatLeaf<(i32 imm), [{
118 return (uint32_t)(-N->getZExtValue()) < 4096;
121 def imm0_255_neg : PatLeaf<(i32 imm), [{
122 return (uint32_t)(-N->getZExtValue()) < 255;
125 def imm0_255_not : PatLeaf<(i32 imm), [{
126 return (uint32_t)(~N->getZExtValue()) < 255;
129 // Define Thumb2 specific addressing modes.
131 // t2addrmode_imm12 := reg + imm12
132 def t2addrmode_imm12 : Operand<i32>,
133 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
134 let PrintMethod = "printT2AddrModeImm12Operand";
135 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
138 // t2addrmode_imm8 := reg +/- imm8
139 def t2addrmode_imm8 : Operand<i32>,
140 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
141 let PrintMethod = "printT2AddrModeImm8Operand";
142 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
145 def t2am_imm8_offset : Operand<i32>,
146 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
147 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
150 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
151 def t2addrmode_imm8s4 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
153 let PrintMethod = "printT2AddrModeImm8s4Operand";
154 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
157 def t2am_imm8s4_offset : Operand<i32> {
158 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
161 // t2addrmode_so_reg := reg + (reg << imm2)
162 def t2addrmode_so_reg : Operand<i32>,
163 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
164 let PrintMethod = "printT2AddrModeSoRegOperand";
165 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
169 //===----------------------------------------------------------------------===//
170 // Multiclass helpers...
173 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
174 /// unary operation that produces a value. These are predicable and can be
175 /// changed to modify CPSR.
176 multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode,
177 bit Cheap = 0, bit ReMat = 0> {
179 def i : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
181 [(set rGPR:$dst, (opnode t2_so_imm:$src))]> {
182 let isAsCheapAsAMove = Cheap;
183 let isReMaterializable = ReMat;
184 let Inst{31-27} = 0b11110;
186 let Inst{24-21} = opcod;
187 let Inst{20} = ?; // The S bit.
188 let Inst{19-16} = 0b1111; // Rn
192 def r : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVr,
193 opc, ".w\t$dst, $src",
194 [(set rGPR:$dst, (opnode rGPR:$src))]> {
195 let Inst{31-27} = 0b11101;
196 let Inst{26-25} = 0b01;
197 let Inst{24-21} = opcod;
198 let Inst{20} = ?; // The S bit.
199 let Inst{19-16} = 0b1111; // Rn
200 let Inst{14-12} = 0b000; // imm3
201 let Inst{7-6} = 0b00; // imm2
202 let Inst{5-4} = 0b00; // type
205 def s : T2sI<(outs rGPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
206 opc, ".w\t$dst, $src",
207 [(set rGPR:$dst, (opnode t2_so_reg:$src))]> {
208 let Inst{31-27} = 0b11101;
209 let Inst{26-25} = 0b01;
210 let Inst{24-21} = opcod;
211 let Inst{20} = ?; // The S bit.
212 let Inst{19-16} = 0b1111; // Rn
216 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
217 /// binary operation that produces a value. These are predicable and can be
218 /// changed to modify CPSR.
219 multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
220 bit Commutable = 0, string wide =""> {
222 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
223 opc, "\t$dst, $lhs, $rhs",
224 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> {
225 let Inst{31-27} = 0b11110;
227 let Inst{24-21} = opcod;
228 let Inst{20} = ?; // The S bit.
232 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
233 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
234 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
235 let isCommutable = Commutable;
236 let Inst{31-27} = 0b11101;
237 let Inst{26-25} = 0b01;
238 let Inst{24-21} = opcod;
239 let Inst{20} = ?; // The S bit.
240 let Inst{14-12} = 0b000; // imm3
241 let Inst{7-6} = 0b00; // imm2
242 let Inst{5-4} = 0b00; // type
245 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
246 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
247 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> {
248 let Inst{31-27} = 0b11101;
249 let Inst{26-25} = 0b01;
250 let Inst{24-21} = opcod;
251 let Inst{20} = ?; // The S bit.
255 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
256 // the ".w" prefix to indicate that they are wide.
257 multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
258 bit Commutable = 0> :
259 T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
261 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
262 /// reversed. It doesn't define the 'rr' form since it's handled by its
263 /// T2I_bin_irs counterpart.
264 multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> {
266 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
267 opc, ".w\t$dst, $rhs, $lhs",
268 [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> {
269 let Inst{31-27} = 0b11110;
271 let Inst{24-21} = opcod;
272 let Inst{20} = ?; // The S bit.
276 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
277 opc, "\t$dst, $rhs, $lhs",
278 [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> {
279 let Inst{31-27} = 0b11101;
280 let Inst{26-25} = 0b01;
281 let Inst{24-21} = opcod;
282 let Inst{20} = ?; // The S bit.
286 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
287 /// instruction modifies the CPSR register.
288 let Defs = [CPSR] in {
289 multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
290 bit Commutable = 0> {
292 def ri : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
293 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
294 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
295 let Inst{31-27} = 0b11110;
297 let Inst{24-21} = opcod;
298 let Inst{20} = 1; // The S bit.
302 def rr : T2I<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr,
303 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
304 [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> {
305 let isCommutable = Commutable;
306 let Inst{31-27} = 0b11101;
307 let Inst{26-25} = 0b01;
308 let Inst{24-21} = opcod;
309 let Inst{20} = 1; // The S bit.
310 let Inst{14-12} = 0b000; // imm3
311 let Inst{7-6} = 0b00; // imm2
312 let Inst{5-4} = 0b00; // type
315 def rs : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
316 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
317 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
318 let Inst{31-27} = 0b11101;
319 let Inst{26-25} = 0b01;
320 let Inst{24-21} = opcod;
321 let Inst{20} = 1; // The S bit.
326 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
327 /// patterns for a binary operation that produces a value.
328 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
329 bit Commutable = 0> {
331 def ri : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
332 opc, ".w\t$dst, $lhs, $rhs",
333 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
334 let Inst{31-27} = 0b11110;
337 let Inst{23-21} = op23_21;
338 let Inst{20} = 0; // The S bit.
342 def ri12 : T2I<(outs rGPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
343 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
344 [(set rGPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
345 let Inst{31-27} = 0b11110;
348 let Inst{23-21} = op23_21;
349 let Inst{20} = 0; // The S bit.
353 def rr : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr,
354 opc, ".w\t$dst, $lhs, $rhs",
355 [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> {
356 let isCommutable = Commutable;
357 let Inst{31-27} = 0b11101;
358 let Inst{26-25} = 0b01;
360 let Inst{23-21} = op23_21;
361 let Inst{20} = 0; // The S bit.
362 let Inst{14-12} = 0b000; // imm3
363 let Inst{7-6} = 0b00; // imm2
364 let Inst{5-4} = 0b00; // type
367 def rs : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
368 opc, ".w\t$dst, $lhs, $rhs",
369 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
370 let Inst{31-27} = 0b11101;
371 let Inst{26-25} = 0b01;
373 let Inst{23-21} = op23_21;
374 let Inst{20} = 0; // The S bit.
378 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
379 /// for a binary operation that produces a value and use the carry
380 /// bit. It's not predicable.
381 let Uses = [CPSR] in {
382 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
383 bit Commutable = 0> {
385 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
386 opc, "\t$dst, $lhs, $rhs",
387 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>,
388 Requires<[IsThumb2]> {
389 let Inst{31-27} = 0b11110;
391 let Inst{24-21} = opcod;
392 let Inst{20} = 0; // The S bit.
396 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
397 opc, ".w\t$dst, $lhs, $rhs",
398 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>,
399 Requires<[IsThumb2]> {
400 let isCommutable = Commutable;
401 let Inst{31-27} = 0b11101;
402 let Inst{26-25} = 0b01;
403 let Inst{24-21} = opcod;
404 let Inst{20} = 0; // The S bit.
405 let Inst{14-12} = 0b000; // imm3
406 let Inst{7-6} = 0b00; // imm2
407 let Inst{5-4} = 0b00; // type
410 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
411 opc, ".w\t$dst, $lhs, $rhs",
412 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>,
413 Requires<[IsThumb2]> {
414 let Inst{31-27} = 0b11101;
415 let Inst{26-25} = 0b01;
416 let Inst{24-21} = opcod;
417 let Inst{20} = 0; // The S bit.
421 // Carry setting variants
422 let Defs = [CPSR] in {
423 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
424 bit Commutable = 0> {
426 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
427 opc, "\t$dst, $lhs, $rhs",
428 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>,
429 Requires<[IsThumb2]> {
430 let Inst{31-27} = 0b11110;
432 let Inst{24-21} = opcod;
433 let Inst{20} = 1; // The S bit.
437 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
438 opc, ".w\t$dst, $lhs, $rhs",
439 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>,
440 Requires<[IsThumb2]> {
441 let isCommutable = Commutable;
442 let Inst{31-27} = 0b11101;
443 let Inst{26-25} = 0b01;
444 let Inst{24-21} = opcod;
445 let Inst{20} = 1; // The S bit.
446 let Inst{14-12} = 0b000; // imm3
447 let Inst{7-6} = 0b00; // imm2
448 let Inst{5-4} = 0b00; // type
451 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
452 opc, ".w\t$dst, $lhs, $rhs",
453 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>,
454 Requires<[IsThumb2]> {
455 let Inst{31-27} = 0b11101;
456 let Inst{26-25} = 0b01;
457 let Inst{24-21} = opcod;
458 let Inst{20} = 1; // The S bit.
464 /// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
465 let Defs = [CPSR] in {
466 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
468 def ri : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
469 !strconcat(opc, "s"), ".w\t$dst, $rhs, $lhs",
470 [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> {
471 let Inst{31-27} = 0b11110;
473 let Inst{24-21} = opcod;
474 let Inst{20} = 1; // The S bit.
478 def rs : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
479 !strconcat(opc, "s"), "\t$dst, $rhs, $lhs",
480 [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> {
481 let Inst{31-27} = 0b11101;
482 let Inst{26-25} = 0b01;
483 let Inst{24-21} = opcod;
484 let Inst{20} = 1; // The S bit.
489 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
490 // rotate operation that produces a value.
491 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
493 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
494 opc, ".w\t$dst, $lhs, $rhs",
495 [(set rGPR:$dst, (opnode rGPR:$lhs, imm1_31:$rhs))]> {
496 let Inst{31-27} = 0b11101;
497 let Inst{26-21} = 0b010010;
498 let Inst{19-16} = 0b1111; // Rn
499 let Inst{5-4} = opcod;
502 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iMOVsr,
503 opc, ".w\t$dst, $lhs, $rhs",
504 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
505 let Inst{31-27} = 0b11111;
506 let Inst{26-23} = 0b0100;
507 let Inst{22-21} = opcod;
508 let Inst{15-12} = 0b1111;
509 let Inst{7-4} = 0b0000;
513 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
514 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
515 /// a explicit result, only implicitly set CPSR.
516 let Defs = [CPSR] in {
517 multiclass T2I_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
519 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
520 opc, ".w\t$lhs, $rhs",
521 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> {
522 let Inst{31-27} = 0b11110;
524 let Inst{24-21} = opcod;
525 let Inst{20} = 1; // The S bit.
527 let Inst{11-8} = 0b1111; // Rd
530 def rr : T2I<(outs), (ins GPR:$lhs, rGPR:$rhs), IIC_iCMPr,
531 opc, ".w\t$lhs, $rhs",
532 [(opnode GPR:$lhs, rGPR:$rhs)]> {
533 let Inst{31-27} = 0b11101;
534 let Inst{26-25} = 0b01;
535 let Inst{24-21} = opcod;
536 let Inst{20} = 1; // The S bit.
537 let Inst{14-12} = 0b000; // imm3
538 let Inst{11-8} = 0b1111; // Rd
539 let Inst{7-6} = 0b00; // imm2
540 let Inst{5-4} = 0b00; // type
543 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
544 opc, ".w\t$lhs, $rhs",
545 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> {
546 let Inst{31-27} = 0b11101;
547 let Inst{26-25} = 0b01;
548 let Inst{24-21} = opcod;
549 let Inst{20} = 1; // The S bit.
550 let Inst{11-8} = 0b1111; // Rd
555 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
556 multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> {
557 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
558 opc, ".w\t$dst, $addr",
559 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
560 let Inst{31-27} = 0b11111;
561 let Inst{26-25} = 0b00;
562 let Inst{24} = signed;
564 let Inst{22-21} = opcod;
565 let Inst{20} = 1; // load
567 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
568 opc, "\t$dst, $addr",
569 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
570 let Inst{31-27} = 0b11111;
571 let Inst{26-25} = 0b00;
572 let Inst{24} = signed;
574 let Inst{22-21} = opcod;
575 let Inst{20} = 1; // load
577 // Offset: index==TRUE, wback==FALSE
578 let Inst{10} = 1; // The P bit.
579 let Inst{8} = 0; // The W bit.
581 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
582 opc, ".w\t$dst, $addr",
583 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
584 let Inst{31-27} = 0b11111;
585 let Inst{26-25} = 0b00;
586 let Inst{24} = signed;
588 let Inst{22-21} = opcod;
589 let Inst{20} = 1; // load
590 let Inst{11-6} = 0b000000;
592 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
593 opc, ".w\t$dst, $addr",
594 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
595 let isReMaterializable = 1;
596 let Inst{31-27} = 0b11111;
597 let Inst{26-25} = 0b00;
598 let Inst{24} = signed;
599 let Inst{23} = ?; // add = (U == '1')
600 let Inst{22-21} = opcod;
601 let Inst{20} = 1; // load
602 let Inst{19-16} = 0b1111; // Rn
606 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
607 multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> {
608 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
609 opc, ".w\t$src, $addr",
610 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
611 let Inst{31-27} = 0b11111;
612 let Inst{26-23} = 0b0001;
613 let Inst{22-21} = opcod;
614 let Inst{20} = 0; // !load
616 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
617 opc, "\t$src, $addr",
618 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
619 let Inst{31-27} = 0b11111;
620 let Inst{26-23} = 0b0000;
621 let Inst{22-21} = opcod;
622 let Inst{20} = 0; // !load
624 // Offset: index==TRUE, wback==FALSE
625 let Inst{10} = 1; // The P bit.
626 let Inst{8} = 0; // The W bit.
628 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
629 opc, ".w\t$src, $addr",
630 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
631 let Inst{31-27} = 0b11111;
632 let Inst{26-23} = 0b0000;
633 let Inst{22-21} = opcod;
634 let Inst{20} = 0; // !load
635 let Inst{11-6} = 0b000000;
639 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
640 /// register and one whose operand is a register rotated by 8/16/24.
641 multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
642 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
643 opc, ".w\t$dst, $src",
644 [(set rGPR:$dst, (opnode rGPR:$src))]> {
645 let Inst{31-27} = 0b11111;
646 let Inst{26-23} = 0b0100;
647 let Inst{22-20} = opcod;
648 let Inst{19-16} = 0b1111; // Rn
649 let Inst{15-12} = 0b1111;
651 let Inst{5-4} = 0b00; // rotate
653 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
654 opc, ".w\t$dst, $src, ror $rot",
655 [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]> {
656 let Inst{31-27} = 0b11111;
657 let Inst{26-23} = 0b0100;
658 let Inst{22-20} = opcod;
659 let Inst{19-16} = 0b1111; // Rn
660 let Inst{15-12} = 0b1111;
662 let Inst{5-4} = {?,?}; // rotate
666 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
667 multiclass T2I_unary_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
668 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
670 [(set rGPR:$dst, (opnode rGPR:$src))]>,
671 Requires<[HasT2ExtractPack]> {
672 let Inst{31-27} = 0b11111;
673 let Inst{26-23} = 0b0100;
674 let Inst{22-20} = opcod;
675 let Inst{19-16} = 0b1111; // Rn
676 let Inst{15-12} = 0b1111;
678 let Inst{5-4} = 0b00; // rotate
680 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
681 opc, "\t$dst, $src, ror $rot",
682 [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]>,
683 Requires<[HasT2ExtractPack]> {
684 let Inst{31-27} = 0b11111;
685 let Inst{26-23} = 0b0100;
686 let Inst{22-20} = opcod;
687 let Inst{19-16} = 0b1111; // Rn
688 let Inst{15-12} = 0b1111;
690 let Inst{5-4} = {?,?}; // rotate
694 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
696 multiclass T2I_unary_rrot_sxtb16<bits<3> opcod, string opc> {
697 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
698 opc, "\t$dst, $src", []> {
699 let Inst{31-27} = 0b11111;
700 let Inst{26-23} = 0b0100;
701 let Inst{22-20} = opcod;
702 let Inst{19-16} = 0b1111; // Rn
703 let Inst{15-12} = 0b1111;
705 let Inst{5-4} = 0b00; // rotate
707 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
708 opc, "\t$dst, $src, ror $rot", []> {
709 let Inst{31-27} = 0b11111;
710 let Inst{26-23} = 0b0100;
711 let Inst{22-20} = opcod;
712 let Inst{19-16} = 0b1111; // Rn
713 let Inst{15-12} = 0b1111;
715 let Inst{5-4} = {?,?}; // rotate
719 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
720 /// register and one whose operand is a register rotated by 8/16/24.
721 multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
722 def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iALUr,
723 opc, "\t$dst, $LHS, $RHS",
724 [(set rGPR:$dst, (opnode rGPR:$LHS, rGPR:$RHS))]>,
725 Requires<[HasT2ExtractPack]> {
726 let Inst{31-27} = 0b11111;
727 let Inst{26-23} = 0b0100;
728 let Inst{22-20} = opcod;
729 let Inst{15-12} = 0b1111;
731 let Inst{5-4} = 0b00; // rotate
733 def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot),
734 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
735 [(set rGPR:$dst, (opnode rGPR:$LHS,
736 (rotr rGPR:$RHS, rot_imm:$rot)))]>,
737 Requires<[HasT2ExtractPack]> {
738 let Inst{31-27} = 0b11111;
739 let Inst{26-23} = 0b0100;
740 let Inst{22-20} = opcod;
741 let Inst{15-12} = 0b1111;
743 let Inst{5-4} = {?,?}; // rotate
747 // DO variant - disassembly only, no pattern
749 multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> {
750 def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iALUr,
751 opc, "\t$dst, $LHS, $RHS", []> {
752 let Inst{31-27} = 0b11111;
753 let Inst{26-23} = 0b0100;
754 let Inst{22-20} = opcod;
755 let Inst{15-12} = 0b1111;
757 let Inst{5-4} = 0b00; // rotate
759 def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot),
760 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> {
761 let Inst{31-27} = 0b11111;
762 let Inst{26-23} = 0b0100;
763 let Inst{22-20} = opcod;
764 let Inst{15-12} = 0b1111;
766 let Inst{5-4} = {?,?}; // rotate
770 //===----------------------------------------------------------------------===//
772 //===----------------------------------------------------------------------===//
774 //===----------------------------------------------------------------------===//
775 // Miscellaneous Instructions.
778 // LEApcrel - Load a pc-relative address into a register without offending the
780 let neverHasSideEffects = 1 in {
781 let isReMaterializable = 1 in
782 def t2LEApcrel : T2XI<(outs rGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
783 "adr${p}.w\t$dst, #$label", []> {
784 let Inst{31-27} = 0b11110;
785 let Inst{25-24} = 0b10;
786 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
789 let Inst{19-16} = 0b1111; // Rn
792 } // neverHasSideEffects
793 def t2LEApcrelJT : T2XI<(outs rGPR:$dst),
794 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
795 "adr${p}.w\t$dst, #${label}_${id}", []> {
796 let Inst{31-27} = 0b11110;
797 let Inst{25-24} = 0b10;
798 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
801 let Inst{19-16} = 0b1111; // Rn
805 // ADD r, sp, {so_imm|i12}
806 def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
807 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> {
808 let Inst{31-27} = 0b11110;
810 let Inst{24-21} = 0b1000;
811 let Inst{20} = ?; // The S bit.
812 let Inst{19-16} = 0b1101; // Rn = sp
815 def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
816 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> {
817 let Inst{31-27} = 0b11110;
819 let Inst{24-21} = 0b0000;
820 let Inst{20} = 0; // The S bit.
821 let Inst{19-16} = 0b1101; // Rn = sp
826 def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
827 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> {
828 let Inst{31-27} = 0b11101;
829 let Inst{26-25} = 0b01;
830 let Inst{24-21} = 0b1000;
831 let Inst{20} = ?; // The S bit.
832 let Inst{19-16} = 0b1101; // Rn = sp
836 // SUB r, sp, {so_imm|i12}
837 def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
838 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> {
839 let Inst{31-27} = 0b11110;
841 let Inst{24-21} = 0b1101;
842 let Inst{20} = ?; // The S bit.
843 let Inst{19-16} = 0b1101; // Rn = sp
846 def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
847 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> {
848 let Inst{31-27} = 0b11110;
850 let Inst{24-21} = 0b0101;
851 let Inst{20} = 0; // The S bit.
852 let Inst{19-16} = 0b1101; // Rn = sp
857 def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
859 "sub", "\t$dst, $sp, $rhs", []> {
860 let Inst{31-27} = 0b11101;
861 let Inst{26-25} = 0b01;
862 let Inst{24-21} = 0b1101;
863 let Inst{20} = ?; // The S bit.
864 let Inst{19-16} = 0b1101; // Rn = sp
868 // Signed and unsigned division on v7-M
869 def t2SDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
870 "sdiv", "\t$dst, $a, $b",
871 [(set rGPR:$dst, (sdiv rGPR:$a, rGPR:$b))]>,
872 Requires<[HasDivide]> {
873 let Inst{31-27} = 0b11111;
874 let Inst{26-21} = 0b011100;
876 let Inst{15-12} = 0b1111;
877 let Inst{7-4} = 0b1111;
880 def t2UDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
881 "udiv", "\t$dst, $a, $b",
882 [(set rGPR:$dst, (udiv rGPR:$a, rGPR:$b))]>,
883 Requires<[HasDivide]> {
884 let Inst{31-27} = 0b11111;
885 let Inst{26-21} = 0b011101;
887 let Inst{15-12} = 0b1111;
888 let Inst{7-4} = 0b1111;
891 //===----------------------------------------------------------------------===//
892 // Load / store Instructions.
896 let canFoldAsLoad = 1, isReMaterializable = 1 in
897 defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>;
899 // Loads with zero extension
900 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
901 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
903 // Loads with sign extension
904 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
905 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
907 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
909 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
910 (ins t2addrmode_imm8s4:$addr),
911 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
912 def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
913 (ins i32imm:$addr), IIC_iLoadi,
914 "ldrd", "\t$dst1, $addr", []> {
915 let Inst{19-16} = 0b1111; // Rn
917 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
919 // zextload i1 -> zextload i8
920 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
921 (t2LDRBi12 t2addrmode_imm12:$addr)>;
922 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
923 (t2LDRBi8 t2addrmode_imm8:$addr)>;
924 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
925 (t2LDRBs t2addrmode_so_reg:$addr)>;
926 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
927 (t2LDRBpci tconstpool:$addr)>;
929 // extload -> zextload
930 // FIXME: Reduce the number of patterns by legalizing extload to zextload
932 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
933 (t2LDRBi12 t2addrmode_imm12:$addr)>;
934 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
935 (t2LDRBi8 t2addrmode_imm8:$addr)>;
936 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
937 (t2LDRBs t2addrmode_so_reg:$addr)>;
938 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
939 (t2LDRBpci tconstpool:$addr)>;
941 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
942 (t2LDRBi12 t2addrmode_imm12:$addr)>;
943 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
944 (t2LDRBi8 t2addrmode_imm8:$addr)>;
945 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
946 (t2LDRBs t2addrmode_so_reg:$addr)>;
947 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
948 (t2LDRBpci tconstpool:$addr)>;
950 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
951 (t2LDRHi12 t2addrmode_imm12:$addr)>;
952 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
953 (t2LDRHi8 t2addrmode_imm8:$addr)>;
954 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
955 (t2LDRHs t2addrmode_so_reg:$addr)>;
956 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
957 (t2LDRHpci tconstpool:$addr)>;
959 // FIXME: The destination register of the loads and stores can't be PC, but
960 // can be SP. We need another regclass (similar to rGPR) to represent
961 // that. Not a pressing issue since these are selected manually,
965 let mayLoad = 1, neverHasSideEffects = 1 in {
966 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
967 (ins t2addrmode_imm8:$addr),
968 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
969 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
972 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb),
973 (ins GPR:$base, t2am_imm8_offset:$offset),
974 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
975 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
978 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
979 (ins t2addrmode_imm8:$addr),
980 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
981 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
983 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
984 (ins GPR:$base, t2am_imm8_offset:$offset),
985 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
986 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
989 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
990 (ins t2addrmode_imm8:$addr),
991 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
992 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
994 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
995 (ins GPR:$base, t2am_imm8_offset:$offset),
996 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
997 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
1000 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1001 (ins t2addrmode_imm8:$addr),
1002 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1003 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
1005 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1006 (ins GPR:$base, t2am_imm8_offset:$offset),
1007 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1008 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
1011 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1012 (ins t2addrmode_imm8:$addr),
1013 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1014 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
1016 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1017 (ins GPR:$base, t2am_imm8_offset:$offset),
1018 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1019 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
1021 } // mayLoad = 1, neverHasSideEffects = 1
1023 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1024 // for disassembly only.
1025 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1026 class T2IldT<bit signed, bits<2> type, string opc>
1027 : T2Ii8<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, opc,
1028 "\t$dst, $addr", []> {
1029 let Inst{31-27} = 0b11111;
1030 let Inst{26-25} = 0b00;
1031 let Inst{24} = signed;
1033 let Inst{22-21} = type;
1034 let Inst{20} = 1; // load
1036 let Inst{10-8} = 0b110; // PUW.
1039 def t2LDRT : T2IldT<0, 0b10, "ldrt">;
1040 def t2LDRBT : T2IldT<0, 0b00, "ldrbt">;
1041 def t2LDRHT : T2IldT<0, 0b01, "ldrht">;
1042 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt">;
1043 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht">;
1046 defm t2STR :T2I_st<0b10,"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
1047 defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1048 defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1051 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1052 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1053 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
1054 IIC_iStorer, "strd", "\t$src1, $addr", []>;
1057 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1058 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1059 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1060 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1062 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1064 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1065 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1066 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1067 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1069 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1071 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1072 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1073 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1074 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1076 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1078 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1079 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1080 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1081 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1083 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1085 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1086 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1087 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1088 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1090 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1092 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1093 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1094 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1095 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1097 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1099 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1101 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1102 class T2IstT<bits<2> type, string opc>
1103 : T2Ii8<(outs GPR:$src), (ins t2addrmode_imm8:$addr), IIC_iStorei, opc,
1104 "\t$src, $addr", []> {
1105 let Inst{31-27} = 0b11111;
1106 let Inst{26-25} = 0b00;
1107 let Inst{24} = 0; // not signed
1109 let Inst{22-21} = type;
1110 let Inst{20} = 0; // store
1112 let Inst{10-8} = 0b110; // PUW
1115 def t2STRT : T2IstT<0b10, "strt">;
1116 def t2STRBT : T2IstT<0b00, "strbt">;
1117 def t2STRHT : T2IstT<0b01, "strht">;
1119 // ldrd / strd pre / post variants
1120 // For disassembly only.
1122 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1123 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1124 "ldrd", "\t$dst1, $dst2, [$base, $imm]!", []>;
1126 def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1127 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1128 "ldrd", "\t$dst1, $dst2, [$base], $imm", []>;
1130 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
1131 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1132 NoItinerary, "strd", "\t$src1, $src2, [$base, $imm]!", []>;
1134 def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1135 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1136 NoItinerary, "strd", "\t$src1, $src2, [$base], $imm", []>;
1138 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1139 // data/instruction access. These are for disassembly only.
1141 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
1142 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
1143 multiclass T2Ipl<bit instr, bit write, string opc> {
1145 def i12 : T2I<(outs), (ins GPR:$base, i32imm:$imm), IIC_iLoadi, opc,
1146 "\t[$base, $imm]", []> {
1147 let Inst{31-25} = 0b1111100;
1148 let Inst{24} = instr;
1149 let Inst{23} = 1; // U = 1
1151 let Inst{21} = write;
1153 let Inst{15-12} = 0b1111;
1156 def i8 : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1157 "\t[$base, $imm]", []> {
1158 let Inst{31-25} = 0b1111100;
1159 let Inst{24} = instr;
1160 let Inst{23} = 0; // U = 0
1162 let Inst{21} = write;
1164 let Inst{15-12} = 0b1111;
1165 let Inst{11-8} = 0b1100;
1168 def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1169 "\t[pc, $imm]", []> {
1170 let Inst{31-25} = 0b1111100;
1171 let Inst{24} = instr;
1172 let Inst{23} = ?; // add = (U == 1)
1174 let Inst{21} = write;
1176 let Inst{19-16} = 0b1111; // Rn = 0b1111
1177 let Inst{15-12} = 0b1111;
1180 def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoadi, opc,
1181 "\t[$base, $a]", []> {
1182 let Inst{31-25} = 0b1111100;
1183 let Inst{24} = instr;
1184 let Inst{23} = 0; // add = TRUE for T1
1186 let Inst{21} = write;
1188 let Inst{15-12} = 0b1111;
1189 let Inst{11-6} = 0000000;
1190 let Inst{5-4} = 0b00; // no shift is applied
1193 def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoadi, opc,
1194 "\t[$base, $a, lsl $shamt]", []> {
1195 let Inst{31-25} = 0b1111100;
1196 let Inst{24} = instr;
1197 let Inst{23} = 0; // add = TRUE for T1
1199 let Inst{21} = write;
1201 let Inst{15-12} = 0b1111;
1202 let Inst{11-6} = 0000000;
1206 defm t2PLD : T2Ipl<0, 0, "pld">;
1207 defm t2PLDW : T2Ipl<0, 1, "pldw">;
1208 defm t2PLI : T2Ipl<1, 0, "pli">;
1210 //===----------------------------------------------------------------------===//
1211 // Load / store multiple Instructions.
1214 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1215 def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1216 reglist:$dsts, variable_ops), IIC_iLoadm,
1217 "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> {
1218 let Inst{31-27} = 0b11101;
1219 let Inst{26-25} = 0b00;
1220 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1222 let Inst{21} = 0; // The W bit.
1223 let Inst{20} = 1; // Load
1226 def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1227 reglist:$dsts, variable_ops), IIC_iLoadm,
1228 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
1229 "$addr.addr = $wb", []> {
1230 let Inst{31-27} = 0b11101;
1231 let Inst{26-25} = 0b00;
1232 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1234 let Inst{21} = 1; // The W bit.
1235 let Inst{20} = 1; // Load
1237 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1239 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1240 def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1241 reglist:$srcs, variable_ops), IIC_iStorem,
1242 "stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> {
1243 let Inst{31-27} = 0b11101;
1244 let Inst{26-25} = 0b00;
1245 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1247 let Inst{21} = 0; // The W bit.
1248 let Inst{20} = 0; // Store
1251 def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1252 reglist:$srcs, variable_ops),
1254 "stm${addr:submode}${p}${addr:wide}\t$addr!, $srcs",
1255 "$addr.addr = $wb", []> {
1256 let Inst{31-27} = 0b11101;
1257 let Inst{26-25} = 0b00;
1258 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1260 let Inst{21} = 1; // The W bit.
1261 let Inst{20} = 0; // Store
1263 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1265 //===----------------------------------------------------------------------===//
1266 // Move Instructions.
1269 let neverHasSideEffects = 1 in
1270 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
1271 "mov", ".w\t$dst, $src", []> {
1272 let Inst{31-27} = 0b11101;
1273 let Inst{26-25} = 0b01;
1274 let Inst{24-21} = 0b0010;
1275 let Inst{20} = ?; // The S bit.
1276 let Inst{19-16} = 0b1111; // Rn
1277 let Inst{14-12} = 0b000;
1278 let Inst{7-4} = 0b0000;
1281 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1282 let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
1283 def t2MOVi : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
1284 "mov", ".w\t$dst, $src",
1285 [(set rGPR:$dst, t2_so_imm:$src)]> {
1286 let Inst{31-27} = 0b11110;
1288 let Inst{24-21} = 0b0010;
1289 let Inst{20} = ?; // The S bit.
1290 let Inst{19-16} = 0b1111; // Rn
1294 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1295 def t2MOVi16 : T2I<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1296 "movw", "\t$dst, $src",
1297 [(set rGPR:$dst, imm0_65535:$src)]> {
1298 let Inst{31-27} = 0b11110;
1300 let Inst{24-21} = 0b0010;
1301 let Inst{20} = 0; // The S bit.
1305 let Constraints = "$src = $dst" in
1306 def t2MOVTi16 : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$imm), IIC_iMOVi,
1307 "movt", "\t$dst, $imm",
1309 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1310 let Inst{31-27} = 0b11110;
1312 let Inst{24-21} = 0b0110;
1313 let Inst{20} = 0; // The S bit.
1317 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1319 //===----------------------------------------------------------------------===//
1320 // Extend Instructions.
1325 defm t2SXTB : T2I_unary_rrot<0b100, "sxtb",
1326 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1327 defm t2SXTH : T2I_unary_rrot<0b000, "sxth",
1328 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1329 defm t2SXTB16 : T2I_unary_rrot_sxtb16<0b010, "sxtb16">;
1331 defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab",
1332 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1333 defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah",
1334 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1335 defm t2SXTAB16 : T2I_bin_rrot_DO<0b010, "sxtab16">;
1337 // TODO: SXT(A){B|H}16 - done for disassembly only
1341 let AddedComplexity = 16 in {
1342 defm t2UXTB : T2I_unary_rrot<0b101, "uxtb",
1343 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1344 defm t2UXTH : T2I_unary_rrot<0b001, "uxth",
1345 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1346 defm t2UXTB16 : T2I_unary_rrot_uxtb16<0b011, "uxtb16",
1347 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1349 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1350 // The transformation should probably be done as a combiner action
1351 // instead so we can include a check for masking back in the upper
1352 // eight bits of the source into the lower eight bits of the result.
1353 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1354 // (t2UXTB16r_rot rGPR:$Src, 24)>, Requires<[HasT2ExtractPack]>;
1355 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1356 (t2UXTB16r_rot rGPR:$Src, 8)>, Requires<[HasT2ExtractPack]>;
1358 defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
1359 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1360 defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah",
1361 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1362 defm t2UXTAB16 : T2I_bin_rrot_DO<0b011, "uxtab16">;
1365 //===----------------------------------------------------------------------===//
1366 // Arithmetic Instructions.
1369 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1370 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1371 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1372 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1374 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1375 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1376 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1377 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1378 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1380 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1381 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1382 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1383 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1384 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1385 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1386 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1387 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1390 defm t2RSB : T2I_rbin_is <0b1110, "rsb",
1391 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1392 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1393 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1395 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1396 // The assume-no-carry-in form uses the negation of the input since add/sub
1397 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1398 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1400 // The AddedComplexity preferences the first variant over the others since
1401 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1402 let AddedComplexity = 1 in
1403 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1404 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1405 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1406 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1407 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1408 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1409 let AddedComplexity = 1 in
1410 def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm),
1411 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1412 def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm),
1413 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1414 // The with-carry-in form matches bitwise not instead of the negation.
1415 // Effectively, the inverse interpretation of the carry flag already accounts
1416 // for part of the negation.
1417 let AddedComplexity = 1 in
1418 def : T2Pat<(adde rGPR:$src, imm0_255_not:$imm),
1419 (t2SBCSri rGPR:$src, imm0_255_not:$imm)>;
1420 def : T2Pat<(adde rGPR:$src, t2_so_imm_not:$imm),
1421 (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>;
1423 // Select Bytes -- for disassembly only
1425 def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel",
1426 "\t$dst, $a, $b", []> {
1427 let Inst{31-27} = 0b11111;
1428 let Inst{26-24} = 0b010;
1430 let Inst{22-20} = 0b010;
1431 let Inst{15-12} = 0b1111;
1433 let Inst{6-4} = 0b000;
1436 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1437 // And Miscellaneous operations -- for disassembly only
1438 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1439 list<dag> pat = [/* For disassembly only; pattern left blank */]>
1440 : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), NoItinerary, opc,
1441 "\t$dst, $a, $b", pat> {
1442 let Inst{31-27} = 0b11111;
1443 let Inst{26-23} = 0b0101;
1444 let Inst{22-20} = op22_20;
1445 let Inst{15-12} = 0b1111;
1446 let Inst{7-4} = op7_4;
1449 // Saturating add/subtract -- for disassembly only
1451 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1452 [(set rGPR:$dst, (int_arm_qadd rGPR:$a, rGPR:$b))]>;
1453 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1454 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1455 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1456 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1457 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1458 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1459 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1460 [(set rGPR:$dst, (int_arm_qsub rGPR:$a, rGPR:$b))]>;
1461 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1462 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1463 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1464 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1465 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1466 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1467 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1468 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1470 // Signed/Unsigned add/subtract -- for disassembly only
1472 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1473 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1474 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1475 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1476 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1477 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1478 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1479 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1480 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1481 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1482 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1483 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1485 // Signed/Unsigned halving add/subtract -- for disassembly only
1487 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1488 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1489 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1490 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1491 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1492 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1493 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1494 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1495 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1496 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1497 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1498 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1500 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1502 def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst),
1503 (ins rGPR:$a, rGPR:$b),
1504 NoItinerary, "usad8", "\t$dst, $a, $b", []> {
1505 let Inst{15-12} = 0b1111;
1507 def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst),
1508 (ins rGPR:$a, rGPR:$b, rGPR:$acc), NoItinerary, "usada8",
1509 "\t$dst, $a, $b, $acc", []>;
1511 // Signed/Unsigned saturate -- for disassembly only
1513 def t2SSAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, sat_shift:$sh),
1514 NoItinerary, "ssat", "\t$dst, $bit_pos, $a$sh",
1515 [/* For disassembly only; pattern left blank */]> {
1516 let Inst{31-27} = 0b11110;
1517 let Inst{25-22} = 0b1100;
1522 def t2SSAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary,
1523 "ssat16", "\t$dst, $bit_pos, $a",
1524 [/* For disassembly only; pattern left blank */]> {
1525 let Inst{31-27} = 0b11110;
1526 let Inst{25-22} = 0b1100;
1529 let Inst{21} = 1; // sh = '1'
1530 let Inst{14-12} = 0b000; // imm3 = '000'
1531 let Inst{7-6} = 0b00; // imm2 = '00'
1534 def t2USAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, sat_shift:$sh),
1535 NoItinerary, "usat", "\t$dst, $bit_pos, $a$sh",
1536 [/* For disassembly only; pattern left blank */]> {
1537 let Inst{31-27} = 0b11110;
1538 let Inst{25-22} = 0b1110;
1543 def t2USAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary,
1544 "usat16", "\t$dst, $bit_pos, $a",
1545 [/* For disassembly only; pattern left blank */]> {
1546 let Inst{31-27} = 0b11110;
1547 let Inst{25-22} = 0b1110;
1550 let Inst{21} = 1; // sh = '1'
1551 let Inst{14-12} = 0b000; // imm3 = '000'
1552 let Inst{7-6} = 0b00; // imm2 = '00'
1555 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
1556 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
1558 //===----------------------------------------------------------------------===//
1559 // Shift and rotate Instructions.
1562 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1563 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1564 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1565 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1567 let Uses = [CPSR] in {
1568 def t2MOVrx : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1569 "rrx", "\t$dst, $src",
1570 [(set rGPR:$dst, (ARMrrx rGPR:$src))]> {
1571 let Inst{31-27} = 0b11101;
1572 let Inst{26-25} = 0b01;
1573 let Inst{24-21} = 0b0010;
1574 let Inst{20} = ?; // The S bit.
1575 let Inst{19-16} = 0b1111; // Rn
1576 let Inst{14-12} = 0b000;
1577 let Inst{7-4} = 0b0011;
1581 let Defs = [CPSR] in {
1582 def t2MOVsrl_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1583 "lsrs", ".w\t$dst, $src, #1",
1584 [(set rGPR:$dst, (ARMsrl_flag rGPR:$src))]> {
1585 let Inst{31-27} = 0b11101;
1586 let Inst{26-25} = 0b01;
1587 let Inst{24-21} = 0b0010;
1588 let Inst{20} = 1; // The S bit.
1589 let Inst{19-16} = 0b1111; // Rn
1590 let Inst{5-4} = 0b01; // Shift type.
1591 // Shift amount = Inst{14-12:7-6} = 1.
1592 let Inst{14-12} = 0b000;
1593 let Inst{7-6} = 0b01;
1595 def t2MOVsra_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1596 "asrs", ".w\t$dst, $src, #1",
1597 [(set rGPR:$dst, (ARMsra_flag rGPR:$src))]> {
1598 let Inst{31-27} = 0b11101;
1599 let Inst{26-25} = 0b01;
1600 let Inst{24-21} = 0b0010;
1601 let Inst{20} = 1; // The S bit.
1602 let Inst{19-16} = 0b1111; // Rn
1603 let Inst{5-4} = 0b10; // Shift type.
1604 // Shift amount = Inst{14-12:7-6} = 1.
1605 let Inst{14-12} = 0b000;
1606 let Inst{7-6} = 0b01;
1610 //===----------------------------------------------------------------------===//
1611 // Bitwise Instructions.
1614 defm t2AND : T2I_bin_w_irs<0b0000, "and",
1615 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1616 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1617 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1618 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1619 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1621 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1622 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1624 let Constraints = "$src = $dst" in
1625 def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm),
1626 IIC_iUNAsi, "bfc", "\t$dst, $imm",
1627 [(set rGPR:$dst, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
1628 let Inst{31-27} = 0b11110;
1630 let Inst{24-20} = 0b10110;
1631 let Inst{19-16} = 0b1111; // Rn
1635 def t2SBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
1636 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
1637 let Inst{31-27} = 0b11110;
1639 let Inst{24-20} = 0b10100;
1643 def t2UBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
1644 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
1645 let Inst{31-27} = 0b11110;
1647 let Inst{24-20} = 0b11100;
1651 // A8.6.18 BFI - Bitfield insert (Encoding T1)
1652 let Constraints = "$src = $dst" in
1653 def t2BFI : T2I<(outs rGPR:$dst),
1654 (ins rGPR:$src, rGPR:$val, bf_inv_mask_imm:$imm),
1655 IIC_iALUi, "bfi", "\t$dst, $val, $imm",
1656 [(set rGPR:$dst, (ARMbfi rGPR:$src, rGPR:$val,
1657 bf_inv_mask_imm:$imm))]> {
1658 let Inst{31-27} = 0b11110;
1660 let Inst{24-20} = 0b10110;
1664 defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS,
1667 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
1668 let AddedComplexity = 1 in
1669 defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
1672 let AddedComplexity = 1 in
1673 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
1674 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
1676 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
1677 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
1678 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
1679 Requires<[IsThumb2]>;
1681 def : T2Pat<(t2_so_imm_not:$src),
1682 (t2MVNi t2_so_imm_not:$src)>;
1684 //===----------------------------------------------------------------------===//
1685 // Multiply Instructions.
1687 let isCommutable = 1 in
1688 def t2MUL: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1689 "mul", "\t$dst, $a, $b",
1690 [(set rGPR:$dst, (mul rGPR:$a, rGPR:$b))]> {
1691 let Inst{31-27} = 0b11111;
1692 let Inst{26-23} = 0b0110;
1693 let Inst{22-20} = 0b000;
1694 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1695 let Inst{7-4} = 0b0000; // Multiply
1698 def t2MLA: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1699 "mla", "\t$dst, $a, $b, $c",
1700 [(set rGPR:$dst, (add (mul rGPR:$a, rGPR:$b), rGPR:$c))]> {
1701 let Inst{31-27} = 0b11111;
1702 let Inst{26-23} = 0b0110;
1703 let Inst{22-20} = 0b000;
1704 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1705 let Inst{7-4} = 0b0000; // Multiply
1708 def t2MLS: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1709 "mls", "\t$dst, $a, $b, $c",
1710 [(set rGPR:$dst, (sub rGPR:$c, (mul rGPR:$a, rGPR:$b)))]> {
1711 let Inst{31-27} = 0b11111;
1712 let Inst{26-23} = 0b0110;
1713 let Inst{22-20} = 0b000;
1714 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1715 let Inst{7-4} = 0b0001; // Multiply and Subtract
1718 // Extra precision multiplies with low / high results
1719 let neverHasSideEffects = 1 in {
1720 let isCommutable = 1 in {
1721 def t2SMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
1722 "smull", "\t$ldst, $hdst, $a, $b", []> {
1723 let Inst{31-27} = 0b11111;
1724 let Inst{26-23} = 0b0111;
1725 let Inst{22-20} = 0b000;
1726 let Inst{7-4} = 0b0000;
1729 def t2UMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
1730 "umull", "\t$ldst, $hdst, $a, $b", []> {
1731 let Inst{31-27} = 0b11111;
1732 let Inst{26-23} = 0b0111;
1733 let Inst{22-20} = 0b010;
1734 let Inst{7-4} = 0b0000;
1738 // Multiply + accumulate
1739 def t2SMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1740 "smlal", "\t$ldst, $hdst, $a, $b", []>{
1741 let Inst{31-27} = 0b11111;
1742 let Inst{26-23} = 0b0111;
1743 let Inst{22-20} = 0b100;
1744 let Inst{7-4} = 0b0000;
1747 def t2UMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1748 "umlal", "\t$ldst, $hdst, $a, $b", []>{
1749 let Inst{31-27} = 0b11111;
1750 let Inst{26-23} = 0b0111;
1751 let Inst{22-20} = 0b110;
1752 let Inst{7-4} = 0b0000;
1755 def t2UMAAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1756 "umaal", "\t$ldst, $hdst, $a, $b", []>{
1757 let Inst{31-27} = 0b11111;
1758 let Inst{26-23} = 0b0111;
1759 let Inst{22-20} = 0b110;
1760 let Inst{7-4} = 0b0110;
1762 } // neverHasSideEffects
1764 // Rounding variants of the below included for disassembly only
1766 // Most significant word multiply
1767 def t2SMMUL : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1768 "smmul", "\t$dst, $a, $b",
1769 [(set rGPR:$dst, (mulhs rGPR:$a, rGPR:$b))]> {
1770 let Inst{31-27} = 0b11111;
1771 let Inst{26-23} = 0b0110;
1772 let Inst{22-20} = 0b101;
1773 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1774 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1777 def t2SMMULR : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1778 "smmulr", "\t$dst, $a, $b", []> {
1779 let Inst{31-27} = 0b11111;
1780 let Inst{26-23} = 0b0110;
1781 let Inst{22-20} = 0b101;
1782 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1783 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1786 def t2SMMLA : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1787 "smmla", "\t$dst, $a, $b, $c",
1788 [(set rGPR:$dst, (add (mulhs rGPR:$a, rGPR:$b), rGPR:$c))]> {
1789 let Inst{31-27} = 0b11111;
1790 let Inst{26-23} = 0b0110;
1791 let Inst{22-20} = 0b101;
1792 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1793 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1796 def t2SMMLAR : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1797 "smmlar", "\t$dst, $a, $b, $c", []> {
1798 let Inst{31-27} = 0b11111;
1799 let Inst{26-23} = 0b0110;
1800 let Inst{22-20} = 0b101;
1801 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1802 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1805 def t2SMMLS : T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1806 "smmls", "\t$dst, $a, $b, $c",
1807 [(set rGPR:$dst, (sub rGPR:$c, (mulhs rGPR:$a, rGPR:$b)))]> {
1808 let Inst{31-27} = 0b11111;
1809 let Inst{26-23} = 0b0110;
1810 let Inst{22-20} = 0b110;
1811 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1812 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1815 def t2SMMLSR : T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1816 "smmlsr", "\t$dst, $a, $b, $c", []> {
1817 let Inst{31-27} = 0b11111;
1818 let Inst{26-23} = 0b0110;
1819 let Inst{22-20} = 0b110;
1820 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1821 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1824 multiclass T2I_smul<string opc, PatFrag opnode> {
1825 def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1826 !strconcat(opc, "bb"), "\t$dst, $a, $b",
1827 [(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16),
1828 (sext_inreg rGPR:$b, i16)))]> {
1829 let Inst{31-27} = 0b11111;
1830 let Inst{26-23} = 0b0110;
1831 let Inst{22-20} = 0b001;
1832 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1833 let Inst{7-6} = 0b00;
1834 let Inst{5-4} = 0b00;
1837 def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1838 !strconcat(opc, "bt"), "\t$dst, $a, $b",
1839 [(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16),
1840 (sra rGPR:$b, (i32 16))))]> {
1841 let Inst{31-27} = 0b11111;
1842 let Inst{26-23} = 0b0110;
1843 let Inst{22-20} = 0b001;
1844 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1845 let Inst{7-6} = 0b00;
1846 let Inst{5-4} = 0b01;
1849 def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1850 !strconcat(opc, "tb"), "\t$dst, $a, $b",
1851 [(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)),
1852 (sext_inreg rGPR:$b, i16)))]> {
1853 let Inst{31-27} = 0b11111;
1854 let Inst{26-23} = 0b0110;
1855 let Inst{22-20} = 0b001;
1856 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1857 let Inst{7-6} = 0b00;
1858 let Inst{5-4} = 0b10;
1861 def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1862 !strconcat(opc, "tt"), "\t$dst, $a, $b",
1863 [(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)),
1864 (sra rGPR:$b, (i32 16))))]> {
1865 let Inst{31-27} = 0b11111;
1866 let Inst{26-23} = 0b0110;
1867 let Inst{22-20} = 0b001;
1868 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1869 let Inst{7-6} = 0b00;
1870 let Inst{5-4} = 0b11;
1873 def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
1874 !strconcat(opc, "wb"), "\t$dst, $a, $b",
1875 [(set rGPR:$dst, (sra (opnode rGPR:$a,
1876 (sext_inreg rGPR:$b, i16)), (i32 16)))]> {
1877 let Inst{31-27} = 0b11111;
1878 let Inst{26-23} = 0b0110;
1879 let Inst{22-20} = 0b011;
1880 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1881 let Inst{7-6} = 0b00;
1882 let Inst{5-4} = 0b00;
1885 def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
1886 !strconcat(opc, "wt"), "\t$dst, $a, $b",
1887 [(set rGPR:$dst, (sra (opnode rGPR:$a,
1888 (sra rGPR:$b, (i32 16))), (i32 16)))]> {
1889 let Inst{31-27} = 0b11111;
1890 let Inst{26-23} = 0b0110;
1891 let Inst{22-20} = 0b011;
1892 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1893 let Inst{7-6} = 0b00;
1894 let Inst{5-4} = 0b01;
1899 multiclass T2I_smla<string opc, PatFrag opnode> {
1900 def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1901 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1902 [(set rGPR:$dst, (add rGPR:$acc,
1903 (opnode (sext_inreg rGPR:$a, i16),
1904 (sext_inreg rGPR:$b, i16))))]> {
1905 let Inst{31-27} = 0b11111;
1906 let Inst{26-23} = 0b0110;
1907 let Inst{22-20} = 0b001;
1908 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1909 let Inst{7-6} = 0b00;
1910 let Inst{5-4} = 0b00;
1913 def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1914 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1915 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sext_inreg rGPR:$a, i16),
1916 (sra rGPR:$b, (i32 16)))))]> {
1917 let Inst{31-27} = 0b11111;
1918 let Inst{26-23} = 0b0110;
1919 let Inst{22-20} = 0b001;
1920 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1921 let Inst{7-6} = 0b00;
1922 let Inst{5-4} = 0b01;
1925 def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1926 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1927 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
1928 (sext_inreg rGPR:$b, i16))))]> {
1929 let Inst{31-27} = 0b11111;
1930 let Inst{26-23} = 0b0110;
1931 let Inst{22-20} = 0b001;
1932 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1933 let Inst{7-6} = 0b00;
1934 let Inst{5-4} = 0b10;
1937 def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1938 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1939 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
1940 (sra rGPR:$b, (i32 16)))))]> {
1941 let Inst{31-27} = 0b11111;
1942 let Inst{26-23} = 0b0110;
1943 let Inst{22-20} = 0b001;
1944 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1945 let Inst{7-6} = 0b00;
1946 let Inst{5-4} = 0b11;
1949 def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1950 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1951 [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
1952 (sext_inreg rGPR:$b, i16)), (i32 16))))]> {
1953 let Inst{31-27} = 0b11111;
1954 let Inst{26-23} = 0b0110;
1955 let Inst{22-20} = 0b011;
1956 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1957 let Inst{7-6} = 0b00;
1958 let Inst{5-4} = 0b00;
1961 def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1962 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1963 [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
1964 (sra rGPR:$b, (i32 16))), (i32 16))))]> {
1965 let Inst{31-27} = 0b11111;
1966 let Inst{26-23} = 0b0110;
1967 let Inst{22-20} = 0b011;
1968 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1969 let Inst{7-6} = 0b00;
1970 let Inst{5-4} = 0b01;
1974 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1975 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1977 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
1978 def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs rGPR:$ldst,rGPR:$hdst),
1979 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
1980 [/* For disassembly only; pattern left blank */]>;
1981 def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs rGPR:$ldst,rGPR:$hdst),
1982 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
1983 [/* For disassembly only; pattern left blank */]>;
1984 def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs rGPR:$ldst,rGPR:$hdst),
1985 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
1986 [/* For disassembly only; pattern left blank */]>;
1987 def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs rGPR:$ldst,rGPR:$hdst),
1988 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
1989 [/* For disassembly only; pattern left blank */]>;
1991 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1992 // These are for disassembly only.
1994 def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
1995 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
1996 let Inst{15-12} = 0b1111;
1998 def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
1999 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
2000 let Inst{15-12} = 0b1111;
2002 def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2003 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
2004 let Inst{15-12} = 0b1111;
2006 def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2007 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
2008 let Inst{15-12} = 0b1111;
2010 def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst),
2011 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlad",
2012 "\t$dst, $a, $b, $acc", []>;
2013 def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst),
2014 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smladx",
2015 "\t$dst, $a, $b, $acc", []>;
2016 def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst),
2017 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsd",
2018 "\t$dst, $a, $b, $acc", []>;
2019 def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst),
2020 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsdx",
2021 "\t$dst, $a, $b, $acc", []>;
2022 def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs rGPR:$ldst,rGPR:$hdst),
2023 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlald",
2024 "\t$ldst, $hdst, $a, $b", []>;
2025 def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs rGPR:$ldst,rGPR:$hdst),
2026 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaldx",
2027 "\t$ldst, $hdst, $a, $b", []>;
2028 def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs rGPR:$ldst,rGPR:$hdst),
2029 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsld",
2030 "\t$ldst, $hdst, $a, $b", []>;
2031 def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs rGPR:$ldst,rGPR:$hdst),
2032 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsldx",
2033 "\t$ldst, $hdst, $a, $b", []>;
2035 //===----------------------------------------------------------------------===//
2036 // Misc. Arithmetic Instructions.
2039 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2040 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2041 : T2I<oops, iops, itin, opc, asm, pattern> {
2042 let Inst{31-27} = 0b11111;
2043 let Inst{26-22} = 0b01010;
2044 let Inst{21-20} = op1;
2045 let Inst{15-12} = 0b1111;
2046 let Inst{7-6} = 0b10;
2047 let Inst{5-4} = op2;
2050 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2051 "clz", "\t$dst, $src", [(set rGPR:$dst, (ctlz rGPR:$src))]>;
2053 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2054 "rbit", "\t$dst, $src",
2055 [(set rGPR:$dst, (ARMrbit rGPR:$src))]>;
2057 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2058 "rev", ".w\t$dst, $src", [(set rGPR:$dst, (bswap rGPR:$src))]>;
2060 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2061 "rev16", ".w\t$dst, $src",
2063 (or (and (srl rGPR:$src, (i32 8)), 0xFF),
2064 (or (and (shl rGPR:$src, (i32 8)), 0xFF00),
2065 (or (and (srl rGPR:$src, (i32 8)), 0xFF0000),
2066 (and (shl rGPR:$src, (i32 8)), 0xFF000000)))))]>;
2068 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2069 "revsh", ".w\t$dst, $src",
2072 (or (srl (and rGPR:$src, 0xFF00), (i32 8)),
2073 (shl rGPR:$src, (i32 8))), i16))]>;
2075 def t2PKHBT : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, i32imm:$shamt),
2076 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt",
2077 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF),
2078 (and (shl rGPR:$src2, (i32 imm:$shamt)),
2080 Requires<[HasT2ExtractPack]> {
2081 let Inst{31-27} = 0b11101;
2082 let Inst{26-25} = 0b01;
2083 let Inst{24-20} = 0b01100;
2084 let Inst{5} = 0; // BT form
2088 // Alternate cases for PKHBT where identities eliminate some nodes.
2089 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2090 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2091 Requires<[HasT2ExtractPack]>;
2092 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$shamt)),
2093 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$shamt)>,
2094 Requires<[HasT2ExtractPack]>;
2096 def t2PKHTB : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, i32imm:$shamt),
2097 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
2098 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF0000),
2099 (and (sra rGPR:$src2, imm16_31:$shamt),
2101 Requires<[HasT2ExtractPack]> {
2102 let Inst{31-27} = 0b11101;
2103 let Inst{26-25} = 0b01;
2104 let Inst{24-20} = 0b01100;
2105 let Inst{5} = 1; // TB form
2109 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2110 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2111 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, (i32 16))),
2112 (t2PKHTB rGPR:$src1, rGPR:$src2, 16)>,
2113 Requires<[HasT2ExtractPack]>;
2114 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2115 (and (srl rGPR:$src2, imm1_15:$shamt), 0xFFFF)),
2116 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$shamt)>,
2117 Requires<[HasT2ExtractPack]>;
2119 //===----------------------------------------------------------------------===//
2120 // Comparison Instructions...
2122 let isCompare = 1 in {
2123 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2124 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2125 defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
2126 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2129 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2130 // Compare-to-zero still works out, just not the relationals
2131 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2132 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2133 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2134 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2136 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2137 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2139 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2140 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2142 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2143 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
2144 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2145 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
2147 // Conditional moves
2148 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2149 // a two-value operand where a dag node expects two operands. :(
2150 let neverHasSideEffects = 1 in {
2151 def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr,
2152 "mov", ".w\t$dst, $true",
2153 [/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>,
2154 RegConstraint<"$false = $dst"> {
2155 let Inst{31-27} = 0b11101;
2156 let Inst{26-25} = 0b01;
2157 let Inst{24-21} = 0b0010;
2158 let Inst{20} = 0; // The S bit.
2159 let Inst{19-16} = 0b1111; // Rn
2160 let Inst{14-12} = 0b000;
2161 let Inst{7-4} = 0b0000;
2164 def t2MOVCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true),
2165 IIC_iCMOVi, "mov", ".w\t$dst, $true",
2166 [/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
2167 RegConstraint<"$false = $dst"> {
2168 let Inst{31-27} = 0b11110;
2170 let Inst{24-21} = 0b0010;
2171 let Inst{20} = 0; // The S bit.
2172 let Inst{19-16} = 0b1111; // Rn
2176 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2177 string opc, string asm, list<dag> pattern>
2178 : T2I<oops, iops, itin, opc, asm, pattern> {
2179 let Inst{31-27} = 0b11101;
2180 let Inst{26-25} = 0b01;
2181 let Inst{24-21} = 0b0010;
2182 let Inst{20} = 0; // The S bit.
2183 let Inst{19-16} = 0b1111; // Rn
2184 let Inst{5-4} = opcod; // Shift type.
2186 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$dst),
2187 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2188 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
2189 RegConstraint<"$false = $dst">;
2190 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$dst),
2191 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2192 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
2193 RegConstraint<"$false = $dst">;
2194 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$dst),
2195 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2196 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
2197 RegConstraint<"$false = $dst">;
2198 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$dst),
2199 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2200 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
2201 RegConstraint<"$false = $dst">;
2202 } // neverHasSideEffects
2204 //===----------------------------------------------------------------------===//
2205 // Atomic operations intrinsics
2208 // memory barriers protect the atomic sequences
2209 let hasSideEffects = 1 in {
2210 def t2DMBsy : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "dmb", "",
2211 [(ARMMemBarrier)]>, Requires<[IsThumb, HasDB]> {
2212 let Inst{31-4} = 0xF3BF8F5;
2213 // FIXME: add support for options other than a full system DMB
2214 let Inst{3-0} = 0b1111;
2217 def t2DSBsy : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "dsb", "",
2218 [(ARMSyncBarrier)]>, Requires<[IsThumb, HasDB]> {
2219 let Inst{31-4} = 0xF3BF8F4;
2220 // FIXME: add support for options other than a full system DSB
2221 let Inst{3-0} = 0b1111;
2225 // Helper class for multiclass T2MemB -- for disassembly only
2226 class T2I_memb<string opc, string asm>
2227 : T2I<(outs), (ins), NoItinerary, opc, asm,
2228 [/* For disassembly only; pattern left blank */]>,
2229 Requires<[IsThumb2, HasV7]> {
2230 let Inst{31-20} = 0xf3b;
2231 let Inst{15-14} = 0b10;
2235 multiclass T2MemB<bits<4> op7_4, string opc> {
2237 def st : T2I_memb<opc, "\tst"> {
2238 let Inst{7-4} = op7_4;
2239 let Inst{3-0} = 0b1110;
2242 def ish : T2I_memb<opc, "\tish"> {
2243 let Inst{7-4} = op7_4;
2244 let Inst{3-0} = 0b1011;
2247 def ishst : T2I_memb<opc, "\tishst"> {
2248 let Inst{7-4} = op7_4;
2249 let Inst{3-0} = 0b1010;
2252 def nsh : T2I_memb<opc, "\tnsh"> {
2253 let Inst{7-4} = op7_4;
2254 let Inst{3-0} = 0b0111;
2257 def nshst : T2I_memb<opc, "\tnshst"> {
2258 let Inst{7-4} = op7_4;
2259 let Inst{3-0} = 0b0110;
2262 def osh : T2I_memb<opc, "\tosh"> {
2263 let Inst{7-4} = op7_4;
2264 let Inst{3-0} = 0b0011;
2267 def oshst : T2I_memb<opc, "\toshst"> {
2268 let Inst{7-4} = op7_4;
2269 let Inst{3-0} = 0b0010;
2273 // These DMB variants are for disassembly only.
2274 defm t2DMB : T2MemB<0b0101, "dmb">;
2276 // These DSB variants are for disassembly only.
2277 defm t2DSB : T2MemB<0b0100, "dsb">;
2279 // ISB has only full system option -- for disassembly only
2280 def t2ISBsy : T2I_memb<"isb", ""> {
2281 let Inst{7-4} = 0b0110;
2282 let Inst{3-0} = 0b1111;
2285 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2286 InstrItinClass itin, string opc, string asm, string cstr,
2287 list<dag> pattern, bits<4> rt2 = 0b1111>
2288 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2289 let Inst{31-27} = 0b11101;
2290 let Inst{26-20} = 0b0001101;
2291 let Inst{11-8} = rt2;
2292 let Inst{7-6} = 0b01;
2293 let Inst{5-4} = opcod;
2294 let Inst{3-0} = 0b1111;
2296 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2297 InstrItinClass itin, string opc, string asm, string cstr,
2298 list<dag> pattern, bits<4> rt2 = 0b1111>
2299 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2300 let Inst{31-27} = 0b11101;
2301 let Inst{26-20} = 0b0001100;
2302 let Inst{11-8} = rt2;
2303 let Inst{7-6} = 0b01;
2304 let Inst{5-4} = opcod;
2307 let mayLoad = 1 in {
2308 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2309 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
2311 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2312 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
2314 def t2LDREX : Thumb2I<(outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2315 Size4Bytes, NoItinerary,
2316 "ldrex", "\t$dest, [$ptr]", "",
2318 let Inst{31-27} = 0b11101;
2319 let Inst{26-20} = 0b0000101;
2320 let Inst{11-8} = 0b1111;
2321 let Inst{7-0} = 0b00000000; // imm8 = 0
2323 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$dest, rGPR:$dest2), (ins rGPR:$ptr),
2324 AddrModeNone, Size4Bytes, NoItinerary,
2325 "ldrexd", "\t$dest, $dest2, [$ptr]", "",
2329 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2330 def t2STREXB : T2I_strex<0b00, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2331 AddrModeNone, Size4Bytes, NoItinerary,
2332 "strexb", "\t$success, $src, [$ptr]", "", []>;
2333 def t2STREXH : T2I_strex<0b01, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2334 AddrModeNone, Size4Bytes, NoItinerary,
2335 "strexh", "\t$success, $src, [$ptr]", "", []>;
2336 def t2STREX : Thumb2I<(outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2337 AddrModeNone, Size4Bytes, NoItinerary,
2338 "strex", "\t$success, $src, [$ptr]", "",
2340 let Inst{31-27} = 0b11101;
2341 let Inst{26-20} = 0b0000100;
2342 let Inst{7-0} = 0b00000000; // imm8 = 0
2344 def t2STREXD : T2I_strex<0b11, (outs rGPR:$success),
2345 (ins rGPR:$src, rGPR:$src2, rGPR:$ptr),
2346 AddrModeNone, Size4Bytes, NoItinerary,
2347 "strexd", "\t$success, $src, $src2, [$ptr]", "", [],
2351 // Clear-Exclusive is for disassembly only.
2352 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2353 [/* For disassembly only; pattern left blank */]>,
2354 Requires<[IsARM, HasV7]> {
2355 let Inst{31-20} = 0xf3b;
2356 let Inst{15-14} = 0b10;
2358 let Inst{7-4} = 0b0010;
2361 //===----------------------------------------------------------------------===//
2365 // __aeabi_read_tp preserves the registers r1-r3.
2367 Defs = [R0, R12, LR, CPSR] in {
2368 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2369 "bl\t__aeabi_read_tp",
2370 [(set R0, ARMthread_pointer)]> {
2371 let Inst{31-27} = 0b11110;
2372 let Inst{15-14} = 0b11;
2377 //===----------------------------------------------------------------------===//
2378 // SJLJ Exception handling intrinsics
2379 // eh_sjlj_setjmp() is an instruction sequence to store the return
2380 // address and save #0 in R0 for the non-longjmp case.
2381 // Since by its nature we may be coming from some other function to get
2382 // here, and we're using the stack frame for the containing function to
2383 // save/restore registers, we can't keep anything live in regs across
2384 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2385 // when we get here from a longjmp(). We force everthing out of registers
2386 // except for our own input by listing the relevant registers in Defs. By
2387 // doing so, we also cause the prologue/epilogue code to actively preserve
2388 // all of the callee-saved resgisters, which is exactly what we want.
2389 // $val is a scratch register for our use.
2391 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2392 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2393 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2394 D31 ], hasSideEffects = 1, isBarrier = 1 in {
2395 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
2396 AddrModeNone, SizeSpecial, NoItinerary,
2397 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
2398 "adds\t$val, #7\n\t"
2399 "str\t$val, [$src, #4]\n\t"
2402 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
2404 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>,
2405 Requires<[IsThumb2, HasVFP2]>;
2409 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2410 hasSideEffects = 1, isBarrier = 1 in {
2411 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
2412 AddrModeNone, SizeSpecial, NoItinerary,
2413 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
2414 "adds\t$val, #7\n\t"
2415 "str\t$val, [$src, #4]\n\t"
2418 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
2420 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>,
2421 Requires<[IsThumb2, NoVFP]>;
2425 //===----------------------------------------------------------------------===//
2426 // Control-Flow Instructions
2429 // FIXME: remove when we have a way to marking a MI with these properties.
2430 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2432 // FIXME: Should pc be an implicit operand like PICADD, etc?
2433 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2434 hasExtraDefRegAllocReq = 1 in
2435 def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
2436 reglist:$dsts, variable_ops), IIC_Br,
2437 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
2438 "$addr.addr = $wb", []> {
2439 let Inst{31-27} = 0b11101;
2440 let Inst{26-25} = 0b00;
2441 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
2443 let Inst{21} = 1; // The W bit.
2444 let Inst{20} = 1; // Load
2447 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2448 let isPredicable = 1 in
2449 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2451 [(br bb:$target)]> {
2452 let Inst{31-27} = 0b11110;
2453 let Inst{15-14} = 0b10;
2457 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2460 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
2461 IIC_Br, "mov\tpc, $target$jt",
2462 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
2463 let Inst{31-27} = 0b11101;
2464 let Inst{26-20} = 0b0100100;
2465 let Inst{19-16} = 0b1111;
2466 let Inst{14-12} = 0b000;
2467 let Inst{11-8} = 0b1111; // Rd = pc
2468 let Inst{7-4} = 0b0000;
2471 // FIXME: Add a non-pc based case that can be predicated.
2474 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2475 IIC_Br, "tbb\t$index$jt", []> {
2476 let Inst{31-27} = 0b11101;
2477 let Inst{26-20} = 0b0001101;
2478 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2479 let Inst{15-8} = 0b11110000;
2480 let Inst{7-4} = 0b0000; // B form
2485 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2486 IIC_Br, "tbh\t$index$jt", []> {
2487 let Inst{31-27} = 0b11101;
2488 let Inst{26-20} = 0b0001101;
2489 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2490 let Inst{15-8} = 0b11110000;
2491 let Inst{7-4} = 0b0001; // H form
2494 // Generic versions of the above two instructions, for disassembly only
2496 def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2497 "tbb", "\t[$a, $b]", []>{
2498 let Inst{31-27} = 0b11101;
2499 let Inst{26-20} = 0b0001101;
2500 let Inst{15-8} = 0b11110000;
2501 let Inst{7-4} = 0b0000; // B form
2504 def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2505 "tbh", "\t[$a, $b, lsl #1]", []> {
2506 let Inst{31-27} = 0b11101;
2507 let Inst{26-20} = 0b0001101;
2508 let Inst{15-8} = 0b11110000;
2509 let Inst{7-4} = 0b0001; // H form
2511 } // isNotDuplicable, isIndirectBranch
2513 } // isBranch, isTerminator, isBarrier
2515 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2516 // a two-value operand where a dag node expects two operands. :(
2517 let isBranch = 1, isTerminator = 1 in
2518 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
2520 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
2521 let Inst{31-27} = 0b11110;
2522 let Inst{15-14} = 0b10;
2528 let Defs = [ITSTATE] in
2529 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
2530 AddrModeNone, Size2Bytes, IIC_iALUx,
2531 "it$mask\t$cc", "", []> {
2532 // 16-bit instruction.
2533 let Inst{31-16} = 0x0000;
2534 let Inst{15-8} = 0b10111111;
2537 // Branch and Exchange Jazelle -- for disassembly only
2539 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
2540 [/* For disassembly only; pattern left blank */]> {
2541 let Inst{31-27} = 0b11110;
2543 let Inst{25-20} = 0b111100;
2544 let Inst{15-14} = 0b10;
2548 // Change Processor State is a system instruction -- for disassembly only.
2549 // The singleton $opt operand contains the following information:
2550 // opt{4-0} = mode from Inst{4-0}
2551 // opt{5} = changemode from Inst{17}
2552 // opt{8-6} = AIF from Inst{8-6}
2553 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
2554 def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
2555 [/* For disassembly only; pattern left blank */]> {
2556 let Inst{31-27} = 0b11110;
2558 let Inst{25-20} = 0b111010;
2559 let Inst{15-14} = 0b10;
2563 // A6.3.4 Branches and miscellaneous control
2564 // Table A6-14 Change Processor State, and hint instructions
2565 // Helper class for disassembly only.
2566 class T2I_hint<bits<8> op7_0, string opc, string asm>
2567 : T2I<(outs), (ins), NoItinerary, opc, asm,
2568 [/* For disassembly only; pattern left blank */]> {
2569 let Inst{31-20} = 0xf3a;
2570 let Inst{15-14} = 0b10;
2572 let Inst{10-8} = 0b000;
2573 let Inst{7-0} = op7_0;
2576 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
2577 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
2578 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
2579 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
2580 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
2582 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
2583 [/* For disassembly only; pattern left blank */]> {
2584 let Inst{31-20} = 0xf3a;
2585 let Inst{15-14} = 0b10;
2587 let Inst{10-8} = 0b000;
2588 let Inst{7-4} = 0b1111;
2591 // Secure Monitor Call is a system instruction -- for disassembly only
2592 // Option = Inst{19-16}
2593 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
2594 [/* For disassembly only; pattern left blank */]> {
2595 let Inst{31-27} = 0b11110;
2596 let Inst{26-20} = 0b1111111;
2597 let Inst{15-12} = 0b1000;
2600 // Store Return State is a system instruction -- for disassembly only
2601 def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
2602 [/* For disassembly only; pattern left blank */]> {
2603 let Inst{31-27} = 0b11101;
2604 let Inst{26-20} = 0b0000010; // W = 1
2607 def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
2608 [/* For disassembly only; pattern left blank */]> {
2609 let Inst{31-27} = 0b11101;
2610 let Inst{26-20} = 0b0000000; // W = 0
2613 def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
2614 [/* For disassembly only; pattern left blank */]> {
2615 let Inst{31-27} = 0b11101;
2616 let Inst{26-20} = 0b0011010; // W = 1
2619 def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
2620 [/* For disassembly only; pattern left blank */]> {
2621 let Inst{31-27} = 0b11101;
2622 let Inst{26-20} = 0b0011000; // W = 0
2625 // Return From Exception is a system instruction -- for disassembly only
2626 def t2RFEDBW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfedb", "\t$base!",
2627 [/* For disassembly only; pattern left blank */]> {
2628 let Inst{31-27} = 0b11101;
2629 let Inst{26-20} = 0b0000011; // W = 1
2632 def t2RFEDB : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeab", "\t$base",
2633 [/* For disassembly only; pattern left blank */]> {
2634 let Inst{31-27} = 0b11101;
2635 let Inst{26-20} = 0b0000001; // W = 0
2638 def t2RFEIAW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base!",
2639 [/* For disassembly only; pattern left blank */]> {
2640 let Inst{31-27} = 0b11101;
2641 let Inst{26-20} = 0b0011011; // W = 1
2644 def t2RFEIA : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base",
2645 [/* For disassembly only; pattern left blank */]> {
2646 let Inst{31-27} = 0b11101;
2647 let Inst{26-20} = 0b0011001; // W = 0
2650 //===----------------------------------------------------------------------===//
2651 // Non-Instruction Patterns
2654 // Two piece so_imms.
2655 def : T2Pat<(or rGPR:$LHS, t2_so_imm2part:$RHS),
2656 (t2ORRri (t2ORRri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2657 (t2_so_imm2part_2 imm:$RHS))>;
2658 def : T2Pat<(xor rGPR:$LHS, t2_so_imm2part:$RHS),
2659 (t2EORri (t2EORri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2660 (t2_so_imm2part_2 imm:$RHS))>;
2661 def : T2Pat<(add rGPR:$LHS, t2_so_imm2part:$RHS),
2662 (t2ADDri (t2ADDri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2663 (t2_so_imm2part_2 imm:$RHS))>;
2664 def : T2Pat<(add rGPR:$LHS, t2_so_neg_imm2part:$RHS),
2665 (t2SUBri (t2SUBri rGPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
2666 (t2_so_neg_imm2part_2 imm:$RHS))>;
2668 // 32-bit immediate using movw + movt.
2669 // This is a single pseudo instruction to make it re-materializable. Remove
2670 // when we can do generalized remat.
2671 let isReMaterializable = 1 in
2672 def t2MOVi32imm : T2Ix2<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
2673 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2674 [(set rGPR:$dst, (i32 imm:$src))]>;
2676 // ConstantPool, GlobalAddress, and JumpTable
2677 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
2678 Requires<[IsThumb2, DontUseMovt]>;
2679 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
2680 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
2681 Requires<[IsThumb2, UseMovt]>;
2683 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2684 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
2686 // Pseudo instruction that combines ldr from constpool and add pc. This should
2687 // be expanded into two instructions late to allow if-conversion and
2689 let canFoldAsLoad = 1, isReMaterializable = 1 in
2690 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
2692 "${:comment} ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
2693 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
2695 Requires<[IsThumb2]>;
2697 //===----------------------------------------------------------------------===//
2698 // Move between special register and ARM core register -- for disassembly only
2702 def t2MRS : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
2703 [/* For disassembly only; pattern left blank */]> {
2704 let Inst{31-27} = 0b11110;
2706 let Inst{25-21} = 0b11111;
2707 let Inst{20} = 0; // The R bit.
2708 let Inst{15-14} = 0b10;
2713 def t2MRSsys : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
2714 [/* For disassembly only; pattern left blank */]> {
2715 let Inst{31-27} = 0b11110;
2717 let Inst{25-21} = 0b11111;
2718 let Inst{20} = 1; // The R bit.
2719 let Inst{15-14} = 0b10;
2724 def t2MSR : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
2725 "\tcpsr$mask, $src",
2726 [/* For disassembly only; pattern left blank */]> {
2727 let Inst{31-27} = 0b11110;
2729 let Inst{25-21} = 0b11100;
2730 let Inst{20} = 0; // The R bit.
2731 let Inst{15-14} = 0b10;
2736 def t2MSRsys : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
2737 "\tspsr$mask, $src",
2738 [/* For disassembly only; pattern left blank */]> {
2739 let Inst{31-27} = 0b11110;
2741 let Inst{25-21} = 0b11100;
2742 let Inst{20} = 1; // The R bit.
2743 let Inst{15-14} = 0b10;