1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // Shifted operands. No register controlled shifts for Thumb2.
15 // Note: We do not support rrx shifted operands yet.
16 def t2_so_reg : Operand<i32>, // reg imm
17 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
19 let PrintMethod = "printT2SOOperand";
20 let MIOperandInfo = (ops GPR, i32imm);
23 // t2_so_imm_XFORM - Return a t2_so_imm value packed into the format
24 // described for t2_so_imm def below.
25 def t2_so_imm_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(
27 ARM_AM::getT2SOImmVal(N->getZExtValue()), MVT::i32);
30 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
31 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
32 return CurDAG->getTargetConstant(
33 ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())), MVT::i32);
36 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
37 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
38 return CurDAG->getTargetConstant(
39 ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())), MVT::i32);
42 // t2_so_imm - Match a 32-bit immediate operand, which is an
43 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
44 // immediate splatted into multiple bytes of the word. t2_so_imm values are
45 // represented in the imm field in the same 12-bit form that they are encoded
46 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
47 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
48 def t2_so_imm : Operand<i32>,
50 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
51 }], t2_so_imm_XFORM> {
52 let PrintMethod = "printT2SOImmOperand";
55 // t2_so_imm_not - Match an immediate that is a complement
57 def t2_so_imm_not : Operand<i32>,
59 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
60 }], t2_so_imm_not_XFORM> {
61 let PrintMethod = "printT2SOImmOperand";
64 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
65 def t2_so_imm_neg : Operand<i32>,
67 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
68 }], t2_so_imm_neg_XFORM> {
69 let PrintMethod = "printT2SOImmOperand";
72 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
73 def imm1_31 : PatLeaf<(i32 imm), [{
74 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
77 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
78 def imm0_4095 : PatLeaf<(i32 imm), [{
79 return (uint32_t)N->getZExtValue() < 4096;
82 def imm0_4095_neg : PatLeaf<(i32 imm), [{
83 return (uint32_t)(-N->getZExtValue()) < 4096;
86 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
88 def imm0_65535 : PatLeaf<(i32 imm), [{
89 return (uint32_t)N->getZExtValue() < 65536;
93 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
95 def bf_inv_mask_imm : Operand<i32>,
97 uint32_t v = (uint32_t)N->getZExtValue();
100 // naive checker. should do better, but simple is best for now since it's
101 // more likely to be correct.
102 while (v & 1) v >>= 1; // shift off the leading 1's
105 while (!(v & 1)) v >>=1; // shift off the mask
106 while (v & 1) v >>= 1; // shift off the trailing 1's
108 // if this is a mask for clearing a bitfield, what's left should be zero.
111 let PrintMethod = "printBitfieldInvMaskImmOperand";
114 /// Split a 32-bit immediate into two 16 bit parts.
115 def t2_lo16 : SDNodeXForm<imm, [{
116 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
120 def t2_hi16 : SDNodeXForm<imm, [{
121 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
124 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
125 // Returns true if all low 16-bits are 0.
126 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
130 // Define Thumb2 specific addressing modes.
132 // t2addrmode_imm12 := reg + imm12
133 def t2addrmode_imm12 : Operand<i32>,
134 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
135 let PrintMethod = "printT2AddrModeImm12Operand";
136 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
139 // t2addrmode_imm8 := reg - imm8 (also reg + imm8 for some instructions)
140 def t2addrmode_imm8 : Operand<i32>,
141 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
142 let PrintMethod = "printT2AddrModeImm8Operand";
143 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
146 // t2addrmode_imm8s4 := reg + (imm8 << 2)
147 def t2addrmode_imm8s4 : Operand<i32>,
148 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
149 let PrintMethod = "printT2AddrModeImm8Operand";
150 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
153 // t2addrmode_so_reg := reg + reg << imm2
154 def t2addrmode_so_reg : Operand<i32>,
155 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
156 let PrintMethod = "printT2AddrModeSoRegOperand";
157 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
161 //===----------------------------------------------------------------------===//
162 // Multiclass helpers...
165 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
166 /// unary operation that produces a value. These are predicable and can be
167 /// changed to modify CPSR.
168 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
170 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
172 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
173 let isAsCheapAsAMove = Cheap;
174 let isReMaterializable = ReMat;
177 def r : T2I<(outs GPR:$dst), (ins GPR:$src),
179 [(set GPR:$dst, (opnode GPR:$src))]>;
181 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
183 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
186 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
187 // binary operation that produces a value. These are predicable and can be
188 /// changed to modify CPSR.
189 multiclass T2I_bin_irs<string opc, PatFrag opnode, bit Commutable = 0> {
191 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
192 opc, " $dst, $lhs, $rhs",
193 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
195 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
196 opc, " $dst, $lhs, $rhs",
197 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
198 let isCommutable = Commutable;
201 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
202 opc, " $dst, $lhs, $rhs",
203 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
206 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
207 /// reversed. It doesn't define the 'rr' form since it's handled by its
208 /// T2I_bin_irs counterpart.
209 multiclass T2I_rbin_is<string opc, PatFrag opnode> {
211 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
212 opc, " $dst, $rhs, $lhs",
213 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
215 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
216 opc, " $dst, $rhs, $lhs",
217 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
220 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
221 /// instruction modifies the CPSR register.
222 let Defs = [CPSR] in {
223 multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
225 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
226 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
227 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
229 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
230 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
231 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
232 let isCommutable = Commutable;
235 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
236 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
237 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
241 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
242 /// patterns for a binary operation that produces a value.
243 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
245 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
246 opc, " $dst, $lhs, $rhs",
247 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
249 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
250 !strconcat(opc, "w"), " $dst, $lhs, $rhs",
251 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
253 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
254 opc, " $dst, $lhs, $rhs",
255 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
256 let isCommutable = Commutable;
259 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
260 opc, " $dst, $lhs, $rhs",
261 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
264 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
265 /// binary operation that produces a value and use and define the carry bit.
266 /// It's not predicable.
267 let Uses = [CPSR] in {
268 multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
270 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
271 opc, " $dst, $lhs, $rhs",
272 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
273 Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
275 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
276 opc, " $dst, $lhs, $rhs",
277 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
278 Requires<[IsThumb, HasThumb2, CarryDefIsUnused]> {
279 let isCommutable = Commutable;
282 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
283 opc, " $dst, $lhs, $rhs",
284 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
285 Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
286 // Carry setting variants
288 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
289 !strconcat(opc, "s $dst, $lhs, $rhs"),
290 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
291 Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
295 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
296 !strconcat(opc, "s $dst, $lhs, $rhs"),
297 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
298 Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
300 let isCommutable = Commutable;
303 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
304 !strconcat(opc, "s $dst, $lhs, $rhs"),
305 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
306 Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
312 /// T2I_rsc_is - Same as T2I_adde_sube_irs except the order of operands are
313 /// reversed. It doesn't define the 'rr' form since it's handled by its
314 /// T2I_adde_sube_irs counterpart.
315 let Defs = [CPSR], Uses = [CPSR] in {
316 multiclass T2I_rsc_is<string opc, PatFrag opnode> {
318 def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
319 opc, " $dst, $rhs, $lhs",
320 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
321 Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
323 def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
324 opc, " $dst, $rhs, $lhs",
325 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
326 Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
328 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
329 !strconcat(opc, "s $dst, $rhs, $lhs"),
330 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
331 Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
335 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
336 !strconcat(opc, "s $dst, $rhs, $lhs"),
337 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
338 Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
344 /// T2I_rbin_s_is - Same as T2I_bin_s_irs except the order of operands are
345 /// reversed. It doesn't define the 'rr' form since it's handled by its
346 /// T2I_bin_s_irs counterpart.
347 let Defs = [CPSR] in {
348 multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
350 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
351 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
352 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
354 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
355 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
356 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
360 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
361 // rotate operation that produces a value.
362 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
364 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
365 opc, " $dst, $lhs, $rhs",
366 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
368 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
369 opc, " $dst, $lhs, $rhs",
370 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
373 /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
374 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
375 /// a explicit result, only implicitly set CPSR.
376 let Uses = [CPSR] in {
377 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
379 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
381 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
383 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs),
385 [(opnode GPR:$lhs, GPR:$rhs)]>;
387 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
389 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
393 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
394 multiclass T2I_ld<string opc, PatFrag opnode> {
395 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr),
397 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
398 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr),
400 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
401 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr),
403 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
404 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr),
406 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
409 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
410 multiclass T2I_st<string opc, PatFrag opnode> {
411 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr),
413 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
414 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr),
416 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
417 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr),
419 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
422 /// T2I_picld - Defines the PIC load pattern.
423 class T2I_picld<string opc, PatFrag opnode> :
424 T2I<(outs GPR:$dst), (ins addrmodepc:$addr),
425 !strconcat("${addr:label}:\n\t", opc), " $dst, $addr",
426 [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
428 /// T2I_picst - Defines the PIC store pattern.
429 class T2I_picst<string opc, PatFrag opnode> :
430 T2I<(outs), (ins GPR:$src, addrmodepc:$addr),
431 !strconcat("${addr:label}:\n\t", opc), " $src, $addr",
432 [(opnode GPR:$src, addrmodepc:$addr)]>;
434 //===----------------------------------------------------------------------===//
436 //===----------------------------------------------------------------------===//
438 //===----------------------------------------------------------------------===//
439 // Miscellaneous Instructions.
442 let isNotDuplicable = 1 in
443 def t2PICADD : T2XI<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
444 "$cp:\n\tadd $dst, pc",
445 [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
448 // LEApcrel - Load a pc-relative address into a register without offending the
450 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
451 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
452 "${:private}PCRELL${:uid}+8))\n"),
453 !strconcat("${:private}PCRELL${:uid}:\n\t",
454 "add$p $dst, pc, #PCRELV${:uid}")),
457 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
458 (ins i32imm:$label, i32imm:$id, pred:$p),
459 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
460 "${:private}PCRELL${:uid}+8))\n"),
461 !strconcat("${:private}PCRELL${:uid}:\n\t",
462 "add$p $dst, pc, #PCRELV${:uid}")),
465 // ADD rd, sp, #so_imm
466 def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
467 "add $dst, $sp, $imm",
470 // ADD rd, sp, #imm12
471 def t2ADDrSPi12 : T2XI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm),
472 "addw $dst, $sp, $imm",
475 def t2ADDrSPs : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
476 "addw $dst, $sp, $rhs",
480 //===----------------------------------------------------------------------===//
481 // Load / store Instructions.
485 let canFoldAsLoad = 1 in
486 defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>;
488 // Loads with zero extension
489 defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
490 defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
492 // Loads with sign extension
493 defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
494 defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
498 def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr),
499 "ldrd", " $dst, $addr", []>;
500 def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr),
501 "ldrd", " $dst, $addr", []>;
504 // zextload i1 -> zextload i8
505 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
506 (t2LDRBi12 t2addrmode_imm12:$addr)>;
507 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
508 (t2LDRBi8 t2addrmode_imm8:$addr)>;
509 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
510 (t2LDRBs t2addrmode_so_reg:$addr)>;
511 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
512 (t2LDRBpci tconstpool:$addr)>;
514 // extload -> zextload
515 // FIXME: Reduce the number of patterns by legalizing extload to zextload
517 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
518 (t2LDRBi12 t2addrmode_imm12:$addr)>;
519 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
520 (t2LDRBi8 t2addrmode_imm8:$addr)>;
521 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
522 (t2LDRBs t2addrmode_so_reg:$addr)>;
523 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
524 (t2LDRBpci tconstpool:$addr)>;
526 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
527 (t2LDRBi12 t2addrmode_imm12:$addr)>;
528 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
529 (t2LDRBi8 t2addrmode_imm8:$addr)>;
530 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
531 (t2LDRBs t2addrmode_so_reg:$addr)>;
532 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
533 (t2LDRBpci tconstpool:$addr)>;
535 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
536 (t2LDRHi12 t2addrmode_imm12:$addr)>;
537 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
538 (t2LDRHi8 t2addrmode_imm8:$addr)>;
539 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
540 (t2LDRHs t2addrmode_so_reg:$addr)>;
541 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
542 (t2LDRHpci tconstpool:$addr)>;
545 defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
546 defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
547 defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
551 def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr),
552 "strd", " $src, $addr", []>;
555 // Address computation and loads and stores in PIC mode.
556 let isNotDuplicable = 1, AddedComplexity = 10 in {
557 let canFoldAsLoad = 1 in
558 def t2PICLDR : T2I_picld<"ldr", UnOpFrag<(load node:$Src)>>;
560 def t2PICLDRH : T2I_picld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
561 def t2PICLDRB : T2I_picld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
562 def t2PICLDRSH : T2I_picld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
563 def t2PICLDRSB : T2I_picld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
565 def t2PICSTR : T2I_picst<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
566 def t2PICSTRH : T2I_picst<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
567 def t2PICSTRB : T2I_picst<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
568 } // isNotDuplicable = 1, AddedComplexity = 10
570 //===----------------------------------------------------------------------===//
571 // Move Instructions.
574 let neverHasSideEffects = 1 in
575 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src),
576 "mov", " $dst, $src", []>;
578 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
579 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
580 "mov", " $dst, $src",
581 [(set GPR:$dst, t2_so_imm:$src)]>;
583 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
584 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src),
585 "movw", " $dst, $src",
586 [(set GPR:$dst, imm0_65535:$src)]>;
588 // FIXME: Also available in ARM mode.
589 let Constraints = "$src = $dst" in
590 def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
591 "movt", " $dst, $imm",
593 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
595 //===----------------------------------------------------------------------===//
596 // Arithmetic Instructions.
599 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
600 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
602 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
603 defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
604 defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
606 defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>;
607 defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>;
610 defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
611 defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
612 defm t2RSC : T2I_rsc_is <"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
614 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
615 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
616 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
617 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
618 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
621 //===----------------------------------------------------------------------===//
622 // Shift and rotate Instructions.
625 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
626 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
627 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
628 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
630 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
631 "mov", " $dst, $src, rrx",
632 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
634 //===----------------------------------------------------------------------===//
635 // Bitwise Instructions.
638 defm t2AND : T2I_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
639 defm t2ORR : T2I_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
640 defm t2EOR : T2I_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
642 defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
644 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
645 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
647 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
649 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
650 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
652 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
653 let AddedComplexity = 1 in
654 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
656 def : T2Pat<(t2_so_imm_not:$src),
657 (t2MVNi t2_so_imm_not:$src)>;
659 // A8.6.17 BFC - Bitfield clear
660 // FIXME: Also available in ARM mode.
661 let Constraints = "$src = $dst" in
662 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
663 "bfc", " $dst, $imm",
664 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
666 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
668 //===----------------------------------------------------------------------===//
669 // Multiply Instructions.
671 let isCommutable = 1 in
672 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
673 "mul", " $dst, $a, $b",
674 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
676 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
677 "mla", " $dst, $a, $b, $c",
678 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
680 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
681 "mls", " $dst, $a, $b, $c",
682 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
684 // FIXME: SMULL, etc.
686 //===----------------------------------------------------------------------===//
687 // Misc. Arithmetic Instructions.
690 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
691 "clz", " $dst, $src",
692 [(set GPR:$dst, (ctlz GPR:$src))]>;
694 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
695 "rev", " $dst, $src",
696 [(set GPR:$dst, (bswap GPR:$src))]>;
698 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
699 "rev16", " $dst, $src",
701 (or (and (srl GPR:$src, (i32 8)), 0xFF),
702 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
703 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
704 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
709 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
710 "revsh", " $dst, $src",
713 (or (srl (and GPR:$src, 0xFFFF), (i32 8)),
714 (shl GPR:$src, (i32 8))), i16))]>;
718 //===----------------------------------------------------------------------===//
719 // Comparison Instructions...
722 defm t2CMP : T2I_cmp_is<"cmp",
723 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
724 defm t2CMPz : T2I_cmp_is<"cmp",
725 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
727 defm t2CMN : T2I_cmp_is<"cmn",
728 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
729 defm t2CMNz : T2I_cmp_is<"cmn",
730 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
732 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
733 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
735 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
736 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
738 defm t2TST : T2I_cmp_is<"tst",
739 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
740 defm t2TEQ : T2I_cmp_is<"teq",
741 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
743 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
744 // Short range conditional branch. Looks awesome for loops. Need to figure
745 // out how to use this one.
747 // FIXME: Conditional moves
749 //===----------------------------------------------------------------------===//
750 // Control-Flow Instructions
753 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
754 let isPredicable = 1 in
755 def t2B : T2XI<(outs), (ins brtarget:$target),
759 let isNotDuplicable = 1, isIndirectBranch = 1 in {
760 def t2BR_JTr : T2JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
761 "mov pc, $target \n$jt",
762 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
766 (ins t2addrmode_so_reg:$target, jtblock_operand:$jt, i32imm:$id),
767 "ldr pc, $target \n$jt",
768 [(ARMbrjt (i32 (load t2addrmode_so_reg:$target)), tjumptable:$jt,
773 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
774 "add pc, $target, $idx \n$jt",
775 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, imm:$id)]>;
776 } // isNotDuplicate, isIndirectBranch
777 } // isBranch, isTerminator, isBarrier
779 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
780 // a two-value operand where a dag node expects two operands. :(
781 let isBranch = 1, isTerminator = 1 in
782 def t2Bcc : T2I<(outs), (ins brtarget:$target),
784 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
786 //===----------------------------------------------------------------------===//
787 // Non-Instruction Patterns
790 // ConstantPool, GlobalAddress, and JumpTable
791 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
792 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
793 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
794 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
796 // Large immediate handling.
798 def : T2Pat<(i32 imm:$src),
799 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>;