1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops GPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant
53 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>,
56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
59 // t2_so_imm_not - Match an immediate that is a complement
61 def t2_so_imm_not : Operand<i32>,
63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
64 }], t2_so_imm_not_XFORM>;
66 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
67 def t2_so_imm_neg : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
70 }], t2_so_imm_neg_XFORM>;
72 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
73 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
74 // to get the first/second pieces.
75 def t2_so_imm2part : Operand<i32>,
77 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
81 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
82 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
83 return CurDAG->getTargetConstant(V, MVT::i32);
86 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
87 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
88 return CurDAG->getTargetConstant(V, MVT::i32);
91 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
92 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
96 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
97 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
98 return CurDAG->getTargetConstant(V, MVT::i32);
101 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
102 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
103 return CurDAG->getTargetConstant(V, MVT::i32);
106 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
107 def imm1_31 : PatLeaf<(i32 imm), [{
108 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
111 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
112 def imm0_4095 : Operand<i32>,
113 PatLeaf<(i32 imm), [{
114 return (uint32_t)N->getZExtValue() < 4096;
117 def imm0_4095_neg : PatLeaf<(i32 imm), [{
118 return (uint32_t)(-N->getZExtValue()) < 4096;
121 def imm0_255_neg : PatLeaf<(i32 imm), [{
122 return (uint32_t)(-N->getZExtValue()) < 255;
125 def imm0_255_not : PatLeaf<(i32 imm), [{
126 return (uint32_t)(~N->getZExtValue()) < 255;
129 // Define Thumb2 specific addressing modes.
131 // t2addrmode_imm12 := reg + imm12
132 def t2addrmode_imm12 : Operand<i32>,
133 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
134 let PrintMethod = "printT2AddrModeImm12Operand";
135 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
138 // t2addrmode_imm8 := reg +/- imm8
139 def t2addrmode_imm8 : Operand<i32>,
140 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
141 let PrintMethod = "printT2AddrModeImm8Operand";
142 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
145 def t2am_imm8_offset : Operand<i32>,
146 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
147 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
150 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
151 def t2addrmode_imm8s4 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
153 let PrintMethod = "printT2AddrModeImm8s4Operand";
154 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
157 def t2am_imm8s4_offset : Operand<i32> {
158 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
161 // t2addrmode_so_reg := reg + (reg << imm2)
162 def t2addrmode_so_reg : Operand<i32>,
163 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
164 let PrintMethod = "printT2AddrModeSoRegOperand";
165 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
169 //===----------------------------------------------------------------------===//
170 // Multiclass helpers...
173 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
174 /// unary operation that produces a value. These are predicable and can be
175 /// changed to modify CPSR.
176 multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode,
177 bit Cheap = 0, bit ReMat = 0> {
179 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
181 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
182 let isAsCheapAsAMove = Cheap;
183 let isReMaterializable = ReMat;
184 let Inst{31-27} = 0b11110;
186 let Inst{24-21} = opcod;
187 let Inst{20} = ?; // The S bit.
188 let Inst{19-16} = 0b1111; // Rn
192 def r : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
193 opc, ".w\t$dst, $src",
194 [(set GPR:$dst, (opnode GPR:$src))]> {
195 let Inst{31-27} = 0b11101;
196 let Inst{26-25} = 0b01;
197 let Inst{24-21} = opcod;
198 let Inst{20} = ?; // The S bit.
199 let Inst{19-16} = 0b1111; // Rn
200 let Inst{14-12} = 0b000; // imm3
201 let Inst{7-6} = 0b00; // imm2
202 let Inst{5-4} = 0b00; // type
205 def s : T2sI<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
206 opc, ".w\t$dst, $src",
207 [(set GPR:$dst, (opnode t2_so_reg:$src))]> {
208 let Inst{31-27} = 0b11101;
209 let Inst{26-25} = 0b01;
210 let Inst{24-21} = opcod;
211 let Inst{20} = ?; // The S bit.
212 let Inst{19-16} = 0b1111; // Rn
216 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
217 /// binary operation that produces a value. These are predicable and can be
218 /// changed to modify CPSR.
219 multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
220 bit Commutable = 0, string wide =""> {
222 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
223 opc, "\t$dst, $lhs, $rhs",
224 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
225 let Inst{31-27} = 0b11110;
227 let Inst{24-21} = opcod;
228 let Inst{20} = ?; // The S bit.
232 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
233 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
234 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
235 let isCommutable = Commutable;
236 let Inst{31-27} = 0b11101;
237 let Inst{26-25} = 0b01;
238 let Inst{24-21} = opcod;
239 let Inst{20} = ?; // The S bit.
240 let Inst{14-12} = 0b000; // imm3
241 let Inst{7-6} = 0b00; // imm2
242 let Inst{5-4} = 0b00; // type
245 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
246 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
247 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
248 let Inst{31-27} = 0b11101;
249 let Inst{26-25} = 0b01;
250 let Inst{24-21} = opcod;
251 let Inst{20} = ?; // The S bit.
255 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
256 // the ".w" prefix to indicate that they are wide.
257 multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
258 bit Commutable = 0> :
259 T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
261 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
262 /// reversed. It doesn't define the 'rr' form since it's handled by its
263 /// T2I_bin_irs counterpart.
264 multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> {
266 def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
267 opc, ".w\t$dst, $rhs, $lhs",
268 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
269 let Inst{31-27} = 0b11110;
271 let Inst{24-21} = opcod;
272 let Inst{20} = ?; // The S bit.
276 def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
277 opc, "\t$dst, $rhs, $lhs",
278 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
279 let Inst{31-27} = 0b11101;
280 let Inst{26-25} = 0b01;
281 let Inst{24-21} = opcod;
282 let Inst{20} = ?; // The S bit.
286 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
287 /// instruction modifies the CPSR register.
288 let Defs = [CPSR] in {
289 multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
290 bit Commutable = 0> {
292 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
293 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
294 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
295 let Inst{31-27} = 0b11110;
297 let Inst{24-21} = opcod;
298 let Inst{20} = 1; // The S bit.
302 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
303 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
304 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
305 let isCommutable = Commutable;
306 let Inst{31-27} = 0b11101;
307 let Inst{26-25} = 0b01;
308 let Inst{24-21} = opcod;
309 let Inst{20} = 1; // The S bit.
310 let Inst{14-12} = 0b000; // imm3
311 let Inst{7-6} = 0b00; // imm2
312 let Inst{5-4} = 0b00; // type
315 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
316 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
317 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
318 let Inst{31-27} = 0b11101;
319 let Inst{26-25} = 0b01;
320 let Inst{24-21} = opcod;
321 let Inst{20} = 1; // The S bit.
326 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
327 /// patterns for a binary operation that produces a value.
328 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
329 bit Commutable = 0> {
331 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
332 opc, ".w\t$dst, $lhs, $rhs",
333 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
334 let Inst{31-27} = 0b11110;
337 let Inst{23-21} = op23_21;
338 let Inst{20} = 0; // The S bit.
342 def ri12 : T2I<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
343 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
344 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
345 let Inst{31-27} = 0b11110;
348 let Inst{23-21} = op23_21;
349 let Inst{20} = 0; // The S bit.
353 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
354 opc, ".w\t$dst, $lhs, $rhs",
355 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
356 let isCommutable = Commutable;
357 let Inst{31-27} = 0b11101;
358 let Inst{26-25} = 0b01;
360 let Inst{23-21} = op23_21;
361 let Inst{20} = 0; // The S bit.
362 let Inst{14-12} = 0b000; // imm3
363 let Inst{7-6} = 0b00; // imm2
364 let Inst{5-4} = 0b00; // type
367 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
368 opc, ".w\t$dst, $lhs, $rhs",
369 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
370 let Inst{31-27} = 0b11101;
371 let Inst{26-25} = 0b01;
373 let Inst{23-21} = op23_21;
374 let Inst{20} = 0; // The S bit.
378 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
379 /// for a binary operation that produces a value and use the carry
380 /// bit. It's not predicable.
381 let Uses = [CPSR] in {
382 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
383 bit Commutable = 0> {
385 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
386 opc, "\t$dst, $lhs, $rhs",
387 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
388 Requires<[IsThumb2]> {
389 let Inst{31-27} = 0b11110;
391 let Inst{24-21} = opcod;
392 let Inst{20} = 0; // The S bit.
396 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
397 opc, ".w\t$dst, $lhs, $rhs",
398 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
399 Requires<[IsThumb2]> {
400 let isCommutable = Commutable;
401 let Inst{31-27} = 0b11101;
402 let Inst{26-25} = 0b01;
403 let Inst{24-21} = opcod;
404 let Inst{20} = 0; // The S bit.
405 let Inst{14-12} = 0b000; // imm3
406 let Inst{7-6} = 0b00; // imm2
407 let Inst{5-4} = 0b00; // type
410 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
411 opc, ".w\t$dst, $lhs, $rhs",
412 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
413 Requires<[IsThumb2]> {
414 let Inst{31-27} = 0b11101;
415 let Inst{26-25} = 0b01;
416 let Inst{24-21} = opcod;
417 let Inst{20} = 0; // The S bit.
421 // Carry setting variants
422 let Defs = [CPSR] in {
423 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
424 bit Commutable = 0> {
426 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
427 opc, "\t$dst, $lhs, $rhs",
428 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
429 Requires<[IsThumb2]> {
430 let Inst{31-27} = 0b11110;
432 let Inst{24-21} = opcod;
433 let Inst{20} = 1; // The S bit.
437 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
438 opc, ".w\t$dst, $lhs, $rhs",
439 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
440 Requires<[IsThumb2]> {
441 let isCommutable = Commutable;
442 let Inst{31-27} = 0b11101;
443 let Inst{26-25} = 0b01;
444 let Inst{24-21} = opcod;
445 let Inst{20} = 1; // The S bit.
446 let Inst{14-12} = 0b000; // imm3
447 let Inst{7-6} = 0b00; // imm2
448 let Inst{5-4} = 0b00; // type
451 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
452 opc, ".w\t$dst, $lhs, $rhs",
453 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
454 Requires<[IsThumb2]> {
455 let Inst{31-27} = 0b11101;
456 let Inst{26-25} = 0b01;
457 let Inst{24-21} = opcod;
458 let Inst{20} = 1; // The S bit.
464 /// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
465 let Defs = [CPSR] in {
466 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
468 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
469 !strconcat(opc, "s"), ".w\t$dst, $rhs, $lhs",
470 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
471 let Inst{31-27} = 0b11110;
473 let Inst{24-21} = opcod;
474 let Inst{20} = 1; // The S bit.
478 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
479 !strconcat(opc, "s"), "\t$dst, $rhs, $lhs",
480 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
481 let Inst{31-27} = 0b11101;
482 let Inst{26-25} = 0b01;
483 let Inst{24-21} = opcod;
484 let Inst{20} = 1; // The S bit.
489 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
490 // rotate operation that produces a value.
491 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
493 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
494 opc, ".w\t$dst, $lhs, $rhs",
495 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]> {
496 let Inst{31-27} = 0b11101;
497 let Inst{26-21} = 0b010010;
498 let Inst{19-16} = 0b1111; // Rn
499 let Inst{5-4} = opcod;
502 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr,
503 opc, ".w\t$dst, $lhs, $rhs",
504 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
505 let Inst{31-27} = 0b11111;
506 let Inst{26-23} = 0b0100;
507 let Inst{22-21} = opcod;
508 let Inst{15-12} = 0b1111;
509 let Inst{7-4} = 0b0000;
513 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
514 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
515 /// a explicit result, only implicitly set CPSR.
516 let Defs = [CPSR] in {
517 multiclass T2I_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
519 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
520 opc, ".w\t$lhs, $rhs",
521 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> {
522 let Inst{31-27} = 0b11110;
524 let Inst{24-21} = opcod;
525 let Inst{20} = 1; // The S bit.
527 let Inst{11-8} = 0b1111; // Rd
530 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
531 opc, ".w\t$lhs, $rhs",
532 [(opnode GPR:$lhs, GPR:$rhs)]> {
533 let Inst{31-27} = 0b11101;
534 let Inst{26-25} = 0b01;
535 let Inst{24-21} = opcod;
536 let Inst{20} = 1; // The S bit.
537 let Inst{14-12} = 0b000; // imm3
538 let Inst{11-8} = 0b1111; // Rd
539 let Inst{7-6} = 0b00; // imm2
540 let Inst{5-4} = 0b00; // type
543 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
544 opc, ".w\t$lhs, $rhs",
545 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> {
546 let Inst{31-27} = 0b11101;
547 let Inst{26-25} = 0b01;
548 let Inst{24-21} = opcod;
549 let Inst{20} = 1; // The S bit.
550 let Inst{11-8} = 0b1111; // Rd
555 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
556 multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> {
557 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
558 opc, ".w\t$dst, $addr",
559 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
560 let Inst{31-27} = 0b11111;
561 let Inst{26-25} = 0b00;
562 let Inst{24} = signed;
564 let Inst{22-21} = opcod;
565 let Inst{20} = 1; // load
567 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
568 opc, "\t$dst, $addr",
569 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
570 let Inst{31-27} = 0b11111;
571 let Inst{26-25} = 0b00;
572 let Inst{24} = signed;
574 let Inst{22-21} = opcod;
575 let Inst{20} = 1; // load
577 // Offset: index==TRUE, wback==FALSE
578 let Inst{10} = 1; // The P bit.
579 let Inst{8} = 0; // The W bit.
581 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
582 opc, ".w\t$dst, $addr",
583 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
584 let Inst{31-27} = 0b11111;
585 let Inst{26-25} = 0b00;
586 let Inst{24} = signed;
588 let Inst{22-21} = opcod;
589 let Inst{20} = 1; // load
590 let Inst{11-6} = 0b000000;
592 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
593 opc, ".w\t$dst, $addr",
594 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
595 let isReMaterializable = 1;
596 let Inst{31-27} = 0b11111;
597 let Inst{26-25} = 0b00;
598 let Inst{24} = signed;
599 let Inst{23} = ?; // add = (U == '1')
600 let Inst{22-21} = opcod;
601 let Inst{20} = 1; // load
602 let Inst{19-16} = 0b1111; // Rn
606 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
607 multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> {
608 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
609 opc, ".w\t$src, $addr",
610 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
611 let Inst{31-27} = 0b11111;
612 let Inst{26-23} = 0b0001;
613 let Inst{22-21} = opcod;
614 let Inst{20} = 0; // !load
616 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
617 opc, "\t$src, $addr",
618 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
619 let Inst{31-27} = 0b11111;
620 let Inst{26-23} = 0b0000;
621 let Inst{22-21} = opcod;
622 let Inst{20} = 0; // !load
624 // Offset: index==TRUE, wback==FALSE
625 let Inst{10} = 1; // The P bit.
626 let Inst{8} = 0; // The W bit.
628 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
629 opc, ".w\t$src, $addr",
630 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
631 let Inst{31-27} = 0b11111;
632 let Inst{26-23} = 0b0000;
633 let Inst{22-21} = opcod;
634 let Inst{20} = 0; // !load
635 let Inst{11-6} = 0b000000;
639 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
640 /// register and one whose operand is a register rotated by 8/16/24.
641 multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
642 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
643 opc, ".w\t$dst, $src",
644 [(set GPR:$dst, (opnode GPR:$src))]> {
645 let Inst{31-27} = 0b11111;
646 let Inst{26-23} = 0b0100;
647 let Inst{22-20} = opcod;
648 let Inst{19-16} = 0b1111; // Rn
649 let Inst{15-12} = 0b1111;
651 let Inst{5-4} = 0b00; // rotate
653 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
654 opc, ".w\t$dst, $src, ror $rot",
655 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]> {
656 let Inst{31-27} = 0b11111;
657 let Inst{26-23} = 0b0100;
658 let Inst{22-20} = opcod;
659 let Inst{19-16} = 0b1111; // Rn
660 let Inst{15-12} = 0b1111;
662 let Inst{5-4} = {?,?}; // rotate
666 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
667 multiclass T2I_unary_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
668 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
670 [(set GPR:$dst, (opnode GPR:$src))]>,
671 Requires<[HasT2ExtractPack]> {
672 let Inst{31-27} = 0b11111;
673 let Inst{26-23} = 0b0100;
674 let Inst{22-20} = opcod;
675 let Inst{19-16} = 0b1111; // Rn
676 let Inst{15-12} = 0b1111;
678 let Inst{5-4} = 0b00; // rotate
680 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
681 opc, "\t$dst, $src, ror $rot",
682 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
683 Requires<[HasT2ExtractPack]> {
684 let Inst{31-27} = 0b11111;
685 let Inst{26-23} = 0b0100;
686 let Inst{22-20} = opcod;
687 let Inst{19-16} = 0b1111; // Rn
688 let Inst{15-12} = 0b1111;
690 let Inst{5-4} = {?,?}; // rotate
694 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
696 multiclass T2I_unary_rrot_sxtb16<bits<3> opcod, string opc> {
697 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
698 opc, "\t$dst, $src", []> {
699 let Inst{31-27} = 0b11111;
700 let Inst{26-23} = 0b0100;
701 let Inst{22-20} = opcod;
702 let Inst{19-16} = 0b1111; // Rn
703 let Inst{15-12} = 0b1111;
705 let Inst{5-4} = 0b00; // rotate
707 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
708 opc, "\t$dst, $src, ror $rot", []> {
709 let Inst{31-27} = 0b11111;
710 let Inst{26-23} = 0b0100;
711 let Inst{22-20} = opcod;
712 let Inst{19-16} = 0b1111; // Rn
713 let Inst{15-12} = 0b1111;
715 let Inst{5-4} = {?,?}; // rotate
719 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
720 /// register and one whose operand is a register rotated by 8/16/24.
721 multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
722 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
723 opc, "\t$dst, $LHS, $RHS",
724 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
725 Requires<[HasT2ExtractPack]> {
726 let Inst{31-27} = 0b11111;
727 let Inst{26-23} = 0b0100;
728 let Inst{22-20} = opcod;
729 let Inst{15-12} = 0b1111;
731 let Inst{5-4} = 0b00; // rotate
733 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
734 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
735 [(set GPR:$dst, (opnode GPR:$LHS,
736 (rotr GPR:$RHS, rot_imm:$rot)))]>,
737 Requires<[HasT2ExtractPack]> {
738 let Inst{31-27} = 0b11111;
739 let Inst{26-23} = 0b0100;
740 let Inst{22-20} = opcod;
741 let Inst{15-12} = 0b1111;
743 let Inst{5-4} = {?,?}; // rotate
747 // DO variant - disassembly only, no pattern
749 multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> {
750 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
751 opc, "\t$dst, $LHS, $RHS", []> {
752 let Inst{31-27} = 0b11111;
753 let Inst{26-23} = 0b0100;
754 let Inst{22-20} = opcod;
755 let Inst{15-12} = 0b1111;
757 let Inst{5-4} = 0b00; // rotate
759 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
760 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> {
761 let Inst{31-27} = 0b11111;
762 let Inst{26-23} = 0b0100;
763 let Inst{22-20} = opcod;
764 let Inst{15-12} = 0b1111;
766 let Inst{5-4} = {?,?}; // rotate
770 //===----------------------------------------------------------------------===//
772 //===----------------------------------------------------------------------===//
774 //===----------------------------------------------------------------------===//
775 // Miscellaneous Instructions.
778 // LEApcrel - Load a pc-relative address into a register without offending the
780 let neverHasSideEffects = 1 in {
781 let isReMaterializable = 1 in
782 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
783 "adr$p.w\t$dst, #$label", []> {
784 let Inst{31-27} = 0b11110;
785 let Inst{25-24} = 0b10;
786 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
789 let Inst{19-16} = 0b1111; // Rn
792 } // neverHasSideEffects
793 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
794 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
795 "adr$p.w\t$dst, #${label}_${id}", []> {
796 let Inst{31-27} = 0b11110;
797 let Inst{25-24} = 0b10;
798 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
801 let Inst{19-16} = 0b1111; // Rn
805 // ADD r, sp, {so_imm|i12}
806 def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
807 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> {
808 let Inst{31-27} = 0b11110;
810 let Inst{24-21} = 0b1000;
811 let Inst{20} = ?; // The S bit.
812 let Inst{19-16} = 0b1101; // Rn = sp
815 def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
816 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> {
817 let Inst{31-27} = 0b11110;
819 let Inst{24-21} = 0b0000;
820 let Inst{20} = 0; // The S bit.
821 let Inst{19-16} = 0b1101; // Rn = sp
826 def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
827 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> {
828 let Inst{31-27} = 0b11101;
829 let Inst{26-25} = 0b01;
830 let Inst{24-21} = 0b1000;
831 let Inst{20} = ?; // The S bit.
832 let Inst{19-16} = 0b1101; // Rn = sp
836 // SUB r, sp, {so_imm|i12}
837 def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
838 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> {
839 let Inst{31-27} = 0b11110;
841 let Inst{24-21} = 0b1101;
842 let Inst{20} = ?; // The S bit.
843 let Inst{19-16} = 0b1101; // Rn = sp
846 def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
847 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> {
848 let Inst{31-27} = 0b11110;
850 let Inst{24-21} = 0b0101;
851 let Inst{20} = 0; // The S bit.
852 let Inst{19-16} = 0b1101; // Rn = sp
857 def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
859 "sub", "\t$dst, $sp, $rhs", []> {
860 let Inst{31-27} = 0b11101;
861 let Inst{26-25} = 0b01;
862 let Inst{24-21} = 0b1101;
863 let Inst{20} = ?; // The S bit.
864 let Inst{19-16} = 0b1101; // Rn = sp
868 // Signed and unsigned division on v7-M
869 def t2SDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
870 "sdiv", "\t$dst, $a, $b",
871 [(set GPR:$dst, (sdiv GPR:$a, GPR:$b))]>,
872 Requires<[HasDivide]> {
873 let Inst{31-27} = 0b11111;
874 let Inst{26-21} = 0b011100;
876 let Inst{15-12} = 0b1111;
877 let Inst{7-4} = 0b1111;
880 def t2UDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
881 "udiv", "\t$dst, $a, $b",
882 [(set GPR:$dst, (udiv GPR:$a, GPR:$b))]>,
883 Requires<[HasDivide]> {
884 let Inst{31-27} = 0b11111;
885 let Inst{26-21} = 0b011101;
887 let Inst{15-12} = 0b1111;
888 let Inst{7-4} = 0b1111;
891 // Pseudo instruction that will expand into a t2SUBrSPi + a copy.
892 let usesCustomInserter = 1 in { // Expanded after instruction selection.
893 def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
894 NoItinerary, "${:comment} sub.w\t$dst, $sp, $imm", []>;
895 def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
896 NoItinerary, "${:comment} subw\t$dst, $sp, $imm", []>;
897 def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
898 NoItinerary, "${:comment} sub\t$dst, $sp, $rhs", []>;
899 } // usesCustomInserter
902 //===----------------------------------------------------------------------===//
903 // Load / store Instructions.
907 let canFoldAsLoad = 1, isReMaterializable = 1 in
908 defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>;
910 // Loads with zero extension
911 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
912 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
914 // Loads with sign extension
915 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
916 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
918 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
920 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
921 (ins t2addrmode_imm8s4:$addr),
922 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
923 def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
924 (ins i32imm:$addr), IIC_iLoadi,
925 "ldrd", "\t$dst1, $addr", []> {
926 let Inst{19-16} = 0b1111; // Rn
928 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
930 // zextload i1 -> zextload i8
931 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
932 (t2LDRBi12 t2addrmode_imm12:$addr)>;
933 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
934 (t2LDRBi8 t2addrmode_imm8:$addr)>;
935 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
936 (t2LDRBs t2addrmode_so_reg:$addr)>;
937 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
938 (t2LDRBpci tconstpool:$addr)>;
940 // extload -> zextload
941 // FIXME: Reduce the number of patterns by legalizing extload to zextload
943 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
944 (t2LDRBi12 t2addrmode_imm12:$addr)>;
945 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
946 (t2LDRBi8 t2addrmode_imm8:$addr)>;
947 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
948 (t2LDRBs t2addrmode_so_reg:$addr)>;
949 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
950 (t2LDRBpci tconstpool:$addr)>;
952 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
953 (t2LDRBi12 t2addrmode_imm12:$addr)>;
954 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
955 (t2LDRBi8 t2addrmode_imm8:$addr)>;
956 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
957 (t2LDRBs t2addrmode_so_reg:$addr)>;
958 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
959 (t2LDRBpci tconstpool:$addr)>;
961 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
962 (t2LDRHi12 t2addrmode_imm12:$addr)>;
963 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
964 (t2LDRHi8 t2addrmode_imm8:$addr)>;
965 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
966 (t2LDRHs t2addrmode_so_reg:$addr)>;
967 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
968 (t2LDRHpci tconstpool:$addr)>;
971 let mayLoad = 1, neverHasSideEffects = 1 in {
972 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
973 (ins t2addrmode_imm8:$addr),
974 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
975 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
978 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb),
979 (ins GPR:$base, t2am_imm8_offset:$offset),
980 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
981 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
984 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
985 (ins t2addrmode_imm8:$addr),
986 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
987 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
989 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
990 (ins GPR:$base, t2am_imm8_offset:$offset),
991 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
992 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
995 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
996 (ins t2addrmode_imm8:$addr),
997 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
998 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
1000 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1001 (ins GPR:$base, t2am_imm8_offset:$offset),
1002 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1003 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
1006 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1007 (ins t2addrmode_imm8:$addr),
1008 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1009 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
1011 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1012 (ins GPR:$base, t2am_imm8_offset:$offset),
1013 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1014 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
1017 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1018 (ins t2addrmode_imm8:$addr),
1019 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1020 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
1022 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1023 (ins GPR:$base, t2am_imm8_offset:$offset),
1024 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1025 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
1027 } // mayLoad = 1, neverHasSideEffects = 1
1029 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1030 // for disassembly only.
1031 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1032 class T2IldT<bit signed, bits<2> type, string opc>
1033 : T2Ii8<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, opc,
1034 "\t$dst, $addr", []> {
1035 let Inst{31-27} = 0b11111;
1036 let Inst{26-25} = 0b00;
1037 let Inst{24} = signed;
1039 let Inst{22-21} = type;
1040 let Inst{20} = 1; // load
1042 let Inst{10-8} = 0b110; // PUW.
1045 def t2LDRT : T2IldT<0, 0b10, "ldrt">;
1046 def t2LDRBT : T2IldT<0, 0b00, "ldrbt">;
1047 def t2LDRHT : T2IldT<0, 0b01, "ldrht">;
1048 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt">;
1049 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht">;
1052 defm t2STR :T2I_st<0b10,"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
1053 defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1054 defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1057 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1058 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1059 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
1060 IIC_iStorer, "strd", "\t$src1, $addr", []>;
1063 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1064 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1065 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1066 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1068 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1070 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1071 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1072 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1073 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1075 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1077 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1078 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1079 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1080 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1082 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1084 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1085 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1086 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1087 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1089 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1091 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1092 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1093 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1094 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1096 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1098 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1099 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1100 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1101 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1103 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1105 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1107 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1108 class T2IstT<bits<2> type, string opc>
1109 : T2Ii8<(outs GPR:$src), (ins t2addrmode_imm8:$addr), IIC_iStorei, opc,
1110 "\t$src, $addr", []> {
1111 let Inst{31-27} = 0b11111;
1112 let Inst{26-25} = 0b00;
1113 let Inst{24} = 0; // not signed
1115 let Inst{22-21} = type;
1116 let Inst{20} = 0; // store
1118 let Inst{10-8} = 0b110; // PUW
1121 def t2STRT : T2IstT<0b10, "strt">;
1122 def t2STRBT : T2IstT<0b00, "strbt">;
1123 def t2STRHT : T2IstT<0b01, "strht">;
1125 // ldrd / strd pre / post variants
1126 // For disassembly only.
1128 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1129 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1130 "ldrd", "\t$dst1, $dst2, [$base, $imm]!", []>;
1132 def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1133 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1134 "ldrd", "\t$dst1, $dst2, [$base], $imm", []>;
1136 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
1137 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1138 NoItinerary, "strd", "\t$src1, $src2, [$base, $imm]!", []>;
1140 def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1141 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1142 NoItinerary, "strd", "\t$src1, $src2, [$base], $imm", []>;
1144 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1145 // data/instruction access. These are for disassembly only.
1147 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
1148 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
1149 multiclass T2Ipl<bit instr, bit write, string opc> {
1151 def i12 : T2I<(outs), (ins GPR:$base, i32imm:$imm), IIC_iLoadi, opc,
1152 "\t[$base, $imm]", []> {
1153 let Inst{31-25} = 0b1111100;
1154 let Inst{24} = instr;
1155 let Inst{23} = 1; // U = 1
1157 let Inst{21} = write;
1159 let Inst{15-12} = 0b1111;
1162 def i8 : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1163 "\t[$base, $imm]", []> {
1164 let Inst{31-25} = 0b1111100;
1165 let Inst{24} = instr;
1166 let Inst{23} = 0; // U = 0
1168 let Inst{21} = write;
1170 let Inst{15-12} = 0b1111;
1171 let Inst{11-8} = 0b1100;
1174 def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1175 "\t[pc, $imm]", []> {
1176 let Inst{31-25} = 0b1111100;
1177 let Inst{24} = instr;
1178 let Inst{23} = ?; // add = (U == 1)
1180 let Inst{21} = write;
1182 let Inst{19-16} = 0b1111; // Rn = 0b1111
1183 let Inst{15-12} = 0b1111;
1186 def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoadi, opc,
1187 "\t[$base, $a]", []> {
1188 let Inst{31-25} = 0b1111100;
1189 let Inst{24} = instr;
1190 let Inst{23} = 0; // add = TRUE for T1
1192 let Inst{21} = write;
1194 let Inst{15-12} = 0b1111;
1195 let Inst{11-6} = 0000000;
1196 let Inst{5-4} = 0b00; // no shift is applied
1199 def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoadi, opc,
1200 "\t[$base, $a, lsl $shamt]", []> {
1201 let Inst{31-25} = 0b1111100;
1202 let Inst{24} = instr;
1203 let Inst{23} = 0; // add = TRUE for T1
1205 let Inst{21} = write;
1207 let Inst{15-12} = 0b1111;
1208 let Inst{11-6} = 0000000;
1212 defm t2PLD : T2Ipl<0, 0, "pld">;
1213 defm t2PLDW : T2Ipl<0, 1, "pldw">;
1214 defm t2PLI : T2Ipl<1, 0, "pli">;
1216 //===----------------------------------------------------------------------===//
1217 // Load / store multiple Instructions.
1220 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1221 def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1222 reglist:$dsts, variable_ops), IIC_iLoadm,
1223 "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> {
1224 let Inst{31-27} = 0b11101;
1225 let Inst{26-25} = 0b00;
1226 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1228 let Inst{21} = 0; // The W bit.
1229 let Inst{20} = 1; // Load
1232 def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1233 reglist:$dsts, variable_ops), IIC_iLoadm,
1234 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
1235 "$addr.addr = $wb", []> {
1236 let Inst{31-27} = 0b11101;
1237 let Inst{26-25} = 0b00;
1238 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1240 let Inst{21} = 1; // The W bit.
1241 let Inst{20} = 1; // Load
1243 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1245 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1246 def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1247 reglist:$srcs, variable_ops), IIC_iStorem,
1248 "stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> {
1249 let Inst{31-27} = 0b11101;
1250 let Inst{26-25} = 0b00;
1251 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1253 let Inst{21} = 0; // The W bit.
1254 let Inst{20} = 0; // Store
1257 def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1258 reglist:$srcs, variable_ops),
1260 "stm${addr:submode}${p}${addr:wide}\t$addr!, $srcs",
1261 "$addr.addr = $wb", []> {
1262 let Inst{31-27} = 0b11101;
1263 let Inst{26-25} = 0b00;
1264 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1266 let Inst{21} = 1; // The W bit.
1267 let Inst{20} = 0; // Store
1269 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1271 //===----------------------------------------------------------------------===//
1272 // Move Instructions.
1275 let neverHasSideEffects = 1 in
1276 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
1277 "mov", ".w\t$dst, $src", []> {
1278 let Inst{31-27} = 0b11101;
1279 let Inst{26-25} = 0b01;
1280 let Inst{24-21} = 0b0010;
1281 let Inst{20} = ?; // The S bit.
1282 let Inst{19-16} = 0b1111; // Rn
1283 let Inst{14-12} = 0b000;
1284 let Inst{7-4} = 0b0000;
1287 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1288 let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
1289 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
1290 "mov", ".w\t$dst, $src",
1291 [(set GPR:$dst, t2_so_imm:$src)]> {
1292 let Inst{31-27} = 0b11110;
1294 let Inst{24-21} = 0b0010;
1295 let Inst{20} = ?; // The S bit.
1296 let Inst{19-16} = 0b1111; // Rn
1300 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1301 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1302 "movw", "\t$dst, $src",
1303 [(set GPR:$dst, imm0_65535:$src)]> {
1304 let Inst{31-27} = 0b11110;
1306 let Inst{24-21} = 0b0010;
1307 let Inst{20} = 0; // The S bit.
1311 let Constraints = "$src = $dst" in
1312 def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi,
1313 "movt", "\t$dst, $imm",
1315 (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]> {
1316 let Inst{31-27} = 0b11110;
1318 let Inst{24-21} = 0b0110;
1319 let Inst{20} = 0; // The S bit.
1323 def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>;
1325 //===----------------------------------------------------------------------===//
1326 // Extend Instructions.
1331 defm t2SXTB : T2I_unary_rrot<0b100, "sxtb",
1332 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1333 defm t2SXTH : T2I_unary_rrot<0b000, "sxth",
1334 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1335 defm t2SXTB16 : T2I_unary_rrot_sxtb16<0b010, "sxtb16">;
1337 defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab",
1338 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1339 defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah",
1340 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1341 defm t2SXTAB16 : T2I_bin_rrot_DO<0b010, "sxtab16">;
1343 // TODO: SXT(A){B|H}16 - done for disassembly only
1347 let AddedComplexity = 16 in {
1348 defm t2UXTB : T2I_unary_rrot<0b101, "uxtb",
1349 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1350 defm t2UXTH : T2I_unary_rrot<0b001, "uxth",
1351 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1352 defm t2UXTB16 : T2I_unary_rrot_uxtb16<0b011, "uxtb16",
1353 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1355 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1356 // The transformation should probably be done as a combiner action
1357 // instead so we can include a check for masking back in the upper
1358 // eight bits of the source into the lower eight bits of the result.
1359 //def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1360 // (t2UXTB16r_rot GPR:$Src, 24)>, Requires<[HasT2ExtractPack]>;
1361 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1362 (t2UXTB16r_rot GPR:$Src, 8)>, Requires<[HasT2ExtractPack]>;
1364 defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
1365 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1366 defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah",
1367 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1368 defm t2UXTAB16 : T2I_bin_rrot_DO<0b011, "uxtab16">;
1371 //===----------------------------------------------------------------------===//
1372 // Arithmetic Instructions.
1375 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1376 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1377 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1378 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1380 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1381 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1382 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1383 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1384 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1386 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1387 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1388 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1389 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1390 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1391 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1392 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1393 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1396 defm t2RSB : T2I_rbin_is <0b1110, "rsb",
1397 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1398 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1399 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1401 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1402 // The assume-no-carry-in form uses the negation of the input since add/sub
1403 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1404 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1406 // The AddedComplexity preferences the first variant over the others since
1407 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1408 let AddedComplexity = 1 in
1409 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1410 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1411 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1412 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1413 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1414 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1415 let AddedComplexity = 1 in
1416 def : T2Pat<(addc GPR:$src, imm0_255_neg:$imm),
1417 (t2SUBSri GPR:$src, imm0_255_neg:$imm)>;
1418 def : T2Pat<(addc GPR:$src, t2_so_imm_neg:$imm),
1419 (t2SUBSri GPR:$src, t2_so_imm_neg:$imm)>;
1420 // The with-carry-in form matches bitwise not instead of the negation.
1421 // Effectively, the inverse interpretation of the carry flag already accounts
1422 // for part of the negation.
1423 let AddedComplexity = 1 in
1424 def : T2Pat<(adde GPR:$src, imm0_255_not:$imm),
1425 (t2SBCSri GPR:$src, imm0_255_not:$imm)>;
1426 def : T2Pat<(adde GPR:$src, t2_so_imm_not:$imm),
1427 (t2SBCSri GPR:$src, t2_so_imm_not:$imm)>;
1429 // Select Bytes -- for disassembly only
1431 def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel",
1432 "\t$dst, $a, $b", []> {
1433 let Inst{31-27} = 0b11111;
1434 let Inst{26-24} = 0b010;
1436 let Inst{22-20} = 0b010;
1437 let Inst{15-12} = 0b1111;
1439 let Inst{6-4} = 0b000;
1442 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1443 // And Miscellaneous operations -- for disassembly only
1444 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1445 list<dag> pat = [/* For disassembly only; pattern left blank */]>
1446 : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, opc,
1447 "\t$dst, $a, $b", pat> {
1448 let Inst{31-27} = 0b11111;
1449 let Inst{26-23} = 0b0101;
1450 let Inst{22-20} = op22_20;
1451 let Inst{15-12} = 0b1111;
1452 let Inst{7-4} = op7_4;
1455 // Saturating add/subtract -- for disassembly only
1457 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1458 [(set GPR:$dst, (int_arm_qadd GPR:$a, GPR:$b))]>;
1459 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1460 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1461 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1462 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1463 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1464 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1465 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1466 [(set GPR:$dst, (int_arm_qsub GPR:$a, GPR:$b))]>;
1467 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1468 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1469 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1470 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1471 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1472 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1473 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1474 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1476 // Signed/Unsigned add/subtract -- for disassembly only
1478 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1479 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1480 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1481 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1482 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1483 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1484 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1485 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1486 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1487 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1488 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1489 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1491 // Signed/Unsigned halving add/subtract -- for disassembly only
1493 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1494 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1495 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1496 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1497 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1498 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1499 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1500 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1501 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1502 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1503 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1504 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1506 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1508 def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1509 NoItinerary, "usad8", "\t$dst, $a, $b", []> {
1510 let Inst{15-12} = 0b1111;
1512 def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst),
1513 (ins GPR:$a, GPR:$b, GPR:$acc), NoItinerary, "usada8",
1514 "\t$dst, $a, $b, $acc", []>;
1516 // Signed/Unsigned saturate -- for disassembly only
1518 def t2SSATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1519 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
1520 [/* For disassembly only; pattern left blank */]> {
1521 let Inst{31-27} = 0b11110;
1522 let Inst{25-22} = 0b1100;
1525 let Inst{21} = 0; // sh = '0'
1528 def t2SSATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1529 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt",
1530 [/* For disassembly only; pattern left blank */]> {
1531 let Inst{31-27} = 0b11110;
1532 let Inst{25-22} = 0b1100;
1535 let Inst{21} = 1; // sh = '1'
1538 def t2SSAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
1539 "ssat16", "\t$dst, $bit_pos, $a",
1540 [/* For disassembly only; pattern left blank */]> {
1541 let Inst{31-27} = 0b11110;
1542 let Inst{25-22} = 0b1100;
1545 let Inst{21} = 1; // sh = '1'
1546 let Inst{14-12} = 0b000; // imm3 = '000'
1547 let Inst{7-6} = 0b00; // imm2 = '00'
1550 def t2USATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1551 NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt",
1552 [/* For disassembly only; pattern left blank */]> {
1553 let Inst{31-27} = 0b11110;
1554 let Inst{25-22} = 0b1110;
1557 let Inst{21} = 0; // sh = '0'
1560 def t2USATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1561 NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt",
1562 [/* For disassembly only; pattern left blank */]> {
1563 let Inst{31-27} = 0b11110;
1564 let Inst{25-22} = 0b1110;
1567 let Inst{21} = 1; // sh = '1'
1570 def t2USAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
1571 "usat16", "\t$dst, $bit_pos, $a",
1572 [/* For disassembly only; pattern left blank */]> {
1573 let Inst{31-27} = 0b11110;
1574 let Inst{25-22} = 0b1110;
1577 let Inst{21} = 1; // sh = '1'
1578 let Inst{14-12} = 0b000; // imm3 = '000'
1579 let Inst{7-6} = 0b00; // imm2 = '00'
1582 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSATlsl imm:$pos, GPR:$a, 0)>;
1583 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USATlsl imm:$pos, GPR:$a, 0)>;
1585 //===----------------------------------------------------------------------===//
1586 // Shift and rotate Instructions.
1589 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1590 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1591 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1592 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1594 let Uses = [CPSR] in {
1595 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1596 "rrx", "\t$dst, $src",
1597 [(set GPR:$dst, (ARMrrx GPR:$src))]> {
1598 let Inst{31-27} = 0b11101;
1599 let Inst{26-25} = 0b01;
1600 let Inst{24-21} = 0b0010;
1601 let Inst{20} = ?; // The S bit.
1602 let Inst{19-16} = 0b1111; // Rn
1603 let Inst{14-12} = 0b000;
1604 let Inst{7-4} = 0b0011;
1608 let Defs = [CPSR] in {
1609 def t2MOVsrl_flag : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1610 "lsrs", ".w\t$dst, $src, #1",
1611 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]> {
1612 let Inst{31-27} = 0b11101;
1613 let Inst{26-25} = 0b01;
1614 let Inst{24-21} = 0b0010;
1615 let Inst{20} = 1; // The S bit.
1616 let Inst{19-16} = 0b1111; // Rn
1617 let Inst{5-4} = 0b01; // Shift type.
1618 // Shift amount = Inst{14-12:7-6} = 1.
1619 let Inst{14-12} = 0b000;
1620 let Inst{7-6} = 0b01;
1622 def t2MOVsra_flag : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1623 "asrs", ".w\t$dst, $src, #1",
1624 [(set GPR:$dst, (ARMsra_flag GPR:$src))]> {
1625 let Inst{31-27} = 0b11101;
1626 let Inst{26-25} = 0b01;
1627 let Inst{24-21} = 0b0010;
1628 let Inst{20} = 1; // The S bit.
1629 let Inst{19-16} = 0b1111; // Rn
1630 let Inst{5-4} = 0b10; // Shift type.
1631 // Shift amount = Inst{14-12:7-6} = 1.
1632 let Inst{14-12} = 0b000;
1633 let Inst{7-6} = 0b01;
1637 //===----------------------------------------------------------------------===//
1638 // Bitwise Instructions.
1641 defm t2AND : T2I_bin_w_irs<0b0000, "and",
1642 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1643 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1644 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1645 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1646 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1648 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1649 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1651 let Constraints = "$src = $dst" in
1652 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1653 IIC_iUNAsi, "bfc", "\t$dst, $imm",
1654 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]> {
1655 let Inst{31-27} = 0b11110;
1657 let Inst{24-20} = 0b10110;
1658 let Inst{19-16} = 0b1111; // Rn
1662 def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1663 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
1664 let Inst{31-27} = 0b11110;
1666 let Inst{24-20} = 0b10100;
1670 def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1671 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
1672 let Inst{31-27} = 0b11110;
1674 let Inst{24-20} = 0b11100;
1678 // A8.6.18 BFI - Bitfield insert (Encoding T1)
1679 let Constraints = "$src = $dst" in
1680 def t2BFI : T2I<(outs GPR:$dst),
1681 (ins GPR:$src, GPR:$val, bf_inv_mask_imm:$imm),
1682 IIC_iALUi, "bfi", "\t$dst, $val, $imm",
1683 [(set GPR:$dst, (ARMbfi GPR:$src, GPR:$val,
1684 bf_inv_mask_imm:$imm))]> {
1685 let Inst{31-27} = 0b11110;
1687 let Inst{24-20} = 0b10110;
1691 defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS,
1694 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
1695 let AddedComplexity = 1 in
1696 defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
1699 let AddedComplexity = 1 in
1700 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
1701 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
1703 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
1704 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
1705 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>,
1706 Requires<[IsThumb2]>;
1708 def : T2Pat<(t2_so_imm_not:$src),
1709 (t2MVNi t2_so_imm_not:$src)>;
1711 //===----------------------------------------------------------------------===//
1712 // Multiply Instructions.
1714 let isCommutable = 1 in
1715 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1716 "mul", "\t$dst, $a, $b",
1717 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]> {
1718 let Inst{31-27} = 0b11111;
1719 let Inst{26-23} = 0b0110;
1720 let Inst{22-20} = 0b000;
1721 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1722 let Inst{7-4} = 0b0000; // Multiply
1725 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1726 "mla", "\t$dst, $a, $b, $c",
1727 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]> {
1728 let Inst{31-27} = 0b11111;
1729 let Inst{26-23} = 0b0110;
1730 let Inst{22-20} = 0b000;
1731 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1732 let Inst{7-4} = 0b0000; // Multiply
1735 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1736 "mls", "\t$dst, $a, $b, $c",
1737 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]> {
1738 let Inst{31-27} = 0b11111;
1739 let Inst{26-23} = 0b0110;
1740 let Inst{22-20} = 0b000;
1741 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1742 let Inst{7-4} = 0b0001; // Multiply and Subtract
1745 // Extra precision multiplies with low / high results
1746 let neverHasSideEffects = 1 in {
1747 let isCommutable = 1 in {
1748 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1749 "smull", "\t$ldst, $hdst, $a, $b", []> {
1750 let Inst{31-27} = 0b11111;
1751 let Inst{26-23} = 0b0111;
1752 let Inst{22-20} = 0b000;
1753 let Inst{7-4} = 0b0000;
1756 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1757 "umull", "\t$ldst, $hdst, $a, $b", []> {
1758 let Inst{31-27} = 0b11111;
1759 let Inst{26-23} = 0b0111;
1760 let Inst{22-20} = 0b010;
1761 let Inst{7-4} = 0b0000;
1765 // Multiply + accumulate
1766 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1767 "smlal", "\t$ldst, $hdst, $a, $b", []>{
1768 let Inst{31-27} = 0b11111;
1769 let Inst{26-23} = 0b0111;
1770 let Inst{22-20} = 0b100;
1771 let Inst{7-4} = 0b0000;
1774 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1775 "umlal", "\t$ldst, $hdst, $a, $b", []>{
1776 let Inst{31-27} = 0b11111;
1777 let Inst{26-23} = 0b0111;
1778 let Inst{22-20} = 0b110;
1779 let Inst{7-4} = 0b0000;
1782 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1783 "umaal", "\t$ldst, $hdst, $a, $b", []>{
1784 let Inst{31-27} = 0b11111;
1785 let Inst{26-23} = 0b0111;
1786 let Inst{22-20} = 0b110;
1787 let Inst{7-4} = 0b0110;
1789 } // neverHasSideEffects
1791 // Rounding variants of the below included for disassembly only
1793 // Most significant word multiply
1794 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1795 "smmul", "\t$dst, $a, $b",
1796 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]> {
1797 let Inst{31-27} = 0b11111;
1798 let Inst{26-23} = 0b0110;
1799 let Inst{22-20} = 0b101;
1800 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1801 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1804 def t2SMMULR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1805 "smmulr", "\t$dst, $a, $b", []> {
1806 let Inst{31-27} = 0b11111;
1807 let Inst{26-23} = 0b0110;
1808 let Inst{22-20} = 0b101;
1809 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1810 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1813 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1814 "smmla", "\t$dst, $a, $b, $c",
1815 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]> {
1816 let Inst{31-27} = 0b11111;
1817 let Inst{26-23} = 0b0110;
1818 let Inst{22-20} = 0b101;
1819 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1820 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1823 def t2SMMLAR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1824 "smmlar", "\t$dst, $a, $b, $c", []> {
1825 let Inst{31-27} = 0b11111;
1826 let Inst{26-23} = 0b0110;
1827 let Inst{22-20} = 0b101;
1828 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1829 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1832 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1833 "smmls", "\t$dst, $a, $b, $c",
1834 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]> {
1835 let Inst{31-27} = 0b11111;
1836 let Inst{26-23} = 0b0110;
1837 let Inst{22-20} = 0b110;
1838 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1839 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1842 def t2SMMLSR : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1843 "smmlsr", "\t$dst, $a, $b, $c", []> {
1844 let Inst{31-27} = 0b11111;
1845 let Inst{26-23} = 0b0110;
1846 let Inst{22-20} = 0b110;
1847 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1848 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1851 multiclass T2I_smul<string opc, PatFrag opnode> {
1852 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1853 !strconcat(opc, "bb"), "\t$dst, $a, $b",
1854 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1855 (sext_inreg GPR:$b, i16)))]> {
1856 let Inst{31-27} = 0b11111;
1857 let Inst{26-23} = 0b0110;
1858 let Inst{22-20} = 0b001;
1859 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1860 let Inst{7-6} = 0b00;
1861 let Inst{5-4} = 0b00;
1864 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1865 !strconcat(opc, "bt"), "\t$dst, $a, $b",
1866 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1867 (sra GPR:$b, (i32 16))))]> {
1868 let Inst{31-27} = 0b11111;
1869 let Inst{26-23} = 0b0110;
1870 let Inst{22-20} = 0b001;
1871 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1872 let Inst{7-6} = 0b00;
1873 let Inst{5-4} = 0b01;
1876 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1877 !strconcat(opc, "tb"), "\t$dst, $a, $b",
1878 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1879 (sext_inreg GPR:$b, i16)))]> {
1880 let Inst{31-27} = 0b11111;
1881 let Inst{26-23} = 0b0110;
1882 let Inst{22-20} = 0b001;
1883 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1884 let Inst{7-6} = 0b00;
1885 let Inst{5-4} = 0b10;
1888 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1889 !strconcat(opc, "tt"), "\t$dst, $a, $b",
1890 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1891 (sra GPR:$b, (i32 16))))]> {
1892 let Inst{31-27} = 0b11111;
1893 let Inst{26-23} = 0b0110;
1894 let Inst{22-20} = 0b001;
1895 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1896 let Inst{7-6} = 0b00;
1897 let Inst{5-4} = 0b11;
1900 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1901 !strconcat(opc, "wb"), "\t$dst, $a, $b",
1902 [(set GPR:$dst, (sra (opnode GPR:$a,
1903 (sext_inreg GPR:$b, i16)), (i32 16)))]> {
1904 let Inst{31-27} = 0b11111;
1905 let Inst{26-23} = 0b0110;
1906 let Inst{22-20} = 0b011;
1907 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1908 let Inst{7-6} = 0b00;
1909 let Inst{5-4} = 0b00;
1912 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1913 !strconcat(opc, "wt"), "\t$dst, $a, $b",
1914 [(set GPR:$dst, (sra (opnode GPR:$a,
1915 (sra GPR:$b, (i32 16))), (i32 16)))]> {
1916 let Inst{31-27} = 0b11111;
1917 let Inst{26-23} = 0b0110;
1918 let Inst{22-20} = 0b011;
1919 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1920 let Inst{7-6} = 0b00;
1921 let Inst{5-4} = 0b01;
1926 multiclass T2I_smla<string opc, PatFrag opnode> {
1927 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1928 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1929 [(set GPR:$dst, (add GPR:$acc,
1930 (opnode (sext_inreg GPR:$a, i16),
1931 (sext_inreg GPR:$b, i16))))]> {
1932 let Inst{31-27} = 0b11111;
1933 let Inst{26-23} = 0b0110;
1934 let Inst{22-20} = 0b001;
1935 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1936 let Inst{7-6} = 0b00;
1937 let Inst{5-4} = 0b00;
1940 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1941 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1942 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1943 (sra GPR:$b, (i32 16)))))]> {
1944 let Inst{31-27} = 0b11111;
1945 let Inst{26-23} = 0b0110;
1946 let Inst{22-20} = 0b001;
1947 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1948 let Inst{7-6} = 0b00;
1949 let Inst{5-4} = 0b01;
1952 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1953 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1954 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1955 (sext_inreg GPR:$b, i16))))]> {
1956 let Inst{31-27} = 0b11111;
1957 let Inst{26-23} = 0b0110;
1958 let Inst{22-20} = 0b001;
1959 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1960 let Inst{7-6} = 0b00;
1961 let Inst{5-4} = 0b10;
1964 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1965 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1966 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1967 (sra GPR:$b, (i32 16)))))]> {
1968 let Inst{31-27} = 0b11111;
1969 let Inst{26-23} = 0b0110;
1970 let Inst{22-20} = 0b001;
1971 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1972 let Inst{7-6} = 0b00;
1973 let Inst{5-4} = 0b11;
1976 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1977 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1978 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1979 (sext_inreg GPR:$b, i16)), (i32 16))))]> {
1980 let Inst{31-27} = 0b11111;
1981 let Inst{26-23} = 0b0110;
1982 let Inst{22-20} = 0b011;
1983 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1984 let Inst{7-6} = 0b00;
1985 let Inst{5-4} = 0b00;
1988 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1989 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1990 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1991 (sra GPR:$b, (i32 16))), (i32 16))))]> {
1992 let Inst{31-27} = 0b11111;
1993 let Inst{26-23} = 0b0110;
1994 let Inst{22-20} = 0b011;
1995 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1996 let Inst{7-6} = 0b00;
1997 let Inst{5-4} = 0b01;
2001 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2002 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2004 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2005 def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs GPR:$ldst,GPR:$hdst),
2006 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
2007 [/* For disassembly only; pattern left blank */]>;
2008 def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs GPR:$ldst,GPR:$hdst),
2009 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
2010 [/* For disassembly only; pattern left blank */]>;
2011 def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs GPR:$ldst,GPR:$hdst),
2012 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
2013 [/* For disassembly only; pattern left blank */]>;
2014 def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs GPR:$ldst,GPR:$hdst),
2015 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
2016 [/* For disassembly only; pattern left blank */]>;
2018 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2019 // These are for disassembly only.
2021 def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2022 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
2023 let Inst{15-12} = 0b1111;
2025 def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2026 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
2027 let Inst{15-12} = 0b1111;
2029 def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2030 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
2031 let Inst{15-12} = 0b1111;
2033 def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2034 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
2035 let Inst{15-12} = 0b1111;
2037 def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst),
2038 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlad",
2039 "\t$dst, $a, $b, $acc", []>;
2040 def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst),
2041 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smladx",
2042 "\t$dst, $a, $b, $acc", []>;
2043 def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst),
2044 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsd",
2045 "\t$dst, $a, $b, $acc", []>;
2046 def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst),
2047 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsdx",
2048 "\t$dst, $a, $b, $acc", []>;
2049 def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs GPR:$ldst,GPR:$hdst),
2050 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlald",
2051 "\t$ldst, $hdst, $a, $b", []>;
2052 def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs GPR:$ldst,GPR:$hdst),
2053 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaldx",
2054 "\t$ldst, $hdst, $a, $b", []>;
2055 def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs GPR:$ldst,GPR:$hdst),
2056 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsld",
2057 "\t$ldst, $hdst, $a, $b", []>;
2058 def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs GPR:$ldst,GPR:$hdst),
2059 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsldx",
2060 "\t$ldst, $hdst, $a, $b", []>;
2062 //===----------------------------------------------------------------------===//
2063 // Misc. Arithmetic Instructions.
2066 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2067 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2068 : T2I<oops, iops, itin, opc, asm, pattern> {
2069 let Inst{31-27} = 0b11111;
2070 let Inst{26-22} = 0b01010;
2071 let Inst{21-20} = op1;
2072 let Inst{15-12} = 0b1111;
2073 let Inst{7-6} = 0b10;
2074 let Inst{5-4} = op2;
2077 def t2CLZ : T2I_misc<0b11, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2078 "clz", "\t$dst, $src", [(set GPR:$dst, (ctlz GPR:$src))]>;
2080 def t2RBIT : T2I_misc<0b01, 0b10, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2081 "rbit", "\t$dst, $src",
2082 [(set GPR:$dst, (ARMrbit GPR:$src))]>;
2084 def t2REV : T2I_misc<0b01, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2085 "rev", ".w\t$dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>;
2087 def t2REV16 : T2I_misc<0b01, 0b01, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2088 "rev16", ".w\t$dst, $src",
2090 (or (and (srl GPR:$src, (i32 8)), 0xFF),
2091 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
2092 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
2093 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
2095 def t2REVSH : T2I_misc<0b01, 0b11, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2096 "revsh", ".w\t$dst, $src",
2099 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
2100 (shl GPR:$src, (i32 8))), i16))]>;
2102 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
2103 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt",
2104 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
2105 (and (shl GPR:$src2, (i32 imm:$shamt)),
2107 Requires<[HasT2ExtractPack]> {
2108 let Inst{31-27} = 0b11101;
2109 let Inst{26-25} = 0b01;
2110 let Inst{24-20} = 0b01100;
2111 let Inst{5} = 0; // BT form
2115 // Alternate cases for PKHBT where identities eliminate some nodes.
2116 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
2117 (t2PKHBT GPR:$src1, GPR:$src2, 0)>,
2118 Requires<[HasT2ExtractPack]>;
2119 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
2120 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>,
2121 Requires<[HasT2ExtractPack]>;
2123 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
2124 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
2125 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
2126 (and (sra GPR:$src2, imm16_31:$shamt),
2128 Requires<[HasT2ExtractPack]> {
2129 let Inst{31-27} = 0b11101;
2130 let Inst{26-25} = 0b01;
2131 let Inst{24-20} = 0b01100;
2132 let Inst{5} = 1; // TB form
2136 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2137 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2138 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
2139 (t2PKHTB GPR:$src1, GPR:$src2, 16)>,
2140 Requires<[HasT2ExtractPack]>;
2141 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
2142 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
2143 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>,
2144 Requires<[HasT2ExtractPack]>;
2146 //===----------------------------------------------------------------------===//
2147 // Comparison Instructions...
2150 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2151 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2152 defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
2153 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2155 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2156 // Compare-to-zero still works out, just not the relationals
2157 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2158 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2159 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2160 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2162 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2163 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2165 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2166 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2168 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2169 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
2170 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2171 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
2173 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
2174 // Short range conditional branch. Looks awesome for loops. Need to figure
2175 // out how to use this one.
2178 // Conditional moves
2179 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2180 // a two-value operand where a dag node expects two operands. :(
2181 let neverHasSideEffects = 1 in {
2182 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr,
2183 "mov", ".w\t$dst, $true",
2184 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
2185 RegConstraint<"$false = $dst"> {
2186 let Inst{31-27} = 0b11101;
2187 let Inst{26-25} = 0b01;
2188 let Inst{24-21} = 0b0010;
2189 let Inst{20} = 0; // The S bit.
2190 let Inst{19-16} = 0b1111; // Rn
2191 let Inst{14-12} = 0b000;
2192 let Inst{7-4} = 0b0000;
2195 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
2196 IIC_iCMOVi, "mov", ".w\t$dst, $true",
2197 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
2198 RegConstraint<"$false = $dst"> {
2199 let Inst{31-27} = 0b11110;
2201 let Inst{24-21} = 0b0010;
2202 let Inst{20} = 0; // The S bit.
2203 let Inst{19-16} = 0b1111; // Rn
2207 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2208 string opc, string asm, list<dag> pattern>
2209 : T2I<oops, iops, itin, opc, asm, pattern> {
2210 let Inst{31-27} = 0b11101;
2211 let Inst{26-25} = 0b01;
2212 let Inst{24-21} = 0b0010;
2213 let Inst{20} = 0; // The S bit.
2214 let Inst{19-16} = 0b1111; // Rn
2215 let Inst{5-4} = opcod; // Shift type.
2217 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs GPR:$dst),
2218 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2219 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
2220 RegConstraint<"$false = $dst">;
2221 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs GPR:$dst),
2222 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2223 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
2224 RegConstraint<"$false = $dst">;
2225 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs GPR:$dst),
2226 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2227 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
2228 RegConstraint<"$false = $dst">;
2229 def t2MOVCCror : T2I_movcc_sh<0b11, (outs GPR:$dst),
2230 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2231 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
2232 RegConstraint<"$false = $dst">;
2233 } // neverHasSideEffects
2235 //===----------------------------------------------------------------------===//
2236 // Atomic operations intrinsics
2239 // memory barriers protect the atomic sequences
2240 let hasSideEffects = 1 in {
2241 def t2Int_MemBarrierV7 : AInoP<(outs), (ins),
2242 ThumbFrm, NoItinerary,
2244 [(ARMMemBarrierV7)]>,
2245 Requires<[IsThumb2]> {
2246 let Inst{31-4} = 0xF3BF8F5;
2247 // FIXME: add support for options other than a full system DMB
2248 let Inst{3-0} = 0b1111;
2251 def t2Int_SyncBarrierV7 : AInoP<(outs), (ins),
2252 ThumbFrm, NoItinerary,
2254 [(ARMSyncBarrierV7)]>,
2255 Requires<[IsThumb2]> {
2256 let Inst{31-4} = 0xF3BF8F4;
2257 // FIXME: add support for options other than a full system DSB
2258 let Inst{3-0} = 0b1111;
2262 // Helper class for multiclass T2MemB -- for disassembly only
2263 class T2I_memb<string opc, string asm>
2264 : T2I<(outs), (ins), NoItinerary, opc, asm,
2265 [/* For disassembly only; pattern left blank */]>,
2266 Requires<[IsThumb2, HasV7]> {
2267 let Inst{31-20} = 0xf3b;
2268 let Inst{15-14} = 0b10;
2272 multiclass T2MemB<bits<4> op7_4, string opc> {
2274 def st : T2I_memb<opc, "\tst"> {
2275 let Inst{7-4} = op7_4;
2276 let Inst{3-0} = 0b1110;
2279 def ish : T2I_memb<opc, "\tish"> {
2280 let Inst{7-4} = op7_4;
2281 let Inst{3-0} = 0b1011;
2284 def ishst : T2I_memb<opc, "\tishst"> {
2285 let Inst{7-4} = op7_4;
2286 let Inst{3-0} = 0b1010;
2289 def nsh : T2I_memb<opc, "\tnsh"> {
2290 let Inst{7-4} = op7_4;
2291 let Inst{3-0} = 0b0111;
2294 def nshst : T2I_memb<opc, "\tnshst"> {
2295 let Inst{7-4} = op7_4;
2296 let Inst{3-0} = 0b0110;
2299 def osh : T2I_memb<opc, "\tosh"> {
2300 let Inst{7-4} = op7_4;
2301 let Inst{3-0} = 0b0011;
2304 def oshst : T2I_memb<opc, "\toshst"> {
2305 let Inst{7-4} = op7_4;
2306 let Inst{3-0} = 0b0010;
2310 // These DMB variants are for disassembly only.
2311 defm t2DMB : T2MemB<0b0101, "dmb">;
2313 // These DSB variants are for disassembly only.
2314 defm t2DSB : T2MemB<0b0100, "dsb">;
2316 // ISB has only full system option -- for disassembly only
2317 def t2ISBsy : T2I_memb<"isb", ""> {
2318 let Inst{7-4} = 0b0110;
2319 let Inst{3-0} = 0b1111;
2322 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2323 InstrItinClass itin, string opc, string asm, string cstr,
2324 list<dag> pattern, bits<4> rt2 = 0b1111>
2325 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2326 let Inst{31-27} = 0b11101;
2327 let Inst{26-20} = 0b0001101;
2328 let Inst{11-8} = rt2;
2329 let Inst{7-6} = 0b01;
2330 let Inst{5-4} = opcod;
2331 let Inst{3-0} = 0b1111;
2333 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2334 InstrItinClass itin, string opc, string asm, string cstr,
2335 list<dag> pattern, bits<4> rt2 = 0b1111>
2336 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2337 let Inst{31-27} = 0b11101;
2338 let Inst{26-20} = 0b0001100;
2339 let Inst{11-8} = rt2;
2340 let Inst{7-6} = 0b01;
2341 let Inst{5-4} = opcod;
2344 let mayLoad = 1 in {
2345 def t2LDREXB : T2I_ldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2346 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
2348 def t2LDREXH : T2I_ldrex<0b01, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2349 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
2351 def t2LDREX : Thumb2I<(outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2352 Size4Bytes, NoItinerary,
2353 "ldrex", "\t$dest, [$ptr]", "",
2355 let Inst{31-27} = 0b11101;
2356 let Inst{26-20} = 0b0000101;
2357 let Inst{11-8} = 0b1111;
2358 let Inst{7-0} = 0b00000000; // imm8 = 0
2360 def t2LDREXD : T2I_ldrex<0b11, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
2361 AddrModeNone, Size4Bytes, NoItinerary,
2362 "ldrexd", "\t$dest, $dest2, [$ptr]", "",
2366 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2367 def t2STREXB : T2I_strex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2368 AddrModeNone, Size4Bytes, NoItinerary,
2369 "strexb", "\t$success, $src, [$ptr]", "", []>;
2370 def t2STREXH : T2I_strex<0b01, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2371 AddrModeNone, Size4Bytes, NoItinerary,
2372 "strexh", "\t$success, $src, [$ptr]", "", []>;
2373 def t2STREX : Thumb2I<(outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2374 AddrModeNone, Size4Bytes, NoItinerary,
2375 "strex", "\t$success, $src, [$ptr]", "",
2377 let Inst{31-27} = 0b11101;
2378 let Inst{26-20} = 0b0000100;
2379 let Inst{7-0} = 0b00000000; // imm8 = 0
2381 def t2STREXD : T2I_strex<0b11, (outs GPR:$success),
2382 (ins GPR:$src, GPR:$src2, GPR:$ptr),
2383 AddrModeNone, Size4Bytes, NoItinerary,
2384 "strexd", "\t$success, $src, $src2, [$ptr]", "", [],
2388 // Clear-Exclusive is for disassembly only.
2389 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2390 [/* For disassembly only; pattern left blank */]>,
2391 Requires<[IsARM, HasV7]> {
2392 let Inst{31-20} = 0xf3b;
2393 let Inst{15-14} = 0b10;
2395 let Inst{7-4} = 0b0010;
2398 //===----------------------------------------------------------------------===//
2402 // __aeabi_read_tp preserves the registers r1-r3.
2404 Defs = [R0, R12, LR, CPSR] in {
2405 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2406 "bl\t__aeabi_read_tp",
2407 [(set R0, ARMthread_pointer)]> {
2408 let Inst{31-27} = 0b11110;
2409 let Inst{15-14} = 0b11;
2414 //===----------------------------------------------------------------------===//
2415 // SJLJ Exception handling intrinsics
2416 // eh_sjlj_setjmp() is an instruction sequence to store the return
2417 // address and save #0 in R0 for the non-longjmp case.
2418 // Since by its nature we may be coming from some other function to get
2419 // here, and we're using the stack frame for the containing function to
2420 // save/restore registers, we can't keep anything live in regs across
2421 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2422 // when we get here from a longjmp(). We force everthing out of registers
2423 // except for our own input by listing the relevant registers in Defs. By
2424 // doing so, we also cause the prologue/epilogue code to actively preserve
2425 // all of the callee-saved resgisters, which is exactly what we want.
2426 // $val is a scratch register for our use.
2428 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2429 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2430 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2431 D31 ], hasSideEffects = 1, isBarrier = 1 in {
2432 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
2433 AddrModeNone, SizeSpecial, NoItinerary,
2434 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
2435 "adds\t$val, #7\n\t"
2436 "str\t$val, [$src, #4]\n\t"
2439 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
2441 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>,
2442 Requires<[IsThumb2, HasVFP2]>;
2446 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2447 hasSideEffects = 1, isBarrier = 1 in {
2448 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
2449 AddrModeNone, SizeSpecial, NoItinerary,
2450 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
2451 "adds\t$val, #7\n\t"
2452 "str\t$val, [$src, #4]\n\t"
2455 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
2457 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>,
2458 Requires<[IsThumb2, NoVFP]>;
2462 //===----------------------------------------------------------------------===//
2463 // Control-Flow Instructions
2466 // FIXME: remove when we have a way to marking a MI with these properties.
2467 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2469 // FIXME: Should pc be an implicit operand like PICADD, etc?
2470 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2471 hasExtraDefRegAllocReq = 1 in
2472 def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
2473 reglist:$dsts, variable_ops), IIC_Br,
2474 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
2475 "$addr.addr = $wb", []> {
2476 let Inst{31-27} = 0b11101;
2477 let Inst{26-25} = 0b00;
2478 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
2480 let Inst{21} = 1; // The W bit.
2481 let Inst{20} = 1; // Load
2484 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2485 let isPredicable = 1 in
2486 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2488 [(br bb:$target)]> {
2489 let Inst{31-27} = 0b11110;
2490 let Inst{15-14} = 0b10;
2494 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2497 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
2498 IIC_Br, "mov\tpc, $target\n$jt",
2499 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
2500 let Inst{31-27} = 0b11101;
2501 let Inst{26-20} = 0b0100100;
2502 let Inst{19-16} = 0b1111;
2503 let Inst{14-12} = 0b000;
2504 let Inst{11-8} = 0b1111; // Rd = pc
2505 let Inst{7-4} = 0b0000;
2508 // FIXME: Add a non-pc based case that can be predicated.
2511 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2512 IIC_Br, "tbb\t$index\n$jt", []> {
2513 let Inst{31-27} = 0b11101;
2514 let Inst{26-20} = 0b0001101;
2515 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2516 let Inst{15-8} = 0b11110000;
2517 let Inst{7-4} = 0b0000; // B form
2522 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2523 IIC_Br, "tbh\t$index\n$jt", []> {
2524 let Inst{31-27} = 0b11101;
2525 let Inst{26-20} = 0b0001101;
2526 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2527 let Inst{15-8} = 0b11110000;
2528 let Inst{7-4} = 0b0001; // H form
2531 // Generic versions of the above two instructions, for disassembly only
2533 def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2534 "tbb", "\t[$a, $b]", []>{
2535 let Inst{31-27} = 0b11101;
2536 let Inst{26-20} = 0b0001101;
2537 let Inst{15-8} = 0b11110000;
2538 let Inst{7-4} = 0b0000; // B form
2541 def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2542 "tbh", "\t[$a, $b, lsl #1]", []> {
2543 let Inst{31-27} = 0b11101;
2544 let Inst{26-20} = 0b0001101;
2545 let Inst{15-8} = 0b11110000;
2546 let Inst{7-4} = 0b0001; // H form
2548 } // isNotDuplicable, isIndirectBranch
2550 } // isBranch, isTerminator, isBarrier
2552 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2553 // a two-value operand where a dag node expects two operands. :(
2554 let isBranch = 1, isTerminator = 1 in
2555 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
2557 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
2558 let Inst{31-27} = 0b11110;
2559 let Inst{15-14} = 0b10;
2565 let Defs = [ITSTATE] in
2566 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
2567 AddrModeNone, Size2Bytes, IIC_iALUx,
2568 "it$mask\t$cc", "", []> {
2569 // 16-bit instruction.
2570 let Inst{31-16} = 0x0000;
2571 let Inst{15-8} = 0b10111111;
2574 // Branch and Exchange Jazelle -- for disassembly only
2576 def t2BXJ : T2I<(outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2577 [/* For disassembly only; pattern left blank */]> {
2578 let Inst{31-27} = 0b11110;
2580 let Inst{25-20} = 0b111100;
2581 let Inst{15-14} = 0b10;
2585 // Change Processor State is a system instruction -- for disassembly only.
2586 // The singleton $opt operand contains the following information:
2587 // opt{4-0} = mode from Inst{4-0}
2588 // opt{5} = changemode from Inst{17}
2589 // opt{8-6} = AIF from Inst{8-6}
2590 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
2591 def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
2592 [/* For disassembly only; pattern left blank */]> {
2593 let Inst{31-27} = 0b11110;
2595 let Inst{25-20} = 0b111010;
2596 let Inst{15-14} = 0b10;
2600 // A6.3.4 Branches and miscellaneous control
2601 // Table A6-14 Change Processor State, and hint instructions
2602 // Helper class for disassembly only.
2603 class T2I_hint<bits<8> op7_0, string opc, string asm>
2604 : T2I<(outs), (ins), NoItinerary, opc, asm,
2605 [/* For disassembly only; pattern left blank */]> {
2606 let Inst{31-20} = 0xf3a;
2607 let Inst{15-14} = 0b10;
2609 let Inst{10-8} = 0b000;
2610 let Inst{7-0} = op7_0;
2613 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
2614 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
2615 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
2616 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
2617 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
2619 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
2620 [/* For disassembly only; pattern left blank */]> {
2621 let Inst{31-20} = 0xf3a;
2622 let Inst{15-14} = 0b10;
2624 let Inst{10-8} = 0b000;
2625 let Inst{7-4} = 0b1111;
2628 // Secure Monitor Call is a system instruction -- for disassembly only
2629 // Option = Inst{19-16}
2630 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
2631 [/* For disassembly only; pattern left blank */]> {
2632 let Inst{31-27} = 0b11110;
2633 let Inst{26-20} = 0b1111111;
2634 let Inst{15-12} = 0b1000;
2637 // Store Return State is a system instruction -- for disassembly only
2638 def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
2639 [/* For disassembly only; pattern left blank */]> {
2640 let Inst{31-27} = 0b11101;
2641 let Inst{26-20} = 0b0000010; // W = 1
2644 def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
2645 [/* For disassembly only; pattern left blank */]> {
2646 let Inst{31-27} = 0b11101;
2647 let Inst{26-20} = 0b0000000; // W = 0
2650 def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
2651 [/* For disassembly only; pattern left blank */]> {
2652 let Inst{31-27} = 0b11101;
2653 let Inst{26-20} = 0b0011010; // W = 1
2656 def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
2657 [/* For disassembly only; pattern left blank */]> {
2658 let Inst{31-27} = 0b11101;
2659 let Inst{26-20} = 0b0011000; // W = 0
2662 // Return From Exception is a system instruction -- for disassembly only
2663 def t2RFEDBW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfedb", "\t$base!",
2664 [/* For disassembly only; pattern left blank */]> {
2665 let Inst{31-27} = 0b11101;
2666 let Inst{26-20} = 0b0000011; // W = 1
2669 def t2RFEDB : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeab", "\t$base",
2670 [/* For disassembly only; pattern left blank */]> {
2671 let Inst{31-27} = 0b11101;
2672 let Inst{26-20} = 0b0000001; // W = 0
2675 def t2RFEIAW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base!",
2676 [/* For disassembly only; pattern left blank */]> {
2677 let Inst{31-27} = 0b11101;
2678 let Inst{26-20} = 0b0011011; // W = 1
2681 def t2RFEIA : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base",
2682 [/* For disassembly only; pattern left blank */]> {
2683 let Inst{31-27} = 0b11101;
2684 let Inst{26-20} = 0b0011001; // W = 0
2687 //===----------------------------------------------------------------------===//
2688 // Non-Instruction Patterns
2691 // Two piece so_imms.
2692 def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS),
2693 (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2694 (t2_so_imm2part_2 imm:$RHS))>;
2695 def : T2Pat<(xor GPR:$LHS, t2_so_imm2part:$RHS),
2696 (t2EORri (t2EORri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2697 (t2_so_imm2part_2 imm:$RHS))>;
2698 def : T2Pat<(add GPR:$LHS, t2_so_imm2part:$RHS),
2699 (t2ADDri (t2ADDri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2700 (t2_so_imm2part_2 imm:$RHS))>;
2701 def : T2Pat<(add GPR:$LHS, t2_so_neg_imm2part:$RHS),
2702 (t2SUBri (t2SUBri GPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
2703 (t2_so_neg_imm2part_2 imm:$RHS))>;
2705 // 32-bit immediate using movw + movt.
2706 // This is a single pseudo instruction to make it re-materializable. Remove
2707 // when we can do generalized remat.
2708 let isReMaterializable = 1 in
2709 def t2MOVi32imm : T2Ix2<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
2710 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2711 [(set GPR:$dst, (i32 imm:$src))]>;
2713 // ConstantPool, GlobalAddress, and JumpTable
2714 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
2715 Requires<[IsThumb2, DontUseMovt]>;
2716 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
2717 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
2718 Requires<[IsThumb2, UseMovt]>;
2720 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2721 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
2723 // Pseudo instruction that combines ldr from constpool and add pc. This should
2724 // be expanded into two instructions late to allow if-conversion and
2726 let canFoldAsLoad = 1, isReMaterializable = 1 in
2727 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
2729 "${:comment} ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
2730 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
2732 Requires<[IsThumb2]>;
2734 //===----------------------------------------------------------------------===//
2735 // Move between special register and ARM core register -- for disassembly only
2739 def t2MRS : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
2740 [/* For disassembly only; pattern left blank */]> {
2741 let Inst{31-27} = 0b11110;
2743 let Inst{25-21} = 0b11111;
2744 let Inst{20} = 0; // The R bit.
2745 let Inst{15-14} = 0b10;
2750 def t2MRSsys : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
2751 [/* For disassembly only; pattern left blank */]> {
2752 let Inst{31-27} = 0b11110;
2754 let Inst{25-21} = 0b11111;
2755 let Inst{20} = 1; // The R bit.
2756 let Inst{15-14} = 0b10;
2761 def t2MSR : T2I<(outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, "msr",
2762 "\tcpsr$mask, $src",
2763 [/* For disassembly only; pattern left blank */]> {
2764 let Inst{31-27} = 0b11110;
2766 let Inst{25-21} = 0b11100;
2767 let Inst{20} = 0; // The R bit.
2768 let Inst{15-14} = 0b10;
2773 def t2MSRsys : T2I<(outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, "msr",
2774 "\tspsr$mask, $src",
2775 [/* For disassembly only; pattern left blank */]> {
2776 let Inst{31-27} = 0b11110;
2778 let Inst{25-21} = 0b11100;
2779 let Inst{20} = 1; // The R bit.
2780 let Inst{15-14} = 0b10;