1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // Shifted operands. No register controlled shifts for Thumb2.
15 // Note: We do not support rrx shifted operands yet.
16 def t2_so_reg : Operand<i32>, // reg imm
17 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
19 let PrintMethod = "printT2SOOperand";
20 let MIOperandInfo = (ops GPR, i32imm);
23 // t2_so_imm_XFORM - Return a t2_so_imm value packed into the format
24 // described for t2_so_imm def below.
25 def t2_so_imm_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(
27 ARM_AM::getT2SOImmVal(N->getZExtValue()), MVT::i32);
30 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
31 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
32 return CurDAG->getTargetConstant(
33 ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())), MVT::i32);
36 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
37 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
38 return CurDAG->getTargetConstant(
39 ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())), MVT::i32);
42 // t2_so_imm - Match a 32-bit immediate operand, which is an
43 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
44 // immediate splatted into multiple bytes of the word. t2_so_imm values are
45 // represented in the imm field in the same 12-bit form that they are encoded
46 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
47 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
48 def t2_so_imm : Operand<i32>,
50 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
51 }], t2_so_imm_XFORM> {
52 let PrintMethod = "printT2SOImmOperand";
55 // t2_so_imm_not - Match an immediate that is a complement
57 def t2_so_imm_not : Operand<i32>,
59 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
60 }], t2_so_imm_not_XFORM> {
61 let PrintMethod = "printT2SOImmOperand";
64 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
65 def t2_so_imm_neg : Operand<i32>,
67 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
68 }], t2_so_imm_neg_XFORM> {
69 let PrintMethod = "printT2SOImmOperand";
72 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
73 def imm1_31 : PatLeaf<(i32 imm), [{
74 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
77 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
78 def imm0_4095 : PatLeaf<(i32 imm), [{
79 return (uint32_t)N->getZExtValue() < 4096;
82 def imm0_4095_neg : PatLeaf<(i32 imm), [{
83 return (uint32_t)(-N->getZExtValue()) < 4096;
86 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
88 def imm0_65535 : PatLeaf<(i32 imm), [{
89 return (uint32_t)N->getZExtValue() < 65536;
93 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
95 def bf_inv_mask_imm : Operand<i32>,
97 uint32_t v = (uint32_t)N->getZExtValue();
100 // naive checker. should do better, but simple is best for now since it's
101 // more likely to be correct.
102 while (v & 1) v >>= 1; // shift off the leading 1's
105 while (!(v & 1)) v >>=1; // shift off the mask
106 while (v & 1) v >>= 1; // shift off the trailing 1's
108 // if this is a mask for clearing a bitfield, what's left should be zero.
111 let PrintMethod = "printBitfieldInvMaskImmOperand";
114 /// Split a 32-bit immediate into two 16 bit parts.
115 def t2_lo16 : SDNodeXForm<imm, [{
116 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
120 def t2_hi16 : SDNodeXForm<imm, [{
121 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
124 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
125 // Returns true if all low 16-bits are 0.
126 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
130 //===----------------------------------------------------------------------===//
131 // Multiclass helpers...
134 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
135 /// unary operation that produces a value. These are predicable and can be
136 /// changed to modify CPSR.
137 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
139 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
141 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
142 let isAsCheapAsAMove = Cheap;
143 let isReMaterializable = ReMat;
146 def r : T2I<(outs GPR:$dst), (ins GPR:$src),
148 [(set GPR:$dst, (opnode GPR:$src))]>;
150 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
152 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
155 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
156 // binary operation that produces a value. These are predicable and can be
157 /// changed to modify CPSR.
158 multiclass T2I_bin_irs<string opc, PatFrag opnode, bit Commutable = 0> {
160 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
161 opc, " $dst, $lhs, $rhs",
162 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
164 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
165 opc, " $dst, $lhs, $rhs",
166 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
167 let isCommutable = Commutable;
170 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
171 opc, " $dst, $lhs, $rhs",
172 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
175 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
176 /// reversed. It doesn't define the 'rr' form since it's handled by its
177 /// T2I_bin_irs counterpart.
178 multiclass T2I_rbin_is<string opc, PatFrag opnode> {
180 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
181 opc, " $dst, $rhs, $lhs",
182 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
184 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
185 opc, " $dst, $rhs, $lhs",
186 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
189 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
190 /// instruction modifies the CPSR register.
191 let Defs = [CPSR] in {
192 multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
194 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
195 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
196 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
198 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
199 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
200 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
201 let isCommutable = Commutable;
204 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
205 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
206 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
210 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
211 /// patterns for a binary operation that produces a value.
212 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
214 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
215 opc, " $dst, $lhs, $rhs",
216 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
218 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
219 !strconcat(opc, "w"), " $dst, $lhs, $rhs",
220 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
222 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
223 opc, " $dst, $lhs, $rhs",
224 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
225 let isCommutable = Commutable;
228 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
229 opc, " $dst, $lhs, $rhs",
230 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
233 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
234 /// binary operation that produces a value and use and define the carry bit.
235 /// It's not predicable.
236 let Uses = [CPSR] in {
237 multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
239 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
240 opc, " $dst, $lhs, $rhs",
241 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
242 Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
244 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
245 opc, " $dst, $lhs, $rhs",
246 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
247 Requires<[IsThumb, HasThumb2, CarryDefIsUnused]> {
248 let isCommutable = Commutable;
251 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
252 opc, " $dst, $lhs, $rhs",
253 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
254 Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
255 // Carry setting variants
257 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
258 !strconcat(opc, "s $dst, $lhs, $rhs"),
259 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
260 Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
264 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
265 !strconcat(opc, "s $dst, $lhs, $rhs"),
266 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
267 Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
269 let isCommutable = Commutable;
272 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
273 !strconcat(opc, "s $dst, $lhs, $rhs"),
274 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
275 Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
281 /// T2I_rsc_is - Same as T2I_adde_sube_irs except the order of operands are
282 /// reversed. It doesn't define the 'rr' form since it's handled by its
283 /// T2I_adde_sube_irs counterpart.
284 let Defs = [CPSR], Uses = [CPSR] in {
285 multiclass T2I_rsc_is<string opc, PatFrag opnode> {
287 def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
288 opc, " $dst, $rhs, $lhs",
289 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
290 Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
292 def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
293 opc, " $dst, $rhs, $lhs",
294 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
295 Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
297 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
298 !strconcat(opc, "s $dst, $rhs, $lhs"),
299 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
300 Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
304 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
305 !strconcat(opc, "s $dst, $rhs, $lhs"),
306 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
307 Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
313 /// T2I_rbin_s_is - Same as T2I_bin_s_irs except the order of operands are
314 /// reversed. It doesn't define the 'rr' form since it's handled by its
315 /// T2I_bin_s_irs counterpart.
316 let Defs = [CPSR] in {
317 multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
319 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
320 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
321 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
323 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
324 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
325 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
329 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
330 // rotate operation that produces a value.
331 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
333 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
334 opc, " $dst, $lhs, $rhs",
335 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
337 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
338 opc, " $dst, $lhs, $rhs",
339 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
342 /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
343 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
344 /// a explicit result, only implicitly set CPSR.
345 let Uses = [CPSR] in {
346 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
348 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
350 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
352 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs),
354 [(opnode GPR:$lhs, GPR:$rhs)]>;
356 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
358 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
362 //===----------------------------------------------------------------------===//
364 //===----------------------------------------------------------------------===//
366 //===----------------------------------------------------------------------===//
367 // Miscellaneous Instructions.
370 let isNotDuplicable = 1 in
371 def t2PICADD : T2XI<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
372 "$cp:\n\tadd $dst, pc",
373 [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
376 // LEApcrel - Load a pc-relative address into a register without offending the
378 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
379 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
380 "${:private}PCRELL${:uid}+8))\n"),
381 !strconcat("${:private}PCRELL${:uid}:\n\t",
382 "add$p $dst, pc, #PCRELV${:uid}")),
385 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
386 (ins i32imm:$label, i32imm:$id, pred:$p),
387 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
388 "${:private}PCRELL${:uid}+8))\n"),
389 !strconcat("${:private}PCRELL${:uid}:\n\t",
390 "add$p $dst, pc, #PCRELV${:uid}")),
393 // ADD rd, sp, #so_imm
394 def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
395 "add $dst, $sp, $imm",
398 // ADD rd, sp, #imm12
399 def t2ADDrSPi12 : T2XI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm),
400 "addw $dst, $sp, $imm",
403 def t2ADDrSPs : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
404 "addw $dst, $sp, $rhs",
408 //===----------------------------------------------------------------------===//
409 // Load / store Instructions.
412 //===----------------------------------------------------------------------===//
413 // Move Instructions.
416 let neverHasSideEffects = 1 in
417 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src),
418 "mov", " $dst, $src", []>;
420 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
421 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
422 "mov", " $dst, $src",
423 [(set GPR:$dst, t2_so_imm:$src)]>;
425 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
426 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src),
427 "movw", " $dst, $src",
428 [(set GPR:$dst, imm0_65535:$src)]>;
430 // FIXME: Also available in ARM mode.
431 let Constraints = "$src = $dst" in
432 def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
433 "movt", " $dst, $imm",
435 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
437 //===----------------------------------------------------------------------===//
438 // Arithmetic Instructions.
441 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
442 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
444 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
445 defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
446 defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
448 defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>;
449 defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>;
452 defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
453 defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
454 defm t2RSC : T2I_rsc_is <"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
456 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
457 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
458 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
459 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
460 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
463 //===----------------------------------------------------------------------===//
464 // Shift and rotate Instructions.
467 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
468 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
469 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
470 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
472 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
473 "mov", " $dst, $src, rrx",
474 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
476 //===----------------------------------------------------------------------===//
477 // Bitwise Instructions.
480 defm t2AND : T2I_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
481 defm t2ORR : T2I_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
482 defm t2EOR : T2I_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
484 defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
486 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
487 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
489 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
491 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
492 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
494 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
495 let AddedComplexity = 1 in
496 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
498 def : T2Pat<(t2_so_imm_not:$src),
499 (t2MVNi t2_so_imm_not:$src)>;
501 // A8.6.17 BFC - Bitfield clear
502 // FIXME: Also available in ARM mode.
503 let Constraints = "$src = $dst" in
504 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
505 "bfc", " $dst, $imm",
506 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
508 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
510 //===----------------------------------------------------------------------===//
511 // Multiply Instructions.
513 let isCommutable = 1 in
514 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
515 "mul", " $dst, $a, $b",
516 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
518 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
519 "mla", " $dst, $a, $b, $c",
520 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
522 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
523 "mls", " $dst, $a, $b, $c",
524 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
526 // FIXME: SMULL, etc.
528 //===----------------------------------------------------------------------===//
529 // Misc. Arithmetic Instructions.
532 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
533 "clz", " $dst, $src",
534 [(set GPR:$dst, (ctlz GPR:$src))]>;
536 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
537 "rev", " $dst, $src",
538 [(set GPR:$dst, (bswap GPR:$src))]>;
540 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
541 "rev16", " $dst, $src",
543 (or (and (srl GPR:$src, (i32 8)), 0xFF),
544 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
545 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
546 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
551 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
552 "revsh", " $dst, $src",
555 (or (srl (and GPR:$src, 0xFFFF), (i32 8)),
556 (shl GPR:$src, (i32 8))), i16))]>;
560 //===----------------------------------------------------------------------===//
561 // Comparison Instructions...
564 defm t2CMP : T2I_cmp_is<"cmp",
565 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
566 defm t2CMPnz : T2I_cmp_is<"cmp",
567 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
569 defm t2CMN : T2I_cmp_is<"cmn",
570 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
571 defm t2CMNnz : T2I_cmp_is<"cmn",
572 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
574 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
575 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
577 def : T2Pat<(ARMcmpNZ GPR:$src, t2_so_imm_neg:$imm),
578 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
580 // FIXME: TST, TEQ, etc.
582 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
583 // Short range conditional branch. Looks awesome for loops. Need to figure
584 // out how to use this one.
586 // FIXME: Conditional moves
589 //===----------------------------------------------------------------------===//
590 // Non-Instruction Patterns
593 // ConstantPool, GlobalAddress, and JumpTable
594 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
595 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
596 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
597 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
599 // Large immediate handling.
601 def : T2Pat<(i32 imm:$src),
602 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>;