1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
60 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
61 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
65 // t2_so_imm - Match a 32-bit immediate operand, which is an
66 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
67 // immediate splatted into multiple bytes of the word.
68 def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
69 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
70 return ARM_AM::getT2SOImmVal(Imm) != -1;
72 let ParserMatchClass = t2_so_imm_asmoperand;
73 let EncoderMethod = "getT2SOImmOpValue";
74 let DecoderMethod = "DecodeT2SOImm";
77 // t2_so_imm_not - Match an immediate that is a complement
79 def t2_so_imm_not : Operand<i32>,
81 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
82 }], t2_so_imm_not_XFORM>;
84 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
85 def t2_so_imm_neg : Operand<i32>,
87 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
88 }], t2_so_imm_neg_XFORM>;
90 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
91 def imm0_4095 : Operand<i32>,
93 return Imm >= 0 && Imm < 4096;
96 def imm0_4095_neg : PatLeaf<(i32 imm), [{
97 return (uint32_t)(-N->getZExtValue()) < 4096;
100 def imm0_255_neg : PatLeaf<(i32 imm), [{
101 return (uint32_t)(-N->getZExtValue()) < 255;
104 def imm0_255_not : PatLeaf<(i32 imm), [{
105 return (uint32_t)(~N->getZExtValue()) < 255;
108 def lo5AllOne : PatLeaf<(i32 imm), [{
109 // Returns true if all low 5-bits are 1.
110 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
113 // Define Thumb2 specific addressing modes.
115 // t2addrmode_imm12 := reg + imm12
116 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
117 def t2addrmode_imm12 : Operand<i32>,
118 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
119 let PrintMethod = "printAddrModeImm12Operand";
120 let EncoderMethod = "getAddrModeImm12OpValue";
121 let DecoderMethod = "DecodeT2AddrModeImm12";
122 let ParserMatchClass = t2addrmode_imm12_asmoperand;
123 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
126 // t2ldrlabel := imm12
127 def t2ldrlabel : Operand<i32> {
128 let EncoderMethod = "getAddrModeImm12OpValue";
129 let PrintMethod = "printT2LdrLabelOperand";
133 // ADR instruction labels.
134 def t2adrlabel : Operand<i32> {
135 let EncoderMethod = "getT2AdrLabelOpValue";
139 // t2addrmode_posimm8 := reg + imm8
140 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
141 def t2addrmode_posimm8 : Operand<i32> {
142 let PrintMethod = "printT2AddrModeImm8Operand";
143 let EncoderMethod = "getT2AddrModeImm8OpValue";
144 let DecoderMethod = "DecodeT2AddrModeImm8";
145 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
146 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
149 // t2addrmode_negimm8 := reg - imm8
150 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
151 def t2addrmode_negimm8 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
153 let PrintMethod = "printT2AddrModeImm8Operand";
154 let EncoderMethod = "getT2AddrModeImm8OpValue";
155 let DecoderMethod = "DecodeT2AddrModeImm8";
156 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
157 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
160 // t2addrmode_imm8 := reg +/- imm8
161 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
162 def t2addrmode_imm8 : Operand<i32>,
163 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
164 let PrintMethod = "printT2AddrModeImm8Operand";
165 let EncoderMethod = "getT2AddrModeImm8OpValue";
166 let DecoderMethod = "DecodeT2AddrModeImm8";
167 let ParserMatchClass = MemImm8OffsetAsmOperand;
168 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
171 def t2am_imm8_offset : Operand<i32>,
172 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
173 [], [SDNPWantRoot]> {
174 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
175 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
176 let DecoderMethod = "DecodeT2Imm8";
179 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
180 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
181 def t2addrmode_imm8s4 : Operand<i32> {
182 let PrintMethod = "printT2AddrModeImm8s4Operand";
183 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
184 let DecoderMethod = "DecodeT2AddrModeImm8s4";
185 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
186 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
189 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
190 def t2am_imm8s4_offset : Operand<i32> {
191 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
192 let EncoderMethod = "getT2Imm8s4OpValue";
193 let DecoderMethod = "DecodeT2Imm8S4";
196 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
197 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
198 let Name = "MemImm0_1020s4Offset";
200 def t2addrmode_imm0_1020s4 : Operand<i32> {
201 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
202 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
203 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
204 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
205 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
208 // t2addrmode_so_reg := reg + (reg << imm2)
209 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
210 def t2addrmode_so_reg : Operand<i32>,
211 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
212 let PrintMethod = "printT2AddrModeSoRegOperand";
213 let EncoderMethod = "getT2AddrModeSORegOpValue";
214 let DecoderMethod = "DecodeT2AddrModeSOReg";
215 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
216 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
219 // Addresses for the TBB/TBH instructions.
220 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
221 def addrmode_tbb : Operand<i32> {
222 let PrintMethod = "printAddrModeTBB";
223 let ParserMatchClass = addrmode_tbb_asmoperand;
224 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
226 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
227 def addrmode_tbh : Operand<i32> {
228 let PrintMethod = "printAddrModeTBH";
229 let ParserMatchClass = addrmode_tbh_asmoperand;
230 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
233 //===----------------------------------------------------------------------===//
234 // Multiclass helpers...
238 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
239 string opc, string asm, list<dag> pattern>
240 : T2I<oops, iops, itin, opc, asm, pattern> {
245 let Inst{26} = imm{11};
246 let Inst{14-12} = imm{10-8};
247 let Inst{7-0} = imm{7-0};
251 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
252 string opc, string asm, list<dag> pattern>
253 : T2sI<oops, iops, itin, opc, asm, pattern> {
259 let Inst{26} = imm{11};
260 let Inst{14-12} = imm{10-8};
261 let Inst{7-0} = imm{7-0};
264 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
265 string opc, string asm, list<dag> pattern>
266 : T2I<oops, iops, itin, opc, asm, pattern> {
270 let Inst{19-16} = Rn;
271 let Inst{26} = imm{11};
272 let Inst{14-12} = imm{10-8};
273 let Inst{7-0} = imm{7-0};
277 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
278 string opc, string asm, list<dag> pattern>
279 : T2I<oops, iops, itin, opc, asm, pattern> {
284 let Inst{3-0} = ShiftedRm{3-0};
285 let Inst{5-4} = ShiftedRm{6-5};
286 let Inst{14-12} = ShiftedRm{11-9};
287 let Inst{7-6} = ShiftedRm{8-7};
290 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
291 string opc, string asm, list<dag> pattern>
292 : T2sI<oops, iops, itin, opc, asm, pattern> {
297 let Inst{3-0} = ShiftedRm{3-0};
298 let Inst{5-4} = ShiftedRm{6-5};
299 let Inst{14-12} = ShiftedRm{11-9};
300 let Inst{7-6} = ShiftedRm{8-7};
303 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
304 string opc, string asm, list<dag> pattern>
305 : T2I<oops, iops, itin, opc, asm, pattern> {
309 let Inst{19-16} = Rn;
310 let Inst{3-0} = ShiftedRm{3-0};
311 let Inst{5-4} = ShiftedRm{6-5};
312 let Inst{14-12} = ShiftedRm{11-9};
313 let Inst{7-6} = ShiftedRm{8-7};
316 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
317 string opc, string asm, list<dag> pattern>
318 : T2I<oops, iops, itin, opc, asm, pattern> {
326 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
327 string opc, string asm, list<dag> pattern>
328 : T2sI<oops, iops, itin, opc, asm, pattern> {
336 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
337 string opc, string asm, list<dag> pattern>
338 : T2I<oops, iops, itin, opc, asm, pattern> {
342 let Inst{19-16} = Rn;
347 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
348 string opc, string asm, list<dag> pattern>
349 : T2I<oops, iops, itin, opc, asm, pattern> {
355 let Inst{19-16} = Rn;
356 let Inst{26} = imm{11};
357 let Inst{14-12} = imm{10-8};
358 let Inst{7-0} = imm{7-0};
361 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
362 string opc, string asm, list<dag> pattern>
363 : T2sI<oops, iops, itin, opc, asm, pattern> {
369 let Inst{19-16} = Rn;
370 let Inst{26} = imm{11};
371 let Inst{14-12} = imm{10-8};
372 let Inst{7-0} = imm{7-0};
375 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
376 string opc, string asm, list<dag> pattern>
377 : T2I<oops, iops, itin, opc, asm, pattern> {
384 let Inst{14-12} = imm{4-2};
385 let Inst{7-6} = imm{1-0};
388 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
389 string opc, string asm, list<dag> pattern>
390 : T2sI<oops, iops, itin, opc, asm, pattern> {
397 let Inst{14-12} = imm{4-2};
398 let Inst{7-6} = imm{1-0};
401 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
402 string opc, string asm, list<dag> pattern>
403 : T2I<oops, iops, itin, opc, asm, pattern> {
409 let Inst{19-16} = Rn;
413 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
414 string opc, string asm, list<dag> pattern>
415 : T2sI<oops, iops, itin, opc, asm, pattern> {
421 let Inst{19-16} = Rn;
425 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
426 string opc, string asm, list<dag> pattern>
427 : T2I<oops, iops, itin, opc, asm, pattern> {
433 let Inst{19-16} = Rn;
434 let Inst{3-0} = ShiftedRm{3-0};
435 let Inst{5-4} = ShiftedRm{6-5};
436 let Inst{14-12} = ShiftedRm{11-9};
437 let Inst{7-6} = ShiftedRm{8-7};
440 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
441 string opc, string asm, list<dag> pattern>
442 : T2sI<oops, iops, itin, opc, asm, pattern> {
448 let Inst{19-16} = Rn;
449 let Inst{3-0} = ShiftedRm{3-0};
450 let Inst{5-4} = ShiftedRm{6-5};
451 let Inst{14-12} = ShiftedRm{11-9};
452 let Inst{7-6} = ShiftedRm{8-7};
455 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
456 string opc, string asm, list<dag> pattern>
457 : T2I<oops, iops, itin, opc, asm, pattern> {
463 let Inst{19-16} = Rn;
464 let Inst{15-12} = Ra;
469 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
470 dag oops, dag iops, InstrItinClass itin,
471 string opc, string asm, list<dag> pattern>
472 : T2I<oops, iops, itin, opc, asm, pattern> {
478 let Inst{31-23} = 0b111110111;
479 let Inst{22-20} = opc22_20;
480 let Inst{19-16} = Rn;
481 let Inst{15-12} = RdLo;
482 let Inst{11-8} = RdHi;
483 let Inst{7-4} = opc7_4;
488 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
489 /// binary operation that produces a value. These are predicable and can be
490 /// changed to modify CPSR.
491 multiclass T2I_bin_irs<bits<4> opcod, string opc,
492 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
493 PatFrag opnode, string baseOpc, bit Commutable = 0,
496 def ri : T2sTwoRegImm<
497 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
498 opc, "\t$Rd, $Rn, $imm",
499 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
500 let Inst{31-27} = 0b11110;
502 let Inst{24-21} = opcod;
506 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
507 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
508 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
509 let isCommutable = Commutable;
510 let Inst{31-27} = 0b11101;
511 let Inst{26-25} = 0b01;
512 let Inst{24-21} = opcod;
513 let Inst{14-12} = 0b000; // imm3
514 let Inst{7-6} = 0b00; // imm2
515 let Inst{5-4} = 0b00; // type
518 def rs : T2sTwoRegShiftedReg<
519 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
520 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
521 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
522 let Inst{31-27} = 0b11101;
523 let Inst{26-25} = 0b01;
524 let Inst{24-21} = opcod;
526 // Assembly aliases for optional destination operand when it's the same
527 // as the source operand.
528 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
529 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
530 t2_so_imm:$imm, pred:$p,
532 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
533 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
536 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
537 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
538 t2_so_reg:$shift, pred:$p,
542 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
543 // the ".w" suffix to indicate that they are wide.
544 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
545 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
546 PatFrag opnode, string baseOpc, bit Commutable = 0> :
547 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
548 // Assembler aliases w/o the ".w" suffix.
549 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
550 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
553 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
554 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
555 t2_so_reg:$shift, pred:$p,
558 // and with the optional destination operand, too.
559 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
560 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
563 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
564 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
565 t2_so_reg:$shift, pred:$p,
569 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
570 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
571 /// it is equivalent to the T2I_bin_irs counterpart.
572 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
574 def ri : T2sTwoRegImm<
575 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
576 opc, ".w\t$Rd, $Rn, $imm",
577 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
578 let Inst{31-27} = 0b11110;
580 let Inst{24-21} = opcod;
584 def rr : T2sThreeReg<
585 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
586 opc, "\t$Rd, $Rn, $Rm",
587 [/* For disassembly only; pattern left blank */]> {
588 let Inst{31-27} = 0b11101;
589 let Inst{26-25} = 0b01;
590 let Inst{24-21} = opcod;
591 let Inst{14-12} = 0b000; // imm3
592 let Inst{7-6} = 0b00; // imm2
593 let Inst{5-4} = 0b00; // type
596 def rs : T2sTwoRegShiftedReg<
597 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
598 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
599 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
600 let Inst{31-27} = 0b11101;
601 let Inst{26-25} = 0b01;
602 let Inst{24-21} = opcod;
606 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
607 /// instruction modifies the CPSR register.
609 /// These opcodes will be converted to the real non-S opcodes by
610 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
611 let hasPostISelHook = 1, isCodeGenOnly = 1, isPseudo = 1, Defs = [CPSR] in {
612 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
613 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
614 PatFrag opnode, bit Commutable = 0> {
616 def ri : T2sTwoRegImm<
617 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
618 opc, ".w\t$Rd, $Rn, $imm",
619 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]>;
621 def rr : T2sThreeReg<
622 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
623 opc, ".w\t$Rd, $Rn, $Rm",
624 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]>;
626 def rs : T2sTwoRegShiftedReg<
627 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
628 opc, ".w\t$Rd, $Rn, $ShiftedRm",
629 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]>;
633 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
634 /// patterns for a binary operation that produces a value.
635 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
636 bit Commutable = 0> {
638 // The register-immediate version is re-materializable. This is useful
639 // in particular for taking the address of a local.
640 let isReMaterializable = 1 in {
641 def ri : T2sTwoRegImm<
642 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
643 opc, ".w\t$Rd, $Rn, $imm",
644 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
645 let Inst{31-27} = 0b11110;
648 let Inst{23-21} = op23_21;
654 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
655 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
656 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
660 let Inst{31-27} = 0b11110;
661 let Inst{26} = imm{11};
662 let Inst{25-24} = 0b10;
663 let Inst{23-21} = op23_21;
664 let Inst{20} = 0; // The S bit.
665 let Inst{19-16} = Rn;
667 let Inst{14-12} = imm{10-8};
669 let Inst{7-0} = imm{7-0};
672 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iALUr,
673 opc, ".w\t$Rd, $Rn, $Rm",
674 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
675 let isCommutable = Commutable;
676 let Inst{31-27} = 0b11101;
677 let Inst{26-25} = 0b01;
679 let Inst{23-21} = op23_21;
680 let Inst{14-12} = 0b000; // imm3
681 let Inst{7-6} = 0b00; // imm2
682 let Inst{5-4} = 0b00; // type
685 def rs : T2sTwoRegShiftedReg<
686 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
687 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
688 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
689 let Inst{31-27} = 0b11101;
690 let Inst{26-25} = 0b01;
692 let Inst{23-21} = op23_21;
696 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
697 /// for a binary operation that produces a value and use the carry
698 /// bit. It's not predicable.
699 let Defs = [CPSR], Uses = [CPSR] in {
700 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
701 bit Commutable = 0> {
703 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
704 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
705 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
706 Requires<[IsThumb2]> {
707 let Inst{31-27} = 0b11110;
709 let Inst{24-21} = opcod;
713 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
714 opc, ".w\t$Rd, $Rn, $Rm",
715 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
716 Requires<[IsThumb2]> {
717 let isCommutable = Commutable;
718 let Inst{31-27} = 0b11101;
719 let Inst{26-25} = 0b01;
720 let Inst{24-21} = opcod;
721 let Inst{14-12} = 0b000; // imm3
722 let Inst{7-6} = 0b00; // imm2
723 let Inst{5-4} = 0b00; // type
726 def rs : T2sTwoRegShiftedReg<
727 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
728 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
729 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
730 Requires<[IsThumb2]> {
731 let Inst{31-27} = 0b11101;
732 let Inst{26-25} = 0b01;
733 let Inst{24-21} = opcod;
738 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
739 /// version is not needed since this is only for codegen.
741 /// These opcodes will be converted to the real non-S opcodes by
742 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
743 let hasPostISelHook = 1, isCodeGenOnly = 1, isPseudo = 1, Defs = [CPSR] in {
744 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
746 def ri : T2sTwoRegImm<
747 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
748 opc, ".w\t$Rd, $Rn, $imm",
749 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]>;
751 def rs : T2sTwoRegShiftedReg<
752 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
753 IIC_iALUsi, opc, "\t$Rd, $Rn, $ShiftedRm",
754 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>;
758 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
759 // rotate operation that produces a value.
760 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
763 def ri : T2sTwoRegShiftImm<
764 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
765 opc, ".w\t$Rd, $Rm, $imm",
766 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
767 let Inst{31-27} = 0b11101;
768 let Inst{26-21} = 0b010010;
769 let Inst{19-16} = 0b1111; // Rn
770 let Inst{5-4} = opcod;
773 def rr : T2sThreeReg<
774 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
775 opc, ".w\t$Rd, $Rn, $Rm",
776 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
777 let Inst{31-27} = 0b11111;
778 let Inst{26-23} = 0b0100;
779 let Inst{22-21} = opcod;
780 let Inst{15-12} = 0b1111;
781 let Inst{7-4} = 0b0000;
784 // Optional destination register
785 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
786 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
789 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
790 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
794 // Assembler aliases w/o the ".w" suffix.
795 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
796 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
799 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
800 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
804 // and with the optional destination operand, too.
805 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
806 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
809 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
810 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
815 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
816 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
817 /// a explicit result, only implicitly set CPSR.
818 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
819 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
820 PatFrag opnode, string baseOpc> {
821 let isCompare = 1, Defs = [CPSR] in {
823 def ri : T2OneRegCmpImm<
824 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
825 opc, ".w\t$Rn, $imm",
826 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
827 let Inst{31-27} = 0b11110;
829 let Inst{24-21} = opcod;
830 let Inst{20} = 1; // The S bit.
832 let Inst{11-8} = 0b1111; // Rd
835 def rr : T2TwoRegCmp<
836 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
838 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
839 let Inst{31-27} = 0b11101;
840 let Inst{26-25} = 0b01;
841 let Inst{24-21} = opcod;
842 let Inst{20} = 1; // The S bit.
843 let Inst{14-12} = 0b000; // imm3
844 let Inst{11-8} = 0b1111; // Rd
845 let Inst{7-6} = 0b00; // imm2
846 let Inst{5-4} = 0b00; // type
849 def rs : T2OneRegCmpShiftedReg<
850 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
851 opc, ".w\t$Rn, $ShiftedRm",
852 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
853 let Inst{31-27} = 0b11101;
854 let Inst{26-25} = 0b01;
855 let Inst{24-21} = opcod;
856 let Inst{20} = 1; // The S bit.
857 let Inst{11-8} = 0b1111; // Rd
861 // Assembler aliases w/o the ".w" suffix.
862 // No alias here for 'rr' version as not all instantiations of this
863 // multiclass want one (CMP in particular, does not).
864 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
865 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
866 t2_so_imm:$imm, pred:$p)>;
867 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
868 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
873 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
874 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
875 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
877 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
878 opc, ".w\t$Rt, $addr",
879 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
882 let Inst{31-25} = 0b1111100;
883 let Inst{24} = signed;
885 let Inst{22-21} = opcod;
886 let Inst{20} = 1; // load
887 let Inst{19-16} = addr{16-13}; // Rn
888 let Inst{15-12} = Rt;
889 let Inst{11-0} = addr{11-0}; // imm
891 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
893 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
896 let Inst{31-27} = 0b11111;
897 let Inst{26-25} = 0b00;
898 let Inst{24} = signed;
900 let Inst{22-21} = opcod;
901 let Inst{20} = 1; // load
902 let Inst{19-16} = addr{12-9}; // Rn
903 let Inst{15-12} = Rt;
905 // Offset: index==TRUE, wback==FALSE
906 let Inst{10} = 1; // The P bit.
907 let Inst{9} = addr{8}; // U
908 let Inst{8} = 0; // The W bit.
909 let Inst{7-0} = addr{7-0}; // imm
911 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
912 opc, ".w\t$Rt, $addr",
913 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
914 let Inst{31-27} = 0b11111;
915 let Inst{26-25} = 0b00;
916 let Inst{24} = signed;
918 let Inst{22-21} = opcod;
919 let Inst{20} = 1; // load
920 let Inst{11-6} = 0b000000;
923 let Inst{15-12} = Rt;
926 let Inst{19-16} = addr{9-6}; // Rn
927 let Inst{3-0} = addr{5-2}; // Rm
928 let Inst{5-4} = addr{1-0}; // imm
930 let DecoderMethod = "DecodeT2LoadShift";
933 // FIXME: Is the pci variant actually needed?
934 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
935 opc, ".w\t$Rt, $addr",
936 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
937 let isReMaterializable = 1;
938 let Inst{31-27} = 0b11111;
939 let Inst{26-25} = 0b00;
940 let Inst{24} = signed;
941 let Inst{23} = ?; // add = (U == '1')
942 let Inst{22-21} = opcod;
943 let Inst{20} = 1; // load
944 let Inst{19-16} = 0b1111; // Rn
947 let Inst{15-12} = Rt{3-0};
948 let Inst{11-0} = addr{11-0};
952 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
953 multiclass T2I_st<bits<2> opcod, string opc,
954 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
956 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
957 opc, ".w\t$Rt, $addr",
958 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
959 let Inst{31-27} = 0b11111;
960 let Inst{26-23} = 0b0001;
961 let Inst{22-21} = opcod;
962 let Inst{20} = 0; // !load
965 let Inst{15-12} = Rt;
968 let addr{12} = 1; // add = TRUE
969 let Inst{19-16} = addr{16-13}; // Rn
970 let Inst{23} = addr{12}; // U
971 let Inst{11-0} = addr{11-0}; // imm
973 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
975 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
976 let Inst{31-27} = 0b11111;
977 let Inst{26-23} = 0b0000;
978 let Inst{22-21} = opcod;
979 let Inst{20} = 0; // !load
981 // Offset: index==TRUE, wback==FALSE
982 let Inst{10} = 1; // The P bit.
983 let Inst{8} = 0; // The W bit.
986 let Inst{15-12} = Rt;
989 let Inst{19-16} = addr{12-9}; // Rn
990 let Inst{9} = addr{8}; // U
991 let Inst{7-0} = addr{7-0}; // imm
993 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
994 opc, ".w\t$Rt, $addr",
995 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
996 let Inst{31-27} = 0b11111;
997 let Inst{26-23} = 0b0000;
998 let Inst{22-21} = opcod;
999 let Inst{20} = 0; // !load
1000 let Inst{11-6} = 0b000000;
1003 let Inst{15-12} = Rt;
1006 let Inst{19-16} = addr{9-6}; // Rn
1007 let Inst{3-0} = addr{5-2}; // Rm
1008 let Inst{5-4} = addr{1-0}; // imm
1012 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1013 /// register and one whose operand is a register rotated by 8/16/24.
1014 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1015 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1016 opc, ".w\t$Rd, $Rm$rot",
1017 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1018 Requires<[IsThumb2]> {
1019 let Inst{31-27} = 0b11111;
1020 let Inst{26-23} = 0b0100;
1021 let Inst{22-20} = opcod;
1022 let Inst{19-16} = 0b1111; // Rn
1023 let Inst{15-12} = 0b1111;
1027 let Inst{5-4} = rot{1-0}; // rotate
1030 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1031 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1032 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1033 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1034 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1035 Requires<[HasT2ExtractPack, IsThumb2]> {
1037 let Inst{31-27} = 0b11111;
1038 let Inst{26-23} = 0b0100;
1039 let Inst{22-20} = opcod;
1040 let Inst{19-16} = 0b1111; // Rn
1041 let Inst{15-12} = 0b1111;
1043 let Inst{5-4} = rot;
1046 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1048 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1049 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1050 opc, "\t$Rd, $Rm$rot", []>,
1051 Requires<[IsThumb2, HasT2ExtractPack]> {
1053 let Inst{31-27} = 0b11111;
1054 let Inst{26-23} = 0b0100;
1055 let Inst{22-20} = opcod;
1056 let Inst{19-16} = 0b1111; // Rn
1057 let Inst{15-12} = 0b1111;
1059 let Inst{5-4} = rot;
1062 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1063 /// register and one whose operand is a register rotated by 8/16/24.
1064 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1065 : T2ThreeReg<(outs rGPR:$Rd),
1066 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1067 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1068 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1069 Requires<[HasT2ExtractPack, IsThumb2]> {
1071 let Inst{31-27} = 0b11111;
1072 let Inst{26-23} = 0b0100;
1073 let Inst{22-20} = opcod;
1074 let Inst{15-12} = 0b1111;
1076 let Inst{5-4} = rot;
1079 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1080 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1081 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1083 let Inst{31-27} = 0b11111;
1084 let Inst{26-23} = 0b0100;
1085 let Inst{22-20} = opcod;
1086 let Inst{15-12} = 0b1111;
1088 let Inst{5-4} = rot;
1091 //===----------------------------------------------------------------------===//
1093 //===----------------------------------------------------------------------===//
1095 //===----------------------------------------------------------------------===//
1096 // Miscellaneous Instructions.
1099 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1100 string asm, list<dag> pattern>
1101 : T2XI<oops, iops, itin, asm, pattern> {
1105 let Inst{11-8} = Rd;
1106 let Inst{26} = label{11};
1107 let Inst{14-12} = label{10-8};
1108 let Inst{7-0} = label{7-0};
1111 // LEApcrel - Load a pc-relative address into a register without offending the
1113 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1114 (ins t2adrlabel:$addr, pred:$p),
1115 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
1116 let Inst{31-27} = 0b11110;
1117 let Inst{25-24} = 0b10;
1118 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1121 let Inst{19-16} = 0b1111; // Rn
1126 let Inst{11-8} = Rd;
1127 let Inst{23} = addr{12};
1128 let Inst{21} = addr{12};
1129 let Inst{26} = addr{11};
1130 let Inst{14-12} = addr{10-8};
1131 let Inst{7-0} = addr{7-0};
1133 let DecoderMethod = "DecodeT2Adr";
1136 let neverHasSideEffects = 1, isReMaterializable = 1 in
1137 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1139 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1140 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1145 //===----------------------------------------------------------------------===//
1146 // Load / store Instructions.
1150 let canFoldAsLoad = 1, isReMaterializable = 1 in
1151 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1152 UnOpFrag<(load node:$Src)>>;
1154 // Loads with zero extension
1155 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1156 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1157 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1158 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1160 // Loads with sign extension
1161 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1162 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1163 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1164 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1166 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1168 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1169 (ins t2addrmode_imm8s4:$addr),
1170 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1171 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1173 // zextload i1 -> zextload i8
1174 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1175 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1176 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1177 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1178 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1179 (t2LDRBs t2addrmode_so_reg:$addr)>;
1180 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1181 (t2LDRBpci tconstpool:$addr)>;
1183 // extload -> zextload
1184 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1186 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1187 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1188 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1189 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1190 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1191 (t2LDRBs t2addrmode_so_reg:$addr)>;
1192 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1193 (t2LDRBpci tconstpool:$addr)>;
1195 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1196 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1197 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1198 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1199 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1200 (t2LDRBs t2addrmode_so_reg:$addr)>;
1201 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1202 (t2LDRBpci tconstpool:$addr)>;
1204 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1205 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1206 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1207 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1208 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1209 (t2LDRHs t2addrmode_so_reg:$addr)>;
1210 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1211 (t2LDRHpci tconstpool:$addr)>;
1213 // FIXME: The destination register of the loads and stores can't be PC, but
1214 // can be SP. We need another regclass (similar to rGPR) to represent
1215 // that. Not a pressing issue since these are selected manually,
1220 let mayLoad = 1, neverHasSideEffects = 1 in {
1221 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1222 (ins t2addrmode_imm8:$addr),
1223 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1224 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1226 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1229 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1230 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1231 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1232 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1234 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1235 (ins t2addrmode_imm8:$addr),
1236 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1237 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1239 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1241 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1242 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1243 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1244 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1246 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1247 (ins t2addrmode_imm8:$addr),
1248 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1249 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1251 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1253 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1254 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1255 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1256 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1258 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1259 (ins t2addrmode_imm8:$addr),
1260 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1261 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1263 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1265 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1266 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1267 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1268 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1270 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1271 (ins t2addrmode_imm8:$addr),
1272 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1273 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1275 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1277 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1278 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1279 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1280 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1281 } // mayLoad = 1, neverHasSideEffects = 1
1283 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1284 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1285 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1286 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1287 "\t$Rt, $addr", []> {
1290 let Inst{31-27} = 0b11111;
1291 let Inst{26-25} = 0b00;
1292 let Inst{24} = signed;
1294 let Inst{22-21} = type;
1295 let Inst{20} = 1; // load
1296 let Inst{19-16} = addr{12-9};
1297 let Inst{15-12} = Rt;
1299 let Inst{10-8} = 0b110; // PUW.
1300 let Inst{7-0} = addr{7-0};
1303 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1304 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1305 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1306 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1307 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1310 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1311 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1312 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1313 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1314 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1315 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1318 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1319 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1320 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1321 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1324 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1325 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1326 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1327 "str", "\t$Rt, $addr!",
1328 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1329 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1331 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1332 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1333 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1334 "strh", "\t$Rt, $addr!",
1335 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1336 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1339 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1340 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1341 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1342 "strb", "\t$Rt, $addr!",
1343 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1344 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1347 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1348 (ins rGPR:$Rt, addr_offset_none:$Rn,
1349 t2am_imm8_offset:$offset),
1350 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1351 "str", "\t$Rt, $Rn$offset",
1352 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1353 [(set GPRnopc:$Rn_wb,
1354 (post_store rGPR:$Rt, addr_offset_none:$Rn,
1355 t2am_imm8_offset:$offset))]>;
1357 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1358 (ins rGPR:$Rt, addr_offset_none:$Rn,
1359 t2am_imm8_offset:$offset),
1360 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1361 "strh", "\t$Rt, $Rn$offset",
1362 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1363 [(set GPRnopc:$Rn_wb,
1364 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1365 t2am_imm8_offset:$offset))]>;
1367 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1368 (ins rGPR:$Rt, addr_offset_none:$Rn,
1369 t2am_imm8_offset:$offset),
1370 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1371 "strb", "\t$Rt, $Rn$offset",
1372 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1373 [(set GPRnopc:$Rn_wb,
1374 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1375 t2am_imm8_offset:$offset))]>;
1377 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1378 // put the patterns on the instruction definitions directly as ISel wants
1379 // the address base and offset to be separate operands, not a single
1380 // complex operand like we represent the instructions themselves. The
1381 // pseudos map between the two.
1382 let usesCustomInserter = 1,
1383 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1384 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1385 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1387 [(set GPRnopc:$Rn_wb,
1388 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1389 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1390 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1392 [(set GPRnopc:$Rn_wb,
1393 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1394 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1395 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1397 [(set GPRnopc:$Rn_wb,
1398 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1402 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1404 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1405 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1406 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1407 "\t$Rt, $addr", []> {
1408 let Inst{31-27} = 0b11111;
1409 let Inst{26-25} = 0b00;
1410 let Inst{24} = 0; // not signed
1412 let Inst{22-21} = type;
1413 let Inst{20} = 0; // store
1415 let Inst{10-8} = 0b110; // PUW
1419 let Inst{15-12} = Rt;
1420 let Inst{19-16} = addr{12-9};
1421 let Inst{7-0} = addr{7-0};
1424 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1425 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1426 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1428 // ldrd / strd pre / post variants
1429 // For disassembly only.
1431 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1432 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
1433 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1434 let AsmMatchConverter = "cvtT2LdrdPre";
1435 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1438 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1439 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1440 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1441 "$addr.base = $wb", []>;
1443 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1444 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1445 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1446 "$addr.base = $wb", []> {
1447 let AsmMatchConverter = "cvtT2StrdPre";
1448 let DecoderMethod = "DecodeT2STRDPreInstruction";
1451 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1452 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1453 t2am_imm8s4_offset:$imm),
1454 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1455 "$addr.base = $wb", []>;
1457 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1458 // data/instruction access. These are for disassembly only.
1459 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1460 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1461 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1463 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1465 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1466 let Inst{31-25} = 0b1111100;
1467 let Inst{24} = instr;
1469 let Inst{21} = write;
1471 let Inst{15-12} = 0b1111;
1474 let addr{12} = 1; // add = TRUE
1475 let Inst{19-16} = addr{16-13}; // Rn
1476 let Inst{23} = addr{12}; // U
1477 let Inst{11-0} = addr{11-0}; // imm12
1480 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1482 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
1483 let Inst{31-25} = 0b1111100;
1484 let Inst{24} = instr;
1485 let Inst{23} = 0; // U = 0
1487 let Inst{21} = write;
1489 let Inst{15-12} = 0b1111;
1490 let Inst{11-8} = 0b1100;
1493 let Inst{19-16} = addr{12-9}; // Rn
1494 let Inst{7-0} = addr{7-0}; // imm8
1497 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1499 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1500 let Inst{31-25} = 0b1111100;
1501 let Inst{24} = instr;
1502 let Inst{23} = 0; // add = TRUE for T1
1504 let Inst{21} = write;
1506 let Inst{15-12} = 0b1111;
1507 let Inst{11-6} = 0000000;
1510 let Inst{19-16} = addr{9-6}; // Rn
1511 let Inst{3-0} = addr{5-2}; // Rm
1512 let Inst{5-4} = addr{1-0}; // imm2
1514 let DecoderMethod = "DecodeT2LoadShift";
1518 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1519 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1520 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1522 //===----------------------------------------------------------------------===//
1523 // Load / store multiple Instructions.
1526 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1527 InstrItinClass itin_upd, bit L_bit> {
1529 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1530 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1534 let Inst{31-27} = 0b11101;
1535 let Inst{26-25} = 0b00;
1536 let Inst{24-23} = 0b01; // Increment After
1538 let Inst{21} = 0; // No writeback
1539 let Inst{20} = L_bit;
1540 let Inst{19-16} = Rn;
1542 let Inst{14-0} = regs{14-0};
1545 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1546 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1550 let Inst{31-27} = 0b11101;
1551 let Inst{26-25} = 0b00;
1552 let Inst{24-23} = 0b01; // Increment After
1554 let Inst{21} = 1; // Writeback
1555 let Inst{20} = L_bit;
1556 let Inst{19-16} = Rn;
1558 let Inst{14-0} = regs{14-0};
1561 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1562 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1566 let Inst{31-27} = 0b11101;
1567 let Inst{26-25} = 0b00;
1568 let Inst{24-23} = 0b10; // Decrement Before
1570 let Inst{21} = 0; // No writeback
1571 let Inst{20} = L_bit;
1572 let Inst{19-16} = Rn;
1574 let Inst{14-0} = regs{14-0};
1577 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1578 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1582 let Inst{31-27} = 0b11101;
1583 let Inst{26-25} = 0b00;
1584 let Inst{24-23} = 0b10; // Decrement Before
1586 let Inst{21} = 1; // Writeback
1587 let Inst{20} = L_bit;
1588 let Inst{19-16} = Rn;
1590 let Inst{14-0} = regs{14-0};
1594 let neverHasSideEffects = 1 in {
1596 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1597 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1599 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1600 InstrItinClass itin_upd, bit L_bit> {
1602 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1603 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1607 let Inst{31-27} = 0b11101;
1608 let Inst{26-25} = 0b00;
1609 let Inst{24-23} = 0b01; // Increment After
1611 let Inst{21} = 0; // No writeback
1612 let Inst{20} = L_bit;
1613 let Inst{19-16} = Rn;
1615 let Inst{14} = regs{14};
1617 let Inst{12-0} = regs{12-0};
1620 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1621 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1625 let Inst{31-27} = 0b11101;
1626 let Inst{26-25} = 0b00;
1627 let Inst{24-23} = 0b01; // Increment After
1629 let Inst{21} = 1; // Writeback
1630 let Inst{20} = L_bit;
1631 let Inst{19-16} = Rn;
1633 let Inst{14} = regs{14};
1635 let Inst{12-0} = regs{12-0};
1638 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1639 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1643 let Inst{31-27} = 0b11101;
1644 let Inst{26-25} = 0b00;
1645 let Inst{24-23} = 0b10; // Decrement Before
1647 let Inst{21} = 0; // No writeback
1648 let Inst{20} = L_bit;
1649 let Inst{19-16} = Rn;
1651 let Inst{14} = regs{14};
1653 let Inst{12-0} = regs{12-0};
1656 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1657 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1661 let Inst{31-27} = 0b11101;
1662 let Inst{26-25} = 0b00;
1663 let Inst{24-23} = 0b10; // Decrement Before
1665 let Inst{21} = 1; // Writeback
1666 let Inst{20} = L_bit;
1667 let Inst{19-16} = Rn;
1669 let Inst{14} = regs{14};
1671 let Inst{12-0} = regs{12-0};
1676 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1677 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1679 } // neverHasSideEffects
1682 //===----------------------------------------------------------------------===//
1683 // Move Instructions.
1686 let neverHasSideEffects = 1 in
1687 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1688 "mov", ".w\t$Rd, $Rm", []> {
1689 let Inst{31-27} = 0b11101;
1690 let Inst{26-25} = 0b01;
1691 let Inst{24-21} = 0b0010;
1692 let Inst{19-16} = 0b1111; // Rn
1693 let Inst{14-12} = 0b000;
1694 let Inst{7-4} = 0b0000;
1696 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1698 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1701 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1702 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1703 AddedComplexity = 1 in
1704 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1705 "mov", ".w\t$Rd, $imm",
1706 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1707 let Inst{31-27} = 0b11110;
1709 let Inst{24-21} = 0b0010;
1710 let Inst{19-16} = 0b1111; // Rn
1714 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1715 // Use aliases to get that to play nice here.
1716 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1718 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1721 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1722 pred:$p, zero_reg)>;
1723 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1724 pred:$p, zero_reg)>;
1726 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1727 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1728 "movw", "\t$Rd, $imm",
1729 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1730 let Inst{31-27} = 0b11110;
1732 let Inst{24-21} = 0b0010;
1733 let Inst{20} = 0; // The S bit.
1739 let Inst{11-8} = Rd;
1740 let Inst{19-16} = imm{15-12};
1741 let Inst{26} = imm{11};
1742 let Inst{14-12} = imm{10-8};
1743 let Inst{7-0} = imm{7-0};
1746 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1747 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1749 let Constraints = "$src = $Rd" in {
1750 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1751 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1752 "movt", "\t$Rd, $imm",
1754 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1755 let Inst{31-27} = 0b11110;
1757 let Inst{24-21} = 0b0110;
1758 let Inst{20} = 0; // The S bit.
1764 let Inst{11-8} = Rd;
1765 let Inst{19-16} = imm{15-12};
1766 let Inst{26} = imm{11};
1767 let Inst{14-12} = imm{10-8};
1768 let Inst{7-0} = imm{7-0};
1771 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1772 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1775 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1777 //===----------------------------------------------------------------------===//
1778 // Extend Instructions.
1783 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1784 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1785 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1786 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1787 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1789 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1790 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1791 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1792 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1793 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1797 let AddedComplexity = 16 in {
1798 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1799 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1800 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1801 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1802 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1803 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1805 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1806 // The transformation should probably be done as a combiner action
1807 // instead so we can include a check for masking back in the upper
1808 // eight bits of the source into the lower eight bits of the result.
1809 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1810 // (t2UXTB16 rGPR:$Src, 3)>,
1811 // Requires<[HasT2ExtractPack, IsThumb2]>;
1812 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1813 (t2UXTB16 rGPR:$Src, 1)>,
1814 Requires<[HasT2ExtractPack, IsThumb2]>;
1816 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1817 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1818 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1819 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1820 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1823 //===----------------------------------------------------------------------===//
1824 // Arithmetic Instructions.
1827 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1828 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1829 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1830 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1832 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1834 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
1835 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
1836 // AdjustInstrPostInstrSelection where we determine whether or not to
1837 // set the "s" bit based on CPSR liveness.
1839 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
1840 // support for an optional CPSR definition that corresponds to the DAG
1841 // node's second value. We can then eliminate the implicit def of CPSR.
1842 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1843 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1844 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1845 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1846 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1847 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1849 let hasPostISelHook = 1 in {
1850 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1851 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1852 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1853 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1857 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1858 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1860 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1861 // CPSR and the implicit def of CPSR is not needed.
1862 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1863 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1865 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1866 // The assume-no-carry-in form uses the negation of the input since add/sub
1867 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1868 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1870 // The AddedComplexity preferences the first variant over the others since
1871 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1872 let AddedComplexity = 1 in
1873 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1874 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1875 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1876 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1877 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1878 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1879 let AddedComplexity = 1 in
1880 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1881 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1882 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1883 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1884 // The with-carry-in form matches bitwise not instead of the negation.
1885 // Effectively, the inverse interpretation of the carry flag already accounts
1886 // for part of the negation.
1887 let AddedComplexity = 1 in
1888 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1889 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1890 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1891 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1893 // Select Bytes -- for disassembly only
1895 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1896 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1897 Requires<[IsThumb2, HasThumb2DSP]> {
1898 let Inst{31-27} = 0b11111;
1899 let Inst{26-24} = 0b010;
1901 let Inst{22-20} = 0b010;
1902 let Inst{15-12} = 0b1111;
1904 let Inst{6-4} = 0b000;
1907 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1908 // And Miscellaneous operations -- for disassembly only
1909 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1910 list<dag> pat = [/* For disassembly only; pattern left blank */],
1911 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1912 string asm = "\t$Rd, $Rn, $Rm">
1913 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1914 Requires<[IsThumb2, HasThumb2DSP]> {
1915 let Inst{31-27} = 0b11111;
1916 let Inst{26-23} = 0b0101;
1917 let Inst{22-20} = op22_20;
1918 let Inst{15-12} = 0b1111;
1919 let Inst{7-4} = op7_4;
1925 let Inst{11-8} = Rd;
1926 let Inst{19-16} = Rn;
1930 // Saturating add/subtract -- for disassembly only
1932 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1933 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1934 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1935 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1936 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1937 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1938 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1939 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1940 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1941 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1942 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1943 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1944 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1945 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1946 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1947 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1948 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1949 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1950 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1951 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1952 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1953 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1955 // Signed/Unsigned add/subtract -- for disassembly only
1957 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1958 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1959 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1960 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1961 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1962 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1963 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1964 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1965 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1966 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1967 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1968 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1970 // Signed/Unsigned halving add/subtract -- for disassembly only
1972 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1973 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1974 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1975 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1976 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1977 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1978 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1979 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1980 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1981 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1982 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1983 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1985 // Helper class for disassembly only
1986 // A6.3.16 & A6.3.17
1987 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1988 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1989 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1990 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1991 let Inst{31-27} = 0b11111;
1992 let Inst{26-24} = 0b011;
1993 let Inst{23} = long;
1994 let Inst{22-20} = op22_20;
1995 let Inst{7-4} = op7_4;
1998 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1999 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2000 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2001 let Inst{31-27} = 0b11111;
2002 let Inst{26-24} = 0b011;
2003 let Inst{23} = long;
2004 let Inst{22-20} = op22_20;
2005 let Inst{7-4} = op7_4;
2008 // Unsigned Sum of Absolute Differences [and Accumulate].
2009 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2010 (ins rGPR:$Rn, rGPR:$Rm),
2011 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2012 Requires<[IsThumb2, HasThumb2DSP]> {
2013 let Inst{15-12} = 0b1111;
2015 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2016 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2017 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2018 Requires<[IsThumb2, HasThumb2DSP]>;
2020 // Signed/Unsigned saturate.
2021 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2022 string opc, string asm, list<dag> pattern>
2023 : T2I<oops, iops, itin, opc, asm, pattern> {
2029 let Inst{11-8} = Rd;
2030 let Inst{19-16} = Rn;
2031 let Inst{4-0} = sat_imm;
2032 let Inst{21} = sh{5};
2033 let Inst{14-12} = sh{4-2};
2034 let Inst{7-6} = sh{1-0};
2039 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2040 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2041 let Inst{31-27} = 0b11110;
2042 let Inst{25-22} = 0b1100;
2048 def t2SSAT16: T2SatI<
2049 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2050 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2051 Requires<[IsThumb2, HasThumb2DSP]> {
2052 let Inst{31-27} = 0b11110;
2053 let Inst{25-22} = 0b1100;
2056 let Inst{21} = 1; // sh = '1'
2057 let Inst{14-12} = 0b000; // imm3 = '000'
2058 let Inst{7-6} = 0b00; // imm2 = '00'
2059 let Inst{5-4} = 0b00;
2064 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2065 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2066 let Inst{31-27} = 0b11110;
2067 let Inst{25-22} = 0b1110;
2072 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2074 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2075 Requires<[IsThumb2, HasThumb2DSP]> {
2076 let Inst{31-22} = 0b1111001110;
2079 let Inst{21} = 1; // sh = '1'
2080 let Inst{14-12} = 0b000; // imm3 = '000'
2081 let Inst{7-6} = 0b00; // imm2 = '00'
2082 let Inst{5-4} = 0b00;
2085 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2086 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2088 //===----------------------------------------------------------------------===//
2089 // Shift and rotate Instructions.
2092 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2093 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">;
2094 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2095 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">;
2096 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2097 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">;
2098 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2099 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
2101 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2102 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2103 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2105 let Uses = [CPSR] in {
2106 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2107 "rrx", "\t$Rd, $Rm",
2108 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2109 let Inst{31-27} = 0b11101;
2110 let Inst{26-25} = 0b01;
2111 let Inst{24-21} = 0b0010;
2112 let Inst{19-16} = 0b1111; // Rn
2113 let Inst{14-12} = 0b000;
2114 let Inst{7-4} = 0b0011;
2118 let isCodeGenOnly = 1, Defs = [CPSR] in {
2119 def t2MOVsrl_flag : T2TwoRegShiftImm<
2120 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2121 "lsrs", ".w\t$Rd, $Rm, #1",
2122 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2123 let Inst{31-27} = 0b11101;
2124 let Inst{26-25} = 0b01;
2125 let Inst{24-21} = 0b0010;
2126 let Inst{20} = 1; // The S bit.
2127 let Inst{19-16} = 0b1111; // Rn
2128 let Inst{5-4} = 0b01; // Shift type.
2129 // Shift amount = Inst{14-12:7-6} = 1.
2130 let Inst{14-12} = 0b000;
2131 let Inst{7-6} = 0b01;
2133 def t2MOVsra_flag : T2TwoRegShiftImm<
2134 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2135 "asrs", ".w\t$Rd, $Rm, #1",
2136 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2137 let Inst{31-27} = 0b11101;
2138 let Inst{26-25} = 0b01;
2139 let Inst{24-21} = 0b0010;
2140 let Inst{20} = 1; // The S bit.
2141 let Inst{19-16} = 0b1111; // Rn
2142 let Inst{5-4} = 0b10; // Shift type.
2143 // Shift amount = Inst{14-12:7-6} = 1.
2144 let Inst{14-12} = 0b000;
2145 let Inst{7-6} = 0b01;
2149 //===----------------------------------------------------------------------===//
2150 // Bitwise Instructions.
2153 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2154 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2155 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2156 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2157 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2158 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
2159 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2160 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2161 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2163 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2164 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2165 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2168 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2169 string opc, string asm, list<dag> pattern>
2170 : T2I<oops, iops, itin, opc, asm, pattern> {
2175 let Inst{11-8} = Rd;
2176 let Inst{4-0} = msb{4-0};
2177 let Inst{14-12} = lsb{4-2};
2178 let Inst{7-6} = lsb{1-0};
2181 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2182 string opc, string asm, list<dag> pattern>
2183 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2186 let Inst{19-16} = Rn;
2189 let Constraints = "$src = $Rd" in
2190 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2191 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2192 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2193 let Inst{31-27} = 0b11110;
2194 let Inst{26} = 0; // should be 0.
2196 let Inst{24-20} = 0b10110;
2197 let Inst{19-16} = 0b1111; // Rn
2199 let Inst{5} = 0; // should be 0.
2202 let msb{4-0} = imm{9-5};
2203 let lsb{4-0} = imm{4-0};
2206 def t2SBFX: T2TwoRegBitFI<
2207 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2208 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2209 let Inst{31-27} = 0b11110;
2211 let Inst{24-20} = 0b10100;
2215 def t2UBFX: T2TwoRegBitFI<
2216 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2217 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2218 let Inst{31-27} = 0b11110;
2220 let Inst{24-20} = 0b11100;
2224 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2225 let Constraints = "$src = $Rd" in {
2226 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2227 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2228 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2229 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2230 bf_inv_mask_imm:$imm))]> {
2231 let Inst{31-27} = 0b11110;
2232 let Inst{26} = 0; // should be 0.
2234 let Inst{24-20} = 0b10110;
2236 let Inst{5} = 0; // should be 0.
2239 let msb{4-0} = imm{9-5};
2240 let lsb{4-0} = imm{4-0};
2244 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2245 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2246 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2249 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2250 /// unary operation that produces a value. These are predicable and can be
2251 /// changed to modify CPSR.
2252 multiclass T2I_un_irs<bits<4> opcod, string opc,
2253 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2254 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
2256 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2258 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
2259 let isAsCheapAsAMove = Cheap;
2260 let isReMaterializable = ReMat;
2261 let Inst{31-27} = 0b11110;
2263 let Inst{24-21} = opcod;
2264 let Inst{19-16} = 0b1111; // Rn
2268 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2269 opc, ".w\t$Rd, $Rm",
2270 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
2271 let Inst{31-27} = 0b11101;
2272 let Inst{26-25} = 0b01;
2273 let Inst{24-21} = opcod;
2274 let Inst{19-16} = 0b1111; // Rn
2275 let Inst{14-12} = 0b000; // imm3
2276 let Inst{7-6} = 0b00; // imm2
2277 let Inst{5-4} = 0b00; // type
2280 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2281 opc, ".w\t$Rd, $ShiftedRm",
2282 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
2283 let Inst{31-27} = 0b11101;
2284 let Inst{26-25} = 0b01;
2285 let Inst{24-21} = opcod;
2286 let Inst{19-16} = 0b1111; // Rn
2290 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2291 let AddedComplexity = 1 in
2292 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2293 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2294 UnOpFrag<(not node:$Src)>, 1, 1>;
2296 let AddedComplexity = 1 in
2297 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2298 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2300 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2301 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2302 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2303 Requires<[IsThumb2]>;
2305 def : T2Pat<(t2_so_imm_not:$src),
2306 (t2MVNi t2_so_imm_not:$src)>;
2308 //===----------------------------------------------------------------------===//
2309 // Multiply Instructions.
2311 let isCommutable = 1 in
2312 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2313 "mul", "\t$Rd, $Rn, $Rm",
2314 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2315 let Inst{31-27} = 0b11111;
2316 let Inst{26-23} = 0b0110;
2317 let Inst{22-20} = 0b000;
2318 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2319 let Inst{7-4} = 0b0000; // Multiply
2322 def t2MLA: T2FourReg<
2323 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2324 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2325 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2326 let Inst{31-27} = 0b11111;
2327 let Inst{26-23} = 0b0110;
2328 let Inst{22-20} = 0b000;
2329 let Inst{7-4} = 0b0000; // Multiply
2332 def t2MLS: T2FourReg<
2333 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2334 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2335 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2336 let Inst{31-27} = 0b11111;
2337 let Inst{26-23} = 0b0110;
2338 let Inst{22-20} = 0b000;
2339 let Inst{7-4} = 0b0001; // Multiply and Subtract
2342 // Extra precision multiplies with low / high results
2343 let neverHasSideEffects = 1 in {
2344 let isCommutable = 1 in {
2345 def t2SMULL : T2MulLong<0b000, 0b0000,
2346 (outs rGPR:$RdLo, rGPR:$RdHi),
2347 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2348 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2350 def t2UMULL : T2MulLong<0b010, 0b0000,
2351 (outs rGPR:$RdLo, rGPR:$RdHi),
2352 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2353 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2356 // Multiply + accumulate
2357 def t2SMLAL : T2MulLong<0b100, 0b0000,
2358 (outs rGPR:$RdLo, rGPR:$RdHi),
2359 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2360 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2362 def t2UMLAL : T2MulLong<0b110, 0b0000,
2363 (outs rGPR:$RdLo, rGPR:$RdHi),
2364 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2365 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2367 def t2UMAAL : T2MulLong<0b110, 0b0110,
2368 (outs rGPR:$RdLo, rGPR:$RdHi),
2369 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2370 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2371 Requires<[IsThumb2, HasThumb2DSP]>;
2372 } // neverHasSideEffects
2374 // Rounding variants of the below included for disassembly only
2376 // Most significant word multiply
2377 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2378 "smmul", "\t$Rd, $Rn, $Rm",
2379 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2380 Requires<[IsThumb2, HasThumb2DSP]> {
2381 let Inst{31-27} = 0b11111;
2382 let Inst{26-23} = 0b0110;
2383 let Inst{22-20} = 0b101;
2384 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2385 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2388 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2389 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2390 Requires<[IsThumb2, HasThumb2DSP]> {
2391 let Inst{31-27} = 0b11111;
2392 let Inst{26-23} = 0b0110;
2393 let Inst{22-20} = 0b101;
2394 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2395 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2398 def t2SMMLA : T2FourReg<
2399 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2400 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2401 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2402 Requires<[IsThumb2, HasThumb2DSP]> {
2403 let Inst{31-27} = 0b11111;
2404 let Inst{26-23} = 0b0110;
2405 let Inst{22-20} = 0b101;
2406 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2409 def t2SMMLAR: T2FourReg<
2410 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2411 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2412 Requires<[IsThumb2, HasThumb2DSP]> {
2413 let Inst{31-27} = 0b11111;
2414 let Inst{26-23} = 0b0110;
2415 let Inst{22-20} = 0b101;
2416 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2419 def t2SMMLS: T2FourReg<
2420 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2421 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2422 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2423 Requires<[IsThumb2, HasThumb2DSP]> {
2424 let Inst{31-27} = 0b11111;
2425 let Inst{26-23} = 0b0110;
2426 let Inst{22-20} = 0b110;
2427 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2430 def t2SMMLSR:T2FourReg<
2431 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2432 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2433 Requires<[IsThumb2, HasThumb2DSP]> {
2434 let Inst{31-27} = 0b11111;
2435 let Inst{26-23} = 0b0110;
2436 let Inst{22-20} = 0b110;
2437 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2440 multiclass T2I_smul<string opc, PatFrag opnode> {
2441 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2442 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2443 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2444 (sext_inreg rGPR:$Rm, i16)))]>,
2445 Requires<[IsThumb2, HasThumb2DSP]> {
2446 let Inst{31-27} = 0b11111;
2447 let Inst{26-23} = 0b0110;
2448 let Inst{22-20} = 0b001;
2449 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2450 let Inst{7-6} = 0b00;
2451 let Inst{5-4} = 0b00;
2454 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2455 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2456 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2457 (sra rGPR:$Rm, (i32 16))))]>,
2458 Requires<[IsThumb2, HasThumb2DSP]> {
2459 let Inst{31-27} = 0b11111;
2460 let Inst{26-23} = 0b0110;
2461 let Inst{22-20} = 0b001;
2462 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2463 let Inst{7-6} = 0b00;
2464 let Inst{5-4} = 0b01;
2467 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2468 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2469 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2470 (sext_inreg rGPR:$Rm, i16)))]>,
2471 Requires<[IsThumb2, HasThumb2DSP]> {
2472 let Inst{31-27} = 0b11111;
2473 let Inst{26-23} = 0b0110;
2474 let Inst{22-20} = 0b001;
2475 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2476 let Inst{7-6} = 0b00;
2477 let Inst{5-4} = 0b10;
2480 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2481 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2482 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2483 (sra rGPR:$Rm, (i32 16))))]>,
2484 Requires<[IsThumb2, HasThumb2DSP]> {
2485 let Inst{31-27} = 0b11111;
2486 let Inst{26-23} = 0b0110;
2487 let Inst{22-20} = 0b001;
2488 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2489 let Inst{7-6} = 0b00;
2490 let Inst{5-4} = 0b11;
2493 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2494 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2495 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2496 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2497 Requires<[IsThumb2, HasThumb2DSP]> {
2498 let Inst{31-27} = 0b11111;
2499 let Inst{26-23} = 0b0110;
2500 let Inst{22-20} = 0b011;
2501 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2502 let Inst{7-6} = 0b00;
2503 let Inst{5-4} = 0b00;
2506 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2507 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2508 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2509 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2510 Requires<[IsThumb2, HasThumb2DSP]> {
2511 let Inst{31-27} = 0b11111;
2512 let Inst{26-23} = 0b0110;
2513 let Inst{22-20} = 0b011;
2514 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2515 let Inst{7-6} = 0b00;
2516 let Inst{5-4} = 0b01;
2521 multiclass T2I_smla<string opc, PatFrag opnode> {
2523 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2524 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2525 [(set rGPR:$Rd, (add rGPR:$Ra,
2526 (opnode (sext_inreg rGPR:$Rn, i16),
2527 (sext_inreg rGPR:$Rm, i16))))]>,
2528 Requires<[IsThumb2, HasThumb2DSP]> {
2529 let Inst{31-27} = 0b11111;
2530 let Inst{26-23} = 0b0110;
2531 let Inst{22-20} = 0b001;
2532 let Inst{7-6} = 0b00;
2533 let Inst{5-4} = 0b00;
2537 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2538 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2539 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2540 (sra rGPR:$Rm, (i32 16)))))]>,
2541 Requires<[IsThumb2, HasThumb2DSP]> {
2542 let Inst{31-27} = 0b11111;
2543 let Inst{26-23} = 0b0110;
2544 let Inst{22-20} = 0b001;
2545 let Inst{7-6} = 0b00;
2546 let Inst{5-4} = 0b01;
2550 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2551 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2552 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2553 (sext_inreg rGPR:$Rm, i16))))]>,
2554 Requires<[IsThumb2, HasThumb2DSP]> {
2555 let Inst{31-27} = 0b11111;
2556 let Inst{26-23} = 0b0110;
2557 let Inst{22-20} = 0b001;
2558 let Inst{7-6} = 0b00;
2559 let Inst{5-4} = 0b10;
2563 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2564 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2565 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2566 (sra rGPR:$Rm, (i32 16)))))]>,
2567 Requires<[IsThumb2, HasThumb2DSP]> {
2568 let Inst{31-27} = 0b11111;
2569 let Inst{26-23} = 0b0110;
2570 let Inst{22-20} = 0b001;
2571 let Inst{7-6} = 0b00;
2572 let Inst{5-4} = 0b11;
2576 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2577 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2578 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2579 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2580 Requires<[IsThumb2, HasThumb2DSP]> {
2581 let Inst{31-27} = 0b11111;
2582 let Inst{26-23} = 0b0110;
2583 let Inst{22-20} = 0b011;
2584 let Inst{7-6} = 0b00;
2585 let Inst{5-4} = 0b00;
2589 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2590 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2591 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2592 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2593 Requires<[IsThumb2, HasThumb2DSP]> {
2594 let Inst{31-27} = 0b11111;
2595 let Inst{26-23} = 0b0110;
2596 let Inst{22-20} = 0b011;
2597 let Inst{7-6} = 0b00;
2598 let Inst{5-4} = 0b01;
2602 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2603 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2605 // Halfword multiple accumulate long: SMLAL<x><y>
2606 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2607 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2608 [/* For disassembly only; pattern left blank */]>,
2609 Requires<[IsThumb2, HasThumb2DSP]>;
2610 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2611 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2612 [/* For disassembly only; pattern left blank */]>,
2613 Requires<[IsThumb2, HasThumb2DSP]>;
2614 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2615 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2616 [/* For disassembly only; pattern left blank */]>,
2617 Requires<[IsThumb2, HasThumb2DSP]>;
2618 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2619 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2620 [/* For disassembly only; pattern left blank */]>,
2621 Requires<[IsThumb2, HasThumb2DSP]>;
2623 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2624 def t2SMUAD: T2ThreeReg_mac<
2625 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2626 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2627 Requires<[IsThumb2, HasThumb2DSP]> {
2628 let Inst{15-12} = 0b1111;
2630 def t2SMUADX:T2ThreeReg_mac<
2631 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2632 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2633 Requires<[IsThumb2, HasThumb2DSP]> {
2634 let Inst{15-12} = 0b1111;
2636 def t2SMUSD: T2ThreeReg_mac<
2637 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2638 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2639 Requires<[IsThumb2, HasThumb2DSP]> {
2640 let Inst{15-12} = 0b1111;
2642 def t2SMUSDX:T2ThreeReg_mac<
2643 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2644 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2645 Requires<[IsThumb2, HasThumb2DSP]> {
2646 let Inst{15-12} = 0b1111;
2648 def t2SMLAD : T2FourReg_mac<
2649 0, 0b010, 0b0000, (outs rGPR:$Rd),
2650 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2651 "\t$Rd, $Rn, $Rm, $Ra", []>,
2652 Requires<[IsThumb2, HasThumb2DSP]>;
2653 def t2SMLADX : T2FourReg_mac<
2654 0, 0b010, 0b0001, (outs rGPR:$Rd),
2655 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2656 "\t$Rd, $Rn, $Rm, $Ra", []>,
2657 Requires<[IsThumb2, HasThumb2DSP]>;
2658 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2659 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2660 "\t$Rd, $Rn, $Rm, $Ra", []>,
2661 Requires<[IsThumb2, HasThumb2DSP]>;
2662 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2663 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2664 "\t$Rd, $Rn, $Rm, $Ra", []>,
2665 Requires<[IsThumb2, HasThumb2DSP]>;
2666 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2667 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2668 "\t$Ra, $Rd, $Rn, $Rm", []>,
2669 Requires<[IsThumb2, HasThumb2DSP]>;
2670 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2671 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2672 "\t$Ra, $Rd, $Rn, $Rm", []>,
2673 Requires<[IsThumb2, HasThumb2DSP]>;
2674 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2675 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2676 "\t$Ra, $Rd, $Rn, $Rm", []>,
2677 Requires<[IsThumb2, HasThumb2DSP]>;
2678 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2679 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2680 "\t$Ra, $Rd, $Rn, $Rm", []>,
2681 Requires<[IsThumb2, HasThumb2DSP]>;
2683 //===----------------------------------------------------------------------===//
2684 // Division Instructions.
2685 // Signed and unsigned division on v7-M
2687 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2688 "sdiv", "\t$Rd, $Rn, $Rm",
2689 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2690 Requires<[HasDivide, IsThumb2]> {
2691 let Inst{31-27} = 0b11111;
2692 let Inst{26-21} = 0b011100;
2694 let Inst{15-12} = 0b1111;
2695 let Inst{7-4} = 0b1111;
2698 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2699 "udiv", "\t$Rd, $Rn, $Rm",
2700 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2701 Requires<[HasDivide, IsThumb2]> {
2702 let Inst{31-27} = 0b11111;
2703 let Inst{26-21} = 0b011101;
2705 let Inst{15-12} = 0b1111;
2706 let Inst{7-4} = 0b1111;
2709 //===----------------------------------------------------------------------===//
2710 // Misc. Arithmetic Instructions.
2713 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2714 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2715 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2716 let Inst{31-27} = 0b11111;
2717 let Inst{26-22} = 0b01010;
2718 let Inst{21-20} = op1;
2719 let Inst{15-12} = 0b1111;
2720 let Inst{7-6} = 0b10;
2721 let Inst{5-4} = op2;
2725 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2726 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2728 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2729 "rbit", "\t$Rd, $Rm",
2730 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2732 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2733 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2735 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2736 "rev16", ".w\t$Rd, $Rm",
2737 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2739 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2740 "revsh", ".w\t$Rd, $Rm",
2741 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2743 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2744 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2745 (t2REVSH rGPR:$Rm)>;
2747 def t2PKHBT : T2ThreeReg<
2748 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2749 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2750 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2751 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2753 Requires<[HasT2ExtractPack, IsThumb2]> {
2754 let Inst{31-27} = 0b11101;
2755 let Inst{26-25} = 0b01;
2756 let Inst{24-20} = 0b01100;
2757 let Inst{5} = 0; // BT form
2761 let Inst{14-12} = sh{4-2};
2762 let Inst{7-6} = sh{1-0};
2765 // Alternate cases for PKHBT where identities eliminate some nodes.
2766 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2767 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2768 Requires<[HasT2ExtractPack, IsThumb2]>;
2769 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2770 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2771 Requires<[HasT2ExtractPack, IsThumb2]>;
2773 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2774 // will match the pattern below.
2775 def t2PKHTB : T2ThreeReg<
2776 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2777 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2778 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2779 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2781 Requires<[HasT2ExtractPack, IsThumb2]> {
2782 let Inst{31-27} = 0b11101;
2783 let Inst{26-25} = 0b01;
2784 let Inst{24-20} = 0b01100;
2785 let Inst{5} = 1; // TB form
2789 let Inst{14-12} = sh{4-2};
2790 let Inst{7-6} = sh{1-0};
2793 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2794 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2795 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2796 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2797 Requires<[HasT2ExtractPack, IsThumb2]>;
2798 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2799 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2800 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2801 Requires<[HasT2ExtractPack, IsThumb2]>;
2803 //===----------------------------------------------------------------------===//
2804 // Comparison Instructions...
2806 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2807 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2808 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
2810 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2811 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2812 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2813 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2814 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2815 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2817 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2818 // Compare-to-zero still works out, just not the relationals
2819 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2820 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2821 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2822 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2823 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
2826 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2827 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2829 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2830 (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2832 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2833 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2834 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
2836 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2837 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2838 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
2841 // Conditional moves
2842 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2843 // a two-value operand where a dag node expects two operands. :(
2844 let neverHasSideEffects = 1 in {
2845 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2846 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2848 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2849 RegConstraint<"$false = $Rd">;
2851 let isMoveImm = 1 in
2852 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2853 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2855 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2856 RegConstraint<"$false = $Rd">;
2858 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2859 let isCodeGenOnly = 1 in {
2860 let isMoveImm = 1 in
2861 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2863 "movw", "\t$Rd, $imm", []>,
2864 RegConstraint<"$false = $Rd"> {
2865 let Inst{31-27} = 0b11110;
2867 let Inst{24-21} = 0b0010;
2868 let Inst{20} = 0; // The S bit.
2874 let Inst{11-8} = Rd;
2875 let Inst{19-16} = imm{15-12};
2876 let Inst{26} = imm{11};
2877 let Inst{14-12} = imm{10-8};
2878 let Inst{7-0} = imm{7-0};
2881 let isMoveImm = 1 in
2882 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2883 (ins rGPR:$false, i32imm:$src, pred:$p),
2884 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2886 let isMoveImm = 1 in
2887 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2888 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2889 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2890 imm:$cc, CCR:$ccr))*/]>,
2891 RegConstraint<"$false = $Rd"> {
2892 let Inst{31-27} = 0b11110;
2894 let Inst{24-21} = 0b0011;
2895 let Inst{20} = 0; // The S bit.
2896 let Inst{19-16} = 0b1111; // Rn
2900 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2901 string opc, string asm, list<dag> pattern>
2902 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2903 let Inst{31-27} = 0b11101;
2904 let Inst{26-25} = 0b01;
2905 let Inst{24-21} = 0b0010;
2906 let Inst{20} = 0; // The S bit.
2907 let Inst{19-16} = 0b1111; // Rn
2908 let Inst{5-4} = opcod; // Shift type.
2910 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2911 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2912 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2913 RegConstraint<"$false = $Rd">;
2914 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2915 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2916 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2917 RegConstraint<"$false = $Rd">;
2918 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2919 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2920 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2921 RegConstraint<"$false = $Rd">;
2922 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2923 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2924 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2925 RegConstraint<"$false = $Rd">;
2926 } // isCodeGenOnly = 1
2927 } // neverHasSideEffects
2929 //===----------------------------------------------------------------------===//
2930 // Atomic operations intrinsics
2933 // memory barriers protect the atomic sequences
2934 let hasSideEffects = 1 in {
2935 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2936 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2937 Requires<[IsThumb, HasDB]> {
2939 let Inst{31-4} = 0xf3bf8f5;
2940 let Inst{3-0} = opt;
2944 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2945 "dsb", "\t$opt", []>,
2946 Requires<[IsThumb, HasDB]> {
2948 let Inst{31-4} = 0xf3bf8f4;
2949 let Inst{3-0} = opt;
2952 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2954 []>, Requires<[IsThumb2, HasDB]> {
2956 let Inst{31-4} = 0xf3bf8f6;
2957 let Inst{3-0} = opt;
2960 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2961 InstrItinClass itin, string opc, string asm, string cstr,
2962 list<dag> pattern, bits<4> rt2 = 0b1111>
2963 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2964 let Inst{31-27} = 0b11101;
2965 let Inst{26-20} = 0b0001101;
2966 let Inst{11-8} = rt2;
2967 let Inst{7-6} = 0b01;
2968 let Inst{5-4} = opcod;
2969 let Inst{3-0} = 0b1111;
2973 let Inst{19-16} = addr;
2974 let Inst{15-12} = Rt;
2976 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2977 InstrItinClass itin, string opc, string asm, string cstr,
2978 list<dag> pattern, bits<4> rt2 = 0b1111>
2979 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2980 let Inst{31-27} = 0b11101;
2981 let Inst{26-20} = 0b0001100;
2982 let Inst{11-8} = rt2;
2983 let Inst{7-6} = 0b01;
2984 let Inst{5-4} = opcod;
2990 let Inst{19-16} = addr;
2991 let Inst{15-12} = Rt;
2994 let mayLoad = 1 in {
2995 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
2996 AddrModeNone, 4, NoItinerary,
2997 "ldrexb", "\t$Rt, $addr", "", []>;
2998 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
2999 AddrModeNone, 4, NoItinerary,
3000 "ldrexh", "\t$Rt, $addr", "", []>;
3001 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3002 AddrModeNone, 4, NoItinerary,
3003 "ldrex", "\t$Rt, $addr", "", []> {
3006 let Inst{31-27} = 0b11101;
3007 let Inst{26-20} = 0b0000101;
3008 let Inst{19-16} = addr{11-8};
3009 let Inst{15-12} = Rt;
3010 let Inst{11-8} = 0b1111;
3011 let Inst{7-0} = addr{7-0};
3013 let hasExtraDefRegAllocReq = 1 in
3014 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
3015 (ins addr_offset_none:$addr),
3016 AddrModeNone, 4, NoItinerary,
3017 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3020 let Inst{11-8} = Rt2;
3024 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3025 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
3026 (ins rGPR:$Rt, addr_offset_none:$addr),
3027 AddrModeNone, 4, NoItinerary,
3028 "strexb", "\t$Rd, $Rt, $addr", "", []>;
3029 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
3030 (ins rGPR:$Rt, addr_offset_none:$addr),
3031 AddrModeNone, 4, NoItinerary,
3032 "strexh", "\t$Rd, $Rt, $addr", "", []>;
3033 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3034 t2addrmode_imm0_1020s4:$addr),
3035 AddrModeNone, 4, NoItinerary,
3036 "strex", "\t$Rd, $Rt, $addr", "",
3041 let Inst{31-27} = 0b11101;
3042 let Inst{26-20} = 0b0000100;
3043 let Inst{19-16} = addr{11-8};
3044 let Inst{15-12} = Rt;
3045 let Inst{11-8} = Rd;
3046 let Inst{7-0} = addr{7-0};
3050 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
3051 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
3052 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3053 AddrModeNone, 4, NoItinerary,
3054 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3057 let Inst{11-8} = Rt2;
3060 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
3061 Requires<[IsThumb2, HasV7]> {
3062 let Inst{31-16} = 0xf3bf;
3063 let Inst{15-14} = 0b10;
3066 let Inst{11-8} = 0b1111;
3067 let Inst{7-4} = 0b0010;
3068 let Inst{3-0} = 0b1111;
3071 //===----------------------------------------------------------------------===//
3072 // SJLJ Exception handling intrinsics
3073 // eh_sjlj_setjmp() is an instruction sequence to store the return
3074 // address and save #0 in R0 for the non-longjmp case.
3075 // Since by its nature we may be coming from some other function to get
3076 // here, and we're using the stack frame for the containing function to
3077 // save/restore registers, we can't keep anything live in regs across
3078 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3079 // when we get here from a longjmp(). We force everything out of registers
3080 // except for our own input by listing the relevant registers in Defs. By
3081 // doing so, we also cause the prologue/epilogue code to actively preserve
3082 // all of the callee-saved resgisters, which is exactly what we want.
3083 // $val is a scratch register for our use.
3085 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3086 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
3087 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
3088 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3089 AddrModeNone, 0, NoItinerary, "", "",
3090 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3091 Requires<[IsThumb2, HasVFP2]>;
3095 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3096 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
3097 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3098 AddrModeNone, 0, NoItinerary, "", "",
3099 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3100 Requires<[IsThumb2, NoVFP]>;
3104 //===----------------------------------------------------------------------===//
3105 // Control-Flow Instructions
3108 // FIXME: remove when we have a way to marking a MI with these properties.
3109 // FIXME: Should pc be an implicit operand like PICADD, etc?
3110 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3111 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3112 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3113 reglist:$regs, variable_ops),
3114 4, IIC_iLoad_mBr, [],
3115 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3116 RegConstraint<"$Rn = $wb">;
3118 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3119 let isPredicable = 1 in
3120 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3122 [(br bb:$target)]> {
3123 let Inst{31-27} = 0b11110;
3124 let Inst{15-14} = 0b10;
3128 let Inst{26} = target{19};
3129 let Inst{11} = target{18};
3130 let Inst{13} = target{17};
3131 let Inst{21-16} = target{16-11};
3132 let Inst{10-0} = target{10-0};
3135 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3136 def t2BR_JT : t2PseudoInst<(outs),
3137 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3139 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3141 // FIXME: Add a non-pc based case that can be predicated.
3142 def t2TBB_JT : t2PseudoInst<(outs),
3143 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3145 def t2TBH_JT : t2PseudoInst<(outs),
3146 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3148 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3149 "tbb", "\t$addr", []> {
3152 let Inst{31-20} = 0b111010001101;
3153 let Inst{19-16} = Rn;
3154 let Inst{15-5} = 0b11110000000;
3155 let Inst{4} = 0; // B form
3158 let DecoderMethod = "DecodeThumbTableBranch";
3161 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3162 "tbh", "\t$addr", []> {
3165 let Inst{31-20} = 0b111010001101;
3166 let Inst{19-16} = Rn;
3167 let Inst{15-5} = 0b11110000000;
3168 let Inst{4} = 1; // H form
3171 let DecoderMethod = "DecodeThumbTableBranch";
3173 } // isNotDuplicable, isIndirectBranch
3175 } // isBranch, isTerminator, isBarrier
3177 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3178 // a two-value operand where a dag node expects ", "two operands. :(
3179 let isBranch = 1, isTerminator = 1 in
3180 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3182 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3183 let Inst{31-27} = 0b11110;
3184 let Inst{15-14} = 0b10;
3188 let Inst{25-22} = p;
3191 let Inst{26} = target{20};
3192 let Inst{11} = target{19};
3193 let Inst{13} = target{18};
3194 let Inst{21-16} = target{17-12};
3195 let Inst{10-0} = target{11-1};
3197 let DecoderMethod = "DecodeThumb2BCCInstruction";
3200 // Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
3202 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3204 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
3206 def tTAILJMPd: tPseudoExpand<(outs),
3207 (ins uncondbrtarget:$dst, pred:$p, variable_ops),
3209 (t2B uncondbrtarget:$dst, pred:$p)>,
3210 Requires<[IsThumb2, IsDarwin]>;
3214 let Defs = [ITSTATE] in
3215 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3216 AddrModeNone, 2, IIC_iALUx,
3217 "it$mask\t$cc", "", []> {
3218 // 16-bit instruction.
3219 let Inst{31-16} = 0x0000;
3220 let Inst{15-8} = 0b10111111;
3225 let Inst{3-0} = mask;
3227 let DecoderMethod = "DecodeIT";
3230 // Branch and Exchange Jazelle -- for disassembly only
3232 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3234 let Inst{31-27} = 0b11110;
3236 let Inst{25-20} = 0b111100;
3237 let Inst{19-16} = func;
3238 let Inst{15-0} = 0b1000111100000000;
3241 // Compare and branch on zero / non-zero
3242 let isBranch = 1, isTerminator = 1 in {
3243 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3244 "cbz\t$Rn, $target", []>,
3245 T1Misc<{0,0,?,1,?,?,?}>,
3246 Requires<[IsThumb2]> {
3250 let Inst{9} = target{5};
3251 let Inst{7-3} = target{4-0};
3255 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3256 "cbnz\t$Rn, $target", []>,
3257 T1Misc<{1,0,?,1,?,?,?}>,
3258 Requires<[IsThumb2]> {
3262 let Inst{9} = target{5};
3263 let Inst{7-3} = target{4-0};
3269 // Change Processor State is a system instruction.
3270 // FIXME: Since the asm parser has currently no clean way to handle optional
3271 // operands, create 3 versions of the same instruction. Once there's a clean
3272 // framework to represent optional operands, change this behavior.
3273 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3274 !strconcat("cps", asm_op), []> {
3280 let Inst{31-27} = 0b11110;
3282 let Inst{25-20} = 0b111010;
3283 let Inst{19-16} = 0b1111;
3284 let Inst{15-14} = 0b10;
3286 let Inst{10-9} = imod;
3288 let Inst{7-5} = iflags;
3289 let Inst{4-0} = mode;
3290 let DecoderMethod = "DecodeT2CPSInstruction";
3294 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3295 "$imod.w\t$iflags, $mode">;
3296 let mode = 0, M = 0 in
3297 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3298 "$imod.w\t$iflags">;
3299 let imod = 0, iflags = 0, M = 1 in
3300 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3302 // A6.3.4 Branches and miscellaneous control
3303 // Table A6-14 Change Processor State, and hint instructions
3304 class T2I_hint<bits<8> op7_0, string opc, string asm>
3305 : T2I<(outs), (ins), NoItinerary, opc, asm, []> {
3306 let Inst{31-20} = 0xf3a;
3307 let Inst{19-16} = 0b1111;
3308 let Inst{15-14} = 0b10;
3310 let Inst{10-8} = 0b000;
3311 let Inst{7-0} = op7_0;
3314 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3315 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3316 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3317 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3318 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3320 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3322 let Inst{31-20} = 0b111100111010;
3323 let Inst{19-16} = 0b1111;
3324 let Inst{15-8} = 0b10000000;
3325 let Inst{7-4} = 0b1111;
3326 let Inst{3-0} = opt;
3329 // Secure Monitor Call is a system instruction.
3330 // Option = Inst{19-16}
3331 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> {
3332 let Inst{31-27} = 0b11110;
3333 let Inst{26-20} = 0b1111111;
3334 let Inst{15-12} = 0b1000;
3337 let Inst{19-16} = opt;
3340 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3341 string opc, string asm, list<dag> pattern>
3342 : T2I<oops, iops, itin, opc, asm, pattern> {
3344 let Inst{31-25} = 0b1110100;
3345 let Inst{24-23} = Op;
3348 let Inst{20-16} = 0b01101;
3349 let Inst{15-5} = 0b11000000000;
3350 let Inst{4-0} = mode{4-0};
3353 // Store Return State is a system instruction.
3354 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3355 "srsdb", "\tsp!, $mode", []>;
3356 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3357 "srsdb","\tsp, $mode", []>;
3358 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3359 "srsia","\tsp!, $mode", []>;
3360 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3361 "srsia","\tsp, $mode", []>;
3363 // Return From Exception is a system instruction.
3364 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3365 string opc, string asm, list<dag> pattern>
3366 : T2I<oops, iops, itin, opc, asm, pattern> {
3367 let Inst{31-20} = op31_20{11-0};
3370 let Inst{19-16} = Rn;
3371 let Inst{15-0} = 0xc000;
3374 def t2RFEDBW : T2RFE<0b111010000011,
3375 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3376 [/* For disassembly only; pattern left blank */]>;
3377 def t2RFEDB : T2RFE<0b111010000001,
3378 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3379 [/* For disassembly only; pattern left blank */]>;
3380 def t2RFEIAW : T2RFE<0b111010011011,
3381 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3382 [/* For disassembly only; pattern left blank */]>;
3383 def t2RFEIA : T2RFE<0b111010011001,
3384 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3385 [/* For disassembly only; pattern left blank */]>;
3387 //===----------------------------------------------------------------------===//
3388 // Non-Instruction Patterns
3391 // 32-bit immediate using movw + movt.
3392 // This is a single pseudo instruction to make it re-materializable.
3393 // FIXME: Remove this when we can do generalized remat.
3394 let isReMaterializable = 1, isMoveImm = 1 in
3395 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3396 [(set rGPR:$dst, (i32 imm:$src))]>,
3397 Requires<[IsThumb, HasV6T2]>;
3399 // Pseudo instruction that combines movw + movt + add pc (if pic).
3400 // It also makes it possible to rematerialize the instructions.
3401 // FIXME: Remove this when we can do generalized remat and when machine licm
3402 // can properly the instructions.
3403 let isReMaterializable = 1 in {
3404 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3406 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3407 Requires<[IsThumb2, UseMovt]>;
3409 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3411 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3412 Requires<[IsThumb2, UseMovt]>;
3415 // ConstantPool, GlobalAddress, and JumpTable
3416 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3417 Requires<[IsThumb2, DontUseMovt]>;
3418 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3419 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3420 Requires<[IsThumb2, UseMovt]>;
3422 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3423 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3425 // Pseudo instruction that combines ldr from constpool and add pc. This should
3426 // be expanded into two instructions late to allow if-conversion and
3428 let canFoldAsLoad = 1, isReMaterializable = 1 in
3429 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3431 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3433 Requires<[IsThumb2]>;
3434 //===----------------------------------------------------------------------===//
3435 // Coprocessor load/store -- for disassembly only
3437 class T2CI<dag oops, dag iops, string opc, string asm>
3438 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3439 let Inst{27-25} = 0b110;
3442 multiclass T2LdStCop<bits<4> op31_28, bit load, string opc> {
3443 def _OFFSET : T2CI<(outs),
3444 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3445 opc, "\tp$cop, cr$CRd, $addr"> {
3446 let Inst{31-28} = op31_28;
3447 let Inst{24} = 1; // P = 1
3448 let Inst{21} = 0; // W = 0
3449 let Inst{22} = 0; // D = 0
3450 let Inst{20} = load;
3451 let DecoderMethod = "DecodeCopMemInstruction";
3454 def _PRE : T2CI<(outs),
3455 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3456 opc, "\tp$cop, cr$CRd, $addr!"> {
3457 let Inst{31-28} = op31_28;
3458 let Inst{24} = 1; // P = 1
3459 let Inst{21} = 1; // W = 1
3460 let Inst{22} = 0; // D = 0
3461 let Inst{20} = load;
3462 let DecoderMethod = "DecodeCopMemInstruction";
3465 def _POST : T2CI<(outs),
3466 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3467 opc, "\tp$cop, cr$CRd, $addr"> {
3468 let Inst{31-28} = op31_28;
3469 let Inst{24} = 0; // P = 0
3470 let Inst{21} = 1; // W = 1
3471 let Inst{22} = 0; // D = 0
3472 let Inst{20} = load;
3473 let DecoderMethod = "DecodeCopMemInstruction";
3476 def _OPTION : T2CI<(outs),
3477 (ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3478 opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3479 let Inst{31-28} = op31_28;
3480 let Inst{24} = 0; // P = 0
3481 let Inst{23} = 1; // U = 1
3482 let Inst{21} = 0; // W = 0
3483 let Inst{22} = 0; // D = 0
3484 let Inst{20} = load;
3485 let DecoderMethod = "DecodeCopMemInstruction";
3488 def L_OFFSET : T2CI<(outs),
3489 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3490 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3491 let Inst{31-28} = op31_28;
3492 let Inst{24} = 1; // P = 1
3493 let Inst{21} = 0; // W = 0
3494 let Inst{22} = 1; // D = 1
3495 let Inst{20} = load;
3496 let DecoderMethod = "DecodeCopMemInstruction";
3499 def L_PRE : T2CI<(outs),
3500 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3501 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3502 let Inst{31-28} = op31_28;
3503 let Inst{24} = 1; // P = 1
3504 let Inst{21} = 1; // W = 1
3505 let Inst{22} = 1; // D = 1
3506 let Inst{20} = load;
3507 let DecoderMethod = "DecodeCopMemInstruction";
3510 def L_POST : T2CI<(outs),
3511 (ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
3512 postidx_imm8s4:$offset),
3513 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr, $offset"> {
3514 let Inst{31-28} = op31_28;
3515 let Inst{24} = 0; // P = 0
3516 let Inst{21} = 1; // W = 1
3517 let Inst{22} = 1; // D = 1
3518 let Inst{20} = load;
3519 let DecoderMethod = "DecodeCopMemInstruction";
3522 def L_OPTION : T2CI<(outs),
3523 (ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3524 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3525 let Inst{31-28} = op31_28;
3526 let Inst{24} = 0; // P = 0
3527 let Inst{23} = 1; // U = 1
3528 let Inst{21} = 0; // W = 0
3529 let Inst{22} = 1; // D = 1
3530 let Inst{20} = load;
3531 let DecoderMethod = "DecodeCopMemInstruction";
3535 defm t2LDC : T2LdStCop<0b1111, 1, "ldc">;
3536 defm t2STC : T2LdStCop<0b1111, 0, "stc">;
3539 //===----------------------------------------------------------------------===//
3540 // Move between special register and ARM core register -- for disassembly only
3542 // Move to ARM core register from Special Register
3546 // A/R class can only move from CPSR or SPSR.
3547 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []>,
3548 Requires<[IsThumb2,IsARClass]> {
3550 let Inst{31-12} = 0b11110011111011111000;
3551 let Inst{11-8} = Rd;
3552 let Inst{7-0} = 0b0000;
3555 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3557 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []>,
3558 Requires<[IsThumb2,IsARClass]> {
3560 let Inst{31-12} = 0b11110011111111111000;
3561 let Inst{11-8} = Rd;
3562 let Inst{7-0} = 0b0000;
3567 // This MRS has a mask field in bits 7-0 and can take more values than
3568 // the A/R class (a full msr_mask).
3569 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
3570 "mrs", "\t$Rd, $mask", []>,
3571 Requires<[IsThumb2,IsMClass]> {
3574 let Inst{31-12} = 0b11110011111011111000;
3575 let Inst{11-8} = Rd;
3576 let Inst{19-16} = 0b1111;
3577 let Inst{7-0} = mask;
3581 // Move from ARM core register to Special Register
3585 // No need to have both system and application versions, the encodings are the
3586 // same and the assembly parser has no way to distinguish between them. The mask
3587 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3588 // the mask with the fields to be accessed in the special register.
3589 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3590 NoItinerary, "msr", "\t$mask, $Rn", []>,
3591 Requires<[IsThumb2,IsARClass]> {
3594 let Inst{31-21} = 0b11110011100;
3595 let Inst{20} = mask{4}; // R Bit
3596 let Inst{19-16} = Rn;
3597 let Inst{15-12} = 0b1000;
3598 let Inst{11-8} = mask{3-0};
3604 // Move from ARM core register to Special Register
3605 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
3606 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
3607 Requires<[IsThumb2,IsMClass]> {
3610 let Inst{31-21} = 0b11110011100;
3612 let Inst{19-16} = Rn;
3613 let Inst{15-12} = 0b1000;
3614 let Inst{7-0} = SYSm;
3618 //===----------------------------------------------------------------------===//
3619 // Move between coprocessor and ARM core register
3622 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3624 : T2Cop<Op, oops, iops,
3625 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3627 let Inst{27-24} = 0b1110;
3628 let Inst{20} = direction;
3638 let Inst{15-12} = Rt;
3639 let Inst{11-8} = cop;
3640 let Inst{23-21} = opc1;
3641 let Inst{7-5} = opc2;
3642 let Inst{3-0} = CRm;
3643 let Inst{19-16} = CRn;
3646 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3647 list<dag> pattern = []>
3649 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3650 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3651 let Inst{27-24} = 0b1100;
3652 let Inst{23-21} = 0b010;
3653 let Inst{20} = direction;
3661 let Inst{15-12} = Rt;
3662 let Inst{19-16} = Rt2;
3663 let Inst{11-8} = cop;
3664 let Inst{7-4} = opc1;
3665 let Inst{3-0} = CRm;
3668 /* from ARM core register to coprocessor */
3669 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3671 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3672 c_imm:$CRm, imm0_7:$opc2),
3673 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3674 imm:$CRm, imm:$opc2)]>;
3675 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3676 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3677 c_imm:$CRm, imm0_7:$opc2),
3678 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3679 imm:$CRm, imm:$opc2)]>;
3681 /* from coprocessor to ARM core register */
3682 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3683 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3684 c_imm:$CRm, imm0_7:$opc2), []>;
3686 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3687 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3688 c_imm:$CRm, imm0_7:$opc2), []>;
3690 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3691 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3693 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3694 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3697 /* from ARM core register to coprocessor */
3698 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3699 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3701 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3702 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3703 GPR:$Rt2, imm:$CRm)]>;
3704 /* from coprocessor to ARM core register */
3705 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3707 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3709 //===----------------------------------------------------------------------===//
3710 // Other Coprocessor Instructions.
3713 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3714 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3715 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3716 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3717 imm:$CRm, imm:$opc2)]> {
3718 let Inst{27-24} = 0b1110;
3727 let Inst{3-0} = CRm;
3729 let Inst{7-5} = opc2;
3730 let Inst{11-8} = cop;
3731 let Inst{15-12} = CRd;
3732 let Inst{19-16} = CRn;
3733 let Inst{23-20} = opc1;
3736 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3737 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3738 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3739 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3740 imm:$CRm, imm:$opc2)]> {
3741 let Inst{27-24} = 0b1110;
3750 let Inst{3-0} = CRm;
3752 let Inst{7-5} = opc2;
3753 let Inst{11-8} = cop;
3754 let Inst{15-12} = CRd;
3755 let Inst{19-16} = CRn;
3756 let Inst{23-20} = opc1;
3761 //===----------------------------------------------------------------------===//
3762 // Non-Instruction Patterns
3765 // SXT/UXT with no rotate
3766 let AddedComplexity = 16 in {
3767 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3768 Requires<[IsThumb2]>;
3769 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3770 Requires<[IsThumb2]>;
3771 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3772 Requires<[HasT2ExtractPack, IsThumb2]>;
3773 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3774 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3775 Requires<[HasT2ExtractPack, IsThumb2]>;
3776 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3777 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3778 Requires<[HasT2ExtractPack, IsThumb2]>;
3781 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3782 Requires<[IsThumb2]>;
3783 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3784 Requires<[IsThumb2]>;
3785 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3786 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3787 Requires<[HasT2ExtractPack, IsThumb2]>;
3788 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3789 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3790 Requires<[HasT2ExtractPack, IsThumb2]>;
3792 // Atomic load/store patterns
3793 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3794 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3795 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
3796 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
3797 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3798 (t2LDRBs t2addrmode_so_reg:$addr)>;
3799 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3800 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3801 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
3802 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
3803 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3804 (t2LDRHs t2addrmode_so_reg:$addr)>;
3805 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3806 (t2LDRi12 t2addrmode_imm12:$addr)>;
3807 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
3808 (t2LDRi8 t2addrmode_negimm8:$addr)>;
3809 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3810 (t2LDRs t2addrmode_so_reg:$addr)>;
3811 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3812 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3813 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
3814 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3815 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3816 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3817 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3818 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3819 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
3820 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3821 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3822 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3823 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3824 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3825 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
3826 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3827 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3828 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
3831 //===----------------------------------------------------------------------===//
3832 // Assembler aliases
3835 // Aliases for ADC without the ".w" optional width specifier.
3836 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
3837 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3838 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
3839 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3840 pred:$p, cc_out:$s)>;
3842 // Aliases for SBC without the ".w" optional width specifier.
3843 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
3844 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3845 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
3846 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3847 pred:$p, cc_out:$s)>;
3849 // Aliases for ADD without the ".w" optional width specifier.
3850 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3851 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3852 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3853 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3854 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
3855 (t2ADDrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3856 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
3857 (t2ADDrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3858 pred:$p, cc_out:$s)>;
3860 // Aliases for SUB without the ".w" optional width specifier.
3861 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
3862 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3863 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
3864 (t2SUBri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3865 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
3866 (t2SUBrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3867 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
3868 (t2SUBrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3869 pred:$p, cc_out:$s)>;
3871 // Alias for compares without the ".w" optional width specifier.
3872 def : t2InstAlias<"cmn${p} $Rn, $Rm",
3873 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3874 def : t2InstAlias<"teq${p} $Rn, $Rm",
3875 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3876 def : t2InstAlias<"tst${p} $Rn, $Rm",
3877 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3880 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
3881 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
3882 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
3884 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
3886 def : t2InstAlias<"ldr${p} $Rt, $addr",
3887 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3888 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3889 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3890 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3891 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3892 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3893 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3894 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3895 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3897 def : t2InstAlias<"ldr${p} $Rt, $addr",
3898 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3899 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3900 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3901 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3902 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3903 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3904 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3905 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3906 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3908 // Alias for MVN without the ".w" optional width specifier.
3909 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
3910 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
3911 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
3912 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
3914 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
3915 // shift amount is zero (i.e., unspecified).
3916 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
3917 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3918 Requires<[HasT2ExtractPack, IsThumb2]>;
3919 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
3920 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3921 Requires<[HasT2ExtractPack, IsThumb2]>;
3923 // PUSH/POP aliases for STM/LDM
3924 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3925 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3926 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3927 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3929 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
3930 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3931 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3932 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3935 // Alias for RSB without the ".w" optional width specifier, and with optional
3936 // implied destination register.
3937 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
3938 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3939 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
3940 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3941 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
3942 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3943 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
3944 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
3947 // SSAT/USAT optional shift operand.
3948 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
3949 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
3950 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
3951 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
3953 // STM w/o the .w suffix.
3954 def : t2InstAlias<"stm${p} $Rn, $regs",
3955 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
3957 // Alias for STR, STRB, and STRH without the ".w" optional
3959 def : t2InstAlias<"str${p} $Rt, $addr",
3960 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3961 def : t2InstAlias<"strb${p} $Rt, $addr",
3962 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3963 def : t2InstAlias<"strh${p} $Rt, $addr",
3964 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3966 def : t2InstAlias<"str${p} $Rt, $addr",
3967 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3968 def : t2InstAlias<"strb${p} $Rt, $addr",
3969 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3970 def : t2InstAlias<"strh${p} $Rt, $addr",
3971 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3973 // Extend instruction optional rotate operand.
3974 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
3975 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3976 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
3977 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3978 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
3979 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3981 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
3982 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3983 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
3984 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3985 def : t2InstAlias<"sxth${p} $Rd, $Rm",
3986 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3987 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
3988 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3989 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
3990 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3992 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
3993 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3994 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
3995 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3996 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
3997 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3998 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
3999 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4000 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
4001 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4002 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4003 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4005 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4006 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4007 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4008 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4010 // Extend instruction w/o the ".w" optional width specifier.
4011 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4012 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4013 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4014 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4015 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4016 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4018 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4019 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4020 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4021 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4022 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4023 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;